----
- src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 +
- .../dell/snb_ivb_latitude/Kconfig.name | 3 +
- .../snb_ivb_latitude/variants/e6220/data.vbt | Bin 0 -> 3985 bytes
- .../variants/e6220/early_init.c | 14 ++
- .../snb_ivb_latitude/variants/e6220/gpio.c | 192 ++++++++++++++++++
- .../variants/e6220/hda_verb.c | 32 +++
- .../variants/e6220/overridetree.cb | 37 ++++
- 7 files changed, 287 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 84ffe1d33a..baa83baa41 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
- select BOARD_ROMSIZE_KB_6144
- select SOUTHBRIDGE_INTEL_BD82X6X
-
-+config BOARD_DELL_LATITUDE_E6220
-+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+ select BOARD_ROMSIZE_KB_10240
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E6320
- select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- select BOARD_ROMSIZE_KB_10240
-@@ -73,6 +79,7 @@ config MAINBOARD_DIR
- config MAINBOARD_PART_NUMBER
- default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
- default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
-+ default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220
- default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
- default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
-@@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX
- config VARIANT_DIR
- default "e5420" if BOARD_DELL_LATITUDE_E5420
- default "e5520" if BOARD_DELL_LATITUDE_E5520
-+ default "e6220" if BOARD_DELL_LATITUDE_E6220
- default "e6320" if BOARD_DELL_LATITUDE_E6320
- default "e6420" if BOARD_DELL_LATITUDE_E6420
- default "e6520" if BOARD_DELL_LATITUDE_E6520
-@@ -102,6 +110,7 @@ config VGA_BIOS_ID
- default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- || BOARD_DELL_LATITUDE_E5520 \
-+ || BOARD_DELL_LATITUDE_E6220 \
- || BOARD_DELL_LATITUDE_E6320
- default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
- || BOARD_DELL_LATITUDE_E6530
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index ef6a1329a9..349ee7f79e 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
- config BOARD_DELL_LATITUDE_E5520
- bool "Latitude E5520"
-
-+config BOARD_DELL_LATITUDE_E6220
-+ bool "Latitude E6220"
-+
- config BOARD_DELL_LATITUDE_E6320
- bool "Latitude E6320"
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..548075a74500b5d159108089ee29cff802d07db7
-GIT binary patch
-literal 3985
-zcmdT{eP|p-6#wn*-rZ(yH@R-odPzTgZQ6LXjonL|7&YQ0xu#d`$C=h}21|4GP8*0x
-zyjE@hv0Dv(P?c0g{G(_DMJZ@22r8oZ0U9lcR8a)~s33wOSg|T<^?b8?XBzL?#)6`A
-z{N~Nfd-LYan>TOv7WZ{+rcIq264!S1u1&02-MpSC3mf}u-r~BvbgkXEX=|c$bLZBs
-zbsM{{q9-s1nVR3f2C|A`nJsqvC7UwC+1=angV`H%w4saofx<^KL=Lc`x
-zzLTQeOW7vdZsuwwtsUOU>vxajM=zqzp&{y(GCQa@weIb%fzF6`uwy)UhaB+ynus
-zBRr-~^|__t=m5fD9tR81r@XLV3UEc-2I6>o`;@@MXS$rj)&)r+pA?|K2vh+9SHM=N
-zw3d{Uh1~iK)juV`E`v4?cFU@^_DehBU5TFLmFrTyoBPuJ*ExIdxO1!lC!eceSG8i}
-z&Aivl*T2}Cf;*vEJvsN-nR!WWDm8M^Zmcltu96wMRudvHXLxn;xh~EqEM^Gr}m&=vHbwRKjl{%)fM2d8tOI4MM{l!dK
-z4$)%2P!LDJaqX2t;s4$Wy@Q1gZ=x97KlhsvF9`g6&TYocZ_JQN=A1hUE#+kAD@E9jJd7%}~
-zMLIYMDVoel8h1}$+_YJF%DJ&-O)X~`ZoroouO-yDsj)OrPU{{+ph4LJKdD;Bi3a3T
-zbe?Tf8&elW+H+t;5$y~|nhq{o@?k1^-Hg%jhcu{xJyzvgk`0m*Te#GQe$
-z2IjOP{U&oF$`&WsuJN2!=fTnT^W)PwhnW-Ya3)3%H!`OUfy6?#V9r%+wCY}TU0!Cl
-z*kjeex}MZl_aWVoxhXfp&Ur~>>k;onlO4II%~KY!FT|r)!;agdwcf~rXIAVwc6CEj
-zJpE{CBzZ;L-gdYp9)GC8f@wZ%=YBfkLb0_gZP%us?_tgG3TXJ7BDbWb~V23Mt{QT(?mOc#ihbo#YtY#rD
-z7PLiJBSP#J^tiB|7vdE`p9|}IA$}9o7_wSJ;))RELe^~|u{T6dhpd-F;;j&U6|#N}
-z3BN(h4C``3tTE^&!`fqrdks2dSZ^5Oh(X^Omdc+rCapBB)uz~J(k-TSw<-3U^rC6K
-zYl;s|`q{KX)nazFdEs%*@f}l~SsY?~kb2(WgGl=fm!43>4I&2(k1$iaK?FYVZ}~h~1{1T|;>=%b4`yk3XF>siEVHyC@HS
-z8OvVW%DeB`K&~H7>f?&^gQU_A0oM;p0b*k61j!x*S5X(-unS`9rZ
-zG}=vb+R*x})DSq-Q7;uJwKLPuG`Ej6G}#nch4dSqhHo0B2Gq%HbgCyS+pwZ3{?fph
-z!Jo*Dxcw7v7a#rIU2IRmVn4KE$x~88+a7J4zd|_!%xo9z$+P;Q6qA*AQ5FvzlPW^f
-zY&aJUhO1#_o~&$x>1qJKGpC+K<(u_&1197VVWxipk10ERAEpLG3^|JWI~DYG*_Qk)fwt)g^KZ*f*K5tEj9C7Ea`HGyPe8U4wd
-nX2Iz@%Q6UTm;}-X%j^D0i1fiT)I6)4TdrsMY}`L(
-+#include
-+#include
-+#include
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+ | COMB_LPC_EN | COMA_LPC_EN);
-+ mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
-new file mode 100644
-index 0000000000..2306e4cf0a
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_NATIVE,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_GPIO,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_INPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+ .gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio1 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_OUTPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio49 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
-new file mode 100644
-index 0000000000..0c69f0bd0e
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
-+ 0x102804a9, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x102804a9),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862805, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-new file mode 100644
-index 0000000000..9faf27e27b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-@@ -0,0 +1,37 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+ device domain 0 on
-+ subsystemid 0x1028 0x04a9 inherit
-+
-+ device ref igd on
-+ register "gpu_cpu_backlight" = "0x0000046a"
-+ register "gpu_pch_backlight" = "0x13121312"
-+ end
-+
-+ chip southbridge/intel/bd82x6x
-+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
-+ register "usb_port_config" = "{
-+ { 1, 1, 0 },
-+ { 1, 0, 0 },
-+ { 1, 1, 1 },
-+ { 1, 0, 1 },
-+ { 1, 1, 2 },
-+ { 1, 1, 2 },
-+ { 1, 1, 3 },
-+ { 1, 1, 3 },
-+ { 1, 0, 5 },
-+ { 1, 0, 5 },
-+ { 1, 1, 7 },
-+ { 1, 1, 6 },
-+ { 1, 0, 6 },
-+ { 1, 0, 7 },
-+ }"
-+
-+ device ref pcie_rp4 off end
-+ device ref sata1 on
-+ register "sata_port_map" = "0x3b"
-+ end
-+ end
-+ end
-+end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
similarity index 93%
rename from config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
rename to config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
index fe9034b0..9525b8ce 100644
--- a/config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
+++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
@@ -1,7 +1,7 @@
-From ce7d65790b9b8656ebbaa0ca715adff6a9c25588 Mon Sep 17 00:00:00 2001
+From a507fe609a2e99c95218ec430916eaf4c3cb61d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 26/51] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 15/37] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016
diff --git a/config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch b/config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch
deleted file mode 100644
index 7d2133ef..00000000
--- a/config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch
+++ /dev/null
@@ -1,436 +0,0 @@
-From 0889cc6b6f62cba616feff5ae8558be31f298069 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Fri, 8 Mar 2024 09:33:03 -0700
-Subject: [PATCH 16/51] mb/dell: Add Latitude E6330 (Ivy Bridge)
-
-Mainboard is QAL70/LA-7741P. I do not physically have this system;
-someone with physical access to one sent me the output of autoport which
-I then modified to produce this port. I was also sent the VBT binary,
-which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
-version A21 of the vendor firmware. This port has not been tested.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
- .../dell/snb_ivb_latitude/Kconfig.name | 3 +
- .../snb_ivb_latitude/variants/e6330/data.vbt | Bin 0 -> 6144 bytes
- .../variants/e6330/early_init.c | 14 ++
- .../snb_ivb_latitude/variants/e6330/gpio.c | 192 ++++++++++++++++++
- .../variants/e6330/hda_verb.c | 32 +++
- .../variants/e6330/overridetree.cb | 37 ++++
- 7 files changed, 288 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index baa83baa41..49bf225fe2 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
- select BOARD_ROMSIZE_KB_12288
- select SOUTHBRIDGE_INTEL_C216
-
-+config BOARD_DELL_LATITUDE_E6330
-+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+ select BOARD_ROMSIZE_KB_12288
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select SOUTHBRIDGE_INTEL_C216
-+
- config BOARD_DELL_LATITUDE_E6430
- select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- select BOARD_ROMSIZE_KB_12288
-@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER
- default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-+ default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
- default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-
-@@ -101,13 +108,15 @@ config VARIANT_DIR
- default "e6420" if BOARD_DELL_LATITUDE_E6420
- default "e6520" if BOARD_DELL_LATITUDE_E6520
- default "e5530" if BOARD_DELL_LATITUDE_E5530
-+ default "e6330" if BOARD_DELL_LATITUDE_E6330
- default "e6430" if BOARD_DELL_LATITUDE_E6430
- default "e6530" if BOARD_DELL_LATITUDE_E6530
-
- config VGA_BIOS_ID
- default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
- || BOARD_DELL_LATITUDE_E5420
-- default "8086,0166" if BOARD_DELL_LATITUDE_E5530
-+ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \
-+ || BOARD_DELL_LATITUDE_E6330
- default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- || BOARD_DELL_LATITUDE_E5520 \
- || BOARD_DELL_LATITUDE_E6220 \
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 349ee7f79e..d6fc8eb224 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
- config BOARD_DELL_LATITUDE_E5530
- bool "Latitude E5530"
-
-+config BOARD_DELL_LATITUDE_E6330
-+ bool "Latitude E6330"
-+
- config BOARD_DELL_LATITUDE_E6430
- bool "Latitude E6430"
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62
-GIT binary patch
-literal 6144
-zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D
-z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3RvNXNl&Dsr*z_6HAP5GJeST
-znX2JD;{xLa#;c6KGychVn-L6YXkv6Qx)}Y8&ok1DI~ZSM6dCt39%QUAzRh@o@gqjy
-zL0qZ&DhN8ZR3xu$a$Cd{oasU3DNp{CCl6f~PYlq!Hte;Ia0^wn8Vut7>Wl1)s`^E-
-z1DhGxzr8&7h}dMJ3~YBe;)!vVf-T&?{PoMvvRR{!67;Xhz^g^loX
-zja+*c-KJJoxbsm3pTE4THs`cgD{Pt+ga3en-i$P#9Wsra(oqRMr;H$4{gxr)9eF(x
-zg0v@a7aj}rA^Kf#sNb*>at^>P)5li%ycOq*4e;3~RUj$i1e8=rHi&Y_gP4=
-zxz9^%q0dLXqC&Bq<&sDScZwvatjRxB=rcJJiYb?w#4Iy2KTk1F6T>T}E@(DNGa>5R
-z7&Yv)JdHrRI};pfsKLVj=FE=U*=*T4#ncVktknoGelT||SDY`+9WI_IZE`_>@wb<-RI-lu(_~Oy_Zo6={Cdq!uw(fmyz_u^cB&~5IS7g`U
-zdUC}N$J5-C)|`CfUO+?xptr@*hJW$ZhBZk%JaMh_<8!ZGj)z*WU9fcg2`>dT##_?q
-z=Ksx}uxo3jTHTq%E1}97UECE@r}nt3I=3R(HOL7jNg>teSM-g$aU#`3jk}#qh;D?6
-zw=CYuA2#mS+vU%0P&u8RCn4)$8VH-2uy#01%VG0WSX&Fz`LMYj)?NgH_zzWS)G2Pn=k3wYdU|DnWmxbG$>`5lZJMWL92%O14BD!(C-cNFNXFH
-zgVc!G9?@=&(4mNVcSJiLq3=b^rz6@k5qdFVUW{m$A{2|7d!kxz)VSrcQt@4sDoq^f
-z98hXm=YS~qbfiR|LbzHLa*mLXlH${^b4c9%>9%)HO-?LA1gT0mlz!M}8&;(;^x|
-z*H22;juB|7F+k?y(_2~3@STqQ@f^sqD2c8g3x>ciM%siMq~;pKwfE57kw2K@
-z!-ZN0QTVOP@aA5@fEGKjy2+D`t?2KzpPyRQ`JcmHJoc(<#hvyF
-zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+
-ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d
-+#include
-+#include
-+#include
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+ | COMB_LPC_EN | COMA_LPC_EN);
-+ mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+ .gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
-new file mode 100644
-index 0000000000..804733b172
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
-+ 0x10280533, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x10280533),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-new file mode 100644
-index 0000000000..4125159367
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-@@ -0,0 +1,37 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+ device domain 0 on
-+ subsystemid 0x1028 0x0533 inherit
-+
-+ device ref igd on
-+ register "gpu_cpu_backlight" = "0x00001312"
-+ register "gpu_pch_backlight" = "0x13121312"
-+ end
-+
-+ chip southbridge/intel/bd82x6x
-+ register "usb_port_config" = "{
-+ { 1, 2, 0 },
-+ { 1, 0, 0 },
-+ { 1, 0, 1 },
-+ { 1, 1, 1 },
-+ { 1, 1, 2 },
-+ { 1, 1, 2 },
-+ { 1, 2, 3 },
-+ { 1, 2, 3 },
-+ { 1, 2, 4 },
-+ { 1, 1, 4 },
-+ { 1, 1, 5 },
-+ { 1, 1, 5 },
-+ { 1, 2, 6 },
-+ { 1, 0, 6 },
-+ }"
-+
-+ device ref xhci on
-+ register "superspeed_capable_ports" = "0x0000000f"
-+ register "xhci_overcurrent_mapping" = "0x00000c03"
-+ register "xhci_switchable_ports" = "0x0000000f"
-+ end
-+ end
-+ end
-+end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
similarity index 98%
rename from config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
rename to config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
index 28fc679f..091a15c4 100644
--- a/config/coreboot/default/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
+++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
@@ -1,7 +1,7 @@
-From c6181fe0c8b58cb5a4523d5763fc5fcdf61b3f10 Mon Sep 17 00:00:00 2001
+From 9e0a6aa376db81f9409eda92b6783a8262c1fedb Mon Sep 17 00:00:00 2001
From: Angel Pons
Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 27/51] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 16/37] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
diff --git a/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch b/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch
deleted file mode 100644
index 412b8471..00000000
--- a/config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch
+++ /dev/null
@@ -1,440 +0,0 @@
-From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Thu, 26 Oct 2017 21:26:43 +0800
-Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge)
-
-This was adapted from CB:22693 from Iru Cai, which was based on
-autoport. I do not physically have this system. Someone with physical
-access to an E6230 running version A11 of the vendor firmware sent me
-the VBT after running the command `intelvbttool --inlegacy --outvbt
-data.vbt`. This new version of the port has not yet been tested.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
-Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
- .../dell/snb_ivb_latitude/Kconfig.name | 3 +
- .../snb_ivb_latitude/variants/e6230/data.vbt | Bin 0 -> 4280 bytes
- .../variants/e6230/early_init.c | 12 ++
- .../snb_ivb_latitude/variants/e6230/gpio.c | 193 ++++++++++++++++++
- .../variants/e6230/hda_verb.c | 32 +++
- .../variants/e6230/overridetree.cb | 40 ++++
- 7 files changed, 290 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 49bf225fe2..f6e097930b 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
- select BOARD_ROMSIZE_KB_12288
- select SOUTHBRIDGE_INTEL_C216
-
-+config BOARD_DELL_LATITUDE_E6230
-+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+ select BOARD_ROMSIZE_KB_12288
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select SOUTHBRIDGE_INTEL_C216
-+
- config BOARD_DELL_LATITUDE_E6330
- select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- select BOARD_ROMSIZE_KB_12288
-@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER
- default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-+ default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230
- default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
- default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-@@ -108,6 +115,7 @@ config VARIANT_DIR
- default "e6420" if BOARD_DELL_LATITUDE_E6420
- default "e6520" if BOARD_DELL_LATITUDE_E6520
- default "e5530" if BOARD_DELL_LATITUDE_E5530
-+ default "e6230" if BOARD_DELL_LATITUDE_E6230
- default "e6330" if BOARD_DELL_LATITUDE_E6330
- default "e6430" if BOARD_DELL_LATITUDE_E6430
- default "e6530" if BOARD_DELL_LATITUDE_E6530
-@@ -121,7 +129,8 @@ config VGA_BIOS_ID
- || BOARD_DELL_LATITUDE_E5520 \
- || BOARD_DELL_LATITUDE_E6220 \
- || BOARD_DELL_LATITUDE_E6320
-- default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
-+ default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \
-+ || BOARD_DELL_LATITUDE_E6430 \
- || BOARD_DELL_LATITUDE_E6530
-
- endif
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index d6fc8eb224..cb7bbd5cdb 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
- config BOARD_DELL_LATITUDE_E5530
- bool "Latitude E5530"
-
-+config BOARD_DELL_LATITUDE_E6230
-+ bool "Latitude E6230"
-+
- config BOARD_DELL_LATITUDE_E6330
- bool "Latitude E6330"
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66
-GIT binary patch
-literal 4280
-zcmdT{Yiu0V75-*tAG5PFyX&zDekA7P<*tbx&o1`j23L%CmvkLWvN7(mLa6alZ?J`9
-zo3#m4YVlG`2;w12Ajppt~|mMp8L%`XU@4ZyCa_(r`z|Z`bP4p-rEkOMn-R;Ntk#o`b)0sOKRl6
-z?T0eMZS*@LZWP#hD{>
-zSLslxYH@j~%H#VLx+<8~!;a@$n+>Q%xHrQ8KGI21_iL4sI
-zF*$}m$R7Mr9z@Z*ir@Q9eClsSmC+t(g`q~VQ&nIxZenav_^Buc78s8*o@e|t}g
-z1Z-O>lG`>pEuvmL-HpmgSANo!2hWQq2B>Zua$8%tfvQ>!1n@=m9ri_4`H|Rx#SH9n
-zDdRF_-FDP&WjW`L$GK%a6x?yO8l2!^g0HJrtA7TknNzCO?|U!wCv2^-5pJ%LW6!+P
-z)anX%E>`gP%3Er4c6+J9x=Atk1{Abrr1|WSY3P`SO5j!R5F*vbbQ%AaSHnR_+x&Op
-zA%8C-Pk=-Hs+FL90B)E*y3FUTIA1J)&pxRF$tzAkNr7a6_-8v$@j~G~3keqYd5I;y8g^P<
-zfWO_D2@EyVVBxnpv*}hgTeeRzWz9BoISh>M%^k`WXG=5ti$_Wu99)~lWE-qubeXNk
-zla9Tu=Jhyn5T<3$H#?Hfm-`+(d$7IBDx9cEvNv1i-LEDr>r7438bfkPcKod+mwd22
-z%{^(w&NuG)MKl0fTMTXZFJEm~k;KCj*D60g=j!2jsP){tzvOjAJ2nB}At~#%f4?FGT+d8LFnXXtYN&Mm06B
-z(JwUPX-z$$(d(M=uBLvh@h6#K=;~&jQo1p&t3TCgSvQ{3)l)jXr5hjW>fd!z!bW>o
-z-4UjJVdJi_dN@o^hK(1(>dRqzCv2PztLMTLjTqY^YEMMJ{=B#1IV)9~IMg|yl(NPF
-zQSfMX`?(b5)))B!zjy0B$ua20CCLTPl^IS&2=T&Zid9-1*K{VAJP?rxjYC+zGDCe*
-ziQI7VfF17@3`3W-qCN>lPC5CL_c?p0FTGXaGB3i~{ZE
-zr=QtIprytDnU7C*Wj%x0k)O{Y%nUnl%}K%F|J_iVaD&ubW4Qbtx;pZEb9}f^Yd;Ea
-zI1Ha{7Yt~z{LAY++1QG{F6*_4WsUziY{x?%I9B}i5-Tphhk8FGm%Jf!3d-ysG_9>uk%#)4xpxb+ZkJdel#+h}l9j9`1
-zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI{5E<^P=0rLsId@e&
-z-cNvr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg
-Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
-new file mode 100644
-index 0000000000..24c1b32467
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-+ mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
-new file mode 100644
-index 0000000000..c07e4b1c56
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
-@@ -0,0 +1,193 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_OUTPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio17 = GPIO_LEVEL_HIGH,
-+ .gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+ .gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
-new file mode 100644
-index 0000000000..f6876f9e09
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
-+ 0x10280532, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x10280532),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-new file mode 100644
-index 0000000000..3a0fa720da
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-@@ -0,0 +1,40 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+ device domain 0 on
-+ subsystemid 0x1028 0x0532 inherit
-+
-+ device ref igd on
-+ register "gpu_cpu_backlight" = "0x000009e9"
-+ register "gpu_pch_backlight" = "0x13121312"
-+ end
-+
-+ chip southbridge/intel/bd82x6x
-+ register "usb_port_config" = "{
-+ { 1, 1, 0 },
-+ { 1, 1, 0 },
-+ { 1, 0, 1 },
-+ { 1, 2, 1 },
-+ { 1, 0, 2 },
-+ { 1, 0, 2 },
-+ { 1, 0, 3 },
-+ { 1, 1, 3 },
-+ { 1, 2, 4 },
-+ { 1, 1, 4 },
-+ { 1, 1, 5 },
-+ { 1, 1, 5 },
-+ { 1, 2, 6 },
-+ { 1, 0, 6 },
-+ }"
-+
-+ device ref xhci on
-+ register "superspeed_capable_ports" = "0x0000000f"
-+ register "xhci_overcurrent_mapping" = "0x00000c03"
-+ register "xhci_switchable_ports" = "0x0000000f"
-+ end
-+ device ref sata1 on
-+ register "sata_port_map" = "0x31"
-+ end
-+ end
-+ end
-+end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
similarity index 98%
rename from config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
rename to config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
index 92e59129..4ba74757 100644
--- a/config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
+++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
@@ -1,7 +1,7 @@
-From b6f75374fa38e0b097c9eadb4916112707cb6747 Mon Sep 17 00:00:00 2001
+From 6acc310c1d695d47c148296da9da189de21d58be Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 28/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+Subject: [PATCH 17/37] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:
diff --git a/config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
similarity index 90%
rename from config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
rename to config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
index e31cb64c..1cf7c0ac 100644
--- a/config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
+++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
@@ -1,7 +1,7 @@
-From d3045b3dcebd94b78df2129cd81a20adf215e46a Mon Sep 17 00:00:00 2001
+From 7461210ecc7c8e41f3f941bd5ce7943e5f66c711 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 29/51] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 18/37] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -33,7 +33,7 @@ index 417d95fd5d..6fe1b1c456 100644
default "dell/e6400"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index 8059e7ee80..5df5a93296 100644
+index fef0d735b3..fc5df8b11a 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
diff --git a/config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
similarity index 89%
rename from config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
rename to config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
index 988ae4e6..2edfaae3 100644
--- a/config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
+++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
@@ -1,7 +1,7 @@
-From 53f2d47ee6ebaa8d47b076a6c2a1514c91247b95 Mon Sep 17 00:00:00 2001
+From a683dffd774dbbe25cc77c0f7d3853232c17c2bf Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 47/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+Subject: [PATCH 19/37] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe
1 file changed, 4 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 9af063819b..93ba575b95 100644
+index 097e11126c..6430319f6a 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
diff --git a/config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
similarity index 98%
rename from config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch
rename to config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
index 156d5c8d..a0068142 100644
--- a/config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch
+++ b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
@@ -1,7 +1,7 @@
-From 92556743e92cc02524296b653de5241160876218 Mon Sep 17 00:00:00 2001
+From a48ba23bb4a24730fa49b5a10b56c9de873dea8a Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 48/51] mb/dell: Convert E6400 into a variant
+Subject: [PATCH 20/37] mb/dell: Convert E6400 into a variant
All the GM45 Dell Latitudes should be nearly identical, so convert the
E6400 port into a variant so that future ports for the other systems can
diff --git a/config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
similarity index 98%
rename from config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch
rename to config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
index 2cdcd499..af893982 100644
--- a/config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch
+++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
@@ -1,7 +1,7 @@
-From ac8ac2543e3ebbc05f79f37d1460cde532a7ee1c Mon Sep 17 00:00:00 2001
+From b87e6774f0407ea48610c83ea54ab6a4b4a78a24 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 49/51] mb/dell/gm45_latitudes: Add E4300 variant
+Subject: [PATCH 21/37] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin
diff --git a/config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
similarity index 94%
rename from config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
rename to config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
index 71cc67c1..bbdce358 100644
--- a/config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
+++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
@@ -1,7 +1,7 @@
-From 5e8b899654c31fe771e4b1e96c74c93d4509c3b2 Mon Sep 17 00:00:00 2001
+From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 50/51] mb/dell: Add S3 SMI handler for Dell Latitudes
+Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
Integrate the previously added mec5035_smi_sleep() function into
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
diff --git a/config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
similarity index 96%
rename from config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch
rename to config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
index 65f90e2c..ab01c935 100644
--- a/config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch
+++ b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
@@ -1,7 +1,7 @@
-From 1a342c20b8705bbea02d27a73e383ee2808f2558 Mon Sep 17 00:00:00 2001
+From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 51/51] ec/dell/mec5035: Route power button event to host
+Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
power button results in the EC powering off the system without letting
diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
new file mode 100644
index 00000000..c557e9d7
--- /dev/null
+++ b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
@@ -0,0 +1,31 @@
+From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Tue, 31 Dec 2024 14:42:24 +0000
+Subject: [PATCH 24/37] Disable compression on refcode insertion
+
+Compression is not reliably reproducible. In an lbmk release
+context, this means we cannot rely on vendorfile insertion.
+
+Therefore, use uncompressed refcode.
+
+Signed-off-by: Leah Rowe
+---
+ Makefile.mk | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.mk b/Makefile.mk
+index 3969bfbd05..15346569f8 100644
+--- a/Makefile.mk
++++ b/Makefile.mk
+@@ -1392,7 +1392,7 @@ endif
+ cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
+ $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
+ $(CONFIG_CBFS_PREFIX)/refcode-type := stage
+-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
++$(CONFIG_CBFS_PREFIX)/refcode-compression := none
+
+ cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
+ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch b/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch
deleted file mode 100644
index 6c1118bb..00000000
--- a/config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From a1566875789469ebd91e472301be4b359aac0a4c Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Tue, 28 May 2024 17:23:21 -0600
-Subject: [PATCH 24/51] ec/dell/mec5035: Replace defines with enums
-
-Instead of using defines for command IDs and argument values, use enums
-to provide more type safety. This also has the effect of moving the
-command IDs to a more central location instead of defines spread out
-throughout the header.
-
-Change-Id: I788531e8b70e79541213853f177326d217235ef2
-Signed-off-by: Nicholas Chin
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998
-Tested-by: build bot (Jenkins)
-Reviewed-by: Felix Singer
----
- src/ec/dell/mec5035/mec5035.c | 10 +++++-----
- src/ec/dell/mec5035/mec5035.h | 20 ++++++++++++--------
- 2 files changed, 17 insertions(+), 13 deletions(-)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 68b6b2f7fb..dffbb7960c 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -66,17 +66,17 @@ static enum cb_err write_mailbox_regs(const u8 *data, u8 start, u8 count)
- return CB_SUCCESS;
- }
-
--static void ec_command(u8 cmd)
-+static void ec_command(enum mec5035_cmd cmd)
- {
- outb(0, MAILBOX_INDEX);
-- outb(cmd, MAILBOX_DATA);
-+ outb((u8)cmd, MAILBOX_DATA);
- wait_ec();
- }
-
--u8 mec5035_mouse_touchpad(u8 setting)
-+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting)
- {
-- u8 buf[15] = {0};
-- write_mailbox_regs(&setting, 2, 1);
-+ u8 buf[15] = {(u8)setting};
-+ write_mailbox_regs(buf, 2, 1);
- ec_command(CMD_MOUSE_TP);
- /* The vendor firmware reads 15 bytes starting at index 1, presumably
- to get some sort of return code. Though I don't know for sure if
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index fa15a9d621..32f791cb01 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -7,16 +7,20 @@
-
- #define NUM_REGISTERS 32
-
-+enum mec5035_cmd {
-+ CMD_MOUSE_TP = 0x1a,
-+ CMD_RADIO_CTRL = 0x2b,
-+ CMD_CPU_OK = 0xc2,
-+};
-+
- /* Touchpad (TP) and mouse related. The EC seems to
- default to 0 which results in the TP not working. */
--#define CMD_MOUSE_TP 0x1a
--#define SERIAL_MOUSE 0 /* Disable TP, force use of a serial mouse */
--#define PS2_MOUSE 1 /* Disable TP when using a PS/2 mouse */
--#define TP_PS2_MOUSE 2 /* Leave TP enabled when using a PS/2 mouse */
--
--#define CMD_CPU_OK 0xc2
-+enum ec_mouse_setting {
-+ SERIAL_MOUSE = 0, /* Disable TP, force use of a serial mouse */
-+ PS2_MOUSE, /* Disable TP when using a PS/2 mouse */
-+ TP_PS2_MOUSE /* Leave TP enabled when using a PS/2 mouse */
-+};
-
--#define CMD_RADIO_CTRL 0x2b
- #define RADIO_CTRL_NUM_ARGS 3
- enum ec_radio_dev {
- RADIO_WLAN = 0,
-@@ -29,7 +33,7 @@ enum ec_radio_state {
- RADIO_ON
- };
-
--u8 mec5035_mouse_touchpad(u8 setting);
-+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
new file mode 100644
index 00000000..696be518
--- /dev/null
+++ b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
@@ -0,0 +1,187 @@
+From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 21 Apr 2025 02:58:47 +0100
+Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
+
+Signed-off-by: Leah Rowe
+---
+ src/northbridge/intel/e7505/Kconfig | 9 +++++++++
+ src/northbridge/intel/gm45/Kconfig | 9 +++++++++
+ src/northbridge/intel/haswell/Kconfig | 9 +++++++++
+ src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
+ src/northbridge/intel/i945/Kconfig | 9 +++++++++
+ src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
+ src/northbridge/intel/pineview/Kconfig | 9 +++++++++
+ src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
+ src/northbridge/intel/x4x/Kconfig | 9 +++++++++
+ 9 files changed, 85 insertions(+)
+
+diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
+index 039a7396f8..ddcb986f10 100644
+--- a/src/northbridge/intel/e7505/Kconfig
++++ b/src/northbridge/intel/e7505/Kconfig
+@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
+ select NO_CBFS_MCACHE
+ select SMM_TSEG
+ select NEED_SMALL_2MB_PAGE_TABLES
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
+diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
+index fc5df8b11a..95e3644b73 100644
+--- a/src/northbridge/intel/gm45/Kconfig
++++ b/src/northbridge/intel/gm45/Kconfig
+@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
+index 6191cb6ccf..0f5b5c7241 100644
+--- a/src/northbridge/intel/haswell/Kconfig
++++ b/src/northbridge/intel/haswell/Kconfig
+@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
+
+ if NORTHBRIDGE_INTEL_HASWELL
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ config USE_NATIVE_RAMINIT
+ bool "[NOT COMPLETE] Use native raminit"
+ default n
+diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
+index dbb2d7436b..5e9418b6a9 100644
+--- a/src/northbridge/intel/i440bx/Kconfig
++++ b/src/northbridge/intel/i440bx/Kconfig
+@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
+ If your board has 4 DIMM slots, you must use select this option, in
+ your Kconfig file of the board. On boards with 3 DIMM slots,
+ do _not_ select this option.
++
++if NORTHBRIDGE_INTEL_I440BX
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
++endif
+diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
+index 32eff1a611..9479d75c07 100644
+--- a/src/northbridge/intel/i945/Kconfig
++++ b/src/northbridge/intel/i945/Kconfig
+@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
+index 2bafebf92e..16b81705bb 100644
+--- a/src/northbridge/intel/ironlake/Kconfig
++++ b/src/northbridge/intel/ironlake/Kconfig
+@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
+index 59cfcd5e0a..a3ad8d3425 100644
+--- a/src/northbridge/intel/pineview/Kconfig
++++ b/src/northbridge/intel/pineview/Kconfig
+@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
+ config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
+index 973eed8bbd..6387cf926d 100644
+--- a/src/northbridge/intel/sandybridge/Kconfig
++++ b/src/northbridge/intel/sandybridge/Kconfig
+@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
+ default 2 if IGD_DEFAULT_UMA_SIZE_96MB
+ default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
+index 6430319f6a..1803ef5733 100644
+--- a/src/northbridge/intel/x4x/Kconfig
++++ b/src/northbridge/intel/x4x/Kconfig
+@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+--
+2.39.5
+
diff --git a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
similarity index 95%
rename from config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
rename to config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
index 1b6b5372..c411c18b 100644
--- a/config/coreboot/next/patches/0001-soc-intel-skylake-configure-usb-acpi.patch
+++ b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
@@ -1,7 +1,7 @@
-From 18b68185f44599cf6ea6a20816bf6a5eb7aeda17 Mon Sep 17 00:00:00 2001
+From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
From: Felix Singer
Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 1/8] soc/intel/skylake: configure usb acpi
+Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer
@@ -11,7 +11,7 @@ Signed-off-by: Felix Singer
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 22017c848b..c24df2ef75 100644
+index 4ad33496b2..9191ed0ff8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
diff --git a/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
similarity index 86%
rename from config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
rename to config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
index 6e7d4b7c..9d75cec6 100644
--- a/config/coreboot/next/patches/0003-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
+++ b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
@@ -1,7 +1,7 @@
-From b3049cfd11aa0f3c124ed8f87e98a200201ecbdc Mon Sep 17 00:00:00 2001
+From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
From: Mate Kukri
Date: Fri, 22 Nov 2024 21:26:48 +0000
-Subject: [PATCH 3/8] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
+Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
bootblock
Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
diff --git a/config/coreboot/next/patches/0004-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
similarity index 84%
rename from config/coreboot/next/patches/0004-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
rename to config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
index 1ac1a536..df71dc47 100644
--- a/config/coreboot/next/patches/0004-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
+++ b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
@@ -1,106 +1,87 @@
-From e905d7fd1ee1a791f27285715d420263e422ebee Mon Sep 17 00:00:00 2001
-From: Mate Kukri
-Date: Mon, 2 Dec 2024 16:10:22 +0000
-Subject: [PATCH 4/8] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
+From b515ba5b0cd02dc1771f27eaa716582b0827a638 Mon Sep 17 00:00:00 2001
+From: Mate Kukri
+Date: Tue, 31 Dec 2024 22:49:15 +0000
+Subject: [PATCH 28/37] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
-These machine have BootGuard fused and requires deguard to boot coreboot.
-
-Works:
-- Intel GPU
-- Internal screen
-- Ethernet
-- USB
-- EC
- + Fan control
- + Keyboard
- + Battery (T480 has two)
- + Charging via both Type-C ports
- + Debug UART (on T480)
-- WLAN card:
- + WiFi works
- + Bluetooth works
-- M.2 main SSD
-- HDA verbs, Speakers, headphone jack
-- S3 sleep
+These machine have BootGuard fused and requires deguard to
+boot coreboot.
Known issues:
- Alpine Ridge Thunderbolt 3 controller does not work
-- Function keys are handled differently from stock firmware
- + These should inject XF86 keycodes instead of directly
- controlling, volume, brightness, etc in hardware.
-- Nvidia dGPU
+- Some Fn+F{1-12} keys aren't handled correctly
+- Nvidia dGPU is finicky
- Needs option ROM
- Power enable code is buggy
- Nouveau only works on linux 6.8-6.9
-
-Untested (should work):
-- SATA main SSD
-- WWAN slot
- + PCIe x2 NVME drive
- + WWAN card (bus)
-- SD reader (USB)
-- Webcam (USB)
-- External video outputs
+- Headphone jack isn't detected as plugged in despite correct verbs
Thanks to Leah Rowe for helping with the T480s.
-Signed-off-by: Mate Kukri
+Signed-off-by: Mate Kukri
Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
---
- src/device/pci_rom.c | 12 +-
+ src/device/pci_rom.c | 4 +-
src/ec/lenovo/h8/acpi/ec.asl | 2 +-
- src/ec/lenovo/h8/bluetooth.c | 12 +-
- src/ec/lenovo/h8/wwan.c | 12 +-
- src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 42 +++-
- .../lenovo/sklkbl_thinkpad/Kconfig.name | 6 +
- .../lenovo/sklkbl_thinkpad/Makefile.mk | 72 ++++++-
- .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 13 +-
- .../lenovo/sklkbl_thinkpad/bootblock.c | 50 +++++
- .../lenovo/sklkbl_thinkpad/devicetree.cb | 36 ++++
- src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 17 +-
+ src/ec/lenovo/h8/bluetooth.c | 6 +-
+ src/ec/lenovo/h8/wwan.c | 6 +-
+ src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++
+ .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 +
+ .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++
+ .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++
+ .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 +
+ .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++
+ .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++
src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++
src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++
src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 +
- .../lenovo/sklkbl_thinkpad/ramstage.c | 98 ++++++++-
- .../lenovo/sklkbl_thinkpad/romstage.c | 7 -
+ .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++
.../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes
.../variants/t480/gma-mainboard.ads | 19 ++
.../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++
.../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++
.../variants/t480/memory_init_params.c | 20 ++
- .../variants/t480/overridetree.cb | 124 +++++++++++
+ .../variants/t480/overridetree.cb | 103 +++++++++
.../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
.../variants/t480s/gma-mainboard.ads | 19 ++
.../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++
.../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++
.../variants/t480s/memory_init_params.c | 44 ++++
- .../variants/t480s/overridetree.cb | 124 +++++++++++
- .../sklkbl_thinkpad/variants/t480s/spd_0.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_1.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_10.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_11.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_12.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_13.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_14.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_15.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_16.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_17.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_18.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_19.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_2.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_20.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_3.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_4.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_5.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_6.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_7.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_8.bin | Bin 0 -> 512 bytes
- .../sklkbl_thinkpad/variants/t480s/spd_9.bin | Bin 0 -> 512 bytes
- 49 files changed, 1531 insertions(+), 40 deletions(-)
+ .../variants/t480s/overridetree.cb | 103 +++++++++
+ .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes
+ 49 files changed, 1583 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
- delete mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/romstage.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
@@ -113,56 +94,48 @@ Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_12.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_13.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_14.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_15.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_16.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_17.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_18.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_19.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_20.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_3.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
-index d60720eb49..b18dfdd287 100644
+index dc41ef14ce..bba98d9dea 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
-@@ -304,11 +304,11 @@ void pci_rom_ssdt(const struct device *device)
- return;
+@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device)
+ rom = cbrom;
}
-- const char *scope = acpi_device_path(device);
-- if (!scope) {
-- printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
-- return;
-- }
-+ // const char *scope = acpi_device_path(device);
-+ // if (!scope) {
-+ // printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
-+ // return;
-+ // }
-
- /* Supports up to four devices. */
- if ((CBMEM_ID_ROM0 + ngfx) > CBMEM_ID_ROM3) {
-@@ -336,7 +336,7 @@ void pci_rom_ssdt(const struct device *device)
- memcpy(cbrom, rom, cbrom_length);
++#if 0
+ const char *scope = acpi_device_path(device);
+ if (!scope) {
+ printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
+ return;
+ }
++#endif
/* write _ROM method */
- acpigen_write_scope(scope);
+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
- acpigen_write_rom(cbrom, cbrom_length);
+ acpigen_write_rom((void *)rom, rom->size * 512);
acpigen_pop_len(); /* pop scope */
}
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
@@ -179,7 +152,7 @@ index bc54d3b422..8f4a8e1986 100644
#include "thinkpad.asl"
}
diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
-index 16fc8dce39..ef4f6ad1f5 100644
+index 16fc8dce39..be71a24ced 100644
--- a/src/ec/lenovo/h8/bluetooth.c
+++ b/src/ec/lenovo/h8/bluetooth.c
@@ -1,6 +1,6 @@
@@ -190,7 +163,7 @@ index 16fc8dce39..ef4f6ad1f5 100644
#include
#include
#include
-@@ -28,16 +28,16 @@ bool h8_has_bdc(const struct device *dev)
+@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;
@@ -201,19 +174,17 @@ index 16fc8dce39..ef4f6ad1f5 100644
return true;
}
-- if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
-- printk(BIOS_INFO, "H8: BDC installed\n");
-- return true;
-- }
-+ // if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
-+ // printk(BIOS_INFO, "H8: BDC installed\n");
-+ // return true;
-+ // }
++#if 0
+ if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
+ printk(BIOS_INFO, "H8: BDC installed\n");
+ return true;
+ }
++#endif
printk(BIOS_INFO, "H8: BDC not installed\n");
return false;
diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
-index 685886fcce..5e0ae030e2 100644
+index 685886fcce..5cdcf77406 100644
--- a/src/ec/lenovo/h8/wwan.c
+++ b/src/ec/lenovo/h8/wwan.c
@@ -1,6 +1,6 @@
@@ -224,7 +195,7 @@ index 685886fcce..5e0ae030e2 100644
#include
#include
#include
-@@ -26,16 +26,16 @@ bool h8_has_wwan(const struct device *dev)
+@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;
@@ -235,110 +206,85 @@ index 685886fcce..5e0ae030e2 100644
return true;
}
-- if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
-- printk(BIOS_INFO, "H8: WWAN installed\n");
-- return true;
-- }
-+ // if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
-+ // printk(BIOS_INFO, "H8: WWAN installed\n");
-+ // return true;
-+ // }
++#if 0
+ if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
+ printk(BIOS_INFO, "H8: WWAN installed\n");
+ return true;
+ }
++#endif
printk(BIOS_INFO, "H8: WWAN not installed\n");
return false;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-index fcc80dffe3..21076315ab 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+new file mode 100644
+index 0000000000..4998672943
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-@@ -2,16 +2,20 @@
-
- config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
- bool
-- select BOARD_ROMSIZE_KB_12288
+@@ -0,0 +1,57 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++ bool
++ select BOARD_ROMSIZE_KB_16384
+ select EC_LENOVO_H8
+ select EC_LENOVO_PMH7
+ select H8_HAS_BAT_THRESHOLDS_IMPL
+ select H8_HAS_LEDLOGO
+ select H8_HAS_PRIMARY_FN_KEYS
- select HAVE_ACPI_RESUME
- select HAVE_ACPI_TABLES
- # select HAVE_CMOS_DEFAULT
--# select INTEL_GMA_HAVE_VBT
-- select INTEL_LPSS_UART_FOR_CONSOLE
++ select HAVE_ACPI_RESUME
++ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
- select MAINBOARD_HAS_LIBGFXINIT
- select MEMORY_MAPPED_TPM
- select MAINBOARD_HAS_TPM2
-- select NO_UART_ON_SUPERIO
++ select MAINBOARD_HAS_LIBGFXINIT
++ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_USES_IFD_GBE_REGION
- select SOC_INTEL_COMMON_BLOCK_HDA_VERB
- select SPD_READ_BY_WORD
- select SYSTEM_TYPE_LAPTOP
-@@ -19,8 +23,22 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
- config BOARD_LENOVO_E460
- bool
- select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+ select BOARD_ROMSIZE_KB_12288
-+ select INTEL_LPSS_UART_FOR_CONSOLE
- select SOC_INTEL_SKYLAKE
-
++ select MEMORY_MAPPED_TPM
++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
++ select SOC_INTEL_KABYLAKE
++ select SPD_READ_BY_WORD
++ select SYSTEM_TYPE_LAPTOP
++
+config BOARD_LENOVO_T480
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+ select BOARD_ROMSIZE_KB_16384
-+ select SOC_INTEL_KABYLAKE
+
+config BOARD_LENOVO_T480S
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+ select BOARD_ROMSIZE_KB_16384
-+ select SOC_INTEL_KABYLAKE
+
- if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-
- config MAINBOARD_DIR
-@@ -28,18 +46,30 @@ config MAINBOARD_DIR
-
- config VARIANT_DIR
- default "e460" if BOARD_LENOVO_E460
++if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++config MAINBOARD_DIR
++ default "lenovo/sklkbl_thinkpad"
++
++config VARIANT_DIR
+ default "t480" if BOARD_LENOVO_T480
+ default "t480s" if BOARD_LENOVO_T480S
+
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
- config MAINBOARD_PART_NUMBER
- default "E460" if BOARD_LENOVO_E460
++
++config MAINBOARD_PART_NUMBER
+ default "T480" if BOARD_LENOVO_T480
+ default "T480s" if BOARD_LENOVO_T480S
-
- config CBFS_SIZE
- default 0x600000 if BOARD_LENOVO_E460
-+ default 0x900000 if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S
-
- config DIMM_MAX
-- default 4
++
++config CBFS_SIZE
++ default 0x900000
++
++config DIMM_MAX
+ default 2
-
- config DIMM_SPD_SIZE
-- default 256
++
++config DIMM_SPD_SIZE
+ default 512 # DDR4
+
+endif
-+
-+if BOARD_LENOVO_E460
-
- config UART_FOR_CONSOLE
- default 2
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
-index 61d971fe8d..15441c4264 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+new file mode 100644
+index 0000000000..abc273f387
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
-@@ -2,3 +2,9 @@
-
- config BOARD_LENOVO_E460
- bool "ThinkPad E460"
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_T480
+ bool "ThinkPad T480"
@@ -346,97 +292,94 @@ index 61d971fe8d..15441c4264 100644
+config BOARD_LENOVO_T480S
+ bool "ThinkPad T480s"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
-index 6e544fd6b9..49d6ebdb4e 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+new file mode 100644
+index 0000000000..c308239177
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
-@@ -1,7 +1,73 @@
- ## SPDX-License-Identifier: GPL-2.0-only
-
--bootblock-y += bootblock.c
+@@ -0,0 +1,73 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
+bootblock-y += bootblock.c ec.c
-
--ramstage-y += ramstage.c
--ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
++
+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
+
+ramstage-y += ramstage.c ec.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c
- ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin
-+spd_0.bin-file := variants/$(VARIANT_DIR)/spd_0.bin
++spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin
+spd_0.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin
-+spd_1.bin-file := variants/$(VARIANT_DIR)/spd_1.bin
++spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin
+spd_1.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin
-+spd_2.bin-file := variants/$(VARIANT_DIR)/spd_2.bin
++spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin
+spd_2.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin
-+spd_3.bin-file := variants/$(VARIANT_DIR)/spd_3.bin
++spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin
+spd_3.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin
-+spd_4.bin-file := variants/$(VARIANT_DIR)/spd_4.bin
++spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin
+spd_4.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin
-+spd_5.bin-file := variants/$(VARIANT_DIR)/spd_5.bin
++spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin
+spd_5.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin
-+spd_6.bin-file := variants/$(VARIANT_DIR)/spd_6.bin
++spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin
+spd_6.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin
-+spd_7.bin-file := variants/$(VARIANT_DIR)/spd_7.bin
++spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin
+spd_7.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin
-+spd_8.bin-file := variants/$(VARIANT_DIR)/spd_8.bin
++spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin
+spd_8.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin
-+spd_9.bin-file := variants/$(VARIANT_DIR)/spd_9.bin
++spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin
+spd_9.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin
-+spd_10.bin-file := variants/$(VARIANT_DIR)/spd_10.bin
++spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin
+spd_10.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin
-+spd_11.bin-file := variants/$(VARIANT_DIR)/spd_11.bin
++spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin
+spd_11.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin
-+spd_12.bin-file := variants/$(VARIANT_DIR)/spd_12.bin
++spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin
+spd_12.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin
-+spd_13.bin-file := variants/$(VARIANT_DIR)/spd_13.bin
++spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin
+spd_13.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin
-+spd_14.bin-file := variants/$(VARIANT_DIR)/spd_14.bin
++spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin
+spd_14.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin
-+spd_15.bin-file := variants/$(VARIANT_DIR)/spd_15.bin
++spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin
+spd_15.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin
-+spd_16.bin-file := variants/$(VARIANT_DIR)/spd_16.bin
++spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin
+spd_16.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin
-+spd_17.bin-file := variants/$(VARIANT_DIR)/spd_17.bin
++spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin
+spd_17.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin
-+spd_18.bin-file := variants/$(VARIANT_DIR)/spd_18.bin
++spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin
+spd_18.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin
-+spd_19.bin-file := variants/$(VARIANT_DIR)/spd_19.bin
++spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin
+spd_19.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin
-+spd_20.bin-file := variants/$(VARIANT_DIR)/spd_20.bin
++spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin
+spd_20.bin-type := raw
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
-index 16990d45f4..514b95a60f 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+new file mode 100644
+index 0000000000..3a949a2fca
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
-@@ -1,3 +1,12 @@
--/* SPDX-License-Identifier: CC-PDDC */
+@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
-
--/* Please update the license if adding licensable material. */
-+#define BRIGHTNESS_UP()
-+#define BRIGHTNESS_DOWN()
++
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define THINKPAD_EC_GPE 22
+
+Name(\TCRT, 100)
@@ -445,15 +388,25 @@ index 16990d45f4..514b95a60f 100644
+
+#include
+#include
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
-index ccd8ec1b40..55afd3d048 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+new file mode 100644
+index 0000000000..fb660dbdfa
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
-@@ -1,7 +1,57 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
-
+@@ -0,0 +1,60 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
+#include
- #include
++#include
+#include
+#include
+#include "ec.h"
@@ -476,25 +429,22 @@ index ccd8ec1b40..55afd3d048 100644
+
+ microchip_pnp_exit_conf_state(port);
+
-+ // NOTE: this is incredibly hacky and uses a debug backdoor in the EC
-+ // firmware to control the UART GPIOs.
-+ // Unfortunately production EC firmware has no way to do this via regular EC
-+ // commands.
-+
++#ifdef CONFIG_BOARD_LENOVO_T480
+ // Supply debug unlock key
+ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
+
+ // Use debug writes to set UART_TX and UART_RX GPIOs
+ debug_write_dword(0xf0c400 + 0x110, 0x00001000);
+ debug_write_dword(0xf0c400 + 0x114, 0x00001000);
++#endif
+}
+
+
+#define UART_PORT 0x3f8
+#define UART_IRQ 4
-
- void bootblock_mainboard_early_init(void)
- {
++
++void bootblock_mainboard_early_init(void)
++{
+ // Tell EC via BIOS Debug Port 1 that the world isn't on fire
+
+ // Let the EC know that BIOS code is running
@@ -504,17 +454,49 @@ index ccd8ec1b40..55afd3d048 100644
+ // Enable accesses to EC1 interface
+ ec0_write(0, ec0_read(0) | 0x20);
+
++ // Reset LEDs to power on state
++ // (Without this warm reboot leaves LEDs off)
++ ec0_write(0x0c, 0x80);
++ ec0_write(0x0c, 0x07);
++ ec0_write(0x0c, 0x8a);
++
+ // Setup debug UART
+ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
- }
++}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
-index ddb6e8aaa5..745af8c8cd 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+new file mode 100644
+index 0000000000..c07d4d53ca
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
-@@ -8,6 +8,42 @@ chip soc/intel/skylake
- device ref south_xhci on end
- device ref lpc_espi on
- register "serirq_mode" = "SERIRQ_CONTINUOUS"
+@@ -0,0 +1,71 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++chip soc/intel/skylake
++ # IGD Displays
++ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
++
++ register "panel_cfg" = "{
++ .up_delay_ms = 200,
++ .down_delay_ms = 50,
++ .cycle_delay_ms = 600,
++ .backlight_on_delay_ms = 1,
++ .backlight_off_delay_ms = 200,
++ .backlight_pwm_hz = 200,
++ }"
++
++ # Power
++ register "PmConfigSlpS3MinAssert" = "2" # 50ms
++ register "PmConfigSlpS4MinAssert" = "1" # 1s
++ register "PmConfigSlpSusMinAssert" = "3" # 500ms
++ register "PmConfigSlpAMinAssert" = "3" # 2s
++
++ device domain 0 on
++ device ref igpu on end
++ device ref sa_thermal on end
++ device ref thermal on end
++ device ref south_xhci on end
++ device ref lpc_espi on
++ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "gen1_dec" = "0x007c1601"
+ register "gen2_dec" = "0x000c15e1"
@@ -551,33 +533,39 @@ index ddb6e8aaa5..745af8c8cd 100644
+ end
+ end
+
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
++ chip drivers/pc80/tpm
++ device pnp 0c31.0 on end
++ end
++ end
++ device ref hda on end
++ end
++end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-index 967b652853..237500775f 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+new file mode 100644
+index 0000000000..aa4d4de2a6
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-@@ -1,5 +1,10 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
-
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+#define EC_LENOVO_H8_ME_WORKAROUND 1
-+#define THINKPAD_EC_GPE 17
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++DefinitionBlock(
++ "dsdt.aml",
++ "DSDT",
++ ACPI_DSDT_REV_2,
++ OEM_ID,
++ ACPI_TABLE_CREATOR,
++ 0x20110725
++)
++{
++ #include
++ #include
++ #include
+
- #include
- DefinitionBlock(
- "dsdt.aml",
-@@ -14,9 +19,19 @@ DefinitionBlock(
- #include
- #include
-
-- Device (\_SB.PCI0) {
+ Device (\_SB.PCI0)
+ {
- #include
- #include
++ #include
++ #include
+ #include
+ }
+
@@ -587,9 +575,10 @@ index 967b652853..237500775f 100644
+ {
+ Name (_ADR, Zero)
+ }
- }
-
- #include
++ }
++
++ #include
++}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
new file mode 100644
index 0000000000..adb6a60324
@@ -869,21 +858,21 @@ index 0000000000..d89ed712d4
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
-index 6c3b077cc4..b41cca02a7 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+new file mode 100644
+index 0000000000..44c8578852
+--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
-@@ -1,11 +1,105 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
-
+@@ -0,0 +1,105 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
+#include
- #include
++#include
+#include
+#include
+#include
+#include "ec.h"
+#include "gpio.h"
-
--static void init_mainboard(void *chip_info)
++
+#define GPIO_GPU_RST GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON GPP_E23
+
@@ -895,7 +884,7 @@ index 6c3b077cc4..b41cca02a7 100644
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
-+ static const char *dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
++ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
+
+ int dgfx_vram_id;
+
@@ -971,28 +960,14 @@ index 6c3b077cc4..b41cca02a7 100644
+}
+
+static void mainboard_init(void *chip_info)
- {
++{
+ dump_ec_cfg(EC_CFG_PORT);
- }
-
- struct chip_operations mainboard_ops = {
-- .init = init_mainboard,
++}
++
++struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+ .init = mainboard_init,
- };
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c
-deleted file mode 100644
-index 59a62f484e..0000000000
---- a/src/mainboard/lenovo/sklkbl_thinkpad/romstage.c
-+++ /dev/null
-@@ -1,7 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--
--#include
--
--void mainboard_memory_init_params(FSPM_UPD *mupd)
--{
--}
++};
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
@@ -1386,31 +1361,13 @@ index 0000000000..5252a402f9
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
new file mode 100644
-index 0000000000..4b68ec3f49
+index 0000000000..bf66bd3a69
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-@@ -0,0 +1,124 @@
+@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
-+ # IGD Displays
-+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
-+
-+ register "panel_cfg" = "{
-+ .up_delay_ms = 200,
-+ .down_delay_ms = 50,
-+ .cycle_delay_ms = 600,
-+ .backlight_on_delay_ms = 1,
-+ .backlight_off_delay_ms = 200,
-+ .backlight_pwm_hz = 200,
-+ }"
-+
-+ # Power
-+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
-+ register "PmConfigSlpS4MinAssert" = "1" # 1s
-+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
-+ register "PmConfigSlpAMinAssert" = "3" # 2s
-+
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
@@ -1434,12 +1391,9 @@ index 0000000000..4b68ec3f49
+ end
+
+ device ref sata on
-+ # SATA_0 - NC
-+ # SATA_1A - NC
-+ # SATA_1B - NC
-+ # SATA_2 - SATA caddy
-+ register "SataPortsEnable[3]" = "1"
-+ register "SataPortsDevSlp[3]" = "1"
++ # SATA_2 - JHDD1 SATA SSD
++ register "SataPortsEnable[2]" = "1"
++ register "SataPortsDevSlp[2]" = "1"
+ end
+
+ # PCIe controller 1 - 1x4
@@ -1877,7 +1831,7 @@ index 0000000000..b1d96c5a76
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
new file mode 100644
-index 0000000000..085abebbcb
+index 0000000000..001e934b3a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
@@ -0,0 +1,44 @@
@@ -1915,7 +1869,7 @@ index 0000000000..085abebbcb
+ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
+ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
-+ snprintf(spd_name, sizeof spd_name, "spd_%d.bin", spd_idx);
++ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size);
+
+ /* Get SPD for memory slot (CH B) */
@@ -1927,31 +1881,13 @@ index 0000000000..085abebbcb
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
new file mode 100644
-index 0000000000..5f1c38bc03
+index 0000000000..d4afca20c4
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-@@ -0,0 +1,124 @@
+@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
-+ # IGD Displays
-+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
-+
-+ register "panel_cfg" = "{
-+ .up_delay_ms = 200,
-+ .down_delay_ms = 50,
-+ .cycle_delay_ms = 600,
-+ .backlight_on_delay_ms = 1,
-+ .backlight_off_delay_ms = 200,
-+ .backlight_pwm_hz = 200,
-+ }"
-+
-+ # Power
-+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
-+ register "PmConfigSlpS4MinAssert" = "1" # 1s
-+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
-+ register "PmConfigSlpAMinAssert" = "3" # 2s
-+
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
@@ -1975,12 +1911,9 @@ index 0000000000..5f1c38bc03
+ end
+
+ device ref sata on
-+ # SATA_0 - NC
-+ # SATA_1A - NC
-+ # SATA_1B - NC
-+ # SATA_2 - M.2 2280 SATA
-+ register "SataPortsEnable[3]" = "1"
-+ register "SataPortsDevSlp[3]" = "1"
++ # SATA_2 - Main M.2 SATA SSD
++ register "SataPortsEnable[2]" = "1"
++ register "SataPortsDevSlp[2]" = "1"
+ end
+
+ # PCIe controller 1 - 1x2+2x1
@@ -2055,7 +1988,7 @@ index 0000000000..5f1c38bc03
+ end
+ end
+end
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_0.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
new file mode 100644
index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e
GIT binary patch
@@ -2066,7 +1999,7 @@ YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_1.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
new file mode 100644
index 0000000000000000000000000000000000000000..df0f6e58b79286a4aeb690c5027adf7a1f5f668b
GIT binary patch
@@ -2077,7 +2010,7 @@ Yx&j>hH(SqvWezd%<4`dwOs5b40B_I==>Px#
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_10.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
new file mode 100644
index 0000000000000000000000000000000000000000..24f0d8992bc5244c62488da9633e4885f52f3e22
GIT binary patch
@@ -2089,7 +2022,7 @@ PvjPw>z-1}5hGzN!nb#F$
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_11.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
new file mode 100644
index 0000000000000000000000000000000000000000..59b6b9e78263c42aae367ab7d4a784d888f30efe
GIT binary patch
@@ -2101,7 +2034,7 @@ YZDQ=?WT@*Lg7pDLK
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_14.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a2a64a5e1adada3fc00b2e4edc60c77e610881a9
GIT binary patch
@@ -2137,7 +2070,7 @@ GCj$V){1T)9
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_15.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a2a64a5e1adada3fc00b2e4edc60c77e610881a9
GIT binary patch
@@ -2149,7 +2082,7 @@ GCj$V){1T)9
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_16.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
GIT binary patch
@@ -2159,7 +2092,7 @@ NcmZQz7zHCa1ONg600961
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_17.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
new file mode 100644
index 0000000000000000000000000000000000000000..5f23e86606094d3e5d2011db902ebd4a500bbffa
GIT binary patch
@@ -2171,7 +2104,7 @@ V%v%8n7#i08$7jJ^e3JB$0{}ZV7fApB
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_18.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
new file mode 100644
index 0000000000000000000000000000000000000000..05633943eb5af166da66a2e1f4e74948f75782fb
GIT binary patch
@@ -2183,7 +2116,7 @@ Vn70BDFf^?FkI#a;_$28g2LNS*7)Ag9
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_19.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
new file mode 100644
index 0000000000000000000000000000000000000000..857da9c9828cdac842329f6cef4539283777268b
GIT binary patch
@@ -2195,7 +2128,7 @@ GP6hy+m=i1j
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_2.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
new file mode 100644
index 0000000000000000000000000000000000000000..b5b14cf2dfa06ae183b0379da4dc825129e1589f
GIT binary patch
@@ -2206,7 +2139,7 @@ XT>%b$v*cE=%%S%6I8=-Z(%b$+tzbnnL|62aHtp+rc($20QGqazW@LL
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_4.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
new file mode 100644
index 0000000000000000000000000000000000000000..829f149547bc24859646c33d5926938d7a1b90cb
GIT binary patch
@@ -2238,7 +2171,7 @@ XT>%b$o8(ro%%OI594bbI=@bG0z{d&v
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_5.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
GIT binary patch
@@ -2248,7 +2181,7 @@ NcmZQz7zHCa1ONg600961
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_6.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
new file mode 100644
index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
GIT binary patch
@@ -2258,7 +2191,7 @@ NcmZQz7zHCa1ONg600961
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_7.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
new file mode 100644
index 0000000000000000000000000000000000000000..940f1e3cd8e5bd9ea32a82a14edcdcbc8132d8c7
GIT binary patch
@@ -2270,7 +2203,7 @@ E020*^DF6Tf
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_8.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
new file mode 100644
index 0000000000000000000000000000000000000000..30c84410d417ef7afa8705c93cdb64a9f4e915a0
GIT binary patch
@@ -2282,7 +2215,7 @@ H2PXpn6CD!Q
literal 0
HcmV?d00001
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd_9.bin
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
new file mode 100644
index 0000000000000000000000000000000000000000..7facef55b93fe1f67411c00bab84862769461f63
GIT binary patch
diff --git a/config/coreboot/next/patches/0005-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
similarity index 99%
rename from config/coreboot/next/patches/0005-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
rename to config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
index e490a807..eb9263b9 100644
--- a/config/coreboot/next/patches/0005-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
+++ b/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
@@ -1,7 +1,7 @@
-From 534d696a570a50057153669247933ec1a4a2480f Mon Sep 17 00:00:00 2001
+From 75cc0ea09234064318046624845b0afc5afb0ce5 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 5/8] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
+Subject: [PATCH 29/37] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
Signed-off-by: Nicholas Chin
diff --git a/config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch b/config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch
deleted file mode 100644
index a1cf9b75..00000000
--- a/config/coreboot/default/patches/0030-haswell-NRI-Initialise-MPLL.patch
+++ /dev/null
@@ -1,348 +0,0 @@
-From 0966980e52286985fcd0fac6325bdd99f35ebcb8 Mon Sep 17 00:00:00 2001
-From: Angel Pons