8!uus22Br_GkCD$Q)pf!
+zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
+new file mode 100644
+index 0000000000..b50f8da0b5
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
+@@ -0,0 +1,138 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++ .gpio0 = GPIO_MODE_NATIVE,
++ .gpio1 = GPIO_MODE_GPIO,
++ .gpio2 = GPIO_MODE_GPIO,
++ .gpio3 = GPIO_MODE_GPIO,
++ .gpio4 = GPIO_MODE_GPIO,
++ .gpio5 = GPIO_MODE_GPIO,
++ .gpio6 = GPIO_MODE_GPIO,
++ .gpio7 = GPIO_MODE_GPIO,
++ .gpio8 = GPIO_MODE_GPIO,
++ .gpio9 = GPIO_MODE_NATIVE,
++ .gpio10 = GPIO_MODE_NATIVE,
++ .gpio11 = GPIO_MODE_NATIVE,
++ .gpio12 = GPIO_MODE_NATIVE,
++ .gpio13 = GPIO_MODE_GPIO,
++ .gpio14 = GPIO_MODE_GPIO,
++ .gpio15 = GPIO_MODE_NATIVE,
++ .gpio16 = GPIO_MODE_NATIVE,
++ .gpio17 = GPIO_MODE_GPIO,
++ .gpio18 = GPIO_MODE_GPIO,
++ .gpio19 = GPIO_MODE_GPIO,
++ .gpio20 = GPIO_MODE_GPIO,
++ .gpio21 = GPIO_MODE_GPIO,
++ .gpio22 = GPIO_MODE_GPIO,
++ .gpio23 = GPIO_MODE_NATIVE,
++ .gpio24 = GPIO_MODE_GPIO,
++ .gpio25 = GPIO_MODE_NATIVE,
++ .gpio26 = GPIO_MODE_NATIVE,
++ .gpio27 = GPIO_MODE_GPIO,
++ .gpio28 = GPIO_MODE_GPIO,
++ .gpio29 = GPIO_MODE_NATIVE,
++ .gpio30 = GPIO_MODE_NATIVE,
++ .gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++ .gpio1 = GPIO_DIR_INPUT,
++ .gpio2 = GPIO_DIR_INPUT,
++ .gpio3 = GPIO_DIR_INPUT,
++ .gpio4 = GPIO_DIR_INPUT,
++ .gpio5 = GPIO_DIR_INPUT,
++ .gpio6 = GPIO_DIR_INPUT,
++ .gpio7 = GPIO_DIR_INPUT,
++ .gpio8 = GPIO_DIR_INPUT,
++ .gpio13 = GPIO_DIR_INPUT,
++ .gpio14 = GPIO_DIR_INPUT,
++ .gpio17 = GPIO_DIR_INPUT,
++ .gpio18 = GPIO_DIR_INPUT,
++ .gpio19 = GPIO_DIR_INPUT,
++ .gpio20 = GPIO_DIR_INPUT,
++ .gpio21 = GPIO_DIR_INPUT,
++ .gpio22 = GPIO_DIR_INPUT,
++ .gpio24 = GPIO_DIR_INPUT,
++ .gpio27 = GPIO_DIR_INPUT,
++ .gpio28 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++ .gpio1 = GPIO_INVERT,
++ .gpio7 = GPIO_INVERT,
++ .gpio8 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++ .gpio32 = GPIO_MODE_NATIVE,
++ .gpio33 = GPIO_MODE_GPIO,
++ .gpio34 = GPIO_MODE_GPIO,
++ .gpio35 = GPIO_MODE_NATIVE,
++ .gpio36 = GPIO_MODE_GPIO,
++ .gpio37 = GPIO_MODE_GPIO,
++ .gpio38 = GPIO_MODE_GPIO,
++ .gpio39 = GPIO_MODE_GPIO,
++ .gpio40 = GPIO_MODE_NATIVE,
++ .gpio41 = GPIO_MODE_NATIVE,
++ .gpio42 = GPIO_MODE_NATIVE,
++ .gpio43 = GPIO_MODE_NATIVE,
++ .gpio44 = GPIO_MODE_NATIVE,
++ .gpio45 = GPIO_MODE_NATIVE,
++ .gpio46 = GPIO_MODE_NATIVE,
++ .gpio47 = GPIO_MODE_NATIVE,
++ .gpio48 = GPIO_MODE_GPIO,
++ .gpio49 = GPIO_MODE_GPIO,
++ .gpio50 = GPIO_MODE_NATIVE,
++ .gpio51 = GPIO_MODE_NATIVE,
++ .gpio52 = GPIO_MODE_GPIO,
++ .gpio53 = GPIO_MODE_GPIO,
++ .gpio54 = GPIO_MODE_NATIVE,
++ .gpio55 = GPIO_MODE_NATIVE,
++ .gpio56 = GPIO_MODE_GPIO,
++ .gpio57 = GPIO_MODE_GPIO,
++ .gpio58 = GPIO_MODE_NATIVE,
++ .gpio59 = GPIO_MODE_NATIVE,
++ .gpio60 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++ .gpio33 = GPIO_DIR_INPUT,
++ .gpio34 = GPIO_DIR_INPUT,
++ .gpio36 = GPIO_DIR_INPUT,
++ .gpio37 = GPIO_DIR_INPUT,
++ .gpio38 = GPIO_DIR_INPUT,
++ .gpio39 = GPIO_DIR_INPUT,
++ .gpio48 = GPIO_DIR_INPUT,
++ .gpio49 = GPIO_DIR_INPUT,
++ .gpio52 = GPIO_DIR_INPUT,
++ .gpio53 = GPIO_DIR_INPUT,
++ .gpio56 = GPIO_DIR_INPUT,
++ .gpio57 = GPIO_DIR_INPUT,
++ .gpio60 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++ .set1 = {
++ .mode = &pch_gpio_set1_mode,
++ .direction = &pch_gpio_set1_direction,
++ .level = &pch_gpio_set1_level,
++ .blink = &pch_gpio_set1_blink,
++ .invert = &pch_gpio_set1_invert,
++ },
++ .set2 = {
++ .mode = &pch_gpio_set2_mode,
++ .direction = &pch_gpio_set2_direction,
++ .level = &pch_gpio_set2_level,
++ },
++};
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
+new file mode 100644
+index 0000000000..a9948a93dd
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ /* coreboot specific header */
++ 0x111d76b2, /* IDT 92HD71B7X */
++ 0x1028024d, /* Subsystem ID */
++ 13, /* Number of entries */
++
++ /* Pin Widget Verb Table */
++
++ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
++ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
++ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
++ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
++ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
++ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
++ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
++ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
++ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
++};
++
++const u32 pc_beep_verbs[] = {
++ 0x00170500, /* power up codec */
++ 0x00d70500, /* power up speakers */
++ 0x00d70102, /* select mixer (input 0x2) for speakers */
++ 0x00d70740, /* enable speakers output */
++ 0x02770720, /* enable beep input */
++ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
++ 0x00d37000, /* unmute speakers */
++};
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
+new file mode 100644
+index 0000000000..20dfa245fb
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
+@@ -0,0 +1,10 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++chip northbridge/intel/gm45
++ device domain 0 on
++ subsystemid 0x1028 0x024d inherit
++ chip southbridge/intel/i82801ix
++ device pci 1c.2 off end # PCIe Port #3
++ end
++ end
++end
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
deleted file mode 100644
index e38f243d..00000000
--- a/config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
+++ /dev/null
@@ -1,820 +0,0 @@
-From db1cb588b64f17c7ed08201bf1e09ab5393e4b04 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 22/22] mb/dell: Add Latitude E6430 (Ivy Bridge)
-
-Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested.
-This is based on the autoport output with some manual tweaks. The flash
-is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard.
-It can also be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections. [1] The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-Working:
-- Libgfxinit
-- USB EHCI debug (left side usb port is HCD index 2, middle port on the
- right side is HCD index 1)
-- Keyboard
-- Touchpad/trackpoint
-- ExpressCard
-- Audio
-- Ethernet
-- SD card reader
-- mPCIe WiFi
-- SeaBIOS 1.16.2
-- edk2 (MrChromebox' fork, uefipayload_202306)
-- Internal flashing
-
-Not working:
-- S3 suspend: It seems like the EC also controls the DRAM reset gate so
- there may be a command that needs to be implemented for this
-- Physical Wireless switch
-- Battery reporting
-- Brightness hotkeys
-
-Unknown/untested:
-- Dock
-- eSATA
-- TPM
-- dGPU on non-UMA model
-
-[1] https://github.com/nic3-14159/e6400-flash-unlock
-
-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e6430/Kconfig | 36 ++++
- src/mainboard/dell/e6430/Kconfig.name | 2 +
- src/mainboard/dell/e6430/Makefile.inc | 6 +
- src/mainboard/dell/e6430/acpi/ec.asl | 9 +
- src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
- src/mainboard/dell/e6430/acpi/superio.asl | 3 +
- src/mainboard/dell/e6430/acpi_tables.c | 16 ++
- src/mainboard/dell/e6430/board_info.txt | 6 +
- src/mainboard/dell/e6430/cmos.default | 9 +
- src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
- src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++
- src/mainboard/dell/e6430/dsdt.asl | 30 ++++
- src/mainboard/dell/e6430/early_init.c | 38 ++++
- src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
- src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
- src/mainboard/dell/e6430/hda_verb.c | 33 ++++
- src/mainboard/dell/e6430/mainboard.c | 21 +++
- 18 files changed, 589 insertions(+)
- create mode 100644 src/mainboard/dell/e6430/Kconfig
- create mode 100644 src/mainboard/dell/e6430/Kconfig.name
- create mode 100644 src/mainboard/dell/e6430/Makefile.inc
- create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6430/board_info.txt
- create mode 100644 src/mainboard/dell/e6430/cmos.default
- create mode 100644 src/mainboard/dell/e6430/cmos.layout
- create mode 100644 src/mainboard/dell/e6430/data.vbt
- create mode 100644 src/mainboard/dell/e6430/devicetree.cb
- create mode 100644 src/mainboard/dell/e6430/dsdt.asl
- create mode 100644 src/mainboard/dell/e6430/early_init.c
- create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6430/gpio.c
- create mode 100644 src/mainboard/dell/e6430/hda_verb.c
- create mode 100644 src/mainboard/dell/e6430/mainboard.c
-
-diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
-new file mode 100644
-index 0000000000..3178d12aff
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig
-@@ -0,0 +1,36 @@
-+if BOARD_DELL_LATITUDE_E6430
-+
-+config BOARD_SPECIFIC_OPTIONS
-+ def_bool y
-+ select BOARD_ROMSIZE_KB_12288
-+ select EC_ACPI
-+ select EC_DELL_MEC5035
-+ select GFX_GMA_PANEL_1_ON_LVDS
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select HAVE_CMOS_DEFAULT
-+ select HAVE_OPTION_TABLE
-+ select INTEL_INT15
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+ select SERIRQ_CONTINUOUS_MODE
-+ select SOUTHBRIDGE_INTEL_C216
-+ select SYSTEM_TYPE_LAPTOP
-+ select USE_NATIVE_RAMINIT
-+
-+config MAINBOARD_DIR
-+ default "dell/e6430"
-+
-+config MAINBOARD_PART_NUMBER
-+ default "Latitude E6430"
-+
-+config VGA_BIOS_ID
-+ default "8086,0166"
-+
-+config DRAM_RESET_GATE_GPIO
-+ default 60
-+
-+config USBDEBUG_HCD_INDEX
-+ default 2
-+endif
-diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
-new file mode 100644
-index 0000000000..f866b03585
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6430
-+ bool "Latitude E6430"
-diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+ Name (_HID, EISAID("PNP0C09"))
-+ Name (_UID, 0)
-+ Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+ /* FIXME: EC support */
-+ Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+ /* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+/* FIXME: check this function. */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+ /* The lid is open by default. */
-+ gnvs->lids = 1;
-+
-+ /* Temperature at which OS will shutdown */
-+ gnvs->tcrt = 100;
-+ /* Temperature at which OS will throttle CPU */
-+ gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
-new file mode 100644
-index 0000000000..4601a4aaba
---- /dev/null
-+++ b/src/mainboard/dell/e6430/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
-new file mode 100644
-index 0000000000..2a5b30f2b7
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Normal
-diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
-new file mode 100644
-index 0000000000..e85ea4c661
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0 120 r 0 reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384 1 e 4 boot_option
-+388 4 h 0 reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395 4 e 6 debug_level
-+
-+#400 8 r 0 reserved for century byte
-+
-+# coreboot config options: southbridge
-+408 1 e 1 nmi
-+409 2 e 7 power_on_after_fail
-+411 1 e 9 sata_mode
-+
-+# coreboot config options: EC
-+412 1 e 1 bluetooth
-+413 1 e 1 wwan
-+415 1 e 1 wlan
-+
-+# coreboot config options: ME
-+424 1 e 14 me_state
-+425 2 h 0 me_state_prev
-+
-+# coreboot config options: northbridge
-+432 3 e 11 gfx_uma_size
-+435 2 e 12 hybrid_graphics_mode
-+440 8 h 0 volume
-+
-+# VBOOT
-+448 128 r 0 vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896 32 r 0 mrc_scrambler_seed
-+928 32 r 0 mrc_scrambler_seed_s3
-+960 16 r 0 mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984 16 h 0 check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value text
-+1 0 Disable
-+1 1 Enable
-+2 0 Enable
-+2 1 Disable
-+4 0 Fallback
-+4 1 Normal
-+6 0 Emergency
-+6 1 Alert
-+6 2 Critical
-+6 3 Error
-+6 4 Warning
-+6 5 Notice
-+6 6 Info
-+6 7 Debug
-+6 8 Spew
-+7 0 Disable
-+7 1 Enable
-+7 2 Keep
-+9 0 AHCI
-+9 1 Compatible
-+11 0 32M
-+11 1 64M
-+11 2 96M
-+11 3 128M
-+11 4 160M
-+11 5 192M
-+11 6 224M
-+14 0 Normal
-+14 1 Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
-GIT binary patch
-literal 6144
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-zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
-zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
-zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
-zIdrG4zSq6a*B6
-zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu
-zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T
-zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz
-z)}lBfx8o(*hgal&)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ
-zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBXmV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F
-zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P
-z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J
-zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r
-zYCPKK+S_PdhGTnR+18g0GR_nHOE`gieuP-A>69j*W0
-z>h~9>kwTD6>nL4
-zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sGp0XopwxoS
-z0g?6TPW!DCql9>N1GN_$T-UVr&HErC5juykd~Sxy
-zq!PK|<^jJ^DuQ9)7pt`
-z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
-ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
-z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
-zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{
-z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
-qS
-+
-+DefinitionBlock(
-+ "dsdt.aml",
-+ "DSDT",
-+ ACPI_DSDT_REV_2,
-+ OEM_ID,
-+ ACPI_TABLE_CREATOR,
-+ 0x20141018 /* OEM revision */
-+)
-+{
-+ #include
-+ #include "acpi/platform.asl"
-+ #include
-+ #include
-+ #include
-+ #include
-+
-+ Device (\_SB.PCI0)
-+ {
-+ #include
-+ #include
-+ #include
-+ }
-+}
-diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
-new file mode 100644
-index 0000000000..7944157f59
---- /dev/null
-+++ b/src/mainboard/dell/e6430/early_init.c
-@@ -0,0 +1,38 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+ { 1, 1, 0 },
-+ { 1, 1, 0 },
-+ { 1, 1, 1 },
-+ { 1, 1, 1 },
-+ { 1, 0, 2 },
-+ { 1, 1, 2 },
-+ { 1, 1, 3 },
-+ { 1, 1, 3 },
-+ { 1, 1, 4 },
-+ { 1, 1, 4 },
-+ { 1, 1, 5 },
-+ { 1, 1, 5 },
-+ { 1, 2, 6 },
-+ { 1, 2, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-+ mec5035_early_init();
-+}
-+
-+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-+{
-+ read_spd(&spd[0], 0x50, id_only);
-+ read_spd(&spd[2], 0x52, id_only);
-+}
-diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
-new file mode 100644
-index 0000000000..1310830c8e
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+ ports : constant Port_List :=
-+ (
-+ HDMI1, -- mainboard HDMI
-+ DP2, -- dock DP
-+ DP3, -- dock DP
-+ Analog, --mainboard VGA
-+ LVDS,
-+ others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+ .gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
-new file mode 100644
-index 0000000000..56ada95c58
---- /dev/null
-+++ b/src/mainboard/dell/e6430/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
-+ 0x10280534, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x10280534),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
---- /dev/null
-+++ b/src/mainboard/dell/e6430/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+ /* FIXME: fix these values. */
-+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+ GMA_INT15_PANEL_FIT_DEFAULT,
-+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+ .enable_dev = mainboard_enable,
-+};
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
new file mode 100644
index 00000000..bbdce358
--- /dev/null
+++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
@@ -0,0 +1,70 @@
+From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Fri, 3 May 2024 16:31:12 -0600
+Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
+
+Integrate the previously added mec5035_smi_sleep() function into
+mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
+The E6400 does not require the EC command to sucessfully suspend and
+resume from S3, though sending it does enable the breathing effect on
+the power LED while in S3. Without it, all LEDs turn off during S3.
+
+Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/e7240/smihandler.c | 9 +++++++++
+ src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
+ src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
+ 3 files changed, 27 insertions(+)
+ create mode 100644 src/mainboard/dell/e7240/smihandler.c
+ create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
+
+diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/e7240/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
new file mode 100644
index 00000000..ab01c935
--- /dev/null
+++ b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
@@ -0,0 +1,92 @@
+From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Tue, 18 Jun 2024 21:31:08 -0600
+Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
+
+If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
+power button results in the EC powering off the system without letting
+the OS cleanly shutting itself down. This command and argument tells the
+EC to route power button events to the host so that it can determine
+what to do.
+
+The EC command was identified from the ec/google/wilco code, which is
+used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
+Kconfig help text, those ECs run a modified version of Dell's typical
+Latitude EC firmware, so it is likely that the two firmware
+implementations use similar commands. Examining LPC traffic between the
+host and the EC on the Latitude E6400 did reveal that the same command
+was being sent by the vendor firmware to the EC, but this does not
+confirm that it has the same meaning as the command from the Wilco code.
+Sending the command using inb/outb calls in a userspace C program while
+running coreboot without this patch did allow subsequent power button
+events to be handled by the host, confirming that the command was indeed
+the same.
+
+Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
+Signed-off-by: Nicholas Chin
+---
+ src/ec/dell/mec5035/mec5035.c | 8 ++++++++
+ src/ec/dell/mec5035/mec5035.h | 7 +++++++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 85c2ab0140..bdae929a27 100644
+--- a/src/ec/dell/mec5035/mec5035.c
++++ b/src/ec/dell/mec5035/mec5035.c
+@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
+ ec_command(CMD_RADIO_CTRL);
+ }
+
++void mec5035_power_button_route(enum ec_power_button_route target)
++{
++ u8 buf = (u8)target;
++ write_mailbox_regs(&buf, 2, 1);
++ ec_command(CMD_POWER_BUTTON_TO_HOST);
++}
++
+ void mec5035_change_wake(u8 source, enum ec_wake_change change)
+ {
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
+@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
+ /* Unconditionally use this argument for now as this setting
+ is probably the most sensible default out of the 3 choices. */
+ mec5035_mouse_touchpad(TP_PS2_MOUSE);
++ mec5035_power_button_route(HOST);
+
+ pc_keyboard_init(NO_AUX_DEVICE);
+
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index 8d4fded28b..51422598c4 100644
+--- a/src/ec/dell/mec5035/mec5035.h
++++ b/src/ec/dell/mec5035/mec5035.h
+@@ -11,6 +11,7 @@
+ enum mec5035_cmd {
+ CMD_MOUSE_TP = 0x1a,
+ CMD_RADIO_CTRL = 0x2b,
++ CMD_POWER_BUTTON_TO_HOST = 0x3e,
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
+ CMD_SLEEP_ENABLE = 0x64,
+ CMD_CPU_OK = 0xc2,
+@@ -36,6 +37,11 @@ enum ec_radio_state {
+ RADIO_ON
+ };
+
++enum ec_power_button_route {
++ EC = 0,
++ HOST
++};
++
+ #define ACPI_WAKEUP_NUM_ARGS 4
+ enum ec_wake_change {
+ WAKE_OFF = 0,
+@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
+ void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
++void mec5035_power_button_route(enum ec_power_button_route target);
+ void mec5035_change_wake(u8 source, enum ec_wake_change change);
+ void mec5035_sleep_enable(void);
+
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
new file mode 100644
index 00000000..c557e9d7
--- /dev/null
+++ b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
@@ -0,0 +1,31 @@
+From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Tue, 31 Dec 2024 14:42:24 +0000
+Subject: [PATCH 24/37] Disable compression on refcode insertion
+
+Compression is not reliably reproducible. In an lbmk release
+context, this means we cannot rely on vendorfile insertion.
+
+Therefore, use uncompressed refcode.
+
+Signed-off-by: Leah Rowe
+---
+ Makefile.mk | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.mk b/Makefile.mk
+index 3969bfbd05..15346569f8 100644
+--- a/Makefile.mk
++++ b/Makefile.mk
+@@ -1392,7 +1392,7 @@ endif
+ cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
+ $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
+ $(CONFIG_CBFS_PREFIX)/refcode-type := stage
+-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
++$(CONFIG_CBFS_PREFIX)/refcode-compression := none
+
+ cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
+ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch
deleted file mode 100644
index 2c4c9e5f..00000000
--- a/config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 1/1] don't use github for the acpica download
-
-i have the tarball from a previous download, and i placed
-it on libreboot rsync, which then got mirrored to princeton.
-
-today, github's ssl cert was b0rking the hell out and i really
-really wanted to finish a build, and didn't want to wait for
-github to fix their httpd.
-
-so i'm now hosting this specific acpica tarball on rsync.
-
-this patch makes that URL be used, instead of the github one.
-
-that's the 2nd time i've had to patch coreboot's acpica download!
-
-Signed-off-by: Leah Rowe
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index ebc9fcb49a..a857110b4b 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
- MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
- GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
- BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
--IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
-+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
- # CLANG toolchain archive locations
- LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
- CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch b/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
deleted file mode 100644
index cca8901f..00000000
--- a/config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
+++ /dev/null
@@ -1,341 +0,0 @@
-From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 29 Oct 2023 01:18:50 +0000
-Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
- value"
-
-This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
-
-NOTE:
-
-this is done instead of merging:
-https://review.coreboot.org/c/coreboot/+/78623
-
-which is still under review for now
-
-the patch i'm reverting is this one:
-https://review.coreboot.org/c/coreboot/+/78270
-
-this was actually only merged the day before i
-updated coreboot revs in lbmk to the 12 october rev,
-so there's no harm in quickly reverting this for now
-
-however, later on, we will rely on the other patch
----
- src/Kconfig | 3 ++-
- src/cpu/qemu-x86/Kconfig | 3 +++
- src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
- src/northbridge/amd/pi/Kconfig | 4 ++++
- src/soc/amd/picasso/Kconfig | 4 ++++
- src/soc/amd/stoneyridge/Kconfig | 4 ++++
- src/soc/cavium/cn81xx/Kconfig | 3 +++
- src/soc/intel/alderlake/Kconfig | 5 +++++
- src/soc/intel/apollolake/Kconfig | 4 ++++
- src/soc/intel/cannonlake/Kconfig | 4 ++++
- src/soc/intel/elkhartlake/Kconfig | 4 ++++
- src/soc/intel/jasperlake/Kconfig | 4 ++++
- src/soc/intel/meteorlake/Kconfig | 5 +++++
- src/soc/intel/skylake/Kconfig | 4 ++++
- src/soc/intel/tigerlake/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
- src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
- src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
- 20 files changed, 77 insertions(+), 1 deletion(-)
-
-diff --git a/src/Kconfig b/src/Kconfig
-index ae8024089e..1549719dd0 100644
---- a/src/Kconfig
-+++ b/src/Kconfig
-@@ -751,7 +751,8 @@ config RTC
-
- config HEAP_SIZE
- hex
-- default 0x100000
-+ default 0x100000 if FLATTENED_DEVICE_TREE
-+ default 0x4000
-
- config STACK_SIZE
- hex
-diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
-index 0fa999e1ac..f3e2c4cea9 100644
---- a/src/cpu/qemu-x86/Kconfig
-+++ b/src/cpu/qemu-x86/Kconfig
-@@ -35,4 +35,7 @@ config MAX_CPUS
- default 32 if SMM_TSEG
- default 4
-
-+config HEAP_SIZE
-+ default 0x8000
-+
- endif
-diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
-index 7bc3b0bcbb..7f9300f2a7 100644
---- a/src/mainboard/sifive/hifive-unleashed/Kconfig
-+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
-@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
- select FLATTENED_DEVICE_TREE
- select SPI_SDCARD
-
-+config HEAP_SIZE
-+ default 0x10000
-+
- config MAINBOARD_DIR
- default "sifive/hifive-unleashed"
-
-diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
-index 4ffe82a15f..4518db149b 100644
---- a/src/northbridge/amd/pi/Kconfig
-+++ b/src/northbridge/amd/pi/Kconfig
-@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
- hex
- default 0x200000
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- endif # NORTHBRIDGE_AMD_PI
-diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
-index c33f287067..796fe4eb13 100644
---- a/src/soc/amd/picasso/Kconfig
-+++ b/src/soc/amd/picasso/Kconfig
-@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
- bool
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- config SERIRQ_CONTINUOUS_MODE
- bool
- default n
-diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
-index 6ff135e6a8..9af7455bae 100644
---- a/src/soc/amd/stoneyridge/Kconfig
-+++ b/src/soc/amd/stoneyridge/Kconfig
-@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
- bool
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0xc0000
-+
- config EHCI_BAR
- hex
- default 0xfef00000
-diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
-index 77ca97202b..368581f8f1 100644
---- a/src/soc/cavium/cn81xx/Kconfig
-+++ b/src/soc/cavium/cn81xx/Kconfig
-@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
- int
- default 1
-
-+config HEAP_SIZE
-+ default 0x10000
-+
- config STACK_SIZE
- default 0x2000
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 4b960c1d22..82ec8f263e 100644
---- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -215,6 +215,11 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000 if BMP_LOGO
-+ default 0x10000
-+
- config GFX_GMA_DEFAULT_MMIO
- default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
-
-diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
-index 78ec2987ce..bce935d800 100644
---- a/src/soc/intel/apollolake/Kconfig
-+++ b/src/soc/intel/apollolake/Kconfig
-@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
- help
- Name of file to store in the IFWI region.
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 6
-diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
-index a42a3c365b..80237f9810 100644
---- a/src/soc/intel/cannonlake/Kconfig
-+++ b/src/soc/intel/cannonlake/Kconfig
-@@ -160,6 +160,10 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config NHLT_DMIC_1CH_16B
- bool
- depends on ACPI_NHLT
-diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
-index 3361c0ddb9..7f1c767379 100644
---- a/src/soc/intel/elkhartlake/Kconfig
-+++ b/src/soc/intel/elkhartlake/Kconfig
-@@ -104,6 +104,10 @@ config IED_REGION_SIZE
- hex
- default 0x0
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 7
-diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
-index 3d84991e09..ff5def3263 100644
---- a/src/soc/intel/jasperlake/Kconfig
-+++ b/src/soc/intel/jasperlake/Kconfig
-@@ -106,6 +106,10 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- config MAX_ROOT_PORTS
- int
- default 8
-diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
-index 590e8b80e1..48030a1911 100644
---- a/src/soc/intel/meteorlake/Kconfig
-+++ b/src/soc/intel/meteorlake/Kconfig
-@@ -197,6 +197,11 @@ config IED_REGION_SIZE
- hex
- default 0x400000
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000 if BMP_LOGO
-+ default 0x10000
-+
- # Intel recommends reserving the PCIe TBT root port resources as below:
- # - 42 buses
- # - 194 MiB Non-prefetchable memory
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index e0df501460..d6a11363ee 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
- help
- If you set this option to n, will not use native SD controller.
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config IED_REGION_SIZE
- hex
- default 0x400000
-diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
-index c07a0d8365..0a4b7bfdb8 100644
---- a/src/soc/intel/tigerlake/Kconfig
-+++ b/src/soc/intel/tigerlake/Kconfig
-@@ -152,6 +152,10 @@ config IED_REGION_SIZE
- config INTEL_TME
- default n
-
-+config HEAP_SIZE
-+ hex
-+ default 0x10000
-+
- config MAX_ROOT_PORTS
- int
- default 24 if SOC_INTEL_TIGERLAKE_PCH_H
-diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
-index e63bee5451..63ced01067 100644
---- a/src/soc/intel/xeon_sp/Kconfig
-+++ b/src/soc/intel/xeon_sp/Kconfig
-@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
- config ECAM_MMCONF_BUS_NUMBER
- default 256
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config HPET_MIN_TICKS
- hex
- default 0x80
-diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
-index ac166c3038..f54f7716b6 100644
---- a/src/soc/intel/xeon_sp/cpx/Kconfig
-+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
-@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x7C00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config STACK_SIZE
- hex
- default 0x4000
-diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
-index 5d843878e1..c2c3d4e2e8 100644
---- a/src/soc/intel/xeon_sp/skx/Kconfig
-+++ b/src/soc/intel/xeon_sp/skx/Kconfig
-@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x7C00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config IED_REGION_SIZE
- hex
- default 0x400000
-diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
-index 43b87ade14..b1c4c783b7 100644
---- a/src/soc/intel/xeon_sp/spr/Kconfig
-+++ b/src/soc/intel/xeon_sp/spr/Kconfig
-@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x8c00
-
-+config HEAP_SIZE
-+ hex
-+ default 0x80000
-+
- config STACK_SIZE
- hex
- default 0x4000
-diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
-index 0ce92731c0..0eabb00752 100644
---- a/src/soc/qualcomm/ipq40xx/Kconfig
-+++ b/src/soc/qualcomm/ipq40xx/Kconfig
-@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
- help
- Path for utils to combine SBL_ELF and bootblock
-
-+config HEAP_SIZE
-+ hex
-+ default 0x8000
-+
- endif
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
new file mode 100644
index 00000000..696be518
--- /dev/null
+++ b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
@@ -0,0 +1,187 @@
+From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 21 Apr 2025 02:58:47 +0100
+Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
+
+Signed-off-by: Leah Rowe
+---
+ src/northbridge/intel/e7505/Kconfig | 9 +++++++++
+ src/northbridge/intel/gm45/Kconfig | 9 +++++++++
+ src/northbridge/intel/haswell/Kconfig | 9 +++++++++
+ src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
+ src/northbridge/intel/i945/Kconfig | 9 +++++++++
+ src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
+ src/northbridge/intel/pineview/Kconfig | 9 +++++++++
+ src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
+ src/northbridge/intel/x4x/Kconfig | 9 +++++++++
+ 9 files changed, 85 insertions(+)
+
+diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
+index 039a7396f8..ddcb986f10 100644
+--- a/src/northbridge/intel/e7505/Kconfig
++++ b/src/northbridge/intel/e7505/Kconfig
+@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
+ select NO_CBFS_MCACHE
+ select SMM_TSEG
+ select NEED_SMALL_2MB_PAGE_TABLES
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
+diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
+index fc5df8b11a..95e3644b73 100644
+--- a/src/northbridge/intel/gm45/Kconfig
++++ b/src/northbridge/intel/gm45/Kconfig
+@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
+index 6191cb6ccf..0f5b5c7241 100644
+--- a/src/northbridge/intel/haswell/Kconfig
++++ b/src/northbridge/intel/haswell/Kconfig
+@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
+
+ if NORTHBRIDGE_INTEL_HASWELL
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ config USE_NATIVE_RAMINIT
+ bool "[NOT COMPLETE] Use native raminit"
+ default n
+diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
+index dbb2d7436b..5e9418b6a9 100644
+--- a/src/northbridge/intel/i440bx/Kconfig
++++ b/src/northbridge/intel/i440bx/Kconfig
+@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
+ If your board has 4 DIMM slots, you must use select this option, in
+ your Kconfig file of the board. On boards with 3 DIMM slots,
+ do _not_ select this option.
++
++if NORTHBRIDGE_INTEL_I440BX
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
++endif
+diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
+index 32eff1a611..9479d75c07 100644
+--- a/src/northbridge/intel/i945/Kconfig
++++ b/src/northbridge/intel/i945/Kconfig
+@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
+index 2bafebf92e..16b81705bb 100644
+--- a/src/northbridge/intel/ironlake/Kconfig
++++ b/src/northbridge/intel/ironlake/Kconfig
+@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
+index 59cfcd5e0a..a3ad8d3425 100644
+--- a/src/northbridge/intel/pineview/Kconfig
++++ b/src/northbridge/intel/pineview/Kconfig
+@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
+ config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
+index 973eed8bbd..6387cf926d 100644
+--- a/src/northbridge/intel/sandybridge/Kconfig
++++ b/src/northbridge/intel/sandybridge/Kconfig
+@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
+ default 2 if IGD_DEFAULT_UMA_SIZE_96MB
+ default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
+index 6430319f6a..1803ef5733 100644
+--- a/src/northbridge/intel/x4x/Kconfig
++++ b/src/northbridge/intel/x4x/Kconfig
+@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch b/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch
deleted file mode 100644
index 8bca1b0a..00000000
--- a/config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001
-From: Denis 'GNUtoo' Carikli
-Date: Mon, 27 Mar 2017 22:05:16 +0200
-Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when
- waiting for heci
-
-Since until now, the code running on the management engine is:
-- Signed by its manufacturer
-- Proprietary software, without corresponding source code
-It can desirable to run the least ammount possible of such
-code, which is what me_cleaner[1] enables.
-
-It does it by removing partitions of the management engine
-firmwares, however when doing so, the HECI interface might
-not be present anymore.
-
-So it is desirable not to have the RAM initialisation code
-wait forever for the HECI interface to appear.
-
-[1] https://github.com/corna/me_cleaner/
-
-MERGENOTE: Adapted from this patch:
-https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html
-Author on this version of the patch set to same author as in the
-linked one, with same date set, but the commit message is modified
-to match the new code path. Patch author Denis Carikli, but this
-versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023.
-
-Signed-off-by: Leah Rowe
----
- src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
-diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
-index 572e5e7a76..3a68344d97 100644
---- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
-+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
-@@ -8,28 +8,30 @@
- #include
- #include
- #include
-+#include
-
- #define HECIDEV PCI_DEV(0, 0x16, 0)
-
--/* FIXME: add timeout. */
- static void wait_heci_ready(void)
- {
-- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
-- ;
-+ int i = 1000*1000;
-
-+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
-+ udelay(1);
- write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
- }
-
--/* FIXME: add timeout. */
- static void wait_heci_cb_avail(int len)
- {
-+ int i = 1000*1000;
-+
- union {
- struct mei_csr csr;
- u32 raw;
- } csr;
-
-- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
-- ;
-+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
-+ udelay(1);
-
- do {
- csr.raw = read32(DEFAULT_HECIBAR + 0x4);
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
new file mode 100644
index 00000000..c411c18b
--- /dev/null
+++ b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
@@ -0,0 +1,94 @@
+From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
+From: Felix Singer
+Date: Wed, 26 Jun 2024 04:24:31 +0200
+Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
+
+Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
+Signed-off-by: Felix Singer
+---
+ src/soc/intel/skylake/Kconfig | 1 +
+ src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
+ 2 files changed, 56 insertions(+), 1 deletion(-)
+
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index 4ad33496b2..9191ed0ff8 100644
+--- a/src/soc/intel/skylake/Kconfig
++++ b/src/soc/intel/skylake/Kconfig
+@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
+ select CPU_INTEL_COMMON
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select CPU_SUPPORTS_PM_TIMER_EMULATION
++ select DRIVERS_USB_ACPI
+ select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
+ select FSP_COMPRESS_FSP_S_LZ4
+ select FSP_M_XIP
+diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
+index 6538a1475b..dfb81d496e 100644
+--- a/src/soc/intel/skylake/chipset.cb
++++ b/src/soc/intel/skylake/chipset.cb
+@@ -13,7 +13,61 @@ chip soc/intel/skylake
+ device pci 07.0 alias chap off end
+ device pci 08.0 alias gmm off end # Gaussian Mixture Model
+ device pci 13.0 alias ish off end # SensorHub
+- device pci 14.0 alias south_xhci off ops usb_xhci_ops end
++ device pci 14.0 alias south_xhci off ops usb_xhci_ops
++ chip drivers/usb/acpi
++ register "type" = "UPC_TYPE_HUB"
++ device usb 0.0 alias xhci_root_hub off
++ chip drivers/usb/acpi
++ device usb 2.0 alias usb2_port1 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.1 alias usb2_port2 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.2 alias usb2_port3 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.3 alias usb2_port4 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.4 alias usb2_port5 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.5 alias usb2_port6 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.6 alias usb2_port7 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.7 alias usb2_port8 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.8 alias usb2_port9 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.9 alias usb2_port10 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.0 alias usb3_port1 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.1 alias usb3_port2 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.2 alias usb3_port3 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.3 alias usb3_port4 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.4 alias usb3_port5 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.5 alias usb3_port6 off end
++ end
++ end
++ end
++ end
+ device pci 14.1 alias south_xdci off ops usb_xdci_ops end
+ device pci 14.2 alias thermal off end
+ device pci 14.3 alias cio off end
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
new file mode 100644
index 00000000..9d75cec6
--- /dev/null
+++ b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
@@ -0,0 +1,30 @@
+From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
+From: Mate Kukri
+Date: Fri, 22 Nov 2024 21:26:48 +0000
+Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
+ bootblock
+
+Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
+Signed-off-by: Mate Kukri
+---
+ src/soc/intel/skylake/bootblock/pch.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
+index df00bb85a9..beaece960b 100644
+--- a/src/soc/intel/skylake/bootblock/pch.c
++++ b/src/soc/intel/skylake/bootblock/pch.c
+@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
+
+ void pch_early_iorange_init(void)
+ {
+- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+- LPC_IOE_EC_62_66;
++ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
++ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
+
+ const config_t *config = config_of_soc();
+
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
new file mode 100644
index 00000000..df71dc47
--- /dev/null
+++ b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
@@ -0,0 +1,2232 @@
+From b515ba5b0cd02dc1771f27eaa716582b0827a638 Mon Sep 17 00:00:00 2001
+From: Mate Kukri
+Date: Tue, 31 Dec 2024 22:49:15 +0000
+Subject: [PATCH 28/37] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
+
+These machine have BootGuard fused and requires deguard to
+boot coreboot.
+
+Known issues:
+- Alpine Ridge Thunderbolt 3 controller does not work
+- Some Fn+F{1-12} keys aren't handled correctly
+- Nvidia dGPU is finicky
+ - Needs option ROM
+ - Power enable code is buggy
+ - Nouveau only works on linux 6.8-6.9
+- Headphone jack isn't detected as plugged in despite correct verbs
+
+Thanks to Leah Rowe for helping with the T480s.
+
+Signed-off-by: Mate Kukri
+Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
+---
+ src/device/pci_rom.c | 4 +-
+ src/ec/lenovo/h8/acpi/ec.asl | 2 +-
+ src/ec/lenovo/h8/bluetooth.c | 6 +-
+ src/ec/lenovo/h8/wwan.c | 6 +-
+ src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++
+ .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 +
+ .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++
+ .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++
+ .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 +
+ .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++
+ .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++
+ src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 +
+ .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++
+ .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes
+ .../variants/t480/gma-mainboard.ads | 19 ++
+ .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++
+ .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++
+ .../variants/t480/memory_init_params.c | 20 ++
+ .../variants/t480/overridetree.cb | 103 +++++++++
+ .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
+ .../variants/t480s/gma-mainboard.ads | 19 ++
+ .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++
+ .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++
+ .../variants/t480s/memory_init_params.c | 44 ++++
+ .../variants/t480s/overridetree.cb | 103 +++++++++
+ .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes
+ 49 files changed, 1583 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
+
+diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
+index dc41ef14ce..bba98d9dea 100644
+--- a/src/device/pci_rom.c
++++ b/src/device/pci_rom.c
+@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device)
+ rom = cbrom;
+ }
+
++#if 0
+ const char *scope = acpi_device_path(device);
+ if (!scope) {
+ printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
+ return;
+ }
++#endif
+
+ /* write _ROM method */
+- acpigen_write_scope(scope);
++ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
+ acpigen_write_rom((void *)rom, rom->size * 512);
+ acpigen_pop_len(); /* pop scope */
+ }
+diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
+index bc54d3b422..8f4a8e1986 100644
+--- a/src/ec/lenovo/h8/acpi/ec.asl
++++ b/src/ec/lenovo/h8/acpi/ec.asl
+@@ -331,7 +331,7 @@ Device(EC)
+ #include "sleepbutton.asl"
+ #include "lid.asl"
+ #include "beep.asl"
+-#include "thermal.asl"
++//#include "thermal.asl"
+ #include "systemstatus.asl"
+ #include "thinkpad.asl"
+ }
+diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
+index 16fc8dce39..be71a24ced 100644
+--- a/src/ec/lenovo/h8/bluetooth.c
++++ b/src/ec/lenovo/h8/bluetooth.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+
+-#include
++// #include
+ #include
+ #include
+ #include
+@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev)
+ {
+ struct ec_lenovo_h8_config *conf = dev->chip_info;
+
+- if (!conf->has_bdc_detection) {
++ if (1 || !conf->has_bdc_detection) {
+ printk(BIOS_INFO, "H8: BDC detection not implemented. "
+ "Assuming BDC installed\n");
+ return true;
+ }
+
++#if 0
+ if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
+ printk(BIOS_INFO, "H8: BDC installed\n");
+ return true;
+ }
++#endif
+
+ printk(BIOS_INFO, "H8: BDC not installed\n");
+ return false;
+diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
+index 685886fcce..5cdcf77406 100644
+--- a/src/ec/lenovo/h8/wwan.c
++++ b/src/ec/lenovo/h8/wwan.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+
+-#include
++// #include
+ #include
+ #include
+ #include
+@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev)
+ {
+ struct ec_lenovo_h8_config *conf = dev->chip_info;
+
+- if (!conf->has_wwan_detection) {
++ if (1 || !conf->has_wwan_detection) {
+ printk(BIOS_INFO, "H8: WWAN detection not implemented. "
+ "Assuming WWAN installed\n");
+ return true;
+ }
+
++#if 0
+ if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
+ printk(BIOS_INFO, "H8: WWAN installed\n");
+ return true;
+ }
++#endif
+
+ printk(BIOS_INFO, "H8: WWAN not installed\n");
+ return false;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+new file mode 100644
+index 0000000000..4998672943
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+@@ -0,0 +1,57 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++ bool
++ select BOARD_ROMSIZE_KB_16384
++ select EC_LENOVO_H8
++ select EC_LENOVO_PMH7
++ select H8_HAS_BAT_THRESHOLDS_IMPL
++ select H8_HAS_LEDLOGO
++ select H8_HAS_PRIMARY_FN_KEYS
++ select HAVE_ACPI_RESUME
++ select HAVE_ACPI_TABLES
++ select INTEL_GMA_HAVE_VBT
++ select INTEL_INT15
++ select MAINBOARD_HAS_LIBGFXINIT
++ select MAINBOARD_HAS_TPM2
++ select MAINBOARD_USES_IFD_GBE_REGION
++ select MEMORY_MAPPED_TPM
++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
++ select SOC_INTEL_KABYLAKE
++ select SPD_READ_BY_WORD
++ select SYSTEM_TYPE_LAPTOP
++
++config BOARD_LENOVO_T480
++ bool
++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++config BOARD_LENOVO_T480S
++ bool
++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++config MAINBOARD_DIR
++ default "lenovo/sklkbl_thinkpad"
++
++config VARIANT_DIR
++ default "t480" if BOARD_LENOVO_T480
++ default "t480s" if BOARD_LENOVO_T480S
++
++config OVERRIDE_DEVICETREE
++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
++
++config MAINBOARD_PART_NUMBER
++ default "T480" if BOARD_LENOVO_T480
++ default "T480s" if BOARD_LENOVO_T480S
++
++config CBFS_SIZE
++ default 0x900000
++
++config DIMM_MAX
++ default 2
++
++config DIMM_SPD_SIZE
++ default 512 # DDR4
++
++endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+new file mode 100644
+index 0000000000..abc273f387
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_LENOVO_T480
++ bool "ThinkPad T480"
++
++config BOARD_LENOVO_T480S
++ bool "ThinkPad T480s"
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+new file mode 100644
+index 0000000000..c308239177
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+@@ -0,0 +1,73 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++bootblock-y += bootblock.c ec.c
++
++romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
++
++ramstage-y += ramstage.c ec.c
++ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
++
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin
++spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin
++spd_0.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin
++spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin
++spd_1.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin
++spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin
++spd_2.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin
++spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin
++spd_3.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin
++spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin
++spd_4.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin
++spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin
++spd_5.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin
++spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin
++spd_6.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin
++spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin
++spd_7.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin
++spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin
++spd_8.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin
++spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin
++spd_9.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin
++spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin
++spd_10.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin
++spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin
++spd_11.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin
++spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin
++spd_12.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin
++spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin
++spd_13.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin
++spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin
++spd_14.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin
++spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin
++spd_15.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin
++spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin
++spd_16.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin
++spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin
++spd_17.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin
++spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin
++spd_18.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin
++spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin
++spd_19.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin
++spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin
++spd_20.bin-type := raw
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+new file mode 100644
+index 0000000000..3a949a2fca
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++#define THINKPAD_EC_GPE 22
++
++Name(\TCRT, 100)
++Name(\TPSV, 90)
++Name(\FLVL, 0)
++
++#include
++#include
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+new file mode 100644
+index 0000000000..fb660dbdfa
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+@@ -0,0 +1,60 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include "ec.h"
++
++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno)
++{
++ microchip_pnp_enter_conf_state(port);
++
++ // Select LPC I/F LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
++ // Write UART BAR
++ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707);
++ // Set SIRQ4 to UART
++ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART);
++
++ // Configure UART LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_UART);
++ pnp_write(port, UART_ACTIVATE, 0x01);
++ pnp_write(port, UART_CONFIG_SELECT, 0x00);
++
++ microchip_pnp_exit_conf_state(port);
++
++#ifdef CONFIG_BOARD_LENOVO_T480
++ // Supply debug unlock key
++ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
++
++ // Use debug writes to set UART_TX and UART_RX GPIOs
++ debug_write_dword(0xf0c400 + 0x110, 0x00001000);
++ debug_write_dword(0xf0c400 + 0x114, 0x00001000);
++#endif
++}
++
++
++#define UART_PORT 0x3f8
++#define UART_IRQ 4
++
++void bootblock_mainboard_early_init(void)
++{
++ // Tell EC via BIOS Debug Port 1 that the world isn't on fire
++
++ // Let the EC know that BIOS code is running
++ outb(0x11, 0x86);
++ outb(0x6e, 0x86);
++
++ // Enable accesses to EC1 interface
++ ec0_write(0, ec0_read(0) | 0x20);
++
++ // Reset LEDs to power on state
++ // (Without this warm reboot leaves LEDs off)
++ ec0_write(0x0c, 0x80);
++ ec0_write(0x0c, 0x07);
++ ec0_write(0x0c, 0x8a);
++
++ // Setup debug UART
++ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+new file mode 100644
+index 0000000000..c07d4d53ca
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+@@ -0,0 +1,71 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++chip soc/intel/skylake
++ # IGD Displays
++ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
++
++ register "panel_cfg" = "{
++ .up_delay_ms = 200,
++ .down_delay_ms = 50,
++ .cycle_delay_ms = 600,
++ .backlight_on_delay_ms = 1,
++ .backlight_off_delay_ms = 200,
++ .backlight_pwm_hz = 200,
++ }"
++
++ # Power
++ register "PmConfigSlpS3MinAssert" = "2" # 50ms
++ register "PmConfigSlpS4MinAssert" = "1" # 1s
++ register "PmConfigSlpSusMinAssert" = "3" # 500ms
++ register "PmConfigSlpAMinAssert" = "3" # 2s
++
++ device domain 0 on
++ device ref igpu on end
++ device ref sa_thermal on end
++ device ref thermal on end
++ device ref south_xhci on end
++ device ref lpc_espi on
++ register "serirq_mode" = "SERIRQ_CONTINUOUS"
++
++ register "gen1_dec" = "0x007c1601"
++ register "gen2_dec" = "0x000c15e1"
++
++ chip ec/lenovo/pmh7
++ register "backlight_enable" = "true"
++ register "dock_event_enable" = "true"
++ device pnp ff.1 on end # dummy
++ end
++
++ chip ec/lenovo/h8
++ register "beepmask0" = "0x00"
++ register "beepmask1" = "0x86"
++ register "config0" = "0xa6"
++ register "config1" = "0x0d"
++ register "config2" = "0xa8"
++ register "config3" = "0xc4"
++ register "has_keyboard_backlight" = "1"
++ register "event2_enable" = "0xff"
++ register "event3_enable" = "0xff"
++ register "event4_enable" = "0xd0"
++ register "event5_enable" = "0x3c"
++ register "event7_enable" = "0x01"
++ register "event8_enable" = "0x7b"
++ register "event9_enable" = "0xff"
++ register "eventc_enable" = "0xff"
++ register "eventd_enable" = "0xff"
++ register "evente_enable" = "0x9d"
++ device pnp ff.2 on # dummy
++ io 0x60 = 0x62
++ io 0x62 = 0x66
++ io 0x64 = 0x1600
++ io 0x66 = 0x1604
++ end
++ end
++
++ chip drivers/pc80/tpm
++ device pnp 0c31.0 on end
++ end
++ end
++ device ref hda on end
++ end
++end
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+new file mode 100644
+index 0000000000..aa4d4de2a6
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++DefinitionBlock(
++ "dsdt.aml",
++ "DSDT",
++ ACPI_DSDT_REV_2,
++ OEM_ID,
++ ACPI_TABLE_CREATOR,
++ 0x20110725
++)
++{
++ #include
++ #include
++ #include
++
++ Device (\_SB.PCI0)
++ {
++ #include
++ #include
++ #include
++ }
++
++ Scope (\_SB.PCI0.RP01)
++ {
++ Device (PEGP)
++ {
++ Name (_ADR, Zero)
++ }
++ }
++
++ #include
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+new file mode 100644
+index 0000000000..adb6a60324
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+@@ -0,0 +1,153 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include "ec.h"
++
++#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55
++#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa
++
++void microchip_pnp_enter_conf_state(uint16_t port)
++{
++ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port);
++}
++
++void microchip_pnp_exit_conf_state(uint16_t port)
++{
++ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port);
++}
++
++uint8_t pnp_read(uint16_t port, uint8_t index)
++{
++ outb(index, port);
++ return inb(port + 1);
++}
++
++uint32_t pnp_read_le32(uint16_t port, uint8_t index)
++{
++ return (uint32_t) pnp_read(port, index) |
++ (uint32_t) pnp_read(port, index + 1) << 8 |
++ (uint32_t) pnp_read(port, index + 2) << 16 |
++ (uint32_t) pnp_read(port, index + 3) << 24;
++}
++
++void pnp_write(uint16_t port, uint8_t index, uint8_t value)
++{
++ outb(index, port);
++ outb(value, port + 1);
++}
++
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value)
++{
++ pnp_write(port, index, value & 0xff);
++ pnp_write(port, index + 1, value >> 8 & 0xff);
++ pnp_write(port, index + 2, value >> 16 & 0xff);
++ pnp_write(port, index + 3, value >> 24 & 0xff);
++}
++
++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port)
++{
++ while (inb(cmd_port) & EC_OBF)
++ inb(data_port);
++}
++
++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port)
++{
++ while (inb(cmd_port) & EC_IBF)
++ ;
++}
++
++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port)
++{
++ while (!(inb(cmd_port) & EC_OBF))
++ ;
++}
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr)
++{
++ ecN_clear_out_queue(cmd_port, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(EC_READ, cmd_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(addr, data_port);
++ ecN_wait_to_recv(cmd_port, data_port);
++ return inb(data_port);
++}
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val)
++{
++ ecN_clear_out_queue(cmd_port, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(EC_WRITE, cmd_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(addr, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(val, data_port);
++}
++
++uint8_t eeprom_read(uint16_t addr)
++{
++ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(1, EC2_CMD);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(addr, EC2_DATA);
++ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++ return inl(EC2_DATA);
++}
++
++void eeprom_write(uint16_t addr, uint8_t val)
++{
++ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(2, EC2_CMD);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA);
++ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++ inl(EC2_DATA);
++}
++
++uint16_t debug_loaded_keys(void)
++{
++ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86);
++}
++
++static void debug_cmd(uint8_t cmd)
++{
++ ec0_write(EC_DEBUG_CMD, cmd);
++ while (ec0_read(EC_DEBUG_CMD) & 0x80)
++ ;
++}
++
++void debug_read_key(uint8_t i, uint8_t *key)
++{
++ debug_cmd(0x80 | (i & 0xf));
++ for (int j = 0; j < 8; ++j)
++ key[j] = ec0_read(0x3e + j);
++}
++
++void debug_write_key(uint8_t i, const uint8_t *key)
++{
++ for (int j = 0; j < 8; ++j)
++ ec0_write(0x3e + j, key[j]);
++ debug_cmd(0xc0 | (i & 0xf));
++}
++
++uint32_t debug_read_dword(uint32_t addr)
++{
++ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(addr << 8 | 0xE2, EC3_DATA);
++ ecN_wait_to_recv(EC3_CMD, EC3_DATA);
++ return inl(EC3_DATA);
++}
++
++void debug_write_dword(uint32_t addr, uint32_t val)
++{
++ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(addr << 8 | 0xEA, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(val, EC3_DATA);
++}
++
++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf };
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+new file mode 100644
+index 0000000000..d2963c8962
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+@@ -0,0 +1,99 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef SKLKBL_THINKPAD_EC_H
++#define SKLKBL_THINKPAD_EC_H
++
++// EC configuration base address
++#define EC_CFG_PORT 0x4e
++
++// Chip global registers
++#define PNP_LDN_SELECT 0x07
++# define LDN_UART 0x07
++# define LDN_LPCIF 0x0c
++#define EC_DEVICE_ID 0x20
++#define EC_DEVICE_REV 0x21
++
++// LPC I/F registers
++#define LPCIF_SIRQ(i) (0x40 + (i))
++
++#define LPCIF_BAR_CFG 0x60
++#define LPCIF_BAR_MAILBOX 0x64
++#define LPCIF_BAR_8042 0x68
++#define LPCIF_BAR_ACPI_EC0 0x6c
++#define LPCIF_BAR_ACPI_EC1 0x70
++#define LPCIF_BAR_ACPI_EC2 0x74
++#define LPCIF_BAR_ACPI_EC3 0x78
++#define LPCIF_BAR_ACPI_PM0 0x7c
++#define LPCIF_BAR_UART 0x80
++#define LPCIF_BAR_FAST_KYBD 0x84
++#define LPCIF_BAR_EMBED_FLASH 0x88
++#define LPCIF_BAR_GP_SPI 0x8c
++#define LPCIF_BAR_EMI 0x90
++#define LPCIF_BAR_PMH7 0x94
++#define LPCIF_BAR_PORT80_DBG0 0x98
++#define LPCIF_BAR_PORT80_DBG1 0x9c
++#define LPCIF_BAR_RTC 0xa0
++
++// UART registers
++#define UART_ACTIVATE 0x30
++#define UART_CONFIG_SELECT 0xf0
++
++void microchip_pnp_enter_conf_state(uint16_t port);
++void microchip_pnp_exit_conf_state(uint16_t port);
++uint8_t pnp_read(uint16_t port, uint8_t index);
++uint32_t pnp_read_le32(uint16_t port, uint8_t index);
++void pnp_write(uint16_t port, uint8_t index, uint8_t value);
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value);
++
++#define EC0_CMD 0x0066
++#define EC0_DATA 0x0062
++#define EC1_CMD 0x1604
++#define EC1_DATA 0x1600
++#define EC2_CMD 0x1634
++#define EC2_DATA 0x1630
++#define EC3_CMD 0x161c
++#define EC3_DATA 0x1618
++
++#define EC_OBF (1 << 0)
++#define EC_IBF (1 << 1)
++
++#define EC_READ 0x80
++#define EC_WRITE 0x81
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr);
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val);
++
++// EC0 and EC1 mostly are useful with the READ/WRITE commands
++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr)
++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val)
++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr)
++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val)
++
++// Read from the emulated EEPROM
++uint8_t eeprom_read(uint16_t addr);
++
++// Write to the emulated EEPROM
++void eeprom_write(uint16_t addr, uint8_t val);
++
++// Read loaded debug key mask
++uint16_t debug_loaded_keys(void);
++
++// The following location (via either EC0 or EC1) can be used to interact with the debug interface
++#define EC_DEBUG_CMD 0x3d
++
++void debug_read_key(uint8_t i, uint8_t *key);
++
++void debug_write_key(uint8_t i, const uint8_t *key);
++
++uint32_t debug_read_dword(uint32_t addr);
++
++void debug_write_dword(uint32_t addr, uint32_t val);
++
++// RW unlock key index
++#define DEBUG_RW_KEY_IDX 1
++
++// RW unlock key for EC version N24HT37W
++extern const uint8_t debug_rw_key[8];
++
++#endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+new file mode 100644
+index 0000000000..d89ed712d4
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef GPIO_H
++#define GPIO_H
++
++void variant_config_gpios(void);
++
++#endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+new file mode 100644
+index 0000000000..44c8578852
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+@@ -0,0 +1,105 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include
++#include "ec.h"
++#include "gpio.h"
++
++#define GPIO_GPU_RST GPP_E22 // active low
++#define GPIO_1R8VIDEO_AON_ON GPP_E23
++
++#define GPIO_DGFX_PWRGD GPP_F3
++
++#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low
++#define GPIO_DGFX_VRAM_ID0 GPP_D11
++#define GPIO_DGFX_VRAM_ID1 GPP_D12
++
++void mainboard_silicon_init_params(FSP_SIL_UPD *params)
++{
++ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
++
++ int dgfx_vram_id;
++
++ // Setup GPIOs
++ variant_config_gpios();
++
++ // Detect and enable dGPU
++ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low
++ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1;
++ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]);
++
++ // NOTE: i pulled this GPU enable sequence from thin air
++ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default.
++ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels
++ if (get_uint_option("dgpu_enable", 0)) {
++ printk(BIOS_DEBUG, "Enabling discrete GPU\n");
++ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail
++ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU
++ ;
++ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset
++ } else {
++ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n");
++ }
++
++ } else {
++ printk(BIOS_DEBUG, "Discrete GPU not present\n");
++ }
++}
++
++static void dump_ec_cfg(uint16_t port)
++{
++ microchip_pnp_enter_conf_state(port);
++
++ // Device info
++ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID));
++ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV));
++
++ // Switch to LPCIF LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
++
++ // Dump SIRQs
++ for (int i = 0; i <= 15; i += 1)
++ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i)));
++
++ // Dump BARs
++ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG));
++ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX));
++ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042));
++ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0));
++ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1));
++ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2));
++ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3));
++ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0));
++ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART));
++ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD));
++ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH));
++ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI));
++ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI));
++ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7));
++ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0));
++ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1));
++ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC));
++
++ microchip_pnp_exit_conf_state(port);
++}
++
++static void mainboard_enable(struct device *dev)
++{
++ if (CONFIG(VGA_ROM_RUN))
++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
++ GMA_INT15_PANEL_FIT_DEFAULT,
++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++static void mainboard_init(void *chip_info)
++{
++ dump_ec_cfg(EC_CFG_PORT);
++}
++
++struct chip_operations mainboard_ops = {
++ .enable_dev = mainboard_enable,
++ .init = mainboard_init,
++};
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
+GIT binary patch
+literal 4106
+zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+
+z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr
+zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^