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1031 commits

Author SHA1 Message Date
Leah Rowe
c46a71138c Libreboot 25.06 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-30 14:08:48 +01:00
Leah Rowe
b1ef562b76 tree.sh: add sha512 error for check_project_hashes
handle errors on sha512sum - also handle awk errors inside
the mini subshell, and provide overall error handling.

we know that the project.hash file should always exist, and
always be read no matter what; technically, the find command
that proceeds it might not yield any results, but an empty
file would then be produced.

the edge case of an empty file would have lead to an error
beforehand, when configuring the project in function,
configure_project(), so we've already got that covered.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:09 +01:00
Leah Rowe
04bee3834d tree.sh: add error check in check_project_hashes()
when reading old_pjhash, we need to error out where a read
error occurs. such an error is unlikely, but could occur under
certain edge cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:03 +01:00
Leah Rowe
677dfc4d10 tree.sh: more reliable clean in run_make_command
Don't do no-op if it fails; fall back to "clean" instead,
and fail if that fails.

The no-op was there was not all projects have distclean,
but we do intend for them all to be cleaned.

We mitigate further error by only running make-clean if
a makefile exists.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:40:33 +01:00
Leah Rowe
267d4c9034 inject.sh: add missing semicolons
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:39:57 +01:00
Leah Rowe
974bdbb381 vendor.sh: fix bad cbfstool path
i overlooked this one in the previous commit

there is always one.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 11:18:18 +01:00
Leah Rowe
dc6996252a put coreboot utils in elf/coreboot/TREE
not elf/UTIL/TREE

This way, they are automatically deleted when a tree
has to be re-built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 10:11:42 +01:00
Leah Rowe
b77154640d release.sh: use printf to create version files
Don't copy the files directly, because we might be doing
this from a work directory that has no files; in this case,
generic "unknown" variables are used, without generating
any files, so the current logic would produce an error.

However, we do need to create those dot files, because
we then rely on them for building release binaries.

The new logic maintains current behaviour, while fixing
this technical edge-case scenario via mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 18:46:58 +01:00
Leah Rowe
dee6997d0c lib.sh: simplify setvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:49:55 +01:00
Leah Rowe
79ded40f3d lib.sh: simplify chkvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:45:12 +01:00
Leah Rowe
5036a0bc50 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:33:56 +01:00
Leah Rowe
41308ee924 get.sh: simplify fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:26:34 +01:00
Leah Rowe
b5867be214 get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:23:06 +01:00
Leah Rowe
495098d6a7 get.sh: tidy up bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:19:06 +01:00
Leah Rowe
671e3aa27b get.sh: simplify fetch_targets()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:11:20 +01:00
Leah Rowe
09b6e91803 general cleanup in get.sh and vendor.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 01:30:33 +01:00
Leah Rowe
18dacd4c22 xbmk: rename xbmklocal/xbmktmp variables
shorten them

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:57:50 +01:00
Leah Rowe
e981132c82 get.sh: consolidate printf statements
stick it in git_prep, which both single- and multi-tree
projects will use, when downloading git repositories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:50:06 +01:00
Leah Rowe
afc36754b1 get.sh: remove redundant printf in fetch_project
The following execution will result in another printf
that says exactly what is being downloaded.

There is no need to inform the user twice about
what is being downloaded.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:44:57 +01:00
Leah Rowe
ffe387ac6b get.sh: remove superfluous command in try_git()
A git-pull is performed immediately after git-fetch.
Git-pull already performs git-fetch as a prerequisite.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:35:38 +01:00
Leah Rowe
ba7c49c090 vendor.sh: simplify fetch()
the checks at the end of the function are mostly
superfluous, because bad_checksum() is immediately
called just beforehand, and performs the same checks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:33:36 +01:00
Leah Rowe
30bc3732c3 init.sh: error out if .git/ is a symlink
the current behaviour is a relic from the older lbmk
design, before recent auditing.

the current logic would cause xbmk to continue execution,
going into a child process with .git/ being a symlink.

The .git/ directory should never be a symlink, because
it is extremely error-prone.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 17:01:10 +01:00
Leah Rowe
2493203ee5 get.sh: Properly error out if tmpclone fails
We rely on a non-zero exit on other try_ commands, which
works fine there because we then check the file afterward
and error out accordingly.

For git repositories, we assume that both mirrors are
identical and therefore once we get to the first clone
attempt, we assume that it must succeed.

Therefore, if it does not succeed, we must fail. This fixes
a regression I found in testing, where sometimes a failed
patching attempt would not result in an error exit, and
would therefore result in broken sources being present.

In practise, I always very closely watch the terminal when
testing xbmk, especially when updating project patches, so
we probably didn't introduce any broken sources in practice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:46:33 +01:00
Leah Rowe
ad333ae248 tree.sh: Don't auto-run make-oldconfig
This code was introduced to provide fault tolerance,
so that if I forgot to manually update the configs
myself, builds would still succeed, e.g. coreboot
builds.

However, there have been cases in the past where this
introduces settings we don't want, and in general we
do want to know when there is an error in the configs.

The policy should always be: fail early, fail hard.

This also mitigates bugs in U-Boot's build system; for
example, when I last attempted to update the U-Boot
tree for x86, make-oldconfig introduced a lot of junk
settings unrelated, which then introduced code that
would brick the board if you tried it on one, e.g.
it broke booting most Linux kernels via bootflow.

With this change, U-Boot will be easier to handle,
which normally requires manual configuration; the
automated make-oldconfig reconfiguration feature
breaks U-Boot. This will no longer occur, since we
no longer run it manually.

On the other hand, this feature has also prevented
other disastrous bugs in the past, such as when I
forgot to properly set the SPD size on T480; it was
set to 256 bytes, not 512 as is correct. Therefore,
this new design change means I must also be more
vigilant about config changes in project trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:35:02 +01:00
Leah Rowe
97ce531c34 rom.sh: simplify mkcoreboottar()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 05:03:03 +01:00
Leah Rowe
a47e981172 rom.sh: rename mkvendorfiles
it mainly does general tasks, like handling utils
and enabling ccache. the vfiles are a small part.

rename the function accordingly. it is called by
premake, so let's call it corebootpremake.

this change will also make sense when cherry-picked
into cbmk, which does not handle vfiles at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:46:08 +01:00
Leah Rowe
d2e148fdd9 rom.sh: simplify ccache handling for coreboot
we simply do not need to run the make-oldconfig command
at all, and after removing it, the "cook" function seemed
quite redundant so i merged it with mkvendorfiles()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:40:30 +01:00
Leah Rowe
8c3f10ba40 rom.sh: simplify u-boot payload handling
define it with a single variable, rather than several.

this allows several checks to be greatly simplified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 03:09:29 +01:00
Leah Rowe
3e28873532 ifd/hp8300usdt: set the HAP bit by default
In practise, coreboot can set this bit at build time.
We also use ME Soft Temporary Disable by default, on
this platform.

We also use me_cleaner by default, so the me.bin file
added to flash only contains the code that would run
with HAP set anyway.

Therefore, this change is of little practical consequence,
but as a friend put it to me, this change is most technically
correct.

And I'm all about technical correctness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-23 04:52:36 +01:00
Leah Rowe
452aeb6001 coreboot: Remove unused vboot tests
Futility tests enlarge the src tarballs, without much utility.

Uttterly futile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 14:13:11 +01:00
Leah Rowe
64cc91bca3 coreboot/default: Remove unneeded FSP modules
We only need the Kabylake version. We can safely
remove the other ones, thereby significantly
reducing the size of the lbmk release archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 13:48:20 +01:00
Leah Rowe
0216a3104a get.sh: Always update git remotes
Right now, if cache/clone/PROJECT/ already exists,
the logic for pulling new changes doesn't execute,
and neither does the logic for updating remotes.

This is bad when updating revisions, because then
manual updating is required, defeating the purpose
of xbmk's own automation in this regard.

Fix it by only checking the cached download on files,
not Git repositories; the try_git function itself will
already perform this check, before updating remotes
and pulling in new commits from upstream.

The updating only happens when a given target directory
doesn't exist, e.g. src/flashprog/ or src/grub/default/,
so this won't slow down release builds for example.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:45:59 +01:00
Leah Rowe
419733d307 get.sh: re-generate remotes every time
that way, when a remote changes in config/, it
will be updated automatically, without user
intervention.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:22:07 +01:00
Leah Rowe
231b320e63 release.sh: copy version files to rsrc
Otherwise, an "unknown" version number is created.

This regression was caused by the recent optimisation
that reduces the amount of extra work done by init.sh
on child instances of xbmk.

As a result of those changes, now release.sh has to
do some minor initialisation of its own, such as this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:51:31 +01:00
Leah Rowe
fc0720184d xbmk: add fake config makefile args to flashprog
also pcsx-redux

this way, commands like "./mk -u" without argument
will not fail. these fake makefile commands do nothing.

otherwise, an error errors because their makefiles
do not define these options.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:34:28 +01:00
Leah Rowe
f9266601b8 vendor.sh: add colon at the end of a for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:27:22 +01:00
Leah Rowe
8e0c6059d1 rom.sh: skip copyps1bios on dry builds
otherwise, ./mk -d (without arguments) will fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:47:02 +01:00
Leah Rowe
a3250d1447 tree.sh: Don't run make-clean on dry runs
Otherwise, ./mk -d (without arguments) fails for GRUB,
which first requires running autoconf to get a Makefile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:17:27 +01:00
Leah Rowe
24b8e633e0 GRUB: Update to revision 73d1c959e (14 March 2025)
This brings in several changes from upstream:

* 73d1c959e cryptocheck: Add --quiet option
* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory
* 301b4ef25 disk/cryptodisk: Add the "erase secrets" function
* 23ec4535f docs: Document available crypto disks checks
* 10d778c4b commands/search: Add the diskfilter support
* 7a584fbde disk/diskfilter: Introduce the "cryptocheck" command
* ed691c0e0 commands/search: Introduce the --cryptodisk-only argument
* c448f511e kern/rescue_reader: Block the rescue mode until the CLI authentication
* 4abac0ad5 fs/xfs: Fix large extent counters incompat feature support

This commit is of particular interest:

* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-21 13:34:18 +01:00
Leah Rowe
f6b7782283 Revert "vendor.sh: optimise find_me()"
This reverts commit fb7aaa78bb.

it caused a few issues. will re-do later

the old code isn't really broken, just inefficient, because
several files are scanned twice, but in practise the overhead
isn't that great

The error occurs sometimes, when bruteforcing me.bin:

ERROR ./mk: Unhandled error for: mv /home/user/lbmk/tmp/me.bin /home/user/lbmk/cache/tmpdl/check

This revert should fix the issue, for now.
2025-05-20 20:14:09 +01:00
Leah Rowe
fb7aaa78bb vendor.sh: optimise find_me()
i'm adding characters to 7ztest, which isn't being passed
on through because everything runs in subshells; the next
pass would default back to the original string, so a given
file may be checked multiple times.

fix this by mitigation; use the random string from mktemp
as a suffix instead.

in practice, this has not affected performance much, but it
will nevertheless avoid unnecessary work by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-20 02:58:33 +01:00
Leah Rowe
903f78bf08 get.sh: add missing check in fetch_project()
we check the main url, but not backup urls.

this patch fixes that oversight.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:13:29 +01:00
Leah Rowe
f15bb8153a get.sh: stricter URL check in xbmkget()
don't skip if the URL is empty. throw an error instead.

i decree that all links must be properly initialised, because
that is the design of lbmk. where only one link is provided,
such as in a local copy operation, the second would succeed no
better than the first so two identical paths are given.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:09:37 +01:00
Leah Rowe
cdc0fb49e1 get.sh: make xbmkget() easier to understand
the intent once again is that this for loop shall
return, with zero status, if success is observed.

otherwise, the loop breaks and an error is thrown.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:07:01 +01:00
Leah Rowe
620c1dd6fa get.sh: Make xbmkget err on exiting the loop check
The idea in this function is that if a file or repo is
successfully handled, a return will be performed from the
loop.

If the loop exits for any reason, an error is thrown. The
current code is probably fine, but I can forsee future
modifications possibly causing bugs here.

Make it unambiguous, by always throwing an error if execution
reaches the end of the function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 22:59:20 +01:00
Leah Rowe
900da04efa tree.sh: fix up copy_elf(), bad for loop
Because of how sh works, having just the [] line causes
sh to exit, annoyingly without an error message, but it
does cause a non-zero exit.

This bug will have already been triggering, before I added
the recent error handling on files for this for loop.

also do it to the other loop in lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:58:55 +01:00
Leah Rowe
8aaf404dde lib.sh: Use while, not for, to process arguments
This is more reliable against globbing, in context of for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:29:59 +01:00
Leah Rowe
d9c64b2675 xbmk: stricter handling of files on while loops
i overlooked these!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:24:43 +01:00
Leah Rowe
b25a487643 init.sh: looser XBMK_THREADS validation
on child processes, we can simply correct it.

we currently provide an error message, but this is silly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:53:22 +01:00
Leah Rowe
769a97aed5 init.sh: Hardcode XBMK_CACHE for integrity
I never really intended for this to be configurable,
but the cache directory is also used during release
builds.

There's too much that can go wrong, letting the user
decide where their cache is. Simplify it by hardcoding.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:50:06 +01:00
Leah Rowe
265ec0b767 dependencies/debian: add libx86
already present on a few other config files, e.g. arch

i noticed on debian-experimental that i needed to explicitly
install it, whereas it was implicitly installed on debian 12

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 17:40:44 +01:00
Leah Rowe
2702a43a86 init.sh: merge xbmk_lock() with xbmk_set_env()
it's just two lines, and we want much more granular
control of where the lock is enforced. it should be
JUST after confirming that the instance is a parent.

it is at this moment that we should bail if a lock
file exists, because this signals that another instance
of xbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:32:24 +01:00
Leah Rowe
fc4006ce87 init.sh: move xbmk_set_version
it's called before set_pyver, so move it above that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:29:51 +01:00
Leah Rowe
962902a1c4 init.sh: set pyver from set_env
it's related to this function, no point calling from main

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:28:31 +01:00
Leah Rowe
158c56072c init.sh: merge xbmk_mkdirs with set_env
it's just two lines, and they relate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:25:37 +01:00
Leah Rowe
5f022acbf4 init.sh: check version/versiondate once read
once again, we are being stricter in child instances.

we must ensure that these variables are set by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:10:22 +01:00
Leah Rowe
485a60e2f6 init.sh: error if version not read
we no longer rely on the .git version being
read by child instances, so we MUST ensure
that it is being read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:08:49 +01:00
Leah Rowe
99f09f25ef init.sh: only update version files on parent
don't update them on child instances, since it's a waste
of time; the lock file prevents further execution, so we
are just wasting time writing to disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:03:09 +01:00
Leah Rowe
94437278dc init.sh: simplify unknown version creation
we don't need to read or write a file at all, in that case.
we only then need to generate one if running ./mk release.

the scenario in which no .git and no version files exist
is when someone grabs the build system from a snapshot
generated by e.g. forgejo instances. it's ill advised, so
we advise against it, but it is mitigated in code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:54:31 +01:00
Leah Rowe
6b603b9fbf init.sh: only set xbmk version on parent instance
On child instances, we need only read.

Apply the principle of least privilege.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:07:10 +01:00
Leah Rowe
ac36ea7f95 init.sh: initialise variables AFTER path
That way, unnecessary work is avoided on child instances.

Of course, the current check assumes that TMPDIR wasn't
already set by a wily user before running lbmk, but then
those sorts of users probably know what they're doing.

If they don't know, they will soon find out. Therefore, I
have added additional checks on child instances, preventing
the build system from running if XBMK_CACHE is not set; if
it isn't, then that could very easy lead to certain system
files being overwritten.

The user must never know what happens if XBMK_CACHE is unset.
We simply will not allow it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:02:51 +01:00
Leah Rowe
484afcb919 init.sh: merge create_pathdirs with set_pyver
all this function does now is create the python symlink,
based on work that was already performed in set_pyver

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:40:58 +01:00
Leah Rowe
d0bee6b4eb init.sh: Set python version only on parent
Do it after the creation of xbmkpath.

This avoids performing an unnecessary check, since
PATH will have already been corrected for child
instances; Python will already be correct there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:38:11 +01:00
Leah Rowe
4aa69a7d1f init.sh: remove useless command
we mkdir -p xbmklocal, only to remkdir it immediately
afterward, which is the intended behaviour; on parent
instances, xbmklocal is to be re-created fresh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:30:11 +01:00
Leah Rowe
36ffe6ef50 init.sh: remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:29:54 +01:00
Leah Rowe
0343081d90 init.sh: xbmk_create_tmpdir to xbmk_mkdirs
this function now simply creates directories that lbmk
will use, rather than creating specific directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:57 +01:00
Leah Rowe
c75bc0449d init.sh: move gnupath creation to create_tmpdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:15 +01:00
Leah Rowe
253aa81a3f init.sh: move PATH init to set_env
we must only set this in the parent instance, not
child instances. this prevents the variable from
being over-populated with repeated entries.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:26:28 +01:00
Leah Rowe
e05a18d351 init.sh: check the lock file BEFORE git init
this way, initialisation will not be performed erroneously
while another parent instance of lbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:21:30 +01:00
Leah Rowe
cde3b7051e init.sh: return from child in set_env instead
This is earlier than the current check, thus preventing
the initialisation of a git repository and/or the recreation
of xbmktmp and xbmklocal by erroneous parent executions of lbmk
while another parent is running - the latter of which could have
caused a massively unpredictable build failure, so this is also
a pre-emptive bug fix, fixing all kinds of weird bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:18:45 +01:00
Leah Rowe
7ec9ee4228 inject.sh: shorten the nukemode variable name
just call it "nuke". this is what tells whether to remove
vendor files from an archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:12:20 +01:00
Leah Rowe
b48eb161e4 vendor.sh: simplify mksha512sum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:10:57 +01:00
Leah Rowe
ac609d5aae vendor.sh: Remove _dest if it's bad
Also, provide more ample warning to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:59:16 +01:00
Leah Rowe
a3e1ed9823 release.sh: rename relsrc to rsrc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:51:03 +01:00
Leah Rowe
44df3b2bff release.sh: tidy up nuke()
i wasn't ok having that variable initialisation and
then the commands on the same line. it looks messy.

having the commands on a separate line makes the code nice
to read, so let's separate them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:33:23 +01:00
Leah Rowe
3c58181f69 get.sh: remove useless message
the user doesn't care where the temporary git repo is

git shows that information anyway, in the git clone command

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:53:23 +01:00
Leah Rowe
01a0217c1e get.sh: simplify bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:51:12 +01:00
Leah Rowe
4ca57943d7 release.sh: simplify nuke() EVEN MORE, yet again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:03:08 +01:00
Leah Rowe
47a3982bbe release.sh: use x_ on find command for nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:49:24 +01:00
Leah Rowe
6dc71cc024 release.sh: simplify nuke() EVEN MORE
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:38:20 +01:00
Leah Rowe
05c07f7401 get.sh: move nuke() to release.sh
we really only need it there, because the context is
for release archives. normal use of the git repository
doesn't matter in the context of deletions, because that
will not be distributed. only the result of ./mk release
will be distributed.

the builds produced will not change as a result of this,
for people using the normal git repository, because the
files in question are never used anyway, in our configs.

this is being done to make working on local repos easier.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:20:02 +01:00
Leah Rowe
587d245caf release.sh: simplify prep_release_bin()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:17:09 +01:00
Leah Rowe
136bd66c28 mrc.sh: merge extract_mrc with extract_shellball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:00:17 +01:00
Leah Rowe
dbe109d7b5 release.sh: don't move src/docs/
otherwise, ./mk -b (without argument) will fail, on release
archives. also, perhaps i should add an mkhelper to build it?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:43:25 +01:00
Leah Rowe
840d6a1d27 get.sh: FURTHER simplify nuke()
this is getting almost comical now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:17:36 +01:00
Leah Rowe
d2564fd945 get.sh: simplify tmpclone()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 11:08:06 +01:00
Leah Rowe
6dea381614 get.sh: fix bad mkdir command
this is the mkdir call that createsn the directory where
a cached git repository is moved to, during creation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 09:46:54 +01:00
Leah Rowe
6a2ed9428b vendor.sh: Fix broken KBC1126 insertion
On release archives, I overlooked the previous change to
downloads, during the recent implementation of extra safety
checks. I previously checked there whether the variable named
CONFIG_KBC1126_FIRMWARE was defined, and grabbed both; now I
check CONFIG_KBC1126_FW1 and CONFIG_KBC1126_FW2 separately,
grabbing each file separately.

This patch replicates that change for insertions. Otherwise,
hash verification on ROM images will fail, when running the
inject script on release images.

Downloading was being done, reliably, and the extracted files
were correct, so there was no danger if the user was building
from source and flashing that way.

However, checksum verification on full images failed when
inserting into archives. This is not because the files were
wrong; they were *correct*. However, the EC firmware was not
being inserted *at all* on HP EliteBooks, because of this
oversight. The check is now based on whether the paths to
the files themselves are defined, not whether EC firmware
is enabled in the coreboot config; the latter is implied.

With this patch, vendor file insertion once again works
perfectly, without error, on every board. There was no real
danger for users, just a minor inconvenience. Sorry!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 09:44:34 +01:00
Leah Rowe
4313b474a5 vendor.sh: additional safety check
the exit from mkdst can also be non-zero if mv or cp
failed, but there's no way to handle that reliably.

therefore, the checksum verification should be done
one final time, to compensate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 07:03:08 +01:00
Leah Rowe
d668f3a352 vendor.sh: Properly verify SHA512SUM on extraction
I currently check the downloaded files e.g. .exe file, but
then I don't check - or even define - sha512sums for the
files extracted from them e.g. me.bin

This patch fixes that. It also caches the hashed files, so
that extraction is faster on a re-run - this makes release
builds go faster, when running ./mk release

If a checksum is not defined, i.e. blank, then a warning is
given, telling you to check a specific directory. This way,
when adding new vendor files, you can add it first without
specifying the checksum, e.g. me.bin checksum. Then you can
manually inspect the files that were extracted, and define it,
then test again.

In a given pkg.cfg for config/vendor, the following variables
are now available for use:

FSPM_bin_hash for fsp m module
FSPS_bin_hash for fsp s module
EC_FW1_hash for KBC1126 EC firmware (1st file)
EC_FW2_hash for KBC1126 EC firmware (2nd file)
ME_bin_hash for me.bin
MRC_bin_hash for mrc.bin (broadwell boards)
REF_bin_hash for refcode (broadwell boards)
SCH5545EC_bin_hash for sch5545 firmware (Dell Precision T1650)
TBFW_bin_hash for Lenovo ThunderBolt firmware (e.g. T480/T480s)
E6400_VGA_bin_hash for Dell E6400 Nvidia VGA ROM

In practise, most people use release archives, and the
inject script, so I knew those were reliable, because the ROM
images were hashed prior to removing files. This patch benefits
people using lbmk.git directly, without using release files,
because now they know they have a valid file e.g. me.bin

Previously, only the download was checked, not the extracted
files, which meant that the only thing preventing a brick was
the code not being buggy. Any number of bugs could pop up in
the future, so this new level of integrity will protect against
such a scenario, and provide early warning prompting bug fixes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 05:39:18 +01:00
Leah Rowe
a191d22bd6 get.sh: add missing eval to dx_ in nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:41:04 +01:00
Leah Rowe
c8813c9a14 properly exit 1 when calling fx_
in a few places, we use the presence of a file found
by fx_ to cause an exit, but the command that runs
looks something like:

exit 1 "string"

this yields an error, and a non-zero exit, because of
too many arguments to "exit", but we wanted a non-zero
exit anyway.

nevertheless, this is incorrect.

to fix it, eval is used instead. if the never-going-to-exist
condition one day exists where exit 1 actually returns, not,
you know, exits, we will use err instead, with the string
as argument.

this should be fine. it's a bit hacky, but so is fx_, and
it works. fx_ is used in several places to keep the sloccount
down, providing a common way to perform while loops on the
output of a command; that is its only purpose..

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:25:02 +01:00
Leah Rowe
208dfc89bd get.sh: simplify nuke()
more specifically, re-write it so that it can be called with fx_

this means that the single-tree check for nuke.list can be made
much simpler

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:12:04 +01:00
Leah Rowe
46f42291d3 get.sh: fix broken printf statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 18:06:29 +01:00
Leah Rowe
f29aa9c8d5 get.sh: use subshells on try_ functions
This way, we can use x_ which will then print the command
that failed, if we need to debug future errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 17:03:32 +01:00
Leah Rowe
e62886deda get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:59:59 +01:00
Leah Rowe
d9ed03f9ea get.sh submodules: Don't delete files recursively
I overlooked this in a previous patch. It doesn't really
matter, since we're operating on a file anyway, but it's
not correct.

Files should have rm -f on them, not rm -Rf, for deletion.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:52:33 +01:00
Leah Rowe
8d5475ed5b get.sh: simplify fetch_submodules() config check
We already do what the old code does in setcfg, by
virtue of the fact that the st variable is later
checked, after loading this config conditionally,
where the st variable is otherwise blank.

We can avoid the unnecessary work after loading
the config, by returning if the config is absent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:48:25 +01:00
Leah Rowe
21867b7d80 get.sh: simplify fetch_submodules()
We are calling xbmkget in the same way, whether it's
a subfile or subrepo.

Rename these variables to subcurl and subgit, so that we
can call xbmkget unconditionally.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:39:51 +01:00
Leah Rowe
e9fe5a74a2 get.sh: fix caching of crossgcc tarballs
they were always re-downloading every time.

i've basically re-written most of xbmkget.

there was some erroneous conditions under which
it wrongly deleted the cached file, resulting in
it being downloaded again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:28:29 +01:00
Leah Rowe
6089716f07 release.sh: Don't run prep_release with fx_
The result of the printf statement is sorted, making
it do binaries first, which results in a lot of junk
files then being present inside the source archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:17:37 +01:00
Leah Rowe
b04c86e574 git.sh: rename to get.sh
it now handles more than just git, and i forsee
it handling even more in the future, e.g. rsync,
ftp, bittorrent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:00:28 +01:00
Leah Rowe
3c23ff4fa1 git.sh: Only create destination repo on success
Don't leave a broken cache laying around, which would
otherwise break lbmk for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 21:57:34 +01:00
Leah Rowe
ed8a33d6fb git.sh: cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:47:41 +01:00
Leah Rowe
1ca26c5d23 git.sh: Re-implement redundant git downloads
And this time it works.

I'm now calling xbmkget() which in turn calls tmpclone(),
instead of me calling tmpclone() directly.

The git-pull is done on both remotes, regardless of whether
the first succeeds. This way, if I forgot to update a mirror,
downloads would probably still work.

This also fixes an issue people were having, for example where
the gnulib repository of GRUB was always being downloaded
every time.

I'm using a new directory, XBMK_CACHE/clone, instead
of XBMK_CACHE/repo (which I used before), in case people
still have the old caches from before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:25:37 +01:00
Leah Rowe
e38805a944 rom.sh: reduce indendation in check_coreboot_utils
call it via fx_, instead of using a for loop

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:32:07 +01:00
Leah Rowe
6bf24221e6 release.sh: simplify release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:11:34 +01:00
Leah Rowe
66f7ecdb2d release.sh: clean up the vdir after release
do this after moving the version directory within it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:04:48 +01:00
Leah Rowe
d4c0479093 release.sh: remove src_dirname variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:25:35 +01:00
Leah Rowe
6d3a6347c3 release.sh: build in tmp directory first
don't move to the real directory until the work
is done.

that way, a re-try can be done, while analysing
the old files. it is created based on the tmpdir,
under XBMK_CACHE/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:23:41 +01:00
Leah Rowe
a0105e1ab4 release.sh: remove unnecessary mkdir command
the following git clone command creates that directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:07:50 +01:00
Leah Rowe
f4871da9bc release.sh: split up build_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:49:50 +01:00
Leah Rowe
c85aff5c54 release.sh: delete tmp/cache from the tarball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:29:58 +01:00
Leah Rowe
92954eeb38 lib.sh: remove rmgit()
We don't need to call it from git.sh, because it's
only being done when building a release anyway,
and we already run rmgit when doing a release.

The function itself is only two simple fx_ calls,
so we can just do that from build_release().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:20:50 +01:00
Leah Rowe
05b5914b35 lib.sh: remove mk()
i don't need it. i can use fx_ instead, on functions
that previously called mk().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 18:05:32 +01:00
Leah Rowe
c9696e2333 lib.sh: move xbmkget() to git.sh
in cbmk, it's only used from there.

in lbmk, it's also used from vendor.sh.

however, i plan to further expand git.sh at
some point, tidying it up so that git cloning
is also done from xbmkget, with dlop=git and
git.sh would then be renamed to get.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:30:05 +01:00
Leah Rowe
23913bb8d2 lib.sh: move mksha512sum() to vendor.sh
this is unused in cbmk.

it's only used from vendor.sh.

therefore, lbmk shall have it in vendor.sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:20:34 +01:00
Leah Rowe
80f0562e8d lib.sh: split up try_file()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:44:31 +01:00
Leah Rowe
89cd828e87 lib.sh: move _ua to try_file()
it's only used there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:32:50 +01:00
Leah Rowe
308a9ab1e1 mrc.sh: minor cleanup
group the cbfs command to the extract command, since they
are related. this makes it clearer that the following
command to extract refcode is unrelated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:06:25 +01:00
Leah Rowe
40163dcfa4 mrc.sh: update copyright year to include 2025
I've made several modifications to the file, this year.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:05:21 +01:00
Leah Rowe
ef800b652c inject.sh: remove the hashfiles variable
we only use it once, and it's a trivial string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:52:27 +01:00
Leah Rowe
311ae2f8df inject.sh: define xchanged here instead
this is used here, and also needed in cbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:49:14 +01:00
Leah Rowe
76f81697e6 vendor.sh: remove check_vcfg()
We don't need it. The vfile variable is only used in
one place, and only once, for use with setcfg.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:47:43 +01:00
Leah Rowe
97d4d020d9 vendor.sh: simplify getvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:30:27 +01:00
Leah Rowe
57f896ac01 vendor.sh: simplify setvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:23:32 +01:00
Leah Rowe
3879f6c4d8 lib.sh: use fx_ in rmgit()
with fx_, i have more much granular control over
how errors are handled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:21:59 +01:00
Leah Rowe
0911a5a5ae lib.sh: split up xbmkget()
it was too complicated. most of the logic has been moved
to a new function, try_file()

the for loop is handled by xbmkget(), whereas each try
is now handled in try_file()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:16:10 +01:00
Leah Rowe
a449afb287 inject.sh: only compile nvmutil if needed
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:56:28 +01:00
Leah Rowe
2bbf2ae80b inject.sh: simplified serprog check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:52:47 +01:00
Leah Rowe
9c27b7437c vendor.sh: tidy up variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:43:34 +01:00
Leah Rowe
0cc816167b vendor.sh: split up setvfile()
split the actual bootstrapping to getvfile()

setvfile only sets the config, but then it will
call getvfile() to act on that config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:39:01 +01:00
Leah Rowe
7d90d43425 remove another confusing message
the current message says the file name, and implies that
the given file has already been updated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:51:38 +01:00
Leah Rowe
a0c436ad4b inject.sh: Remove confusing path on tar creation
The path is wrong. The correct path is printed afterward.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:48:38 +01:00
Leah Rowe
dcfd3e632e inject.sh: re-add mac address confirmation
it just makes the script more user-friendly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:23:46 +01:00
Leah Rowe
e5af201060 inject.sh: further cleanup for vendor.sh
i moved out more code to vendor.sh, to reduce the
amount of lbmk-only code on inject.sh

this should reduce the number of merge conflicts
even further, when cherry picking from lbmk to cbmk.

in particular, vendor file insertion is now handled
entirely through the "setvfile" function, instead
of from inject.sh, which seems counterintuitive,
but remember that inject.sh also does MAC addresses.

therefore, the inject.sh script is now primarily for
inserting MAC addresses, and handles vendor downloads
in a slightly more convoluted way, but still easy
enough to understand if you read it a bit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:06:41 +01:00
Leah Rowe
0aa99f4bf8 tree.sh: only create elfdir in copy_elf()
otherwise, we create empty directories where build.list
doesn't exist, like on coreboot.

we already create a directory when needed, when actually
copying elf files, so let's just leave it at that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:58:22 +01:00
Leah Rowe
a8e374020c tree.sh: simplified srcdir check on make-clean
this is the check that ksips a given target if the tree
directory does not exist, on the clean command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:19:00 +01:00
Leah Rowe
0f931b508a inject.sh: split to vendor.sh the download parts
to the extent feasible, keep lbmk-specific parts on
inject.sh to a minimum. this will later be used to
re-sync cbmk's inject.sh with lbmk's, because cbmk's
one doesn't handle vendor files.

the way this is designed now, with this patch, will
make cherry-picking lbmk to cbmk easier in the future,
when keeping this part of cbmk in sync with lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 13:03:16 +01:00
Leah Rowe
3554b5aad9 inject.sh: split up the inject functions
generally go for a more linear function order, and
split up any functions.

the objective is to have functions only suitable to
libreboot be separate. more splitting will be done,
and eventually the vendor-download functions will be
split into a new file, as will several other functions.

this is being done as part of an effort to bring the
libreboot and canoeboot versions of inject.sh in sync,
so that from now on, cherry picking between the two
projects will produce fewer merge conflicts and require
a lesser amount of post-merge maintenance.

some other minor cleanup has also been done; for example,
the "need_files" variable is redundant and was removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 10:45:48 +01:00
Leah Rowe
81dbde7e09 lbmk: use x_ instead of err, where appropriate
many places in lbmk used err, because older versions
of x_ did not handle globbing properly.

however, use of x_ is preferable on trivial commands.

the only time err() should be called is what it has
to be, when x_ can't work, or when a more useful error
message is needed, for context.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:54:23 +01:00
Leah Rowe
14d46abced mrc.sh: operate on refcode in tmp area first
that way, the Intel GbE device can be enabled there,
and only then would the refcode file be copied.

otherwise, the current behaviour would leave buggy
refcode in place, if the dd command failed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:31:00 +01:00
Leah Rowe
6e521c2e1e mrc.sh: fix outdated info in the comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:21:58 +01:00
Leah Rowe
23486abef3 inject.sh: use direct comparison for metmp
use of the e function would slow down execution,
and it's mostly unnecessary in this case.

the e function is only needed if we want to confirm
via user message that a file exists. that is not
needed here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:26:33 +01:00
Leah Rowe
91220ce183 inject.sh: use subshell to speed up find_me()
the current test allows a further extraction after
running mecleaner, even if me.bin was found.

further, any recursive calls that exit non-ze
don't lot the loop acthually stop, unless we
subshell that too, otherwise fx_ is returned to
return 0 when a given command it runs returns 1,
or more specifically: the for loop in x_ breaks.

this is by design, and there's not much that can
be done, but this patch should pseed up extraction
a little bit, when dealing with intel me files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:20:33 +01:00
Leah Rowe
ff33ec3352 mk: use zero exit instead, to run trees
that way, with set -u -e, we aren't risking some
buggy sh implementations from causing an error exit
where it shouldn't.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:41:24 +01:00
Leah Rowe
c2b627dc6d remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:36:44 +01:00
Leah Rowe
066402b7e7 mk: remove unnecessary line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:35:40 +01:00
Leah Rowe
7012c00ed1 mk: re-split tree logic to include/tree.sh
I really think mk should just be a small stub.

Better to keep everything separate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:33:49 +01:00
Leah Rowe
50ce1ac9b2 mk: move release functions to idnclude/release.sh
The idea with mk is that it's meant to basically be a
stub for running everything else, while mainly having
the trees logic within it (what was once script/trees).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:28:49 +01:00
Leah Rowe
1ce3e7a3d3 mk: add missing error handli for mk -f
on the release command, that is

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:17:35 +01:00
Leah Rowe
0d876622fc git.sh: re-write tmpclone without caching
remove caching for now. it's buggy as hell.

will re-write the caching feature next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:14:43 +01:00
Leah Rowe
454f11bdd7 git.sh: use setvars for fail variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:50:17 +01:00
Leah Rowe
6bdb15fd32 git.sh: hard fail if git am fails
similar to the last patch, we must ensure that the
inability to patch will cause a hard exit, regardless
of any redundancy we have for cloning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:36:37 +01:00
Leah Rowe
93d4eca04a git.sh: Hard fail if reset fails
We allow a re-try when cloning fails, to account
for redundancy, but resetfail currently doesn't
cause any error exit at all.

This patch mitigates that bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:33:17 +01:00
Leah Rowe
a3ba8acfac init.sh: Only check XBMK_CACHE if it exists
Otherwise, if it doesn't exist, the current check will
wrongly exit with error status, preventing you from
running the build system at all!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:49:49 +01:00
Leah Rowe
021e7615c8 HP 820 G2: Use fam15h cbfstool tree for refcode
We used cbfstool from coreboot 4.13, because it was the
last version to work with the particular format used
for stage files, before the CBFS standard changed in newer
releases of cbfstool.

When I added this board to Libreboot, it was source-only at
first so it didn't matter. I didn't want to do a standalone
cbfstool binary, in case some people decided to use that one
on newer boards, which would cause all sorts of issues.

So I bodged it and just included an import of coreboot 4.13.

Well, the cbfstool from coreboot 4.11, as used for FAM15H
AMD boards, is compatible. I checked the code diff between
the two, and there is no meaningful difference.

I've tested this, and it works, since the last release or
two now includes 820 G2 images, so I  was able to use those
with ./mk inject, to verify whether the refcode file is
still grabbed properly. We need the refcode to handle MRC
on Broadwell platform, but we extract it from an old Google
Chromebook image, that uses the old CBFS stage file layout.

This change solves my problem: the problem was that releases
are bloated further, due to including this extra coreboot
version. This should reduce the size of the next release
considerably, especially after decompressing the tarball.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:46:05 +01:00
Leah Rowe
fe92605244 also fix the other grub trees
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 11:12:34 +01:00
Leah Rowe
a8594762d2 Merge pull request 'fix trying to boot all logical volumes after unlocking an encrypted volume' (#330) from cqst/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/330
2025-05-08 10:11:13 +00:00
cqst
e084b06dc7 fix trying to boot all logical volumes after unlocking an encrypted volume 2025-05-08 02:28:58 -07:00
Leah Rowe
2cea8517f3 init.sh: remove useless export
we already reset to n if not y, afterward

just rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 21:16:50 +01:00
Leah Rowe
1b0afdcea2 init.sh: also allow XBMK_RELEASE=Y or N
as opposed to =n or =y

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:23:32 +01:00
Leah Rowe
570f1417a8 init.sh: Resolve XBMK_CACHE via readlink
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:14:36 +01:00
Leah Rowe
e1af1055ed init.sh: check XBMK_CACHE is a directory instead
it doesn't matter if it's not a file. that's the wrong check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:09:29 +01:00
Leah Rowe
e1628ad8f3 init.sh: export LOCALVERSION in set_env
Don't do it in set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:04:52 +01:00
Leah Rowe
40a944118f init.sh: run set_version before set_env
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:03:51 +01:00
Leah Rowe
cba04aa74b init.sh: Use readlink in pybin()
Use realpath only as a fallback.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:00:13 +01:00
Leah Rowe
a94bd3c093 inject.sh: simplify extract_kbc1126ec()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:08:42 +01:00
Leah Rowe
e3098c61f4 inject.sh: simplified MAC address handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:00:41 +01:00
Leah Rowe
d530e68594 inject.sh: Simplify patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:53:57 +01:00
Leah Rowe
7f71328f0e lib.sh: Remove useless command in err()
We don't need this, since we're exiting anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:23:12 +01:00
Leah Rowe
394b4ea7a5 inject.sh: rename copytb and preprom functions
make them shorter so they go on one line again

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:17:45 +01:00
Leah Rowe
ec5c954337 lib.sh: Simplified fx_() and removed fe_()
Instead of calling fe_, prefix x_ as indicated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:12:10 +01:00
Leah Rowe
1390f7f800 mk: Create serprog tarballs here instead
i simplified rom.sh to use mkhelper for actual image
building.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:21:28 +01:00
Leah Rowe
0ef77e6583 build serprog using fe_ *defined inside mkhelper*
sh macros ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:01:50 +01:00
Leah Rowe
d2e6f989d7 rom.sh: build serprog images with fe_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:44:05 +01:00
Leah Rowe
0faef89946 lib.sh: support any command on find_exec()
right now, we assume "find", but it adds any number of
arguments next to that.

change it instead to support any command, where the
assumption is that it would generate a list of files
and directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:28:55 +01:00
Leah Rowe
2b7f6b7d7c inject.sh: Simplify extract_intel_me_bruteforce()
This is probably about as small as it's going to get.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 10:20:59 +01:00
Leah Rowe
485d785d33 inject.sh: clean up tmp me file before extract
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 21:16:06 +01:00
Leah Rowe
fac99aa2d4 lib.sh: re-add missing break in fe/fx_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 20:24:32 +01:00
Leah Rowe
03300766d1 inject.sh: tidy up extract_intel_me_bruteforce
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:47:08 +01:00
Leah Rowe
4781dbd2a0 inject.sh: fix oversight in me bruteforce
i used i instead of 1, in the variable when running
the extract_archive function.

this didn't trigger since +u was set, and +e was set.

in practise, then, it seems that because of this, and
because my ME extract/insert test was a success, that
none of the archives we use actually have a ME inside
of a file inside of a given downloaded archive.

still, this is technically incorrect, so fix it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:43:44 +01:00
Leah Rowe
cf78583a6d inject.sh: remove unnecessary check
the call stack already falls through with  a bunch of return
1s after a successful run of me_cleaner, so it's really not
necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:32:18 +01:00
Leah Rowe
5657cc1afb inject.sh: don't use subshell for me bruteforce
i needed it on the old version, which used cd

this one stays in the same directory at all times

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:30:55 +01:00
Leah Rowe
5686f35e0f inject.sh: insanely optimise the me bruteforce
use fe_

fe_ ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 18:59:32 +01:00
Leah Rowe
e8be3fd1d4 git.sh: Simplify git am handling
fx_ and fe_ really are the best shell functions ever.

really. they're the best.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 11:09:39 +01:00
Leah Rowe
4c1de1ad12 inject.sh: remove unused function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 04:49:56 +01:00
Leah Rowe
282b939d9d init.sh: New function dx_ to execute path files
Generated by find, this is a wrapper in place of using
for loops everywhere. This simplification temporarily
increases the amount of code, because we don't do this
a lot, but this will reduce the growth of the build
system code size in future changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:37:16 +01:00
Leah Rowe
73074dedee inject.sh: Further simplified FSP extraction
We don't need the copy command at all, since the files
it copies are the only ones that the Python script does
anyway, so now we just make that script output to the
directory, directly, where these files must go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:13:28 +01:00
Leah Rowe
7585336b91 inject.sh: simplify kconfig scanning
Use fe_ with a new function, scankconfig, to do the
same thing. Not only is this simpler, it now also
operates on all coreboot configs for a given target,
whereas it previously only operated on the first one.

This is useful for cases where one config might use a
file that the other one does not; in practise, we don't
do this yet, but it's a theoretical possibility

Also: don't use the function check_defconfig, which is
now redundant and has been removed.

That function also conflicted with another function by
the same name in mk, but fortunately didn't cause an
issue in practise, due to how sh works; when vendor.sh
was used, it was without running the tree commands,
except under a separate lbmk instance.

So this is a simplification, a feature enhancement and
even a bug fix, all wrapped into one!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:05:45 +01:00
Leah Rowe
ef38333f8b lib.sh find_ex: Write sort errors to /dev/null
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:45:31 +01:00
Leah Rowe
c275f35e7e lib.sh x_(): Remove warning of empty args
It's completely unnecessary, and I forsee this
check breaking the build system at some point,
since some commands rely on the output of other
commands. Therefore, I've removed this check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:41:48 +01:00
Leah Rowe
17d826d3a9 lbmk: Replace err with much simpler implementation
The current implementation is insanely over-engineered,
and completely unnecessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:38:19 +01:00
Leah Rowe
f98e34a24d singletree/elfcheck: use fx_, not fe_
fe_ returns an error on the find command, but we rely
on the only error ever being our intentional exit, upon
discovering files.

in singletree, the directory being checked was already
checked first, so we know it's safe not to err on find;
and find not reporting an error if no files are found is
ok.

on elfcheck, it's very much the same thing. In fact, we
very much want it to return 0 if the directory doesn't
exist, or if files don't exist within it.

Therefore, use fx_ which is designed for this use-case.

Quick re-cap: fx and fe execute a given function name with
each line outputting by find as an argument, each time. It
is somewhat similar in scope to find's -exec command.

We use fe_ as shorthand in several places all over lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:33:02 +01:00
Leah Rowe
8ca06463eb rom.sh: Print the rom image path being generated
This message used to exist, and it's a nice feedback
for the user, to confirm that the build went OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:14:44 +01:00
Leah Rowe
dc9fe517cb rom.sh: Safer cprom()
Don't insert special files like GRUB keymaps after
copying to the final destination.

Instead, copy the tmprom to /tmp and operate on that,
in these instances.

This is less efficient, depending on the user's
configuration; if /tmp is on the same file system as
the user's xbmkpwd, it should be fine. However, the
actual performance hit isn't that bad in practise,
on most setups.

If the user's /tmp is a tmpfs, then that means using
tmpfs, but it's one image at a time. It should be OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:08:55 +01:00
Leah Rowe
2be8d1c798 rom.sh: specifically check keymaps in cprom()
"not seauboot" is a valid check at present, but if
i start supporting other arguments in the future,
this code would have to change.

therefore, i change it in advance, on that theory.

this new check is more technically correct. these
lines are triggered when inserting grub keymaps.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:53:43 +01:00
Leah Rowe
89a8cd4936 rom.sh: simplify mkseagrub()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:48:57 +01:00
Leah Rowe
c2182d8219 mk: simplify elfcheck()
fe_() called inside subshell, ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:51:04 +01:00
Leah Rowe
437ac2454c lib.sh: simplify singletree()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:40:08 +01:00
Leah Rowe
62ec3dac07 git.sh: move singletree() to lib.sh
it's also used by mk, to determine which build function
to use (build_project or build_targets).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:31:33 +01:00
Leah Rowe
6b247c93e2 mk: Fix bad error handling for gnu_setver
I mixed logical OR and AND by mistake. Oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe
ee8bb28ba2 GRUB: Mark E820 reserved on coreboot memory
See, coreboot bug report:

https://ticket.coreboot.org/issues/590

We hadn't noticed this for quite a while, since we always
just booted with iomem=relaxed when needing to run cbmem,
since in practise it was always combined with other tasks
that require access to lower memory.

GRUB currently matches coreboot's own mmap for cbmem, but
for example SeaBIOS marks cbmem as E820 reserved. Therefore,
this change replicates the SeaBIOS behaviour.

Without this patch, Linux needs to boot with iomem=relaxed
for cbmem access, for example when running ./cbmem -1

With this patch, cbmem is now accessible regardless. This
patch also prevents Linux from overwriting parts of CBMEM.

Thanks go to Paul Menzel, who wrote this GRUB patch.

Thanks also go to Nicholas Chin, who provided testing, all
the way from Coreboot 25.03 back to Coreboot 4.20. It seems
that this is just something the payloads have to handle.

This means that both SeaBIOS and GRUB no longer have this
bug, in Libreboot; now what remains is to replicate the
test with our U-Boot payload.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe
61ec396ef6 inject.sh: simplify extract_intel_me_bruteforce()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe
e4edc2194d inject.sh: Remove unnecessary check
_dest is already checked in the calling function fetch(),
after extract_tbfw() has been called.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe
f4057d7daa inject.sh extract_intel_me(): reduce indentation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe
b7ca59debe inject.sh: Move FSP extraction only to extract_fsp
Don't do FSP-specific extraction in extract_archive, as
that is not what the latter is for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:07 +01:00
Leah Rowe
eb882de94c inject.sh: tidy up intel me handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:43:38 +01:00
Leah Rowe
153dd76a82 inject.sh: tidy up the deguard command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:41:21 +01:00
Leah Rowe
428c46ca2b lib.sh: set -u -e in err()
Some parts of lbmk set +u +e, to be reset later on
under normal conditions upon exit. We must ensure
such level of integrity in err() as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:20:47 +01:00
Leah Rowe
20c8730858 lib.sh: Provide error message where none is given
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:53:02 +01:00
Leah Rowe
35265731c5 init.sh: Silence the output of git config --global
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:50:50 +01:00
Leah Rowe
5e3aaa1eb8 init.sh: Run git name/email check before init
Otherwise, it returns if init is already done, which
later leads to build errors in coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:49:30 +01:00
Leah Rowe
a3b5626f53 lib.sh: stricter xbmk_err check in err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:35:31 +01:00
Leah Rowe
51b2a1159d lib.sh: simplify err-not-set handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:31:08 +01:00
Leah Rowe
61e5fd1a0b lib.sh: Add warning if x_ is called without args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:28:22 +01:00
Leah Rowe
4020fb4328 lib.sh: simplify err()
Rely once again on err_, but still explicitly add an exit
just below, in case I made a mistake one day.

err() is essentially a trap that triggers in case I mess
up an error function, so that it doesn't reliably exit.

So, the idea is that everything calls err(), and err() is
almost never modified, or modified very carefully.

If error exits were ever broken, the result could be quite
unpredictable, so lbmk has very strict error handling, and
great care is taken to ensure that it does reliably exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:23:11 +01:00
Leah Rowe
b51846da6d init.sh: single-quote xbmklock in xbmk_lock()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:14:50 +01:00
Leah Rowe
8b7bd992f6 init.sh: define lock file in a variable instead
don't hardcode it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:12:23 +01:00
Leah Rowe
9611c19e7e init.sh: tidy up xbmk_child_exec()
make the command style more consistent, for example
relying on x_ inside a subshell to print the command
and arguments if a command failed.

this is a good style, and i'll probably use it in other
places on lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:03:34 +01:00
Leah Rowe
37ca0c90e1 lib.sh err: add missing redirect to stderr
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:18:33 +01:00
Leah Rowe
54291ebb72 lbmk: MUCH safer err function
Don't directly call a variable. Call a function that
checks the variable instead.

The new err function also checks whether an exit was
actually done, and exits 1 if not.

If an exit was done by the given function, but the exit
was zero, this is also corrected to perform an exit 1.

This fixes a longstanding design flaw of lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:13:42 +01:00
Leah Rowe
3f7dc2a55f lib.sh: rename errx to xmsg
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:17:23 +01:00
Leah Rowe
59c94664e3 lib.sh: Make x_ err if first arg is empty
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:14:09 +01:00
Leah Rowe
91bb6cbede lib.sh: Make err_ always exit no matter what
Always certainly redundant, since if -u -e isn't
set, it'll continue to exit anyway.

However, we want to be pedantic about this, since
the safety of lbmk relies entirely on this function
NOT misbehaving.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:10:24 +01:00
Leah Rowe
b19c4f8f67 inject.sh: tidy up TBFW handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:50:23 +01:00
Leah Rowe
439020fbda inject.sh: remove useless comment block
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:56 +01:00
Leah Rowe
6e447876cc init.sh: tidy up the python version check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:12 +01:00
Leah Rowe
7392f6fc8e init.sh: move non-init functions to lib.sh
these were missed in a previous cleanup

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:33:17 +01:00
Leah Rowe
7acec7a3a1 init.sh: simplify dependencies handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:29:19 +01:00
Leah Rowe
93ba36ae45 rom.sh: tidy up copyps1bios()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:19:17 +01:00
Leah Rowe
fc71e52fdf mk: tidy up xgccargs handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:15:00 +01:00
Leah Rowe
184871bc17 mk: remove useless code
this was added a few commits ago, but the previous commit
made me realise it's not needed at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:59 +01:00
Leah Rowe
b6a2dc4ea3 init.sh: tidy up pathdir creation
we can use remkdir here. it does the same thing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:36 +01:00
Leah Rowe
f5b2bdb886 mk: re-make gnupath/ after handling crossgcc
instead of deleting every file within

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:53 +01:00
Leah Rowe
1b7a9fd637 mk: tidy up check_cross_compiler
only initialise variables at the point they're needed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:06 +01:00
Leah Rowe
488d52e784 mk: re-make gnupath/ for each cross compiler
it could be that some were left over before, for some
reason. that isn't currently the case, but this will
avoid the possibility in future.

therefore, this is a preemptive bug fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:05:19 +01:00
Leah Rowe
c33467df1e mk: reduce indentation in check_cross_compiler()
we only call it in one place. the resulting code is still
quite clear.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:02:14 +01:00
Leah Rowe
aa4083443b mk: Allow use of x_ on prefix functions
Use this for the sha512sum command, on the main mk
script at the function check_project_hashes().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:30:37 +01:00
Leah Rowe
8f828e6cd3 mk: tidy up check_project_hashes() sha512sum check
the extra function isn't needed at all. awk can just
handle every line all at once.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:18:41 +01:00
Leah Rowe
7a2f33264d mk: simplify check_gnu_path()
the initial checks are unnecessary, since i always know
what arguments are being provided.

the -f check in the for loop is now an -x instead, more
efficient and complete.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:05:37 +01:00
Leah Rowe
46b968a6e8 inject.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:49:49 +01:00
Leah Rowe
5499ae66bd inject.sh: simplify extract_archive()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:35:28 +01:00
Leah Rowe
72f4412a52 inject.sh: simplified fsp extraction
we know that _dest is always what's set in the coreboot config,
without the ../../../ in it, so just copy both files in a single
function, and call the function twice.

if both files are done on the first call, the second call will
be skipped. if only the first file was done on the  first call,
running the download script again will skip the  first one, and
grab the second one.

this also avoids having to run the decat function twice, in most
cases, so it's a tiny optimisation.

this optimisation only works if both fsp files (s and m) are to
be extracted into the same directory, which is the case anyway,
and this will always be the case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:28:47 +01:00
Leah Rowe
bf569d2b4d inject.sh: Remove redundant code in copy_tbfw
We don't use the tbtmp variable anymore, in this function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:20:48 +01:00
Leah Rowe
8de0ed811f inject.sh: Stricter TBFW handling
Don't copy it until it has been padded properly.

Otherwise, erroneous padding would result in an error,
and who knows what would be left in vendorfiles/ ?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:17:21 +01:00
Leah Rowe
530e4109a2 init.sh: *Re-create* tmpdirs on parent instance
To make sure any old files are removed, always re-create.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:05:38 +01:00
Leah Rowe
498f5a26cc init.sh: Always create xbmklocal
If we're in a release work directory, TMPDIR is already
set, so the local ./tmp won't be created, which would
lead to an error.

Fix it by creating xbmklocal before checking TMPDIR.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:04:34 +01:00
Leah Rowe
00d22f2082 lbmk: Unified local ./tmp handling
Make it an absolute directory, relative to xbmktmp.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:01:19 +01:00
Leah Rowe
0f7b3691ab lib.sh: redirect find errors to /dev/null
this silences confusing error messages that the user
sees on the screen, that are actually benign, and it
will thus reduce the number of people who ask questions
on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:41:20 +01:00
Leah Rowe
7fadb17fd9 lib.sh: Fix bad touch command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:36:43 +01:00
Leah Rowe
0b09d97073 inject.sh: Only build nvmutil once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:35:48 +01:00
Leah Rowe
308df9ca40 inject.sh: always re-build nvmutil
it's not a lot of code, and takes less than a second.

the previous change uses x instead of ?, but this would
cause an error if the nvmutil was already built, because
the makefile might cause a build to be skipped.

therefore, force a re-build to mitigate the error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:28:14 +01:00
Leah Rowe
44a1cc9ef8 util/nvmutil: use x, not ?, for random characters
A user reported that '?' causes an error on zsh. See:

https://codeberg.org/libreboot/lbmk/issues/261

For example:

./mk inject libreboot-XXXXXX.tar.xz setmac ??:??:??:??:??:??

The user got:

 zsh: no matches found: ??:??:??:??:??:??

The mitigation here is to double-quote, e.g.:

./mk inject libreboot-XXXXXX.tar.xz setmac "??:??:??:??:??:??"

However, a lot of people won't do that. Therefore, I will
retain the current behaviour but support x/X for randomness.

Now lbmk uses x by default, instead. I will now update the
documentation, accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:23:10 +01:00
Leah Rowe
a17875c345 lib.sh find_ex: explicitly create the tmp file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:57:39 +01:00
Leah Rowe
0ffaf5c733 init.sh: Explicitly create the xbmktmp directory
mktemp would normally do it, but we must not rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:33:02 +01:00
Leah Rowe
fcc52b986e init.sh: unified handling of ./tmp
not to be confused with /tmp

we use ./tmp inside the lbmk work directory, for large files,
because /tmp might not be very big, or might be a tmpfs

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:32:01 +01:00
Leah Rowe
47762c84ad lib.sh: add fe_ which is fx_ but err on find
In the mk script, we need fx_ to not return errors on the
find command, since it's searching a bunch of directories
where some of them may not exist.

All other instances where fx_ is used, must return an error
if the directory being searched doesn't exist.

For this, fe_() is introduced, which does the same as fx_
but with this much stricter check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:25:11 +01:00
Leah Rowe
d18d1c2cae lbmk: unified execution on find commands
We have a lot of places in lbmk where the output of find is
used, and then some function is executed on the result.

This is messy, and bloats several of these functions.

Now this is unified, into a new function: fx_

What fx_ does is execute a given function, for each result
found, with the arguments for a find command appended.

For example:

find -name ".git"

If you wanted to do: foo "$arg"

Where "arg" is a search result from find, and you wanted
to execute "foo" on each one, you would do:

fx_ foo -name ".git"

The find utility does have an -exec feature, but I've found
that it only works for executables, not functions.

fx_ does not return errors, so "foo" in this example
would have to do its own error handling.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:02:31 +01:00
Leah Rowe
773d2deaca NEW MAINBOARD: Dell Precision T1700 SFF and MT
This is similar to the 9020SFF, but this board has ECC support.
However, the native raminit isn't used here, even though it is
otherwise compatible, because the native init doesn't do ECC yet.

The broadwell mrc.bin has ECC support, which is also used on the
HP EliteBook 820 G2. The MRC for broadwell can be used on haswell
boards such as the T1700.

Add both the SFF and MT variants. Since these are identical to the
9020 variants, except for slightly different PCH enabling ECC, we
can just re-use the 9020 port without issue.

We *could* add a variant to coreboot, for T1700, but there is not
really any pressing need. It is simply the 9020sff/mt with mrc.bin

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 17:18:55 +01:00
Leah Rowe
9b11e93686 mk: include rom.sh directly
remove it from mkhelper files, because rom.sh doesn't
initialise any variables globally, except one that
never changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 11:20:55 +01:00
Leah Rowe
1f7e4b35cb mk: Download vendorfiles before building release
Do it just after creating the src archive. This way,
everything is downloaded all at once.

Otherwise, a momentary lapse of internet uptime will
cause a release build to fail later on, and one of
lbmk's flaws is that this would then mean you must
re-build from scratch.

If we assume that the internet is working within a
short period of time, then this change would mitigate
that possibility. If something did happen during tar
archive creation, that's a much shorter amount of time
that is "wasted".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:56:14 +01:00
Leah Rowe
acb0ea202f lib.sh: Simplify rmgit()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:52:38 +01:00
Leah Rowe
15b76bc202 lib.sh: support multiple arguments in remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:39 +01:00
Leah Rowe
f3ae3dbbbe lib.sh: simplify remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:17 +01:00
Leah Rowe
6c4d88f268 move x_() to lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:24:11 +01:00
Leah Rowe
2ae565ba93 init.sh: move setvars/err_ to lib.sh
these functions make more sense in lib.sh

i made mk link lib.sh first, so that the
functions on init.sh can still use them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 05:54:36 +01:00
Leah Rowe
c073ee9d4f Restore SeaBIOS 9029a010 update, but with AHCI fix
I fixed the AHCI bug, with a patch that I wrote. It works by
restoring the old SeaBIOS AHCI initialisation behaviour, whereby
the AHCI controller is enabled from its current state; the patch
that broke AHCI in coreboot (tested on ThinkPad T420), changed
AHCI initialisation behaviour so that the controller's state is
first reset, prior to enablement.

However, my patch also retains the new AHCI initialisation
behaviour, when a CSM is in use. The AHCI reset patch was done,
by the author, specifically for SeaBIOS in CSM mode, so it makes
sense to only change the behaviour conditionally according to that.

This reverts commit 8245f0b321.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 02:24:07 +01:00
Leah Rowe
8245f0b321 Revert "seabios: bump to rev 9029a010, 4 March 2025"
This reverts commit a08b8d94fc.

From #libreboot IRC today:

07:02 <irys> ooh this is fun. seabios commit 8863cbbd15a73b03153553c562f5b1fb939ad4d7 (ahci: add controller reset) breaks ahci entirely on t420
07:05 <irys> cbmem console on that seabios commit has a timeout then "AHCI/0: device not ready"
07:07 <irys> AHCI works fine if i change config/seabios/default/target.cfg to use the immediate previous seabios commit (df9dd418b3b0e586cb208125094620fc7f90f23d)
07:07 <irys> works in grub payload either way though
07:31 <irys> here, `cbmem -c` after booting the broken rev: https://0x0.st/84oQ.log
07:31 <irys> compared to the working one https://0x0.st/84o1.log
07:33 <irys> i can't report to upstream myself *right now* but i figure you might want to know about this leah

I have downloaded those logs locally for reference, so that an upstream
report can be made to SeaBIOS. For the purposes of this Libreboot commit,
the diff of the logs is as follows (diff -u broken.log working.log):

Taking each diff line out of the log, the relevant entries
seem to be:

Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: Set transfer mode to UDMA-6
+Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: registering: "AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)"

-WARNING - Timeout at ahci_port_setup:477!
-AHCI/0: device not ready (tf 0x80)
-All threads complete.

-2. Payload [memtest]
+2. AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)
+3. Payload [memtest]

-Space available for UMB: c7000-eb800, f5880-f5ff0
-Returned 16777216 bytes of ZoneHigh
+drive 0x000f5fa0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=250069680
+Space available for UMB: c7000-eb800, f5880-f5fa0
+Returned 16773120 bytes of ZoneHigh

Therefore, the revision will be reverted back for now. It was
only about 8 additional patches imported in the update anyway.
2025-05-01 14:30:14 +01:00
Leah Rowe
4c50157234 coreboot/t420_8mb: add missing txtmode config
Reported by irys on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-01 14:29:22 +01:00
Leah Rowe
f21749da8b Libreboot 25.04 Corny Calamity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 12:28:46 +01:00
Leah Rowe
bb5f5cd576 add pico-sdk backport patch fixing gcc 14.x
src/rp2_common/boot_stage2/boot2_w25x10cl.S:142: Error: junk at end of line, first unrecognized character is `0'
src/rp2_common/boot_stage2/boot2_w25x10cl.S:145: Error: garbage following instruction -- `beq 00b'

This should also fix it on Debian sid Experimental, where I'm testing
with GCC 15 and other bleeding edge dependencies.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 11:11:03 +01:00
Leah Rowe
4f77125066 coreboot/fam15h: update submodule for nasm
i forgot to in the last commit, but it didn't matter because
it just meant that coreboot.git's own download logic kicked
in as a fallback. however, it's better to rely on libreboot's
build system for this, since it has redundancy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:38:07 +01:00
Leah Rowe
0f2202554a coreboot/fam15h: update nasm to 2.16.03
this fixed kgpe-d16 build errors on gcc 15 when tested
on debian sid (with gcc-15 installed from experimental)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:32:49 +01:00
Leah Rowe
2009c26f0a serprog: Remove pico2 support for the time being
Many users report bugs, so I'm reverting lbmk back to only
supporting the rp2040 dongles for the time being. The
documentation will be updated to reflect this.

Pico2 support will be re-added at a later date, once more
testing has been done, and fixes made if necessary.
2025-04-30 02:35:34 +01:00
Leah Rowe
a08b8d94fc seabios: bump to rev 9029a010, 4 March 2025
This brings in the following improvements from upstream:

* 9029a010 kconfig: fix the check-lxdialog.sh to work with gcc 14+
* 8863cbbd ahci: add controller reset
* df9dd418 update pci_pad_mem64 handling
* a4fc1845 add romfile_loadbool()
* a2725e28 drop acpi tables and hex includes
* 35aa9a72 drop obsolete acpi table code
* 1b598a1d usb-hid: Support multiple USB HID devices by storing them in a linked list

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:52:56 +01:00
Leah Rowe
342eca6f3d update untitled
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:26:34 +01:00
Leah Rowe
b0a6d4711a coreboot413: add alper's fix to cbfstool for gcc15
otherwise, it won't compile on gcc 15 (pragma fix from
earlier on, used on the other coreboot trees)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:59:39 +01:00
Leah Rowe
628ae867c9 flashprog: bump to rev e060018 (1 March 2025)
This brings in the following upstream changes:

* e060018 flashchips: Explicitly zero-initialize in .qpi_read_params
* ff9526b dediprog: Use dual-i/o default only for SF600Plus-G2
* 5a72cfb flashchips: Fix block-protection bits for 4BA Puya chips
* 284d55b flashchips: Add WPS bit description for GD25Q128C
* 37e07a8 flashchips: Add missing QE bit descriptions
* 3646b18 flashchips: Add GigaDevice GD25LF128E 166MHz, 1.8V part
* d4eb532 flashchips: Add GigaDevice GD25LF80E..GD25LF64E 166MHz, 1.8V parts
* 38d037f flashchips: Add GigaDevice GD25LB512MF..GD55LB02GF 1.8V parts
* 1da0293 flashchips: Add GigaDevice GD25LB512ME..GD55LB02GE 1.8V parts
* 6d728e6 flashchips: Add GigaDevice GD25B512MF..GD55B02GF 3.3V parts
* 493a4e0 flashchips: Update and split GD25Q256D entry
* 648dfdc spi25: Fix cosmetic debug-print error due to unitialized buffer
* cfd607d layout: Show a warning if no region is included
* ec287e2 ich_descriptors_tool: Change region name EC/BMC -> EC_BMC
* 39a4f7d sb600spi: Request more `lspci` details
* 404529d memory_bus.c: Add missing copyright notice
* fbea0fe udev rules: Restore mode/group configuration
* c90d6c4 flashchips: Add some 25LC series EEPROMs
* ee8cf1c Provide no-op probe function, always returning 1
* 4e6155a spi25: Add SPI25_EEPROM enum and handle < 3-byte addresses
* 9512c9c Add missing copyright notices to recently created files
* 06fbccc flashchips: Add GigaDevice GD25LB256E 1.8V part
* bc001da flashchips: Add some GigaDevice GD25L*256 1.8V parts
* 7d0f556 flashchips: Update GigaDevice 1.8V family up to GD25LQ128
* 7f8c12d flashchips: Add GigaDevice GD25LQ20, update family up to GD25LQ16
* 565471c flashchips: Add GigaDevice GD25B512ME..GD55B02GE 3.3V parts
* 6ee2f89 flashchips: Update GigaDevice GD25Q/B/R 128Mbit, 3.3V parts
* c230c69 flashchips: Add remaining Puya PY25Q..H 3.3V parts
* 06e0264 flashchips: Add Puya PY25Q..H family up to PY25Q128H
* fe21b43 flashchips: Add remaining P25Q..H family 3.3V chips
* 1c5d829 flashchips: Add Puya P25Q40SH, P25Q80SH, P25Q16SH 3.3V parts
* b0cae5e flashchips: Add Puya P25Q06H, P25Q11H, P25Q21H 3.3V parts
* b09136b flashchips: Add Puya P25Q05..16H 3.3V parts
* ed8b82c flashchips: Add Fudan FM25Q128 3.3V part
* 4a35134 flashchips: Add Fudan FM25Q08A 3.3V part
* 7f7bffa flashchips: Add Fudan FM25Q64, update FM25Q08..Q32
* c591518 flashchips: Add Fudan FM25Q02/Q04 3.3V parts
* fea6e16 flashchips: Add Winbond W25Q16JV_M (DTR version)
* 56d727e flashchips: Add newer gen. XTX Tech. XT25F..F 3.3V parts
* c64a803 flashchips: Add XTX Tech. XT25F..B 3.3V family
* 46e4209 flashchips: Add XTX Tech. XT25F02E/04D/08B 3.3V parts
* 6bc88e7 flashchips: Add Boya/BoHong BY25Q32/64/128 3.3V variants
* 3cddff4 flashchips: Complete Boya/BoHong BY25D family
* 34e3de6 flashchips: Add Zetta Device ZD25LQ64/128 1.8V parts
* f050370 selfcheck: Check dummy-cycle settings when QPI is advertised
* d40037a selfcheck: Check for WP functions when BP bits are given
* 2a1036b flashchips: Fix up GD25Q128C write-protect support
* d4e41d3 flashchips: Add SST26VF080A
* 04c1cf7 Add .envrc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:43:45 +01:00
Leah Rowe
5e96db5a2b further gcc-15 fix for gmp on -std=23
the fix in the previous revision wasn't being applied
properly, because the build system of gmp generates
a conftest.c file, and the entry being made for it was
actually coming from this place in the configure file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 23:21:59 +01:00
Leah Rowe
9a9cd26b2d coreboot/default and fam15h: gmp fix, gcc15 hostcc
gcc 15 defaults to -std=c23, but the older gcc was
using -std=c17. The new c23 breaks GMP, so let's add
a patch from upstream (GMP project) to fix it.

this has been done to both coreboot trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 22:16:09 +01:00
Leah Rowe
80007223c8 lib.sh: Provide printf for mktarball
Just to let the user know lbmk hasn't died.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 19:51:15 +01:00
Leah Rowe
a16c483e5f Merge pull request 'coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler' (#318) from alpernebbi/lbmk:coreboot-fam15h-gcc15 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/318
2025-04-29 17:13:45 +00:00
Alper Nebi Yasak
685685ab0e coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler
Building the fam15h tree results in one of the same nonstring errors
we also had when building the default tree. Copy the relevant patch from
the default tree, while dropping a hunk that we don't need in this old
version.

Another build error is about bool being a reserved keyword now:

  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: error: 'bool' cannot be used here
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |             ^~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: note: 'bool' is a keyword with '-std=c23' onwards
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:18: error: expected identifier or '(' before 'struct'
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |                  ^~~~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c: In function 'mkcond_expr':
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7708:19: error: expected ')' before ',' token
   7708 |         bool(state, test);
        |                   ^
        |                   )
  [...]

Fix that by adding a patch that renames the function to bool_().

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 19:54:12 +03:00
Leah Rowe
02110f2bc1 Merge pull request 'coreboot: Add patch to fix build with GCC 15 as host compiler' (#317) from alpernebbi/lbmk:coreboot-gcc15-nonstring into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/317
2025-04-29 16:31:07 +00:00
Alper Nebi Yasak
5ad1de3931 coreboot: Add patch to fix build with GCC 15 as host compiler
Building coreboot host tools with GCC 15 results in build errors:

  In file included from .../lbmk/src/coreboot/default/util/cbfstool/console/console.h:7,
                   from .../lbmk/src/coreboot/default/src/commonlib/fsp_relocate.c:3:
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:170:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    170 |         [BIOS_EMERG]   = "EMERG",
        |                          ^~~~~~~
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:171:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    171 |         [BIOS_ALERT]   = "ALERT",
        |                          ^~~~~~~
  [...]
  ../cbfstool/common.c: In function 'bintohex':
  ../cbfstool/common.c:195:43: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (17 chars into 16 available) [-Werror=unterminated-string-initialization]
    195 |         static const char translate[16] = "0123456789abcdef";
        |                                           ^~~~~~~~~~~~~~~~~~

Add a patch that marks the latter with the "nonstring" attribute, and
disable the warning for the former because I couldn't figure out how to
add that attribute there.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 17:45:46 +03:00
Leah Rowe
9e7bceb7fa Merge pull request 'seabios: Fix malloc_fn function pointer in romfile patch' (#313) from alpernebbi/lbmk:seabios-romfile-malloc-fptr into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/313
2025-04-29 13:55:18 +00:00
Leah Rowe
686e136f15 Merge pull request 'dependencies/debian: Fix libusb package name' (#315) from alpernebbi/lbmk:debian-libusb-dependency into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/315
2025-04-29 13:55:06 +00:00
Alper Nebi Yasak
6f120f0158 dependencies/debian: Fix libusb package name
The Debian package for libusb is "libusb-1.0-0". Fix the typo in the
list which is missing the suffix. While we're here, also fix a line
continuation.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:46:24 +03:00
Alper Nebi Yasak
35c853f8b3 seabios: Fix malloc_fn function pointer in romfile patch
One of our SeaBIOS patches causes build errors with GCC 15:

  src/romfile.c: In function 'romfile_loadfile_g':
  src/romfile.c:65:18: error: too many arguments to function 'malloc_fn'; expected 0, have 1
     65 |     char *data = malloc_fn(filesize+add_len);
        |                  ^~~~~~~~~ ~~~~~~~~~~~~~~~~
  src/romfile.c: In function 'romfile_loadfile':
  src/romfile.c:88:50: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
     88 |     char *data = romfile_loadfile_g(name, psize, &malloc_tmphigh, 1);
        |                                                  ^~~~~~~~~~~~~~~
        |                                                  |
        |                                                  void * (*)(u32) {aka void * (*)(unsigned int)}
  src/romfile.c:55:28: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     55 |                    void *(*malloc_fn)(), int add_len)
        |                    ~~~~~~~~^~~~~~~~~~~~
  In file included from src/romfile.c:8:
  src/malloc.h:42:21: note: 'malloc_tmphigh' declared here
     42 | static inline void *malloc_tmphigh(u32 size) {
        |                     ^~~~~~~~~~~~~~
  make: *** [Makefile:142: out/src/romfile.o] Error 1
  make: *** Waiting for unfinished jobs....
  src/optionroms.c: In function 'vgarom_setup':
  src/optionroms.c:468:60: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
    468 |     void *mxm_sis = romfile_loadfile_g("mxm-30-sis", NULL, &malloc_low, 0);
        |                                                            ^~~~~~~~~~~
        |                                                            |
        |                                                            void * (*)(u32) {aka void * (*)(unsigned int)}
  In file included from src/optionroms.c:18:
  src/romfile.h:17:34: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     17 |                          void *(*malloc_fn)(), int add_len);
        |                          ~~~~~~~~^~~~~~~~~~~~
  In file included from src/optionroms.c:16:
  src/malloc.h:30:21: note: 'malloc_low' declared here
     30 | static inline void *malloc_low(u32 size) {
        |                     ^~~~~~~~~~
  make: *** [Makefile:141: out/src/optionroms.o] Error 1
  make: Leaving directory '/tmp/lbmk/src/seabios/default'

This is because the function pointer defined as `void *(*malloc_fn)()`
refers to a function that takes no arguments, unlike `malloc_tmphigh`
which takes an unsigned int. Add the missing argument type.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:37:14 +03:00
Leah Rowe
d8b0e74998 init.sh: fix yet another double quote for dotfiles
i missed this one, in another recent revision

double-quote because of the dot, for bash users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 14:11:56 +01:00
Leah Rowe
780844112a Merge pull request 'Update U-Boot to v2025.10' (#305) from alpernebbi/lbmk:uboot-v2025.04 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/305
2025-04-29 12:50:55 +00:00
Alper Nebi Yasak
1265927ca3 u-boot: gru: Disable INIT_SP_RELATIVE
Recently, gru boards were migrated to use common stack addresses with
U-Boot commit 5e7cd8a11995 ("rockchip: Use common bss and stack
addresses on RK3399") and commit 49f8131e5594 ("rockchip: rk3399-gru:
Use TPL with common bss and stack addresses"). This is done with the
ROCKCHIP_COMMON_STACK_ADDR config.

With POSITION_INDEPENDENT, INIT_SP_RELATIVE defaults to enabled as well.
However, ROCKCHIP_COMMON_STACK_ADDR selects HAS_CUSTOM_SYS_INIT_SP_ADDR,
which depends on INIT_SP_RELATIVE being disabled. So this results in a
configuration warning:

  WARNING: unmet direct dependencies detected for HAS_CUSTOM_SYS_INIT_SP_ADDR
    Depends on [n]: ARM [=y] && ARCH_KIRKWOOD [=n] || ARC [=n] || ARM [=y] && !INIT_SP_RELATIVE [=y] || MIPS [=n] || PPC [=n] || RISCV [=n]
    Selected by [y]:
    - ROCKCHIP_COMMON_STACK_ADDR [=y] && ARM [=y] && ARCH_ROCKCHIP [=y] && SPL_SHARES_INIT_SP_ADDR [=y]

I'm not sure if adhering to the Rockchip values means we can't be
position-independent. Disabling INIT_SP_RELATIVE still appears to keep
my kevin board working, so let's do that for now.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:11 +03:00
Alper Nebi Yasak
5bea1fade9 u-boot: arm64: Expand our modified defconfigs to full configs
Run `./mk -l u-boot` to regenerate full configs from our new defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:01 +03:00
Alper Nebi Yasak
fd56d8ada1 u-boot: arm64: Merge our modifications into new defconfigs
Apply our preserved changes to the new U-Boot defconfigs. Upstream
rearranged memory layouts for Rockchip boards to a unified layout, which
got rid of CUSTOM_SYS_INIT_SP_ADDR and HAS_CUSTOM_SYS_INIT_SP_ADDR, and
will need a change to a related INIT_SP_RELATIVE later.

Normalize the positions of each line in the config by regenerating the
defconfig by `./mk -l u-boot` and then `./mk -s u-boot`, so that the
diff looks all green when we actually expand it to the full config.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:28:08 +03:00
Alper Nebi Yasak
ed9ddd7415 u-boot: arm64: Add new upstream defconfigs
Copy over the new upstream defconfigs from the refreshed U-Boot trees,
so we can fold our modifications into them. Manually done, but like:

    do_defconfig() {
        ours="$1"
        theirs="$2"
        tree="$3"

        cp src/u-boot/${tree}/configs/${theirs}_defconfig \
           config/u-boot/${ours}/config/default
    }

    do_defconfig  amd64coreboot   coreboot64        x86_64
    do_defconfig  i386coreboot    coreboot          x86
    do_defconfig  gru_bob         chromebook_bob    default
    do_defconfig  gru_kevin       chromebook_kevin  default
    do_defconfig  qemu_arm_12mb   qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:27:32 +03:00
Alper Nebi Yasak
b1fa44858c u-boot: arm64: Rebase to v2025.04
Set the U-Boot revision to the commit hash for v2025.04, and rebase the
patches for the default U-Boot tree to accommodate for upstream changes:

 - The SPL/TPL/VPL phases are being unified under the xPL name, so
   there's a config rename.
 - Some test macros were renamed, for the video-related patches.
 - Add some missing hunks for video damage series.
 - Upstream Makefile adds another argument to the binman call.
 - The SWIG related patch is merged upstream, drop it.

I'm not sure if src/u-boot/* directories are regenerated on new builds,
so it may be necessary to remove them manually after applying this.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:58 +03:00
Alper Nebi Yasak
976fc6890a u-boot: arm64: Save our modifications to the upstream defconfigs
Run diffconfig from Linux to track our modifications to the old upstream
defconfigs, so we can apply them to the new ones. Restore the original
defconfigs to highlight our changes here, and upstream changes in the
next commit. Done manually, but something like:

  do_diff() {
      ours="$1"
      theirs="$2"
      tree="$3"

      diffconfig \
          src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default \
          >config/u-boot/${ours}/config/diffconfig

      cp src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default
  }

  do_diff amd64coreboot    coreboot64        x86_64
  do_diff i386coreboot     coreboot          x86
  do_diff gru_bob          chromebook_bob    default
  do_diff gru_kevin        chromebook_kevin  default
  do_diff qemu_arm64_12mb  qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:22 +03:00
Alper Nebi Yasak
418570a617 u-boot: arm64: Turn configs into defconfigs
Run `./mk -s u-boot` to convert our configs into defconfigs, so we can
keep our changes to the old upstream defconfigs and re-apply them to the
new upstream defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:12 +03:00
Leah Rowe
093a86d9c0 init.sh: don't use eval to read version files
it's not necessary, and was the cause of a recent issue,
which i mitigated, but why mitigate it?

prevent bugs. don't use eval unless absolutely necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 12:01:13 +01:00
Leah Rowe
3045079947 init.sh: use backslash for dotfiles in eval
see:

commit f0c629dcc6
Author: Leah Rowe <leah@libreboot.org>
Date:   Sat Apr 12 13:51:49 2025 +0100

    lib.sh: write version/versiondate to dotfiles

and this bug report:

https://codeberg.org/libreboot/lbmk/issues/284

The report indicates that the above commit broke bash,
when sh (on the user's system) is bash.

I know sometimes when using bash, I need to use the
back slash when dealing with dots, e.g. when grepping
something.

Also double quote references to dotfiles, e.g. when
directing the output of printf.

I never noticed the issue myself, since I use dash.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:53:32 +01:00
Leah Rowe
da108d1c04 mk: Don't run mkhelpers if mode is set
If the mode string is empty, then it's a build command.

See commit:

commit b1ea416575
Author: Leah Rowe <leah@libreboot.org>
Date:   Wed Apr 23 03:54:08 2025 +0100

    mk: remove mkhelp() and use x_() instead

This commit removed the following check:

If mode isn't set, run an mkhelper, otherwise don't.

Because this simplification removed that behaviour,
running e.g. "./mk -m coreboot x200_8mb" would result
in the mkcorebootbin function being executed, which is
normally putting the coreboot rom together.

Since it wasn't built in this case, an error is thrown.
This change therefore restores the previous behaviour,
fixing the bug.

First reported in this error report:
https://codeberg.org/libreboot/lbmk/issues/306

This commit fixes the issue.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:25:39 +01:00
Leah Rowe
71a58a38ab mk: condense main() again
i prefer it this way. this reverses the change that
i made a few revisions ago

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:07:25 +01:00
Leah Rowe
f3882b9bf2 init.sh: make git name/email error more useful
instruct the user what to do in these conditions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:02:04 +01:00
Leah Rowe
9cebda333d init.sh: move git name/mail check to xbmk_git_init
the command -v check has been removed, since this function
already calls git immediately, which would accomplish the
same thing since that causes an error if git isn't there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:54:43 +01:00
Leah Rowe
ea081adc4c init.sh: tidy up the git name/email check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:51:56 +01:00
Leah Rowe
3292bded69 mk: make main() more readable
now that main is so small, some of the condensed
lines can be loosened up.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:46:30 +01:00
Leah Rowe
97a5e3d15e mk: move git check to init.sh xbmk_set_version
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:44:11 +01:00
Leah Rowe
11cd952060 init.sh: tidy up xbmk_init()
more version-related code moved to xbmk_set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:41:05 +01:00
Leah Rowe
f6c5c8d396 mk: move git_init to init.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:35:45 +01:00
Leah Rowe
ec1c92238c init.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:23:37 +01:00
Leah Rowe
e009f09e7f init.sh: clean up setvars
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:11:52 +01:00
Leah Rowe
9ec7215340 init.sh setvars: make err a printf for eval
setvars is always invoked with eval, so make the error
condition a message for eval, to ensure that it is reliably
handled, in case of error condition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:07:52 +01:00
Leah Rowe
18ad654a1f init.sh: merge xbmk_child_init with xbmk_init
the for loop at the end of xbmk_init does essentially
the same thing. adapt accordingly, and merge.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:02:26 +01:00
Leah Rowe
1526820247 init.sh: split xbmk_child_init into functions
one function, for one task. skeleton functions for
performing multiple tasks. that is the basic coding
style guideline for lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:47:28 +01:00
Leah Rowe
0280cd4c0e init.sh: move parent fork to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:28:13 +01:00
Leah Rowe
a0e1d42ff7 init.sh: Provide more complete error info
On initialisation of the child instance, ./mk is
executed, but an error from it won't reveal what
command was actually executed.

This change makes that the case, since x_ does
print the command that caused an error.

This is useful for debugging. However, we don't
want x_ to cause a real exit, because we still
need to handle the lock file from the parent
instance.

Therefore, the first child instance is executed
inside a subshell, and xbmk_rval is set if that
subshell returns non-zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:18:59 +01:00
Leah Rowe
a8f0623efb update uefitool to rev a072527, 26 Apr 2025
This fixes a problem, in that CMake 4.0 dropped compatibility
with CMake version 3.5; UEFIExtract/CMakeLists.txt had the line:

CMAKE_MINIMUM_REQUIRED(VERSION 3.1.0 FATAL_ERROR)

This is lower than 3.5.

The new version has this:

CMAKE_MINIMUM_REQUIRED(VERSION 3.22)

Which is higher than 3.5, in terms of version number.

This brings in the following upstream changes:

* a072527 Convert other uses of 0xABCD back to ABCDh
* a19aead Revert "Update hexadecimal numbers output format from ABCDh to 0xABCD" due to breaking downstream tools
* 7752279 Improve region access settings info for Intel v2 descriptor
* 6f6debb Add volume header info on NumBlocks and Length used to calcualte alternative size of it
* f64ba09 Minor fix for embedded QHexView on Windows
* 2b23bbd Implement Apple developer signing for macOS builds
* 9cc9518 Update hexadecimal numbers output format from ABCDh to 0xABCD
* 73d07cd Add Kaitai-based parser for Dell DVAR store
* c8b7151 Fix minor bug while presenting the EOF elemement of AppleSysF store
* 892111a Add new fields into Intel Microcode header
* 7cea8ee Remove outdated definition of FLASH_PARAMETERS
* c38ed92 Add missing header comments to goto*dialog.h
* 22bb757 Remove PATH_MAX from realpath
* d61d759 Make sure to wrap all uses of kaitai::kstream into try-catch blocks
* 7ef3719 Add initial support for Insyde H2O FlashDeviceMap rev4
* 97a85f9 Add Microsoft LZMA section GUID
* a077743 Bump version numbers
* 07742a5 Update GUID database
* a12be6b Address review comments
* 9719b0c Update copyright and authors in About UEFITool window
* fbf6afd Expand Type column of the report to fit new FlashDeviceMap store and entry types
* 3cb5dc0 Add SLIC pubkey and marker parsers
* fd0faea Add Phoenix CMDB parser
* 01e2e08 Add FFS volume parser for non-AMI NVRAM areas
* 4e2a8f6 Add Intel uCode parser
* 58366f4 Add Insyde Flash Device Map parser
* b98edf6 Add Phoenix EVSA parser
* f989fdf Add Phoenix FlashMap parser
* 4e600eb Add Apple SysF/Diag parser
* 2d6eaa9 Add EDK2 FTW parser
* ca7d4ca Add Insyde FDC parser
* 34904bd Add KaitaiStruct parsing of Phoenix VSS2
* 489b85f Rewrite VSS and VSS2 NVRAM variable parsers in KaitaiStruct
* 2661b8f Remove manual NVRAM parsing, add EDK2 VSS parser written in KaitaiStruct
* d91115f Also sign UEFIFind and UEFIExtract for macOS
* 0fae05c Add adhoc signature to UEFITool on macOS
* 5e6a1c7 Fix CFBundleIdentifier in UEFITool Info.plist
* 8d7e01c Make sure to initialize counterUncData
* b1ad055 Bump version numbers
* 7dd9014 Update GUID database
* 4e3fa58 Update QHexView, build it as a library for Qt6 builds
* 369f101 Enable building ffsparser_fuzzer during CI/CD, improve readUnaligned to silence Clang UBSAN
* ff42cec UEFIExtract: add support for extracting uncompressedData for tree items that have it
* c94f78a Add missing common/LZMA/SDK/C/7zWindows.h
* b5756f9 Revert old patch from common/LZMA/SDK/C/CpuArch.c
* 65fb4a8 Update LZMA SDK to 24.09
* e66bc7d Apply a small patch to common/zlib/gzguts.h to fix a build issue in macOS
* dcf21fa Update built-in zlib to 1.3.1
* 0af36bd Fix an issue with kaitai_regenerate.sh creating backup files on modern macOS
* fd76e89 Update README.md
* 427d8ec Update README.md
* a824260 Add MX77L12850F
* a777f1f Update main.yml
* 5f23377 Update main.yml
* 932120c Use x64 macos-13 runner for FreeBSD in main.yml
* a8c008c Update macos-12 to macos-latest in main.yml
* 6b853f8 Fix SonarCube Scan action version
* 66565a5 Try using new SonarCube scan action
* 371448d Enable long file paths for UEFIFind
* b0cd7fe Update upload-artifacts action to v4
* 4b868bb Remove CodeQL and PVS-Studio from main.yml
* 214b356 Add AMIC A25LQ64 to internal JEDEC ID database
* 0030ea9 Fix findPattern logic when pattern is at the end of the data
* 3441255 fix: add qt version limit to setDesktopFileName
* 941ee6c Set desktop file name to fix the missing icon when running under Wayland
* c550853 Defined ACCESSPERMS for musl
* bf93a5e Bump version numbers
* d03a8f2 Fixing FreeBSD action
* 0a88da1 Update guids.csv
* 6f9a4c0 Fix off-by-one error in parsing IFWI partition table
* e0b1e02 Update main.yml
* 161c697 Update main.yml
* 573452e Update main.yml
* 166c797 add Micron XM25RH128C
* 0e11189 fix a few misspellings
* daf5851 Update README.md
* 1cba371 Update guids.csv
* 4992474 Fix CPD Extension offset (reverts 29915ca)
* 29915ca Fix CPD Manifest's partition offset

The ACCESSPERMS patch has been removed, because upstream
already dealt with this. Libreboot had made the same fix
independently, without realising that upstream also did.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 20:33:12 +01:00
Leah Rowe
c698972130 rename include/vendor.sh to inject.sh
this matches cbmk, where inject.sh is the file name

this will make future cherry-picks of lbmk->cbmk easier

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:58:29 +01:00
Leah Rowe
24e488aae5 lib.sh: move _ua to the xbmkget function
don't declare it globally, because it's only used here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:30:38 +01:00
Leah Rowe
6779d3f991 move variables out of init.sh to others
move them where they are used, or if they are used
in many places, move them to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:28:49 +01:00
Leah Rowe
848159fa0e lib.sh: rename vendor_checksum
rename it to bad_checksum, so that its use makes more sense

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:21:22 +01:00
Leah Rowe
1de77c6558 lib.sh: move singletree() to git.sh
it is primarily used there, and then in mk,
but only after git.sh is sourced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:19:36 +01:00
Leah Rowe
703fe44431 lib.sh: move cbfs() to rom.sh
it is only ever used there, so move it there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:16:40 +01:00
Leah Rowe
b57952e90d re-split include/init.sh to lib.sh
move non-init functions to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:10:01 +01:00
Leah Rowe
8ecb62c662 rename include/lib.sh to init.sh
this is in prep for the next change, where non-init
functions will be moved to another file, again named
include/lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:04:03 +01:00
Leah Rowe
ce4381169f lib.sh: introduce more top-down function order
a lot of init code was handled outside of any function. the
coding style used in the rest of the build system has now
been introduced, with xbmk_init being the main function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 18:35:41 +01:00
Leah Rowe
15b64cfebe mk/git.sh: remove tree_depend variable
this was used alongside the xgcc linking, so that coreboot
trees could specify that another tree was to be downloaded.

since this variable will no longer be used, it should be
removed, to avoid dead code bloat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 12:02:55 +01:00
Leah Rowe
9b8179c0e5 git.sh: remove unused xgcc linking feature
the "xtree" variable is used by projects such as u-boot,
to export a CROSS_COMPILE variable specifying prefix for
gnu compilers, and for building the named coreboot tree.
for example, xtree can be "default", which is then the
coreboot tree downloaded, for use of crossgcc.

however, it is also used to symlink identical versions
of crossgcc between coreboot trees. this latter feature
was only needed for fam15h boards which were previously
split between two mostly identical coreboot trees, that
were later merged into a single tree, and this feature
is therefore no longer used.

remove this dead code, to reduce bloat in the build system.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:55:51 +01:00
Leah Rowe
4624c6e536 mk: remove unused variables (ser/xp)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:44:33 +01:00
Leah Rowe
aba5b3a353 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:30:32 +01:00
Leah Rowe
0ab7c6ff9c lib.sh: use realpath to get sys python on venv
In the previous revision, I make hardcoded use of
/usr/local/bin and /usr/bin as search locations, instead
of relying on PATH, when the user has a python venv, because
in those cases, we cannot rely on PATH so we use a python
command to detect the venv and then force use of the
normal system path for python.

However, there's no guarantee that the real Python will
indeed live at these locations. For example, some distros
like Nix or Guix will use many locations for different
versions of a given package, and it's for the birds as to
what given package version the user might be running.

Therefore, this patch retains that current hardcoded
assumption of /usr/local/bin and /usr/bin but *only* as
a fallback solution, instead checking realpath first.

The "realpath" command isn't technically POSIX standard,
but in practise it is available on GNU coreutils, Busybox,
and the various BSD userlands.

I could perhaps *import* a realpath utility, and use that,
but this should be fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 06:43:49 +01:00
Leah Rowe
8edea026c5 lib.sh: Force use of System Python to prevent hang
If the user has a virtual environment, the current logic
will cause lbmk to hang. A useful workaround is to force
use of the direct path to the system binary of python.

This works by detecting a virtual environment first, and
deferring to the old behaviour if no venv is found. If one
is found, then it will not rely on PATH, but instead only
search the standard locations /usr/local/bin and /usr/bin.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 05:25:28 +01:00
Leah Rowe
b1b964fa5c lib.sh: further condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:35:18 +01:00
Leah Rowe
9543a325ac lib.sh: further simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:31:40 +01:00
Leah Rowe
9baabed718 lib.sh: condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:27:03 +01:00
Leah Rowe
0c5c5ffc87 lib.sh: simplify mk()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:12:53 +01:00
Leah Rowe
83022b6ba8 lib.sh: simplify cbfs()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:11:20 +01:00
Leah Rowe
13ad839691 lib.sh: simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:04:03 +01:00
Leah Rowe
b1ea416575 mk: remove mkhelp() and use x_() instead
x_ and mkhelp pretty much do the same thing

in fact, there is no functional difference

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:54:08 +01:00
Leah Rowe
4cf64e59ed mk: simplify handling of trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:49:22 +01:00
Leah Rowe
d0581914c7 coreboot/hp8300cmt: purge xhci_overcurrent_mapping
This prevents a build error, as the variable is no longer
used at all by coreboot (EHCI mapping is used as reference
instead).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 10:25:08 +01:00
Leah Rowe
cb52fc4ba8 Fix VBT path on HP Elite desktops
Also: hp8300cmt_16mb did not specify a data.vbt path, even
though it is indeed available in the coreboot tree. This
has been corrected.

The previous lack of VBT on hp8300cmt_16mb wasn't really a
big problem, since coreboot handles initialisation anyway,
and it's basically optional on Linux. Coreboot doesn't parse
VBT at all.

This patch should fix build errors, that were caused on the
recent revision update, where several of the HP desktops
have now been turned into variants.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 07:51:49 +01:00
Leah Rowe
2bee87cfc2 lib.sh: add missing copyright year
alper made a fix to this file a few hours ago, but
forgot to update the copyright header

i'm doing it for alper, as a courtesy

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 04:01:31 +01:00
Leah Rowe
4b7ab403c6 ifd/q45t_am: unlock regions by default
i used ifdtool --unlock to do this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:25:51 +01:00
Leah Rowe
564155277e coreboot/g43t_am3: use ifd-based setup
no-ME setup. with a gbe file. we previously made this
a descriptorless setup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:24:38 +01:00
Leah Rowe
0ddd196375 coreboot/q45t_am3: use ifd-based setup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 02:44:33 +01:00
Leah Rowe
3b2d933842 coreboot/default: add missing submodules
due to a rule in .gitignore, these were ignored, because it
ignores .tar.xz entries in git status

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 01:59:05 +01:00
Leah Rowe
a10d81399c NEW MAINBOARD: Acer Q45T-AM (G43T-AM3 variant)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:16:08 +01:00
Leah Rowe
d114e0a765 mk: don't print confirmation of git pkg.cfg
otherwise, the "list" commands include such text,
where they should not.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:09:27 +01:00
Leah Rowe
f59c24f12a coreboot/g43t_am3: fix data.vbt path
this board became a variant, in the new coreboot revision that
lbmk recently updated to. fix the data.vbt path to prevent error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:06:29 +01:00
Leah Rowe
21020fa319 add missing config/data/coreboot/0
this is a file containing one byte, of value zero

i meant to add it in previous commits, for the resizing
and shrinking of tarballs when inserting or deleting
vendor files

used by include/vendor.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 21:24:53 +01:00
Leah Rowe
2b4629d790 Merge pull request 'lib.sh: Fix python3 detection when 'python' is python2' (#290) from alpernebbi/lbmk:python3-detection-fix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/290
2025-04-21 14:52:28 +00:00
Alper Nebi Yasak
a18d287a81 lib.sh: Fix python3 detection when 'python' is python2
Properly set $pyver to "3" when we detect we can use python3. In the
following version checks, use the $python we detected instead of a
'python' from PATH because the latter might be a python2 while still
co-existing with a python3.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-21 17:45:25 +03:00
Leah Rowe
c7569a6714 coreboot/next: merge with coreboot/default
I also cherry-picked a patch from Heads, that fixes build
issues caused by the hacks in the T480 port; several changes
made by Mate are now ifdef'd based on whether a KabyLake
ThinkPad is specified in defconfig.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 06:38:30 +01:00
Leah Rowe
762c7ff43e coreboot/default: Update, c247f62749b (8 Feb 2025)
This is currently the latest revision of coreboot.

Other coreboot trees to follow. The "next" tree will
also be merged with coreboot/default, in a follow-up
commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 03:26:54 +01:00
Leah Rowe
86e7aa80c5 Update the GRUB revisions
A number of regressions were caused by the recent CVE fixes,
many of which have since been fixed upstream. This includes
several ext4 file system bugs, which caused some systems not
to boot properly, when dealing with very large initramfs files.

No additional patching has been made. This will be tested, and
then used to provide a revision update for Libreboot 20241206.

After this, there are several additional OOT patches that will
be merged, for the next *testing release* of Libreboot.

Update to this revision, for all GRUB trees:
a4da71dafeea519b034beb159dfe80c486c2107c

This brings in the following changes from upstream:
* a4da71daf util/grub-install: Include raid5rec module for RAID 4 as well
* 223fcf808 loader/ia64/efi/linux: Reset grub_errno on failure to allocate
* 6504a8d4b lib/datetime: Specify license in emu module
* 8fef533cf configure: Add -mno-relax on riscv*
* 1fe094855 docs: Document the long options of tpm2_key_protect_init
* 6252eb97c INSTALL: Document the packages needed for TPM2 key protector tests
* 9d4b382aa docs: Update NV index mode of TPM2 key protector
* 2043b6899 tests/tpm2_key_protector_test: Add more NV index mode tests
* 9f66a4719 tests/tpm2_key_protector_test: Reset "ret" on fail
* b7d89e667 tests/tpm2_key_protector_test: Simplify the NV index mode test
* 5934bf51c util/grub-protect: Support NV index mode
* cd9cb944d tpm2_key_protector: Support NV index handles
* fa69deac5 tpm2_key_protector: Unseal key from a buffer
* 75c480885 tss2: Add TPM 2.0 NV index commands
* 041164d00 tss2: Fix the missing authCommand
* 46c9f3a8d tpm2_key_protector: Add tpm2_dump_pcr command
* 617dab9e4 tpm2_key_protector: Dump PCRs on policy fail
* 204a6ddfb loader/i386/linux: Update linux_kernel_params to match upstream
* 6b64f297e loader/xnu: Fix memory leak
* f94d257e8 fs/btrfs: Fix memory leaks
* 81146fb62 loader/i386/linux: Fix resource leak
* 1d0059447 lib/reloacator: Fix memory leaks
* f3f1fcecd disk/ldm: Fix memory leaks
* aae2ea619 fs/ntfs: Fix NULL pointer dereference and possible infinite loop
* 3b25e494d net/drivers/ieee1275/ofnet: Add missing grub_malloc()
* fee6081ec kern/ieee1275/init: Increase MIN_RMA size for CAS negotiation on PowerPC machines
* b66c6f918 fs/zfs: Fix a number of memory leaks in ZFS code
* 1d59f39b5 tests/util/grub-shell: Remove the work directory on successful run and debug is not on
* e0116f3bd tests/grub_cmd_cryptomount: Remove temporary directories if successful and debug is not on
* e6e2b73db tests/grub_cmd_cryptomount: Default TMPDIR to /tmp
* 32b02bb92 tests/grub_cmd_cryptomount: Cleanup the cryptsetup script unless debug is enabled
* c188ca5d5 tests: Cleanup generated files on expected failure in grub_cmd_cryptomount
* 50320c093 tests/util/grub-shell-luks-tester: Add missing line to create RET variable in cleanup
* bb6d3199b tests/util/grub-shell-luks-tester: Find cryptodisk by UUID
* 3fd163e45 tests/util/grub-shell: Default qemuopts to envvar $GRUB_QEMU_OPTS
* ff7f55307 disk/lvm: Add informational messages in error cases of ignored features
* a16b4304a disk/lvm: Add support for cachevol LV
* 9a37d6114 disk/lvm: Add support for integrity LV
* 6c14b87d6 lvm: Match all LVM segments before validation
* d34b9120e disk/lvm: Remove unused cache_pool
* 90848a1f7 disk/lvm: Make cache_lv more generic as ignored_feature_lv
* 488ac8bda commands/ls: Add directory header for dir args
* 096bf59e4 commands/ls: Print full paths for file args
* 90288fc48 commands/ls: Output path for single file arguments given with path
* 6337d84af commands/ls: Show modification time for file paths
* cbfb031b1 commands/ls: Merge print_files_long() and print_files() into print_file()
* 112d2069c commands/ls: Return proper GRUB_ERR_* for functions returning type grub_err_t
* da9740cd5 commands/acpi: Use options enum to index command options
* 1acf11fe4 docs: Capture additional commands restricted by lockdown
* 6a168afd3 docs: Document restricted filesystems in lockdown
* be0ae9583 loader/i386/bsd: Fix type passed for the kernel
* ee27f07a6 kern/partition: Unbreak support for nested partitions
* cb639acea lib/tss2/tss2_structs.h: Fix clang build - remove duplicate typedef
* 696e35b7f include/grub/mm.h: Remove duplicate inclusion of grub/err.h
* 187338f1a script/execute: Don't let trailing blank lines determine the return code
* ff173a1c0 gitignore: Ignore generated files from libtasn
* fbcc38891 util/grub.d/30_os-prober.in: Conditionally show or hide chain and efi menu entries
* 56ccc5ed5 util/grub.d/30_os-prober.in: Fix GRUB_OS_PROBER_SKIP_LIST for non-EFI
* 01f064064 docs: Do not reference non-existent --dumb option
* 3f440b5a5 docs: Replace @lbracechar{} and @rbracechar{} with @{ and @}
* f20988738 fs/xfs: Fix grub_xfs_iterate_dir() return value in case of failure
* 1ed2628b5 fs/xfs: Add new superblock features added in Linux 6.12/6.13
* 348cd416a fs/ext2: Rework out-of-bounds read for inline and external extents
* c730eddd2 disk/ahci: Remove conditional operator for endtime
* f0a08324d term/ns8250-spcr: Return if redirection is disabled
* 7161e2437 commands/file: Fix NULL dereference in the knetbsd tests
* 11b9c2dd0 gdb_helper: Typo hueristic
* 224aefd05 kern/efi/mm: Reset grub_mm_add_region_fn after ExitBootServices() call
* 531750f7b i386/tsc: The GRUB menu gets stuck due to unserialized rdtsc
* f2a1f66e7 kern/i386/tsc_pmtimer: The GRUB menu gets stuck due to failed calibration
* 13f005ed8 loader/i386/linux: Fix cleanup if kernel doesn't support 64-bit addressing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-20 05:43:53 +01:00
Leah Rowe
8d57bf6009 Revert "git.sh: minor cleanup"
This reverts commit e63d8dd20d.
2025-04-18 02:25:16 +01:00
Leah Rowe
a2898771f6 lib.sh: perform root check even earlier
initialising variables, setting PWD, setting version,
this is all unnecessary before the root check, because
the dependencies commands use none of these.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:17:53 +01:00
Leah Rowe
779f600342 lib.sh: tidy up opening logic (put it together)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:10:49 +01:00
Leah Rowe
bac4be99c2 lib.sh: do root check before python check
we don't need python before the root check

principle of least privilege

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:02:10 +01:00
Leah Rowe
e63d8dd20d git.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:52:44 +01:00
Leah Rowe
11078508a2 lib.sh: simplify mktarball()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:33:45 +01:00
Leah Rowe
087bbedc5f vendor.sh: tidy up vendor_download()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:35:48 +01:00
Leah Rowe
e11fd52d95 mk: tidy up check_gnu_path()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:27:33 +01:00
Leah Rowe
3442f4278e mk: simplify check_project_hashes()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:23:32 +01:00
Leah Rowe
6b6a0fa607 lib.sh: fix missing s/TMPDIR/xbmktmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:17:11 +01:00
Leah Rowe
e07a2adb13 lbmk: don't handle TMPDIR directly
lbmk creates TMPDIR as /tmp/xbmk_*, but it's theoretically
possible that something could re-export it by mistake.

this change retains the same initialisation, but further
use is now via a new variable "xbmktmp", that stores the
value of TMPDIR upon lbmk's initialisation of it.

this reduces the chance of such a bug in the future, as
described above, so it is a preemptive/preventative fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:43:22 +01:00
Leah Rowe
9d3b52cd1d rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:31:26 +01:00
Leah Rowe
b4402c5425 vendor.sh: yet even more code cleanup
code equals bugs. code that doesn't exist can't
have bugs, so it is superior by definition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:04:14 +01:00
Leah Rowe
fe5bdc7633 vendor.sh: even more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 22:09:05 +01:00
Leah Rowe
fcedb17a9a vendor.sh: more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:38:20 +01:00
Leah Rowe
4e2b59ed3f vendor.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:20:14 +01:00
Leah Rowe
a3acf4c3f9 vendor.sh: simplify process_release_roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:11:55 +01:00
Leah Rowe
30213a9688 vendor.sh: remove unnecessary check
the next part checks whether the file is below 512k,
so there's no point checking if it's below 2, because
the lowest a file size can be is zero, and expr will
produce a result of -1 if decrementing from zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:04:51 +01:00
Leah Rowe
38df7275f1 git.sh: remove unnecessary comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:14:11 +01:00
Leah Rowe
f5891fb699 git.sh: remove link_crossgcc()
merge it with git_prep

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:10:19 +01:00
Leah Rowe
a685654b90 git.sh: remove move_repo()
merge it with git_prep, since it's only a small
function and only called from there. the merged
code still makes sense and its purpose is still
quite clear on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:54:59 +01:00
Leah Rowe
e4aa62f79a git.sh: remove prep_submodule()
merge it with git_prep, since it's only a tiny
function and only called from there. the for
loop moved to the if block still makes sense
on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:45:00 +01:00
Leah Rowe
2839feb9e4 git.sh: make git_prep command clearer
the "u" argument can actually be any thing. git_prep
handles git submodules only for single-tree projects,
under any candition, or on multi-tree projects if
the number of arguments to git_prep is above four.

"u" is the 5th argument, meant to enable submodule
downloads. it really doesn't matter what this string
says, so let's just make it as clear as possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:32:21 +01:00
Leah Rowe
410fa702c9 mrc.sh: Make proper use of variable inside printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 05:06:21 +01:00
Leah Rowe
075902c3ea simplify a few file checks
the combination of x_ with the "e" function enables
for much simpler file-check error handling, which is
a unique innovation of lbmk as it pertains to sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:49:17 +01:00
Leah Rowe
b2255425eb rom.sh: remove unnecessary check
the cbfs function will call cbfstool, which will perform
the same check, and the same error condition would cause
the same exit behaviour in lbmk. the error message would
also provide output that is just as useful for debugging.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:25 +01:00
Leah Rowe
39640d76a7 lbmk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:03 +01:00
Leah Rowe
c8dc701f3e lib.sh mktarball: stricter tar error handling
There was no error handling, *at all*, on the actual tar
command, due to the lack of set -o pipefail, which we cannot
rely on in sh.

The x_ wrapper can be used in this case, as a mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-16 00:57:54 +01:00
Leah Rowe
58a53d7046 vendor.sh: don't err on bruteforce me extract
it wouldn't exit with error status anyway, since i'm
setting +e here, but if that accidentally changed in
the future, i still wouldn't want this to exit.

the bruteforce me extraction naturally throws a lot of
errors, hence +e, because of how the extraction works,
but the result is checked at the end of the process,
to compensate. hence +e, because otherwise this brute
force extraction would never work.

therefore, this is an extremely theoretical bug fix, the
most quintessential of preemptive bug fixes, to the point
that it is actually rather pedantic.

The ":" in "|| :" will likely *never* be executed, but it
handles the theoretical case where the subshell exits with
non-zero status and +e is set; subshells aren't meant to
behave this way anyway, but who knows what cursed sh
implementation the user is on?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:58:59 +01:00
Leah Rowe
958fa34832 mk check_project_hashes: handle error on sha512sum
We can't do set -o pipefail in POSIX sh, which we're using,
but the build system has x_ which wraps around a command
and executes it, exiting with non-zero status if it does.

This fact enables lbmk to have functionality that is actually
superior to pipefail, since you can more easily control
specifically which parts error.

For example:

foo | bar | foo2 | bar2 | $err "error"

ERROR exits with non-zero status, but foo2, bar and foo
would not exit on error, only bar2 would. In *bash*, which
we avoid, set -o pipefail would make all of them exit on
error, but what if you wanted "bar" to not exit?

With lbmk, you could do, in the above example, and with the
above question asked ("what if you wanted bar not to exit"):

x_ foo | bar | x_ foo2 | bar2 > file | $err "error"

of course, you could also do, if not outputting to "file":

x_ foo | bar | x_ foo2 | x_ bar2

NOTE: in lbmk, $err is a variable containing the name of
a function that does something (whatever you want) and
then exits with non-zero status.

This entire explanation is beyond the scope of simply
providing (and explaining) this fix, but I also wanted to
use this commit as an example of the power of lbmk with
regards to POSIX shell scripting.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:08:25 +01:00
Leah Rowe
8b4b069e3f vendor.sh: remove unnecessary xchanged="y"
in these if clauses, what follows afterward is exactly
the same: set xchanged and return.

Therefore, these lines are redundant and they can be
removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:53:36 +01:00
Leah Rowe
166dbb04c9 vendor.sh: set need_files="n" if skipping patch
This change finally ensures that no insertions will be
attempted, on the basis that readkconfig failed; this
covers the instance whereby vcfg was set, but no scanned
items were indicated e.g. Intel ME files not specified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:49:10 +01:00
Leah Rowe
e90657cc73 vendor.sh: Don't handle vendor files if not needed
This should speed up automated tests. Otherwise, it goes
through all the extra checks that aren't needed, for each
individual type of vendor file, and also errors out when
handling pico serprog images; during automated testing,
on the bin directory, you might try on every tarball, one
of which is the pico tarball and this patch makes lbmk skip
that one too.

In general, we must not perform unnecessary tasks. Doing so
may even cause other bugs that we couldn't easily detect.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 14:09:31 +01:00
Leah Rowe
2e10a45fa3 Revert "lib.sh: use eval for the command in x_"
This reverts commit 3bfdecdc75.

The commit that this reverses, caused sch5545 ec firmware
downloads to fail, due to globbing.
2025-04-13 05:15:13 +01:00
Leah Rowe
738d4bb6b6 lib.sh: fix bad eval writing resized file
x_ cannot be used, where output is redirectod to a file;
only the conventional piping can be used.

same as the last change. this and the other fix were caught
during testing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 04:02:34 +01:00
Leah Rowe
eb9e5d2d5d lib.sh: fix bad eval writing version/versiondate
x_ cannot be used, where output is redirected to a file;
only the convention piping can be used, for errors.

relying on x_ in these cases will cause unpredictable bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 03:57:04 +01:00
Leah Rowe
3bfdecdc75 lib.sh: use eval for the command in x_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:31:25 +01:00
Leah Rowe
4fa3bb9e5b mk: use eval to run mkhelp commands
directly quoting it and running it quoted means
that the shell way try to execute it as a file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:25:01 +01:00
Leah Rowe
9b3635718a mk: tidy up the switch/case block in main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:43:28 +01:00
Leah Rowe
0c381028ab mk: tidier error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
023f9cf049 lib.sh: tidy up the error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
cb3253befb rom.sh: tidy up error handling
same as the last change

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
7af46721bc vendor.sh: tidy up error handling
x_ can be used nowadays on any function, because it
properly handles globbing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
04ebb3b91a vendor.sh: tidy up decat_fspfd()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
0c87fdf96a git.sh: clean up fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
9eb8856b3c mk: Remove unnecessary argument checks on trees()
These checks are no longer necessary, because these
checks are already properly handled in main().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe
52f3d54116 vendor.sh: properly call err_ in fail_inject
i can't call $err (variable), because it's set
to fail_inject. fix this infinite loop, which
was an oversight in the previous commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:19:48 +01:00
Leah Rowe
c4c6692b76 remove xbmk_parent, handle forking in lib.sh
I was using a complicated method of knowing whether
the current instance was parent or a child, to know
whether the lock file and TMPDIR needed to be purged.

It was quite error-prone too. Instead, I'm now handling
it directly from within the if statement that previously
initialised xbmk_parent=y, forking ./mk from there.

The forked instance would not trigger that if clause
again, since then TMPDIR is created, thus avoiding
recursion.

This is an improvement because it doesn't rely on how
the parent handles exit statuses, and it ensures that
the lock/tmp files are never accidentally deleted.

Even if a given program/script that lbmk runs would
export TMPDIR, it doesn't matter because lbmk doesn't,
so it would be unaffected.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:03:40 +01:00
Leah Rowe
fd5431db05 lib.sh: define x_ right after err_
because the top-down function order isn't as reliable
in lib.sh, since this is what first runs, included
in every other script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:40:51 +01:00
Leah Rowe
972681a127 mk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:38:14 +01:00
Leah Rowe
b41cd39b68 lib.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:35:30 +01:00
Leah Rowe
4993950264 mrc.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:32:18 +01:00
Leah Rowe
c158d82298 rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:29:35 +01:00
Leah Rowe
cb36248c8c vendor.sh: tidy up check_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:10:49 +01:00
Leah Rowe
409cab39c5 vendor.sh: tidy up vendor_inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:08:30 +01:00
Leah Rowe
12b1623e47 vendor.sh: tidy up readcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:05:12 +01:00
Leah Rowe
0d85f061e2 vendor.sh: tidy up patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:02:07 +01:00
Leah Rowe
61f2014102 vendor.sh: tidy up process_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:57:29 +01:00
Leah Rowe
5901f36e49 vendor.sh: tidy up patch_rom()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:53:34 +01:00
Leah Rowe
082930ce0e vendor.sh: tidy up inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:50:54 +01:00
Leah Rowe
e1f91f3037 vendor.sh: tidy up modify_mac_addresses()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:43:59 +01:00
Leah Rowe
3181ac5012 script/trees: merge with mk and delete script/
script/ no longer exists. this means that the
only executable script in lbmk is now mk.

script/trees was never called directly; instead,
we used ./update trees in the past, then just ./mk.

this is part of a larger audit to simplify lbmk,
in preparation for the next Libreboot release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:46:09 +01:00
Leah Rowe
3d03dd1a50 mk: remove the legacy "roms" command
we don't need it. the documentation only tells you
now to run ./mk -b coreboot target1 target2 etc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:24:10 +01:00
Leah Rowe
f0c629dcc6 lib.sh: write version/versiondate to dotfiles
write to .version and .versiondate, instead
of version and versiondate.

this will hide them to avoid visual clutter while
analysing files within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:51:49 +01:00
Leah Rowe
23b942c83e lib.sh: hardcode projectname/projectsite
remove the corresponding files, containing these strings

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:44:05 +01:00
Leah Rowe
a03bb793ae remove update/vendor symlinks
these are obsolete commands for backward compatibility,
but they are being removed before the next release.

the documentation has for some now only referenced use
of the ./mk commands, making lbmk live up to its name!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:37:21 +01:00
Leah Rowe
d7f80ebe71 move build to mk
i'm removing all the backward-compatibility in the
build system, so that only the ./mk command is available

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:32:34 +01:00
Leah Rowe
57d58527fd trees: unify the execution of mkhelper commands
provide it in a new function: mkhelp()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:20:16 +01:00
Leah Rowe
e5262da4be trees: tidy up configure_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:07:27 +01:00
Leah Rowe
5179827839 build: make coreboot building an else in "roms"
Otherwise, the current return prevents set -u -e
after the case/switch block, which is a problem if
set +u +e was done at any point before the return.

Remove the return in the roms) section of the case/switch
block, and make the building of coreboot images part of
an else clause.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 12:58:28 +01:00
Leah Rowe
c189257888 trees: don't build dependencies if dry=":"
build_depend is already blanked anyway, but it can't
hurt to have an extra check here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:28:14 +01:00
Leah Rowe
115a66fddd trees: unified handling of flags
this way, the error message will never be incorrect,
which i had to fix in a recent patch.

now, the same string is used for error messages and getopt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:18:15 +01:00
Leah Rowe
3ea633cc79 trees: simplified handling of badhash/do_make
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe
9be40e94a2 trees: don't set mode on ./mk -b
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe
67ad7c2635 trees: don't set mod on ./mk -d
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe
2444894841 trees: don't initialise mode to "all"
this is not necessary. the fetch mode is still handled,
as before, and no make commands will run in this case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:36 +01:00
Leah Rowe
97c50a39a6 trees: clean up some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:10 +01:00
Leah Rowe
cfb14fd8dd vendor.sh: simplified readkconfig()
So much bloat

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:13:05 +01:00
Leah Rowe
5b697b93a2 lib.sh: double-quote pwd to prevent globbing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:11:51 +01:00
Leah Rowe
5a0a24f555 lbmk: unified PWD handling (work directory)
instead of running pwd all the time, run it once in lib.sh,
and export PWD.

for lbmk-specific use of PWD, use xbmkpwd, which contains
the value of PWD as was set by the pwd utility in lib.sh.

many parts of lbmk rely on pwd, and it *must* be correct.
this change adds basic error handling, since pwd can in
fact return errors in some cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:04:53 +01:00
Leah Rowe
a25a29cfbb lib.sh: initialise PATH if it's unset
it's incorrect for PATH not to be set, but some users
may foolishly blank it out before running lbmk.

prevent such issues, by initialising it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:31:26 +01:00
Leah Rowe
1022abf699 move XBMKPATH to include/lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:22:23 +01:00
Leah Rowe
0764c969a2 lbmk: use pwd util, not PWD environmental variable
PWD could be anything, if the user manually exported
it before running lbmk.

always run pwd instead, to get the real string.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:52:18 +01:00
Leah Rowe
f98b9b0110 clean up a few semicolons in the build system
several code lines were condensed together, which
make them less readable. make the code more readable
by having separate commands on separate lines.

i previously did this during my manic build system
audits of 2023 and 2024; condensing lines like this
is overly pedantic and serves no real purpose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:15:00 +01:00
Leah Rowe
8ccb61cc71 trees: err if first argument is not a flag
E.g. ./mk -f coreboot is valid

./mk coreboot -f is not valid

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:51 +01:00
Leah Rowe
947c3e1a17 trees: err if no argument given
We were already covering this from the main build
script, but it's good to also check it here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:19 +01:00
Leah Rowe
edbbde0b12 trees: set dry=":" on ./mk -f
We don't want any build commands to run, when
the -f flag is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:11:24 +01:00
Leah Rowe
33bb0ecf76 trees: clean up initialisation of the dry variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:10:42 +01:00
Leah Rowe
c7636ff1df trees: initialise mode to "all", not ""
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 13:39:55 +01:00
Leah Rowe
d0bd12631a trees: don't abuse the mode variable on -f
The "mode" variable is used as a suffix for make commands,
for example ./mk -m sets mode to "menuconfig", which means
you want to run "make menuconfig".

When fetching sources (./mk -f), I was setting mode to "fetch",
and putting checks in code to avoid use of make when mode was
set to "fetch".

The behaviour now is identical, except that a new variable
called "do_make" is set to "n" when doing ./mk -f, otherwise
set to "y", and this is checked instead. This should make
the meaning of the code somewhat clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 04:47:04 +01:00
Leah Rowe
c4cd876c60 trees: Add missing flag to error output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-09 09:38:59 +01:00
Leah Rowe
5ebcae5235 lbmk: minor code formatting cleanup
some lines were needlessly condensed, and less readable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-06 23:17:33 +01:00
Leah Rowe
70cef71dba grub/xhci: Remove unused patch
I was importing a patch for the z790 boards, but
Libreboot doesn't support this board yet, and the
patch was a hack that may affect other boards.

When I do later merge that board, and I find that the
hack is needed, I'll simply make another grub tree
within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-04 13:57:09 +01:00
Leah Rowe
3f14a470a2 remove _fsp targets (keep _vfsp)
_fsp is obsolete. people should use _vfsp

_fsp was kept for a short while, for backward compatibility,
but nobody really uses it now and it just causes confusion

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-01 08:45:41 +01:00
Leah Rowe
d7312260e7 util/nvmutil: remove excessive comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-25 13:29:16 +00:00
Leah Rowe
e348ea0381 Bump GRUB revision to add 73 security patches
You can find information about these patches here:
https://lists.gnu.org/archive/html/grub-devel/2025-02/msg00024.html

GRUB has been on a crusade as of late, to proactively audit
and fix many security vulnerabilities. This lbmk change brings
in a comprehensive series of patches that fix bugs ranging from
possible buffer overflows, use-after frees, null derefs and so on.

These changes are critical, so a revision release *will* be issued,
for the Libreboot 20241206 release series.

This change imports the following 73 patches which
are present on the upstream GRUB repository (commit IDs
matched to upstream):

* 4dc616657 loader/i386/bsd: Use safe math to avoid underflow
* 490a6ab71 loader/i386/linux: Cast left shift to grub_uint32_t
* a8d6b0633 kern/misc: Add sanity check after grub_strtoul() call
* 8e6e87e79 kern/partition: Add sanity check after grub_strtoul() call
* 5b36a5210 normal/menu: Use safe math to avoid an integer overflow
* 9907d9c27 bus/usb/ehci: Define GRUB_EHCI_TOGGLE as grub_uint32_t
* f8795cde2 misc: Ensure consistent overflow error messages
* 66733f7c7 osdep/unix/getroot: Fix potential underflow
* d13b6e8eb script/execute: Fix potential underflow and NULL dereference
* e3c578a56 fs/sfs: Check if allocated memory is NULL
* 1c06ec900 net: Check if returned pointer for allocated memory is NULL
* dee2c14fd net: Prevent overflows when allocating memory for arrays
* 4beeff8a3 net: Use safe math macros to prevent overflows
* dd6a4c8d1 fs/zfs: Add missing NULL check after grub_strdup() call
* 13065f69d fs/zfs: Check if returned pointer for allocated memory is NULL
* 7f38e32c7 fs/zfs: Prevent overflows when allocating memory for arrays
* 88e491a0f fs/zfs: Use safe math macros to prevent overflows
* cde9f7f33 fs: Prevent overflows when assigning returned values from read_number()
* 84bc0a9a6 fs: Prevent overflows when allocating memory for arrays
* 6608163b0 fs: Use safe math macros to prevent overflows
* fbaddcca5 disk/ieee1275/ofdisk: Call grub_ieee1275_close() when grub_malloc() fails
* 33bd6b5ac disk: Check if returned pointer for allocated memory is NULL
* d8151f983 disk: Prevent overflows when allocating memory for arrays
* c407724da disk: Use safe math macros to prevent overflows
* c4bc55da2 fs: Disable many filesystems under lockdown
* 26db66050 fs/bfs: Disable under lockdown
* 5f31164ae commands/hexdump: Disable memory reading in lockdown mode
* 340e4d058 commands/memrw: Disable memory reading in lockdown mode
* 34824806a commands/minicmd: Block the dump command in lockdown mode
* c68b7d236 commands/test: Stack overflow due to unlimited recursion depth
* dad8f5029 commands/read: Fix an integer overflow when supplying more than 2^31 characters
* b970a5ed9 gettext: Integer overflow leads to heap OOB write
* 09bd6eb58 gettext: Integer overflow leads to heap OOB write or read
* 7580addfc gettext: Remove variables hooks on module unload
* 9c1619773 normal: Remove variables hooks on module unload
* 2123c5bca commands/pgp: Unregister the "check_signatures" hooks on module unload
* 0bf56bce4 commands/ls: Fix NULL dereference
* 05be856a8 commands/extcmd: Missing check for failed allocation
* 98ad84328 kern/dl: Check for the SHF_INFO_LINK flag in grub_dl_relocate_symbols()
* d72208423 kern/dl: Use correct segment in grub_dl_set_mem_attrs()
* 500e5fdd8 kern/dl: Fix for an integer overflow in grub_dl_ref()
* 2c34af908 video/readers/jpeg: Do not permit duplicate SOF0 markers in JPEG
* 0707accab net/tftp: Fix stack buffer overflow in tftp_open()
* 5eef88152 net: Fix OOB write in grub_net_search_config_file()
* aa8b4d7fa net: Remove variables hooks when interface is unregisted
* a1dd8e59d net: Unregister net_default_ip and net_default_mac variables hooks on unload
* d8a937cca script/execute: Limit the recursion depth
* 8a7103fdd kern/partition: Limit recursion in part_iterate()
* 18212f064 kern/disk: Limit recursion depth
* 67f70f70a disk/loopback: Reference tracking for the loopback
* 13febd78d disk/cryptodisk: Require authentication after TPM unlock for CLI access
* 16f196874 kern/file: Implement filesystem reference counting
* a79106872 kern/file: Ensure file->data is set
* d1d6b7ea5 fs/xfs: Ensuring failing to mount sets a grub_errno
* 6ccc77b59 fs/xfs: Fix out-of-bounds read
* 067b6d225 fs/ntfs: Implement attribute verification
* 048777bc2 fs/ntfs: Use a helper function to access attributes
* 237a71184 fs/ntfs: Track the end of the MFT attribute buffer
* aff263187 fs/ntfs: Fix out-of-bounds read
* 7e2f750f0 fs/ext2: Fix out-of-bounds read for inline extents
* edd995a26 fs/jfs: Inconsistent signed/unsigned types usage in return values
* bd999310f fs/jfs: Use full 40 bits offset and address for a data extent
* ab09fd053 fs/jfs: Fix OOB read caused by invalid dir slot index
* 66175696f fs/jfs: Fix OOB read in jfs_getent()
* 1443833a9 fs/iso9660: Fix invalid free
* 965db5970 fs/iso9660: Set a grub_errno if mount fails
* f7c070a2e fs/hfsplus: Set a grub_errno if mount fails
* 563436258 fs/f2fs: Set a grub_errno if mount fails
* 0087bc690 fs/tar: Integer overflow leads to heap OOB write
* 2c8ac08c9 fs/tar: Initialize name in grub_cpio_find_file()
* 417547c10 fs/hfs: Fix stack OOB write with grub_strcpy()
* c1a291b01 fs/ufs: Fix a heap OOB write
* ea703528a misc: Implement grub_strlcpy()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-19 21:26:23 +00:00
Leah Rowe
4b228c11f9 Merge pull request 'Update pico-serprog revision' (#271) from Riku_V/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/271
2025-02-12 21:20:17 +00:00
Riku Viitanen
a8359e30b2 Update pico-serprog revision
Most importantly this should fix issues with rp2350 boards
not synchronizing properly.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2025-02-12 22:19:11 +02:00
Leah Rowe
d2cb954933 util/nvmutil: Fix bad error messages on R/W
The messages didn't really make sense.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-10 20:27:48 +00:00
Leah Rowe
e1e515bd22 util/nvmutil: hardened pledge on help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-07 12:31:46 +00:00
Leah Rowe
ada057a865 Merge pull request 'Simplify the README' (#269) from runxiyu/lbmk:readme-simplification into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/269
2025-02-02 10:32:39 +00:00
runxiyu
9ced146b47 README.md: Use newlines instead of bulleted list for docs/support links
I think newlines look better here. The indent that bullet-pointed lists
have, does not seem natural at the start of the document.

Signed-off-by: runxiyu <me@runxiyu.org>
2025-02-02 07:56:24 +00:00
Runxi Yu
266122592c
README.md: Use the EFF's page on Right to Repair 2025-02-02 15:19:26 +08:00
Runxi Yu
e36aa8c5a5 README.md: Vastly simplify it 2025-02-01 00:18:31 +08:00
Runxi Yu
c17f4381ce README.md: Mention SeaBIOS and U-Boot instead of Tianocore as payloads
SeaBIOS has been supported for a long time and seems to be the
"recommended" payload nowadays (though usually with GRUB too). I haven't
seen Tianocore / EDK II been mentioned in a while. U-Boot support was
added as of Libreboot 20241206-rev8.

Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-02-01 00:08:44 +08:00
Leah Rowe
47eb049cb4 Merge pull request 'deps/arch: genisoimage belongs to cdrtools' (#267) from runxiyu/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/267
2025-01-31 08:45:01 +00:00
Runxi Yu
fa9a0df245
deps/arch: genisoimage belongs to cdrtools
genisoimage is not a an AUR package as suggested by aur_notice. It is
available in the "cdrtools" package in the repositories.

References: https://archlinux.org/packages/extra/x86_64/cdrtools/
Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-01-31 16:38:20 +08:00
Leah Rowe
a98490573b util/nvmutil: only set mac_updated at the end
after setting the checksum too

this is functionally no different, but setting it
at the start didn't sit right with me.

it's more logically correct to set it at the end,
in case any error did not result in an exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:45:57 +00:00
Leah Rowe
6b9cf09ca2 restore old x230 gbe file
i accidentally committed one where i'd changed
the mac address, on a previous revision to nvmutil

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:17:07 +00:00
Leah Rowe
8a43535513 util/nvmutil: Fix bad comparison
We're checking if errno is ENOTDIR, not setting it;
the previous code would always return true, and then
set errno 0, which in the context of this code was
actually OK, so this patch makes no functional difference
in practise.

However, I'm a stickler for technical correctness. I caught
this when trying to compile with clang, because clang is
quite pedantic about checking for exactly this type of bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:10:52 +00:00
Leah Rowe
a65a0c2f96 util/nvmutil: allow ./nvm gbe MAC
previously, if the user ran:

./nvm GBE [MAC address]

it would error, treating the MAC as a command

now if only 3 arguments are provided, and the
3rd argument ins't a valid command, it's treated
as a MAC address and validated accordingly.

this should make nvmutil easier to use, because
I imagine a lot of users forget to use setmac

there's no reason we should be so pedantic. we
should allow it to be used flexibly like this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:07:54 +00:00
Leah Rowe
96356ce94f util/nvmutil: move "e" to swap()
we only use it there, so we should only define it
there. it's used to detect host CPU endianness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:47:20 +00:00
Leah Rowe
b1d8975959 util/nvmutil: Only read up to 4KB on larger gbe
On the 16KB and 128KB files, we still only need to
operate on 4KB at the start of each block, where the
block size is larger than 4KB.

The reason we deal with the entire 4KB block is because
the nvm words (in the 128 byte section) can define an
extended nvm area anywhere after 128 bytes, within the
128 byte block.

We could systematically read where that is being handled,
and handle it; we could then allocate less memory, and
read/write fewer bytes, but many block devices like SSDs
and flash drives have at least a 4KB erase block anyway,
so it's kinda pointless. saving memory would be nice, but
I don't really want to bloat the code.

This is a nice easy optimisation, to avoid wasting an
additional 8KB of memory when handling 16KB files, and
additional 120KB if handling 128KB files, since nf is
what determines how much memory will be allocated.

the alternative would be to use an mmap, and then we
could reasonably handle the idea above for only writing,
surgically, what we need: nvm words and extended nvm
words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:41:55 +00:00
Leah Rowe
6821659bcb util/nvmutil: fix minor mistake (line break)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:46:36 +00:00
Leah Rowe
3bb7520f6d util/nvmutil: do setmac if only filename given
./nvm gbe.bin

with this patch, the above example does the same as:

./nvm gbe.bin setmac

now you can simply specify the gbe file, and it will
randomise the mac address within it, and update the
nvm checksum word.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:40:44 +00:00
Leah Rowe
d94b274fd9 vendor.sh: don't error if grep -v fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:57:30 +00:00
Leah Rowe
6ebdd3c72b vendor.sh: Don't show gbe filename on inject
it's a temporary file, so printing it may confuse
the user. hide it from the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:49:45 +00:00
Leah Rowe
a08748a9ed util/nvmutil: don't say write not needed if errno
otherwise, the output is confusing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:54:06 +00:00
Leah Rowe
6841a351eb util/nvmutil: print dump *after* modification
this way, we still get an error exit for example
when trying to invalidate an already invalid
checksum; this error exit was disabled by the
last revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:50:34 +00:00
Leah Rowe
da0a6c216c util/nvmutil: verbosely print the written MAC
This is for user friendliness. Otherwise, many users
might try to dump afterward if they specified a random
MAC address.

This saves the user from having to re-run with the dump
command, thus saving time for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:37:02 +00:00
Leah Rowe
db5879c6b5 util/nvmutil: minor cleanup in cmd_dump
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:29:14 +00:00
Leah Rowe
bd7215d1eb util/nvmutil: show nvm words written on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:26:59 +00:00
Leah Rowe
c70117c79c util/nvmutil: clean up readonly check on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:18:38 +00:00
Leah Rowe
cf5a63e65c util/nvmutil: Remove useless gbeFileChanged var
We don't need it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:13:20 +00:00
Leah Rowe
83601aa524 util/nvmutil: reset errno if any MAC updated
instead of setting errno in the for loop, set a variable
declaring that the mac was updated, and reset errno based
on that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:08:17 +00:00
Leah Rowe
3e86bf5ce2 util/nvmutil: reset errno when writing a MAC
if checksum verification passed, then we should reset
in case we're operating on a given part and the last
one checked was bad.

a catch-all reset is already performed in writeGbe,
but it's good to do it here too.

in practise, if the 2nd part (part 1) is what failed,
errno still wouldn't be reset.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:05:59 +00:00
Leah Rowe
bcf53cc2cc util/nvmutil: show total number of bytes read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:02:54 +00:00
Leah Rowe
c91cc329cf util/nvmutil: rename tbw/bw to tnw/nw
to match nr in the readGbe function

number of bytes written, and total number
of bytes written.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:59:17 +00:00
Leah Rowe
9060710833 util/nvmutil: err if bytes read lower than nf
same as the last change. just covering edge cases.

we will likely never trigger this error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:57:32 +00:00
Leah Rowe
c72f699d36 util/nvmutil: err if fewer bytes written
it will probably never happen, and this is technically
not an error condition of pread/pwrite, but we need it
to read and write that exact number of bytes, as per nf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:55:05 +00:00
Leah Rowe
d666f67ebe util/nvmutil: Show bytes written in writeGbe
This will be useful for future debugging, and future
work on optimisations.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:47:49 +00:00
Leah Rowe
b2d6393ed5 util/nvmutil swap(): ensure that no overflow occurs
it wouldn't occur, on the current logic, but i wasn't
comfortable having the starting point (on little endian)
being higher than the checked endpoint, in case of
possible integer overflow as a result of future
modifications.

this is therefore a pre-emptive bug fix, because it doesn't
yet fix a bug, but it prevents a bug from being introduced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:48 +00:00
Leah Rowe
063fef14d3 util/nvmutil: make swap() a bit clearer
don't sizecode. show the individual steps clearly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:09 +00:00
Leah Rowe
fd1bbdc96c util/nvmutil: make 0x3f checksum position a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:06:12 +00:00
Leah Rowe
5ddf7f251d util/nvmutil: make 128 (nvm area) a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:03:34 +00:00
Leah Rowe
8850acc7da util/nvmutil swap(): Only handle the nvm area
The 128-byte nvm area is all that we need to handle,
since that is the only thing we actually work on in
nvmutil, based on checksum verification; the latter
implies that bytes must be in the correct order.

The swap() function previously worked on the entire
block, e.g. 4KB on 8KB files, 8KB on 16KB files and
64KB on 128KB files, and it did this twice, so it would
have operated on anywhere between 8KB to 128KB of data.

It now only operates on 256 bytes at a maximum, or 128
bytes if only handling one block. This is a significant
performance optimisation, on big endian host CPUs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 03:56:13 +00:00
Leah Rowe
49506a8832 util/nvmutil: move write checks to writeGbe
doing it in main() is messy. better do it from the
actual function. now the logic in main is clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:52:26 +00:00
Leah Rowe
948377b0e7 util/nvmutil: make cmd_swap its own function again
previous audits sizecoded nvmutil.c, reducing the sloccount,
but this resulted in unreadable code.

move the swap logic (swap parts) back to its own function,
for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:48:51 +00:00
Leah Rowe
6e134c9f4b util/nvmutil: minor cleanup
SIZE_64KB no longer needed, and the malloc error
is needlessly verbose

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:03:27 +00:00
Leah Rowe
98e105ac4f util/nvmutil: allocate less memory for setchecksum
also cmd_brick

where the checksum is being corrected or bricked, we
only need to handle the 128-byte nvm area on one of
the parts

similarly, we only need to allocate half the gbe file
size when doing a copy command.

256 bytes still allocated for setmac (see previous
commit), because we verify both checksums and set both
parts if possible.

with this, nvmutil is now much more memory-efficient.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:25:26 +00:00
Leah Rowe
52e8ea57f7 util/nvmutil: Further reduce memory usage
Allocate memory based on nf instead of partsize.

nf is the number of bytes actually read from each
part of the file.

Now if the user is running setmac for example,
256 bytes of memory will be allocated regardless
of gbe file size, whereas it would have previously
allocated 8KB, 16KB or 128KB depending on the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:05:06 +00:00
Leah Rowe
7a7d356824 util/nvmutil: Remove unnecessary buf16 variable
We can just point to gbe[] directly, in the word macro.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:26:53 +00:00
Leah Rowe
cdf23975bc util/nvmutil: Only allocate needed memory for file
We were allocating 128KB even if we only needed 8KB, for
example. It's not a lot of memory, but the principle of
the matter is that we must respect the user by not wasting
their memory.

The design of nvmutil is that it will never overflow, because
operations are mapped in memory to the exact size of the gbe
file, which can be 8KB, 16KB or 128KB, and this is enforced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:09:04 +00:00
Leah Rowe
ed45da9cae util/nvmutil: Remove unnecessary buffer
The buf variable is only used once, and only so
that we can get a pointer. We can point to buf16
instead, for the same result.

The gbe pointer (size_t) is later converter to
a char * when writing back to the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-25 06:23:22 +00:00
Leah Rowe
ec3148dc3b util/nvmutil: Show specific error for bad cmd argc
For example, if the brick command is used without specifying
a part number. Instead of saying "Invalid argument", show a
much more useful error message to help the user adapt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:14:25 +00:00
Leah Rowe
073420d305 util/nvmutil: cleaner argument handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:10:17 +00:00
Leah Rowe
a6c18734e7 util/nvmutil: extreme pledge/unveil hardening
call pledge *much* earlier, and and lock everything down
much sooner. the point of pledge/unveil is precisely that
your program must operate under the most restrictive set
of conditions possible, and still function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:58:42 +00:00
Leah Rowe
deb307eaf6 util/nvmutil: more minor cleanup
just some line breaks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:03:31 +00:00
Leah Rowe
c14eccaf15 util/nvmutil: more granular MAC parsing errors
tell the user exactly what they got wrong, instead
of simply printing "bad mac address", which is not
very helpful to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:58:51 +00:00
Leah Rowe
88fb9cc90e util/nvmutil: more cleanup
spread out a few lines, so that they are more
readable, and more thoroughly comment some parts.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:45:08 +00:00
Leah Rowe
5aaf27f80c remove errant comment in nvmutil
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:34:07 +00:00
Leah Rowe
c829b45c17 util/nvmutil: support 16kb and 128kb gbe files
See:
https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-mobile-p/intel-600-series-chipset-family-on-package-platform-controller-hub-pch-datash/spi0-for-flash/

The rules described there are universal, and replicated elsewhere
for many other platforms. The rules are simply:

* Flash descriptor is one block size, e.g. 4KB
* GbE is two block sizes, so if IfD is 4KB, GbE is 8KB

Intel defines 16KB and 128KB GbE files in specs, pertaining to
8KB and 64KB block sizes respectively.

The minimum size is 4KB blocksize, for 8KB GbE files which
we already supported. On larger block sizes, the same 4KB
parts are observed: a single 4KB IfD area at the start of
the block, and:

4KB GbE part at the start of the GbE region, and:
4KB GbE part at the start of GbE region plus block size

The empty space inbetween is padding, and we ignore it,
except when running swap/copy commands.

The nvmutil code has been modified, to create a 128KB buffer in
memory instead of 8KB, for loading GbE files.

Partsize is set to GbE file size divided by 2, and only the
area of memory we need to use is mapped; for example, if
we're loading a 8KB GbE file into memory, we only touch
the first 8KB part of the buffer, or first 16KB for 128KB
files.

In practise, we almost never see GbE files with sizes higher
than 8KB, but *we have seen it*, *AND NOW IT'S SUPPORTED!"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:13:28 +00:00
Leah Rowe
a98ca5bf65 util/nvmutil: Prevent unveil allowing dir access
We were checking directories *after* calling unveil, which
means that the sandboxing was incomplete; we only want files
to be accessed, not directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 12:18:45 +00:00
Leah Rowe
68c32034a0 typo: nvme should say nvm in nvmutil.c
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:37:26 +00:00
Leah Rowe
c944c2bbac util/nvmutil: General code cleanup
A lot of size-coding was performed in prior audits, to
make the sloccount lower on nvmutil, but this resulted in
code that wasn't very human readable.

I've reversed some of it and added comments, for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:33:30 +00:00
Leah Rowe
8c65e64e39 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 05:06:34 +00:00
Leah Rowe
f666652fe1 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 01:43:02 +00:00
Leah Rowe
64d3c7b515 grub/xhci: Add xHCI non-root-hub fixes from Nitrokey
See:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790?since=2025-01-13&until=2025-01-13

And more generally, see branch:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790

This brings in a few minor fixes, and also a not-so-minor fix:
Add TT (transaction translation) handling for non-SuperSpeed
devices in xhci.c

More generally, this patchset will improve non-root hub support
in the xHCI code. There is also a patch to work around a quirk
on the MSI Z790-P mainboard, which I'm planning to add to Libreboot
at a later date.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-14 20:34:16 +00:00
Leah Rowe
7bf0d4c2ed add gnults-devel to fedora 41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 23:59:44 +00:00
Leah Rowe
66d084e7f7 grub.cfg: scan luks *inside lvm*
the user might have boot their kernel inside luks
inside lvm for some dumb reason

it's theoretically possible that the user would be
so silly indeed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:45:00 +00:00
Leah Rowe
5a3b0dab96 grub.cfg: Scan *every* LVM device
We were scanning a hardcoded set up LVM volumes, so in practise,
LVM boot didn't really work. We did this because scanning for
asterisk is slow on some machines. However, since LVM is the last
one, and since most users don't boot directly from LVM, it wasn't
that much of an issue in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:19:48 +00:00
Leah Rowe
3c9f4be76f Libreboot 20241206, 8th revision
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 22:47:14 +00:00
Leah Rowe
d4cc94d6b4 rom.sh: don't run mkpicotool on dry builds
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 18:15:22 +00:00
Leah Rowe
de6d2f556f pico-sdk: Import picotool as a dependency
We were previously not handling picotool at all, and
pico-sdk would download picotool itself, at build time.

This means that the source archive, if created, would
not contain picotool. While not strictly required, for
complete corresponding source, since it's a toolchain
and not the actual pico-serprog firmware, it is my policy
that releases must include full corresponding source code,
when it is feasible to do so.

I must say, I intensely dislike cmake, with such burning
passion; I am thoroughly displeased by how hacky this is,
but it works and now nothing is in my way for a Libreboot
20241206 rev8 release!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 17:26:51 +00:00
Leah Rowe
4210ee68ea lib.sh: Much safer python version check
See:
https://docs.python.org/3/library/sys.html#sys.version_info

The sys.version_info tuple is a more reliable way to
get the version. Our previous logic assumed that Python
would always output "Python versionnumber", but this may
not always be how it works. We've seen this for example
where Debian modifies some GNU toolchains to include Debian
something in the output.

Python has a standard method built in for outputting exact
the information we need. In my system, what I got was this:

(3, 11, 2, 'final', 0)

That output was from running this command:

python -c 'import sys; print(sys.version_info[:])'

This is much more robust, so use this instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:54:38 +00:00
Leah Rowe
8c7ba6131c coreboot/next uprev: Fix T480 backlight keys
Backlight controls already worked on the T480/T480s, if you
used software-based controls e.g. set a hotkey for
xbacklight, but the actual Fn buttons on the keyboard did
not function at all; this patch fixes that issue

This also fixes LEDs on T480, on warm reboot, which are
otherwise off. It sets them back to the state they were
at on cold boot.

Both fixes are from Mate Kukri in the new T480 patchset.
In addition to these fixes, Mate made several code quality
improvements as part of efforts to upstream this code into
coreboot's main branch.

Updated coreboot T480 patchset to patchset 25. This change
will be reflected next in a modification to the Libreboot
documentation.

I had to make several other fixes on top of this; see diff.
A debug option was being enabled relating to stack overflow
detection, which we ought to avoid to mitigate over-zealous
build errors and stack corruption at boot; an errant option
for an EC we don't use was also being enabled, by some code
in coreboot relating to a Dasharo board; both issues have
been mitigated in this lbmk patch, by patching the upstream
coreboot build system in this patch.

As part of this change, the coreboot/next tree within lbmk
has been updated. Existing patches have been rebased.

This brings in the following changes from upstream, relative
to the previous revision used on coreboot/next:

* 2f1e4e5e85 mb/hp/snb_ivb_desktops/z220*: Remove leftover old usb configurations
* 9e859154ea mb/hp/snb_ivb_desktops: Remove unused includes
* 70b33cb38d ec/google/chromeec/acpi: Add support for generic LPC memory range
* f2ad73b5d1 mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz
* 044017b4cd mb/google/rauru: Initialize PMICs in romstage
* 397c3e3c52 mb/google/fatcat/var/fatcat: Add touchpad wake source
* e18f0f53cb mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
* a8b4ee246d mb/google/nissa/var/rull: Configure Acoustic noise mitigation
* c09fd09edf tree: Use "true", "false" for has_power_resource
* 1e64875265 mb/google/fatcat: Remove unused <stdio.h>
* f316ab6796 mb/google/fatcat/var/francka: Fix early pad configuration for TPM
* 6ca2c3c415 soc/mediatek/mt8196: Fix indentation in Makefile.mk
* 94c1307fdb soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
* 67b140a949 tree: Use "true", "false" for fine_grained_control
* 97923aebe1 mb/prodrive/atlas: Add initial support for options
* 1a16146795 Fix up CFR's open issues
* 7e8d8cdea2 mb/google/rauru: Initialize SPM
* 3153432b83 soc/intel/alderlake: Add function to force disable memory channels
* 8ea2b0ab46 mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F
* 5f600a8ee9 mb/google/fatcat: Limit Power Limit when battery is missing
* 5213646241 ec/google/chromeec: Add function to detect barrel charger
* 5ef70e5f22 ec/google/chromeec: Add API to check if battery is critically low
* 42fd35b486 ec/google/chromeec: Add API to check if charger is present
* 56370d0283 ec/google/chromeec: Add API to check if a USB PD charger is attached
* 001e7a0b45 soc/mediatek/mt8196: Add MT6685 Clock IC driver
* 5852841ca7 soc/intel/meteorlake: Use ASPM helpers from Alder Lake
* b04f057efd mb/google/rex/var/kanix: Add Synaptics touchpad
* af0c2e7a2e mb/prodrive/atlas: Remove the workaround for CLKREQ pins
* 13316c644b mb/google/fatcat/var/fatcat: Modify interrupt GPIO for LPSS I2C touchpad
* 825e9173b4 soc/mediatek: Distinguish pmic_init_setting function name
* d65ff8492c soc/intel/xeon_sp/spr/acpi: Fix regression
* 291778a1bd mb/google/corsola: Add new board variant Wyrdeer
* 745dcc861d mb/google/corsola: Refactor mipi_panel_power_on function
* 79f60c6b22 mb/google/nissa/var/telith: Disable stylus function
* d7934bdd53 Doc/soc/amd/family15h: Fix URLs to AMD documents
* 3cb7db4075 soc/mediatek/mt8196: Add PMIC MT6316 driver
* 60bce10750 drivers/mipi: Add support for KD_KD110N11_51IE panel
* d4c80054a4 soc/mediatek/mt8189: Enable timer compensation v2.5
* 403846f177 soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE
* b3edaa7b10 mb/google/rauru: Implement SKU ID
* b470b48718 mb/google/rauru: Add support for getting storage id
* 24a5048948 mb/google/nissa/var/pujjo: Add new supported memory part
* c6e27c5fbf mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
* 639def1d84 mb/google/fatcat/var/fatcat: Enable FPS
* acb8c870b2 mb/google/fatcat: Suppress unnecessary extra space in device trees
* d79ba5565d mb/google/nissa/var/telith: Modify PLD for typeC and typeA
* 620d2fab06 soc/mediatek/mt8189: Replace SPDX identifiers to GPL-2.0-only OR MIT
* d90b1322ab commonlib: Refactor CSE sync eventLog
* 4ef6c13b38 mb/google/brya: Adjust EC memory map range to support indexed IO
* 1e90bbadfa ec/google/chromeec: Add indexed IO support
* a8ab708584 mb/google/nissa/var/quandiso2: Create a quandiso2 variant
* 78f610a0ae util/docker/doc.coreboot.org: Allow git to work in envs owned by root
* 38ee22f6da util/docker/doc.coreboot.org: Use Alpine minor instead of point releases
* 0196c3b6a4 util/docker/doc.coreboot.org: Get rid of bash workarounds
* 897b46693b util/docker/doc.coreboot.org: Don't create volumes
* a0c45cbf1f 3rdparty/fsp: Update submodule to upstream master
* aa562d2881 soc/mediatek/mt8189: Add GPIO driver
* 40a863cd60 soc/mediatek/mt8189: Initialize watchdog
* 1380ed0cd2 soc/mediatek: Add support for MediaTek firmware support package
* 4f92943c89 soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability
* 5a73692e0c soc/mediatek/mt8196: Add SPM loader
* 306660c2de util/crossgcc: Update CMake from 3.30.2 to 3.31.3
* f3adc74e44 mb/google/fatcat: Keep GSPIx interface default PCI
* 809e704101 soc/intel/pantherlake: Rename GSPI2 to GSPI0A
* 222ef676f9 soc/intel/pantherlake: Add ACPI name for GSPI2
* 1fda7027c0 util/crossgcc: Update ACPICA from 20230628 to 20241212
* e35175bb38 Update vboot submodule to upstream main
* 9eb4c5aff8 util/ifdtool: Fix memory leaks
* 87ae3573b5 mb/starlabs/starlite_adl: Configure GPIO interrupt for Virtual Button
* eaf87422b1 ec/starlabs/merlin: Add Intel Virtual Button Driver for Tablet Mode
* a1532790b9 docs: Add 24.12 release notes
* 8c0df740c7 mb/google/nissa/var/gothrax: Add probe and GPIO config for HDMI and  touchpanel
* f6fcff5511 docs/security/vboot: Update supported boards
* 0dba17da0c mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
* 2c4af7cd29 mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
* c11558d4c7 mb/asus/p8z77-m: Drop GPIO by I/O
* 4f1a1adef6 mb/topton/adl: Disable mapped SATA port
* 81cbe11361 mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
* 9578c67c77 mb/google/brox: Include CSE reset in mainboard reset expectation
* 5af5e66686 util/cbfstool: eliminate late sign of life event
* 0797c40d52 src/soc/intel/cmn/blk/cse: Log cse sync information
* 9a15a1ed21 soc/intel: Log CSE Sync Early Sign of Life event from a better place
* c812c78618 mb/trulo/var/uldrenite: Support USB_OC on the A0 port
* ee1a766f05 mb/trulo/var/uldrenite: Set GPP_B5 and B6 to ISH function
* 87c9d93a62 mb/google/skywalker: Add MediaTek MT8189 reference board
* 6bd51ce42a soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
* ea646c0514 mb/google/rauru: Add pwrsel init in romstage
* c3265da005 soc/mediatek/mt8196: Add pwrsel driver
* 30d8e1880a ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
* bb85775d92 soc/intel/cmn/acpi: Add ACPI method to get LGMR address
* 84347d0b45 payloads/Linuxboot: Fix u-root build
* 7bcec7a2ef payloads/LinuxBoot: Build x86_64 with host toolchain
* e3150e819d util/crossgcc: Add libstdcxx target
* 61385c4976 soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders
* 6625dee027 soc/mediatek/common: Use array to represent spm_sw_rsv registers
* cd8d6861f6 soc/mediatek/common: Move some functions to spm_v1.c
* 91fe658714 drivers/option: Add forms in cbtables
* 4d4776f320 mb/emulation/qemu-sbsa: Configure flash region for MMU
* dfef1895f2 mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
* caf8f9f60f mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices
* b668c756bf mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
* 941f994809 mb/trulo/var/uldrenite: Configure Network
* 600e7810fb mb/trulo/var/uldrenite: Configure USB ports and mapping
* 0261cbe8e9 mb/trulo/var/uldrenite: Configure serial_io and I2C
* 113205bcd1 mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters
* 0dd227f9c1 mb/trulo/var/uldrenite: Enable DPTF, S0ix and configure FIVR setting
* 0ce153c8df mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
* b57308f437 mb/google/rauru: Add SD card configurations
* e969a3df87 soc/mediatek/mt8196: Add SD card configurations
* 8be835ce3c soc/mediatek/mt8196: Add tracker driver
* 78560f9958 soc/mediatek/mt8196: Add MMinfra driver support
* 0b252ef8b4 util/mtkheader: Add GFH header for mt8189 bootblock code
* 540eb5ba73 cpu/qemu: Enable IDT_IN_EVERY_STAGE
* f9d6fd4e0f soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
* c3dee9eaba cpu/intel/car/romstage: Fix false-positive stack corruption
* b659fb5cea mb/ocp/tiogapass: Wait for BMC
* 7c0556244d drivers/wifi: Update Drive Strength BRI Rsp Table revision
* 70bdd2e1fa cpu/x86/topology: Simplify CPU topology initialization
* 3a2ffba231 soc/intel/xeon_sp: Introduce early_pch_init
* 48ed4b0f85 soc/intel/xeon_sp/lbg: Add support to hide HDA
* a857c81122 arch/x86: Disable DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
* 45dabe846d mb/google/brox: Apply ISH_FW_VERSION in Kconfig
* e0b1a0dbec vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
* c20fd2fc3f 3rdparty/fsp: Update submodule to upstream master
* e5b5fc345a soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
* 673075f102 util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
* 3235b7c6d5 commonlib: Add ELOG_TYPE_FW_CSE_SYNC eventLog type
* 4a0c49e671 soc/intel/pantherlake: Keep image clock configuration enable
* 51cc2bacb6 soc/intel/pantherlake: Disable stack overflow debug options
* eeb6f67eec Docs: Convert bare URLs into hyperlinks
* 2609519704 mb/google/rauru: Implement regulator interface
* 8c6426c1b4 soc/mediatek/mt8196: Add PMIC MT6373 driver
* bda5b83661 mb/google/brya/var/uldrenite: update gpio settings
* afb11d05b9 mb/google/trulo/var/uldrenite: Add memory config
* 46df9e1d38 mb/google/brya/var/marasov: Enable GPP_F9 GPIO for early panel power-on
* 04d33b90ec mb/google/fatcat: config GPP_F23 as ISH gpio pin
* 16ab83b34a soc/mediatek/mt8196: Initialize SSPM
* b793209b80 mb/google/brox/var/jubilant: Disable Tccold Handshake
* 2f1e67bbc7 mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
* a1c50f233d soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
* 8910b6ba7d soc/mediatek/mt8196: Add PMIC MT6363 driver
* c215889442 soc/mediatek/mt8196: Add PMIF and PMIC driver support
* 27fa0595de soc/mediatek/mt8196: Add mtcmos init support
* 61a00269a2 mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
* 38b59164ca ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
* 50c9747d87 drivers/usb/intel_bluetooth: Add GBTR Method
* 0bb4a220a8 soc/intel/common/cnvi: Fix GBTE path in comment
* d33244c3af drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
* 04b9627e07 drivers/usb/intel_bluetooth: Fix GBTE to return Local0
* c3f9dd3af3 drivers/usb/intel_bluetooth: Change the Power Resource to S0
* 1cf8d84f3b mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
* 62a9d670bf mb/google/brya/var/uldrenite: Add HDA verb tables
* 56278eeed8 mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config
* 6d3346068b intel/common/block: Program the right power_limits_config entry
* 35bf4bc59c commonlib: Add generic word-at-a-time optimization to ipchksum()
* e987ba45d6 soc/mediatek/mt8196: Add booker driver
* aa3cfd5c69 haswell NRI: Post-process selected timings
* 4a4ad2b1e6 haswell NRI: Initialise MPLL
* 41c2e1685e soc/intel/xeon_sp: Add PCU PCI drivers
* 8721757aca soc/intel/xeon_sp/skx: Configure IOAPICs
* e9c546b153 arch/x86: Rename breakpoint removal function
* 0351872731 arch/x86: Add breakpoint to stack canary
* 572da7c524 acpi/acpigen: generate Create*Field() from name string directly
* 2e9aebf63f mb/google/fatcat: Enable Intel DPTF support and configure policies
* a8ff286185 mb/google/fatcat: Enable Bayhub Level 2 errata
* 230e646d98 mb/google/fatcat: Remove redundant GPIOs for x1 slot
* fbacae625a soc/intel/ptl: Enable UFS functionality by adding IRQ programming
* b67e001a85 soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
* 2496943b5c mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
* dfdb210e26 soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq
* 223dabef56 soc/intel/common/block: Add const qualifier for input of pirq ops
* afc49fa013 soc/intel/xeon_sp: Remove lpc_lockdown_config
* 1a4ab38035 soc/mediatek/mt8196: Rename SCP to SPM base variables
* 3189afbdee soc/intel/common: Drop locking function fast_spi_set_vcl
* 01bf34cb28 soc/intel/xeon_sp: Support _PRT reporting for domain
* 1399dd8086 soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting
* a5362f6d73 soc/mediatek/mt8196: Enable ARM Trusted Firmware integration
* 42a696090f Update arm-trusted-firmware submodule to upstream master
* 861413b295 mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
* d5a11293ff soc/intel/alderlake: Add support for PCIe speed setting
* 5b447d00f5 soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
* 1c51c3e57f device/pci_ids: Add Pantherlake-H GT2 (DID2)
* 15109603c6 mainboard/ocp/tiogapass: Enable TPM
* 94d200c394 soc/intel/xeon_sp/cpx: Add missing FADT fields
* 534585d7bd soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042
* 98ca450a53 soc/intel/xeon_sp: Use generate_p_state_entries
* 28c03b501e mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
* 74ee80d207 soc/intel/xeon_sp/cpx: Fix register lock
* e1a0e6b738 soc/intel/xeon_sp/skx: Fix CPU init
* b04ecb2a5f arch/x86: Enable support for IOAPIC devices
* a7437ca340 soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
* 0d284bfc36 soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include
* aeb5ccd129 ec/dasharo/ec: add Dasharo features
* 820c7e06d2 soc/mediatek/mt8196: Set DRAMC_PARAM_HEADER_VERSION to 4
* d8104af174 mb/google/rex/var/kanix: Disable FP_MCU based on fw_config
* 075a13b775 mb/google/fatcat: Update Soundwire codec address based on devicetree
* 2411942a05 drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
* 534f81d165 mb/google/fatcat: Update flash layout
* 1b175a64e3 soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number
* 4b574281f0 soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
* 4ce5304879 soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
* 5613f0e6be soc/intel/xeon_sp: Fix debug print
* 0d827a5810 soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
* d3aa108acf drivers/ipmi/ocp: Add missing include
* 37e9c22089 libpayload: configs: Add new config.featuretest to broaden CI
* bcced7caea commonlib/device_tree: Make END token part of struct_size
* 8ad1ee9b0a util/intelp2m: Print the current project version
* 1b9c312273 intelp2m/patform/sunrise: Add unit tests
* 2394795279 intelp2m/patform/lewisburg: Add unit tests
* bce3363412 intelp2m/patform/apollolake: Add unit tests
* 6abf66c8f3 util/intelp2m/parser/template: Add unit test
* 6b43e4ba33 MAINTAINERS: Add Yuchi and Vasiliy for Intel Atom Snow Ridge SoC
* 5cedebf874 soc/intel/xeon_xp: Remove 1 bytes losing in lower DRAM
* cd30d94ae5 mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
* cda1e7e553 mb/google/nissa: Create pujjogatwin variant
* c0ccace4d5 .checkpatch.conf: Set max line length to 96
* 6f2a8ee8cc soc/mediatek/mt8196: Require DRAM blob to exist
* 850cf7d07a Update blobs submodule to upstream main
* 75424efdc4 soc/amd/common/psp/psp_def.h: increase P2C_BUFFER_MAXSIZE
* 179945291c soc/amd/common/psp/rpmc: fix printk format string
* 9b308f4d54 soc/amd/common/psp/psp_smi: report errors in 'handle_psp_command'
* 5613f209c7 soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling
* b1f954bc6c soc/amd/common/block/psp/psp_smi_flash.h: fix struct element types
* ce01117aa5 drivers/spi: add RPMC support
* 78270ef3f1 Documentation/tutorial/managing_local_additions.md: Add symlink info
* 0a7c3ed514 soc/mediatek/mt8195: Fix SCP register address
* 4c8547704f mb/google/rauru: Add 2nd source TAS2563 amps to support beep
* ac83b48cba soc/mediatek/mt8196: Add audio base address definition
* c661933a24 soc/mediatek/common: Add read16/write16 support for PMIF
* c107755701 vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
* a417acdfbc mb/google/fatcat: Remove unnecessary prototype
* d095f1ea45 soc/amd/glinda: Update MCA banks
* 8df4eefd44 soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
* 5c766bc150 mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
* 2007792b08 mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
* 7f54139a81 Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax

Signed-off-by: Leah Rowe <leah@libreboot.org>

wip2

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:11:05 +00:00
Leah Rowe
411fb697df set up python in PATH, ensuring that it is python3
we already check the python version, and set a variable
for it, so that we can reliably use python3, even if
python in PATH doesn't correspond to python3. for
example if a system has python as python2 and python3
as python3

well, we use that when running deguard for example, but
various upstream projects that we use may need python,
and all of them use python3, not 2

so, re-use the python variable set up by lbmk, and
set it up in PATH accordingly. this now makes the note
about python3 obsolete, on docs/build.md in lbwww.git

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 21:48:45 +00:00
Leah Rowe
e8336bcc3c vendor.sh: Proper semantics on prefix file names
They may not actually always be binary blobs, at least not
software. I started referring to these as "vendor files" some
time ago, for this reason.

With this terminology, it applies properly to any sort of file
from the vendor. For example, it may be that in the future, we
start inserting the MFS section of an an Intel ME image, into
the Intel ME.

We already do that with deguard for example (set MFS config),
on MEv11 based setup. That is a vendor *file*, and though it
may still actually be a binary blob, it's not software, but
configuration.

The term "blob" normally means compiled software, in most people's
minds, but the term blob is technically accurate for any blob,
not just software; however, we have to keep people's perception
in mind.

Whereas, "vendor file" is also understood by most people to
include code supplied by the vendor.

We haven't done any releases yet with this ROM image file name
prefix, so it's perfectly OK to handle it now, without handling
the old one for backwards compatibility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:56:23 +00:00
Leah Rowe
63f4578263 vendor.sh: Confirm if need_files=n
Users running setmac on an X200 tarball for example, will
now see it being modified, if they didn't specify
setmac keep, so they might think vendor files are being
inserted, which they are not.

Therefore, a confirmation is provided at the end of the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:20:53 +00:00
Leah Rowe
13b06ae130 vendor.sh: Allow restoring the default GbE file
./mk inject libreboot-YYYYMMDD_board.tar.xz setmac restore

This does the same thing as a normal setmac command, except
that it does not alter the MAC address; it is also not the
same as "keep", which skips *writing* the GbE region in-ROM.

The *restore* argument writes the default, unmodified GbE file
kept by lbmk, unmodified because nvmutil is skipped when the
user specifies this argument.

This option is useful for debugging purposes, because it can
be used to verify whether anything else is being wrongly
modified by the script; the "nuke" command can be executed
afterward, and the hash file inspected versus release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:13:28 +00:00
Leah Rowe
ab8feff92e vendor.sh: set random MAC address *by default*
MAC addresses are generic, inside Libreboot images where
an Intel GbE region is specified.

We commonly get users flashing multiple systems for their
own use, and sometimes they complain that they networking
broke, because they don't know that the MAC address is
identical on each machine.

This still doesn't work around the case where the same machine
is used, e.g. multiple T440p thinkpads, but if they have one
of each model, it can work nicely, because we do in fact
change it for various platforms.

This change will also reduce the number of people at conferences
in the future, where there are multiple Libreboot users, having
MAC address conflicts.

Changing the MAC address is a good practise, so we enforce good
practise. The user can still retain the old behaviour by
using this command:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac keep

The "keep" argument clears new_mac, which will then skip
changing the MAC address. They can also still set an arbitrary
MAC address as an argument for setmac, e.g.:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac 00🇩🇪ad:c0:ff:ee

This change will be covered in the documentation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:48:50 +00:00
Leah Rowe
0ceaa01d45 vendor.sh: add clarification to nogbe warning
if the user ran this on an x60 tarball, the no-gbe
warning seems confusing since that one has intel gbe,
but pre-ifd, so no gbe region in the flash; on pre-ifd
systems e.g. ich7 southbridge, the mac address was baked
into a separate gbe nvm on mask rom, inaccessible to users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:31:14 +00:00
Leah Rowe
4d5caf1dcf vendor.sh: check that the vcfg file exists
setcfg already checks it, but it's good to check anyway

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:32:39 +00:00
Leah Rowe
fc4ee88e16 vendor.sh: error out if nuking failed
We already have code to handle this, but it's possible
that I might break it in the future, due to the complex
logic of this script.

So, I've implemented this catch-all check at the end of
the process. It still relies on the actual setting of
the variables, upon which this check is based, to be set
correctly.

This condition will most certainly never be met, unless
I break some other part of the code in the future. That
is precisely what this overly pedantic check is for.

Example scenarios:

I forget to set xchanged=y, on a new modification.

I set has_hashes erroneously.

The variables are re-used between runs, and not properly
reset; at present, a given run of ./mk inject only
operates on a single target, but this latter fact could
change in the future.

need_files is set erroneously; vendorfiles detected as
being required, when they aren't.

These are just a few examples. As such, this is a preventative
bug fix, because it's preventing a bug.

The main reason I want this i n here is because I need to ensure
that vendor files are properly deleted, for a given release.
If I accidentally includes ones that I'm not supposed to,
inside ROM images, that could be a big problem.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:24:53 +00:00
Leah Rowe
8819a93d89 add line break, part 3
forgot a line break, three times in a rowe

you got a problem with that?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:33:18 +00:00
Leah Rowe
8ce1a00f51 add line break, part 2
because printf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:32:13 +00:00
Leah Rowe
bc2c14e76a add line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:30:23 +00:00
Leah Rowe
c762850311 vendor.sh: prevent double-nuke
where the nuke command is used, we need the files to be
there; if they're not, it will try to nuke them, which will result
in an error in most cases, but there may be some cases where that
isn't true, for instance if only the Intel ME is needed; it'll be
writing zeroes over zeroes.

we want to only allow technically correct behaviour, because
technically correct is the best kind of correct.

it is theoretically possible that a double-nuke might affect
certain behaviours unpredictably. for example, if vendor.sh
later integrates another tool that works whereby the same command
inserts or nukes depending on a certain condition, but with the
same command, and where that command would return zero in both
cases.

this is a preventative bug fix, because it fixes an issue that
does not yet actually occur in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:26:22 +00:00
Leah Rowe
68299ad05c vendor.sh: much more verbose errors/confirmation
the user must be well-informed as to the next step, which
this script directly influences

guide the user accordingly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:15:43 +00:00
Leah Rowe
b8e6d12f3d add libx86 to arch dependencies
needed to compile the "int" tool defined
under config/git/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 14:21:24 +00:00
Leah Rowe
cf8ad497b4 vendor.sh: Remove unnecessary return
The message at the end that states a file was
not modified, is not currently printed when vendor
files are not needed, and setmac is not used.

This patch fixes that, so the user now sees a
confirmation of such change, or lack thereof.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:36:50 +00:00
Leah Rowe
c858099b35 vendor.sh: Download utils even if vcfg unset
This is because the user may have specified setmac.

I tried without this change, on a fresh lbmk, setting
the MAC address on an X200 tarball, and it produced an
error that ifdtool was unavailable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:33:32 +00:00
Leah Rowe
ce16856a24 vendor.sh: Allow setmac if vendorfiles not needed
Observe the following prior patch:

commit 818f3d630c
Author: Leah Rowe <leah@libreboot.org>
Date:   Fri Jan 3 17:06:14 2025 +0000

    vendor.sh: Don't error if vcfg is unset

Now:

This patch made vendor inject more robust, and speeds
up the processing of images where no vendor files are
needed, but it broke setmac on such tar archives.

This new patch works around it. For example, I was
able to run ./mk inject on an X200 tarball to change
the MAC address; no vendorfiles are inserted, because
it's not needed.

The further check for whether a board uses Intel GbE
still protects against accidental modification.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:23:07 +00:00
Leah Rowe
4b51787d07 add less to arch dependencies
probably not actually needed, but it annoys me that it doesn't
come installed by default, and it's needed for certain git
operations

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 00:59:33 +00:00
Leah Rowe
8bd028ec15 lib.sh: Set python after dependencies
otherwise, the user can't install python, which is
in the dependencies. an irony!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 20:53:05 +00:00
Leah Rowe
44b6df7c24 update my copyright years on modified scripts
there are some lbmk scripts that i modified, starting
this year. update the headers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 18:09:03 +00:00
Leah Rowe
818f3d630c vendor.sh: Don't error if vcfg is unset
It should return 1 instead, in readcfg(), because this
is not an error condition; vcfg not being set means
that the board doesn't use vendor files, which is
perfectly normal and should not yield an error.

This fixes a build error under certain conditions,
found during release-build testing.

This bug was exposed when I fixed double quoting issues
as per shellcheck tests.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 17:08:05 +00:00
Leah Rowe
432a1a5bca lib.sh: Fix unescaped quotes in chkvars()
This should be the proper fix now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 16:00:11 +00:00
Leah Rowe
a73b0fd910 Revert "fix more unescaped quotes in eval"
This reverts commit ec6bcc1fba.
2025-01-03 15:56:41 +00:00
Leah Rowe
ec6bcc1fba fix more unescaped quotes in eval
it should fix more build errors that might have appeared
in the aforementioned revision, mentioned in the previous
commit message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 15:43:27 +00:00
Leah Rowe
5284f20b98 fix ./mk dependencies build issue
the bug was actually caused by chkvars

add an escape for the quotes and bam. fixed.

without this, i got the following e.g.

For command: ./mk dependencies debian

Output:

./mk: 1: [: apt-get: unexpected operator
ERROR ./mk: pkg_add unset

Someone reported a similar issue with the Arch one,
which is also now fixed. This regression was caused
by the previous commit:

commit 0cf58c2273
Author: Leah Rowe <leah@libreboot.org>
Date:   Thu Jan 2 23:52:45 2025 +0000

    fix lbmk shellcheck errors

I forgot to escape the double quotes in an eval.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 14:35:31 +00:00
Leah Rowe
d825f9a968 rom.sh: Remove errant GRUB modules check
This check is a good idea, but not viable here,
because the modules naturally aren't set in all
circumstances, so it just causes a build error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:34:42 +00:00
Leah Rowe
4149f3dc81 submodule/grub: use codeberg for 1st gnulib mirror
the gnu.org mirror is always slow for some reason, but only
for gnulib. it may only be for me, because routing in other
countries/networks may differ.

when i'm freshly cloning lbmk modules, gnulib is always really
slow, like 300KB/s (bytes, not bits)

i have 1gbps internet and wish to not have 2005-era speeds,
thank you kindly!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:19:59 +00:00
Leah Rowe
0305975e70 util/nvmutil: Update AUTHORS and COPYING files
Mention Riku's copyright in the COPYING file, and update
my years in that file. Add Riku to the AUTHORS file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:24:09 +00:00
Leah Rowe
20b192e13b util/nvmutil: Describe nvmutil in help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:15:18 +00:00
Leah Rowe
d1ca21628c util/nvmutil: Remove the correct binary on uninstall
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:13:01 +00:00
Leah Rowe
e63fe256df util/spkmodem-recv: More correct Makefile
Set up the DESTDIR variable properly. Otherwise,
this is just style changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:09:55 +00:00
Leah Rowe
efd50ee548 util/nvmutil: Honour the INSTALL variable
Don't assume "install" is the correct command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:08:38 +00:00
Leah Rowe
8008838abb util/nvmutil: Don't clean when doing uninstall
The user might wish to uninstall, but not remove the
build that they just did.

The user can still do make clean if they wish.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:06:12 +00:00
Leah Rowe
982f257f58 util/nvmutil: Proper DESTDIR/PREFIX handling
DESTDIR is the root directory where it goes, which
is normally an empty string; PREFIX is where the
bin directory is located, relative to DESTDIR

Default to /usr/local for PREFIX, not /usr, because
/usr/bin is for system utilities.

nvmutil is a local utility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:03:44 +00:00
Leah Rowe
3f85ae5f85 util/nvmutil: Set CC and CFLAGS only if unset
We don't want to clobber anything that the user set themselves.

Instead, we should respect the user's choice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:48:52 +00:00
Leah Rowe
2c7b9fb941 util/nvmutil: Capitalise BABA
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:45:55 +00:00
Leah Rowe
57f9906f6d util/nvmutil: Add uninstall to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:41:46 +00:00
Leah Rowe
4defe2c608 util/nvmutil: Add distclean to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:39:46 +00:00
Leah Rowe
033e4cd9d5 util/nvmutil: Make the GbE checksum a define
This makes the code easier to understand.

All 2-byte words, stored in little endian order within
the 128-byte GbE NVM area, must add up to 0xBABA.

If it doesn't, then software is supposed to reject that
GbE config. The nvmutil software works on that basis.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:36:44 +00:00
Leah Rowe
874317c4e5 util/nvmutil: nicer hexdump display
make it look like hexdump -C, where individual bytes are
spaced, and there is an additional space after 8 bytes,
per row.

i won't bother with a character display, since that is
meaningless on gbe nvm words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:36:17 +00:00
Leah Rowe
a338e585ee util/nvmutil: show the correct hexdump order
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:26:32 +00:00
Leah Rowe
b032e483ef lib.sh mktarball: cleaner if statement
i also removed that printf, because the path it prints is
actually wrong sometimes; in the recent re-write of vendor.sh,
it prints the correct path instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:58:37 +00:00
Leah Rowe
0cf58c2273 fix lbmk shellcheck errors
There was also a condition in run_make_command that is now
an OR, where it was an AND, on script/trees, to fix the use
of mixed (and erroneous) OR/AND operators.

I'm planning a much more invasive audit than this. These are
light fixes, intended for Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:52:45 +00:00
Leah Rowe
8276560cc9 lib.sh and rom.sh: update my header
i made modifications to them in 2025, so
update them to 2025

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 18:33:55 +00:00
Leah Rowe
08e86d2218 vendor.sh inject: reset err upon return
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 10:17:39 +00:00
Leah Rowe
41275d699c vendor.sh: MUCH, MUCH, MUCH safer ./mk inject
Don't extract to bin/release/

Modify the tarball instead. Previously, the tarball would
not be modified, but a lot of users thought the tarball was
being modified and ignored bin/release/, where the injected
images were actually being saved to.

Don't copy the tarball either. Just modify it in-place.

Don't allow single-rom injection either; only allow the
tarball-based method.

The command syntax has changed, but:
./mk inject tarball.tar.xz

This is the same. What has changed is nuke, and MAC address
modification. Observe:

./mk inject tarball.tar.xz nuke
./mk inject tarball.tar.xz setmac
./mk inject tarball.tar.xz setmac ??:??:??:??:??:??
./mk inject tarball.tar.xz setmac 00:1f:16:??:22:aa

These are just a few examples. The MAC address syntax is
the same as used for nvmutil, which means you can set it
randomly. Also:

./mk inject tarball.tar.xz setmac

You can use the *setmac* command *repeatedly*, even if
you've already injected a given archive. It'll just
update the archive, but skip injecting other files
that were already injected.

If you use setmac without a MAC address, it will randomise
the MAC address. This is therefore very similar to the
command structure used in nvmutil.

The code for injection is generally more robust, with
stronger error checks. This design change was done, so
that the user doesn't accidentally brick their machine.

The non-injected images have a prefix in the file name
saying "DO_NOT_FLASH", and those non-injected images are
padded by 1 byte. That way, the user knows not to flash it
and if they try, flashprog will throw an error.

The prefix and padding is removed on injection. Old images
without the padding/prefix can still be injected, via
tarballs; this new code is backwards-compatible with tarballs
from older Libreboot releases.

A common thing I see sometimes is a user will say they have
a black screen or something, and I say: did you insert vendor
files? And they say yes. And they did. But they extracted and
flashed from the tarball, which wasn't injected, because
they didn't release about bin/release/

No amount of RTFM is justified. The previous design flaw
is a bug. We must always observe user safety first, no matter
what, so that has now been done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 08:46:36 +00:00
Leah Rowe
ed7293494e util/nvmutil: Obey the 79-character per line limit
Must not exceed 79 lines. Some variables and functions have
been renamed, and there has been some minor re-factoring.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 21:10:56 +00:00
Leah Rowe
637b5e36fd util/nvmutil: Tidy up copyright header
I don't like using SPDX for actual copyright declarations.

I only want it to be used for the license identifier.

Also:

I made a *single* change to nvmutil.c in 2024, which means
that I have copyright in all years since and including 2022;
the file said 2022, 2023, 2025, but it's actually 2022-2025.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 20:56:54 +00:00
Leah Rowe
cd28db883e vendor.sh: fix comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 18:30:57 +00:00
Leah Rowe
57971ceb22 util/nvmutil: Fix another straggler
I don't like using strings this way, it looks unclean.

Once again, use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 14:49:24 +00:00
Leah Rowe
15b37b2a1a util/nvmutil: Tidy up pledge calls
I wasn't too happy using shorthand for strings like that.

Tidy it up and use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 21:14:24 +00:00
Leah Rowe
e8799310db hp820g2: fix vendorfile inject and set release=y
I believed that the compressed nature of refcode was the only
non-reproducible thing, but turns out you also need to run
rmodtool on the refcode to make the binary relocatable in
cbfs. This is based on my reading of the coreboot Makefile.

With this change, I can now provide release binaries for
the HP EliteBook 820 G2.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 14:46:13 +00:00
Leah Rowe
f9ab082ec1 fedora41/dependencies: add libuuid-devel
it seems to be required for uuid/uuid.h

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:57:00 +00:00
Leah Rowe
661591f9f0 add uuid-devel to fedora41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:27:11 +00:00
Leah Rowe
1a46c04738 support ./mk dependencies fedora reinstall
dnf reinstall package

or

dnf install package

for reinstall, do this:

./mk dependencies fedora41 re

this is an example command

the 4th argument prefixes "install" in dnf install

a bit hacky but it should work

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:25:27 +00:00
Leah Rowe
d58d63569f fix missing semicolon in grub nvme patch
i  forgot this when rebasing on the recent uprev

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:22:11 +00:00
Leah Rowe
95ea3293df bump seabios to rev 1602647f1 (7 November 2024)
This brings in a *single* change from SeaBIOS, because there
has only been one change in the main branch, and it's a bug fix.

The change from upstream is as follows:

commit 1602647f1be24fe63d11138d802e735c8e674e63
Author: Daniel Khodabakhsh <d.khodabakhsh@gmail.com>
Date:   Thu Nov 7 18:46:16 2024 -0800

    boot: Force display of the boot menu when boot-menu-wait is a negative number

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:31:37 +00:00
Leah Rowe
6d7e6c361b Bump GRUB revision to 6811f6f09 (26 November 2024)
Although this is for a stable release revision, namely
Libreboot 20241206 revision 8, I've carefully audited the
upstream changes and they all seem fine.

Several important bug fixes have been imported with this change.
Most interestly, GRUB has also added support for TPM2 Key
Protectors; we don't use this feature yet, and probably won't
for the time being, since TPM is largely security threatre for
our purposes anyway. There's no harm including all upstream
revisions, up to those ones, since those modules are not yet
added in lbmk.

Most notably, there are several file system fixes, and minor fixes
to the graphics terminal of GRUB. Minor fixes only, in terms of
what Libreboot actually uses at present.

The full list of imported changes are as follows, relative to the
previous GRUB revision, which was b53ec06a1 from 17 June 2024:

* 6811f6f09 tpm2_key_protector: Enable build for powerpc_ieee1275
* ff14b89bd ieee1275/tcg2: Add TCG2 driver for ieee1275 PowerPC firmware
* 72092a864 ieee1275/tcg2: Refactor grub_ieee1275_tpm_init()
* 8c0b5f200 ieee1275/ibmvpm: Move TPM initialization functions to own file
* 7344b3c7c ieee1275: Consolidate repeated definitions of IEEE1275_IHANDLE_INVALID
* 29d1bd2a9 term/ieee1275/serial: Cast 0 to proper type
* 99ee68a01 tss2: Adjust bit fields for big endian targets
* 3770a6905 docs: Document TPM2 key protector
* f898440cc tests: Add tpm2_key_protector_test
* 76a2bcb99 tpm2_key_protector: Add grub-emu support
* 135e0bc88 diskfilter: Look up cryptodisk devices first
* b35480b48 cryptodisk: Wipe out the cached keys from protectors
* 6abf8af3c cryptodisk: Fallback to passphrase
* fba3a474e tpm2_key_protector: Implement NV index
* 550ada7d6 tpm2_key_protector: Support authorized policy
* 5f6a2fd51 util/grub-protect: Add new tool
* ad0c52784 cryptodisk: Support key protectors
* 48e230c31 key_protector: Add TPM2 Key Protector
* 35c9904df tss2: Add TPM2 Software Stack (TSS2) support
* 63a78f4b4 tss2: Add TPM2 types and Marshal/Unmarshal functions
* 2ad159d9b tss2: Add TPM2 buffer handling functions
* 5d260302d key_protector: Add key protectors framework
* 3d60732f9 libtasn1: Add the documentation
* 99cda6788 asn1_test: Test module for libtasn1
* 504058e82 libtasn1: Compile into asn1 module
* 8a0fedef2 asn1_test: Enable the testcase only when GRUB_LONG_MAX is larger than GRUB_INT_MAX
* 66cf4cb14 asn1_test: Use the grub-specific functions and types
* 0d0913fc6 asn1_test: Print the error messages with grub_printf()
* 2e93a8e4b asn1_test: Remove "verbose" and the unnecessary printf()
* b7568e335 asn1_test: Return either 0 or 1 to reflect the results
* d60a04bae asn1_test: Rename the main functions to the test names
* 54e0e19a2 asn1_test: Include asn1_test.h only
* 0ad1d4ba8 libtasn1: Fix the potential buffer overrun
* 4160ca983 libtasn1: Use grub_divmod64() for division
* 8f56e5e5c libtasn1: Adjust the header paths in libtasn1.h
* d86df91cb libtasn1: Replace strcat() with _asn1_str_cat()
* 32fdfe600 libtasn1: Replace strcat() with strcpy() in _asn1_str_cat()
* fa498af7b libtasn1: Disable code not needed in GRUB
* 9a26abbc3 libtasn1: Import libtasn1-4.19.0
* c85c2b9f5 posix_wrap: Tweaks in preparation for libtasn1
* 4f6c46091 kern/fs: Honour file->read_hook() in grub_fs_blocklist_read()
* 792132c72 docs: Fix incorrect and potentially confusing language and minor formatting
* 1763d83f5 docs: Correct GRUB config file name for network boot
* 097fd9d9a docs: Correct chainloader UEFI secure boot info
* f48e6af11 docs: Correct PXE environment variables descriptions
* dd743ba42 loader/multiboot: Do not add modules before successful download
* 9a9082b50 grub-mkimage: Add SBAT metadata into ELF note for PowerPC targets
* f97d4618a grub-mkimage: Create new ELF note for SBAT
* f26b39860 commands/legacycfg: Avoid closing file twice
* 337cb2486 nx: Rename GRUB_DL_ALIGN to DL_ALIGN
* 31de991de kern/acpi: Fix out of bounds access in grub_acpi_xsdt_find_table()
* f5bb766e6 nx: Set the NX compatible flag for the GRUB EFI images
* 94649c026 nx: Set page permissions for loaded modules
* 09ca66673 nx: Add memory attribute get/set API
* 9fb80dd57 modules: Load module sections at page-aligned addresses
* 6e2fe134e modules: Don't allocate space for non-allocable sections
* 2b79d550f modules: Strip .llvm_addrsig sections and similar
* 246c82cda modules: Make .module_license read-only
* 616adeb80 i386/memory: Rename PAGE_SIZE to GRUB_PAGE_SIZE and make it global
* 95a7bfef5 i386/memory: Rename PAGE_SHIFT to GRUB_PAGE_SHIFT
* 1b1061409 i386/msr: Extract and improve MSR support detection code
* 929fafdf5 i386/msr: Rename grub_msr_read() and grub_msr_write()
* d96cfd7bf i386/msr: Merge rdmsr.h and wrmsr.h into msr.h
* 86ec48882 commands/tpm: Skip loopback image measurement
* 3808b1a9b net/drivers/efi/efinet: Skip virtual VLAN devices during card enumeration
* e5f047be0 efi/console: Properly clear leftover artifacts from the screen
* c5ae124e1 kern/riscv/efi/init: Use time register in grub_efi_get_time_ms()
* 9c34d56c2 loader/efi/linux: Reset freed pointer
* 92bed41bf loader/efi/linux: Reuse len variable
* 33cb8aecd lib/x86_64/relocator_asm: Use .quad instead of .long
* 77cd623de lib/x86_64/relocator_asm: Fix comment in code
* 95145eea5 loader/efi/linux: Update comment
* d333e8bb3 util/grub-mkimagexx: Explicitly move modules to __bss_start for MIPS targets
* 34b7f3721 include/grub/offsets.h: Set mod_align to 4 on MIPS
* ed0651673 gentpl: Put boot/mips/startup_raw.S into beginning of the image
* 648f2d16c configure: Add -mno-gpopt option for mips and mipsel targets
* f0710d2d8 lib/xzembed/xz_dec_bcj: Silence warning when no BCJ is available
* e61157bbd fs/erofs: Replace 64-bit modulo with bitwise operations
* 5313fa839 configure: Look for .otf fonts
* 33b94f2a9 loader/efi/chainloader: Do not print device path of chainloaded file
* ab1e6fc04 docs: Document all GRUB modules
* 9537f4403 commands/bli: Fix crash in get_part_uuid()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:13:58 +00:00
Leah Rowe
09a01477df t480/3050micro: force power off post power failure
The T480 has no option table, because it lacks nvram, so the
default option applies, which seems to be power on after power
failure. This is undesirable on a laptop.

It's triggered simply when your laptop battery runs out, and
once triggered, it couldn't be configured at all.

Hard-code this. The documentation will be updated later on
after this patch is pushed, telling those users who want
to change this behaviour how to modify/remove the patch,
if they wish to to do so, because some people may actually
want to run a server on the OptiPlex 3050 Micro (or if they're
crazy like I am, they will host libreboot.org on a ThinkPad).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 01:54:02 +00:00
Leah Rowe
d344cd95ea flashprog: Disable -Werror
We haven't seen any build errors, but it seems flashprog
sets -Werror on CFLAGS. If you provide WARNERROR=no as
a make argument, it avoids -Werror entirely.

This is a preventative fix, for over-zealous compilers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:12:21 +00:00
Leah Rowe
dc95e912bf bump flashprog to revision eb2c041 (14 Nov 2024)
This brings in several important bug fixes from upstream.

With this, the following upstream changes have been imported:

* eb2c041 cli_wp: Fix bail-out when multiple chips are detected
* e05e334 cli_common: Rename local `optarg' variable
* efad610 manibuilder: Include NetBSD (anita tags) in `native' target
* 09289fb manibuilder: Replace unmaintained DEFAULT_TAGS list
* 1457cc6 manibuilder: Stop build testing oldest, EOL targets
* 1faffa5 manibuilder: Fix Ubuntu Noble Numbat (24.04) for amd64
* 61dbe36 udev rules: Use `uaccess' tag instead of `plugdev' group
* 63d30a2 install: Install binary into bin/, not sbin/
* 6ce26a7 flashchips: add Winbond W25R512NW / W74M51NW
* 612519b ichspi: Add Intel Arrow Lake support
* d5a61ef ichspi: Add Intel Lunar Lake support
* 5e0d9b0 ichspi: Add Intel Meteor Lake SoC
* 0ef2eb8 ichspi: Add Intel Snow Ridge SoC
* 42daab1 ichspi: Properly add Emmitsburg PCH
* af26008 ich_descriptors_tool: Add missing options for EHL & C620
* 82fe123 ich_descriptors: Hard code number of masters for newer gens
* 157b818 ich_descriptors: Guard MCH strap handling by chipset version
* db878fb ich_descriptors: Drop chipset detection based on `freq_read`
* b3cc2c6 ich_descriptors: Unify pretty printing of PCH100+ masters
* 8e4151d chipset_enable: Remove hidden-spidev workaround for Elkhart Lake
* 6d72efa chipset_enable: Remove hidden-spidev workaround for all 14nm PCHs
* 092a699 chipset_enable: Remove hidden-spidev workaround for TGP+
* 5bbd324 chipset_enable: Add missing PCI ID for Intel PCH H410
* a088475 chipset_enable: Factor PCH100 hidden-spidev workaround out
* 5eb7a58 Drop 1s delay before automatic verification
* 7427569 libflashprog: Run programmer_shutdown() on failed setup
* 5a9d6ea chipset_enable: Fix memory leaks introduced with AMD SPI100
* e149fbe Only try to check erase opcodes for SPI25 chips
* 07ebc68 Avoid NULL deref in check_block_eraser()
* 2405310 chipset_enable: Mark Intel QM87 as DEP
* 9897063 flashchips: Allow volatile register writes for W25Q128.V
* c972aed flashchips: Configure WP for MX25L25635F/45G
* 8f7122c cli: Add new write-protect CLI
* eed122d layout: Implement flashprog_layout_get_region_range()
* 1f693db cli: Add new `config' CLI for status/config registers
* 85c2cf8 cli: Implement "command" option parser
* 24c0977 cli: Add print function for generic CLI options
* b82aadc cli: Move some declarations into `cli.h`
* a705043 cli: Add a new CLI wrapper
* d39c7d6 cli: Extract basic CLI init into cli_common
* df6ce9f cli: Extract log argument parsing into cli_common
* 0da839b cli: Extract layout argument processing
* d91822a cli: Extract layout argument parsing into cli_common
* e7899a9 cli: Move all long-option keys into cli.h
* 34e783a cli: Extract flash argument parsing into cli_common
* e68b08b cli_classic: Rewrite programmer argument parsing
* 6898f5b spi25_statusreg: Prefer volatile status register writes
* 55e7884 Introduce FLASHPROG_FLAG_NON_VOLATILE_WRSR
* fbba454 Install udev rules
* 768cfc4 flashchips: Add GigaDevice GD25LR512ME

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:03:12 +00:00
Leah Rowe
27c8c1c16b replace liblz4-tool with lz4 and liblz4-dev
In Debian dependencies files. These are available in
Debian Stable, but liblz4-tool is a transitional
package referring to lz4; liblz4-tool transition
package is unavailable in Debian sid, so remove it
from the dependencies files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 22:31:24 +00:00
Leah Rowe
d3a732a64d lib.sh dependencies: support --reinstall argument
./mk dependencies debian --reinstall

Add --reinstall and it'll do:

apt-get install --reinstall

This can be useful when updating from a stable release
to a testing release. The variable, "reinstall" can be
configured for other distros, but it's currently only
configured for Debian-based distros.

Also, it can be anything. For example, you could add -y;
however, a 4th argument will not be accepted. For example,
you cannot do:

./mk dependencies debian --reinstall -y

If you do this, it'll only see --reinstall; similarly, if
you did this command:

./mk dependencies debian -y --reinstall

then -y would be passed, but not --reinstall. This is an
intentional design decision, in case you accidentally pasted
or subshelled something that outputted something undesirable,
to prevent possible abuse.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:53:55 +00:00
Leah Rowe
466ada423d move xbmkpath to XBMK_CACHE/
When doing ./mk release, the build system would create
symlinks inside xbmkpath/ relative to the current work tree,
which will differ from what's in PATH.

Since XBMK_CACHE is already set globally, from the main work
tree and the release-build work tree, that means we can know
reliably that PATH is always correct if we put xbmkpath/
inside XBMK_CACHE.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:25:55 +00:00
Leah Rowe
b0a2384032 Revert "Remove legacy update/vendor commands"
This reverts commit 7813205146.

I'm doing changes for 20241206 rev8. It was a mistake to
remove these; they will be removed again, after rev8.

The documentation standardised on ./mk a while ago now, and
it's almost time to remove these commands. However, anyone
using the old commands ought to be able to, up to and including
any revision of the Libreboot 20241206 release.

It is my intention that these legacy commands finally be
removed for the next testing release, as part of a much wider
build system audit that I'm doing between now and then.

(Libreboot Build System Audit 7 is underway, and several of
these early audit7 changes are going on 20241206 rev8; after
that, I will create a branch named 20241206_branch off of rev8,
and anything in master from then on will contain much wilder
changes, with more conservative changes in 20241206_branch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:06:05 +00:00
Leah Rowe
3d7dd4aa9f Fix U-Boot build issue with Swig 4.3.0
Tested on Debian Sid, as of 30 December 2024, which uses
Swig 4.3.0. Context here:

commit a63456b9191fae2fe49f4b121e025792022e3950
Author: Markus Volk <f_l_k@t-online.de>
Date:   Wed Oct 30 06:07:16 2024 +0100

    scripts/dtc/pylibfdt/libfdt.i_shipped: Use SWIG_AppendOutput

This patch from U-Boot upstream has been backported to the
release revision used by Libreboot. Swig has, since 4.3.0,
changed the language-specific AppendOutput functions, but
the helper macro SWIG_AppendOutput is identical; therefore,
upstream switched to this function.

The benefit of this fix is that since the newly used macro
is also the same on older Swig versions, and behaves the same,
this shouldn't fix building on older Swig versions. For reference,
the initial Libreboot 20241206 release, and revisions of it before
revision 8, was built on Debian 12 which uses Swig 4.1.0.

The rev8 release will still be compiled on Debian 12, but with
this change, it should also compile on Debian Sid, and bleeding
edge distros like Arch Linux.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 20:24:46 +00:00
Leah Rowe
0c81074746 use command -v instead of which
which is a non-standard command, whereas command is part of posix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 19:23:27 +00:00
Leah Rowe
6c7e3ce2d6 trees: remove unnecessary subshell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:38:42 +00:00
Leah Rowe
ad137eae89 trees: only symlink host gcc/gnat to build xgcc
In general, we don't want to mess with the hostcc, unless
we have to. To avoid other breakage, clear what we did
after crossgcc has compiled.

This is a follow-up to the previous patches, matching gcc
to gnat versions and vice versa, when compiling crossgcc.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:36:46 +00:00
Leah Rowe
cfb6de94c3 trees: correction on check_gnu_path
i intend for this function to work generically,
matching gnat to gcc or gcc to gnat, but there was
a hangover from the previous code where it specifically
assumed we were matching gnat

this bug manifested when i tested with gnat being v13
and gcc being v14 in path, where gcc-13 was also
available in path.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 17:59:19 +00:00
Leah Rowe
ec2f071666 trees: match gcc/gnat versions both ways
on debian trixie/sid after updating from stable,
sometimes gcc 13 and gnat 13 are both available, but
gcc resolves to gcc-14 and gnat-14 isn't available.

even when gnat-14 and gcc-14 are available, gnat will
still either resolve to gnat-13, or nothing at all.

in cases where gnat-14 is unavailable, but gcc and gnat 13
are both available, we should match gcc to gnat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 15:29:41 +00:00
Leah Rowe
f64b599627 Merge path.sh into script/trees
The code is simple enough now that I'm happy for it
to just be part of the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:14:19 +00:00
Leah Rowe
295463d281 path.sh: Further cleanup
Remove all symlinks each time, to ensure that no
stragglers are left behind, since they are being
re-generated each time anyway.

The code for determining version numbers has now
been unified under gnu_setver()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:11:45 +00:00
Leah Rowe
5b24e0a5a9 path.sh: More thorough gcc/gnat version check
We were checking the shorthand version number, but
the precise version numbers need to match.

Also: when we searched $PATH/gnat-$gccver, we assumed
that the full version would then match, without checking
it, so now it is checked precisely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:36:34 +00:00
Leah Rowe
7849a07588 path.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:18:57 +00:00
Leah Rowe
17168a87db path.sh: remove unnecessary shebang
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 02:24:23 +00:00
Leah Rowe
e565df94fd Fix globbing issue in lbmk
When doing e.g. $@ we should use double quotes to prevent globbing.

Thanks go to XRevan86 for pointing this out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 01:02:22 +00:00
Leah Rowe
c80cc0a00b remove auto-confirm on distro dependencies
because if it says yes to everything, and the package
manager would otherwise ask whether you want to give
it your first born son, you are therefore agreeing to it.

so remove -y for safety

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:29:04 +00:00
Leah Rowe
01fc65a0a9 Mitigate Debian Trixie/Sid GCC/GNAT version mismatch
When I tested Debian Trixie, and Debian Sid, I saw that
GCC in PATH pointed to gcc-14, but gnat in path pointed
to GNAT-13, even if you manually install gnat-14.

GNAT 14 was marked experimental, but GCC 14 was marked
for use, in the apt repositories.

So this patch doesn't address the mismatch when doing e.g.
apt-get install gcc gnat

I will address the actual package dependency in a follow-up
patch, on the Debian dependencies config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:21:02 +00:00
Leah Rowe
424b0c7103 t480/3050micro: disable hyperthreading
Hyperthreading is a risk factor for spectre/meltdown
and other attacks.

Disabling it is a best practise. Those who need it
can always turn this option back on. Otherwise, disabling
it by default is a simply courtesy to the average user,
in the interest of security.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 02:10:03 +00:00
Leah Rowe
603105f3b4 t480/t480s: Disable TPM2 to mitigate SeaBIOS lag
SeaBIOS was lagging a lot, on startup and when executing
almost any payload, especially when doing anything in the
ESC menu.

I set the debug level to *21*, and thoroughly analysed the
logs. I found entries such as this:

Checking for bootsplash
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_StirRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_GetRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_HierarchyChangeAuth = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc16e
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc1c5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc211
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc25d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2a9
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2f5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc341
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc38d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc3d9
Searching bootorder for: HALT
Mapping hd drive 0x000f49e0 to 0

I'm not quite certain what the problem is, but disabling TPM2
made the problem go away; SeaBIOS is snappy again.

TPM is security threatre anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 01:20:33 +00:00
Leah Rowe
754bd1e6ca rom.sh: Name pico directory serprog_pico
Previously serprog_rp2040, but we now also support
the RP2530 boards.

Therefore, serprog_pico is a nice generic name. The
directory on release archives will now be serprog_pico
instead of serprog_rp2040; it will contain serprog images
for both RP2040 and RP2530 devices.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 16:46:59 +00:00
Leah Rowe
db22308eba add 2024 to Riku's copyright header on rom.sh
he forgot to do this in the recently merged pico2
support. i'm doing it for him as a matter of courtesy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 13:24:01 +00:00
Leah Rowe
4fa5f696db Merge pull request 'rp2530' (#258) from Riku_V/lbmk:rp2530 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/258
2024-12-28 12:26:39 +00:00
Riku Viitanen
a5e0360992 pico-sdk: update to 2.1.0
this brings support for a new microcontroller platform rp2530.

total number of pico boards supported now: 97

TEST: built them all

Tested-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 04:02:08 +02:00
Riku Viitanen
e2f8cc7f3e pico-serprog: enable building for multiple pico chips
rp2040 and rp2530 platforms can't share a cmake build directory. we
could just delete the build directory after every compilation, but that
would be really wasteful (every tool would need to be recomiled every
time. instead create new build directories as new plaforms are found
and symlink them to the point where the build directory used to be.

to find out which platform we're compiling for, we crudely parse the
board headers file.

there surely would be better ways to do this, but this hack works
with all the boards in pico-sdk 2.1.0.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 03:53:25 +02:00
Leah Rowe
ccc2b4d589 add spdx headers to dependencies configs
these used to be separate scripts under gpl 3+, so it makes
sense to clarify the licensing situation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 14:01:07 +00:00
Leah Rowe
a3969701e6 dependencies/debian: fix debian sid
change python3-distutils to python3-distutils-extra

the latter is still available in debian sid, but not
the former. however, installing this should still
provide the additional files required.

with this, the debian script is now compatible with
both debian sid and debian stable(bookworm, presently).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 13:58:29 +00:00
Leah Rowe
8f370cb60d add spdx headers to various config files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 02:24:38 +00:00
Leah Rowe
d591ea4c5d git.sh: don't initialise livepull globally
set this variable in the tmpclone function. otherwise,
certain submodules might always download every time,
when handling multiple projects.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 23:47:48 +00:00
Leah Rowe
b5da9feba3 vendor.sh: Print useful message on ./mk inject
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:25:07 +00:00
Leah Rowe
12c6259cb2 vendor.sh: Handle FSP insertion post-release
The Libreboot 20241206 release provided FSP pre-assembled
and inserted into the ROM images; the only file inserted
by vendor.sh was the Intel ME.

Direct distribution of an unmodified FSP image is permitted
by Intel, provided that the license notice is given among
other requirements. Due to how coreboot works, it must split
up the FSP into subcomponents, and adjust certain pointers
within the -M component (for raminit).

Such build-time modifications are perfectly fine in a coreboot
context, where it is expected that you are building from source.
The end result is simply what you use.

In a distribution such as Libreboot, where we provide pre-built
images, this becomes problematic. It's a technicality of the
license, and it seems that Intel themselves probably intended
for Libreboot to use the FSP this way anyway, since it is they
who seem to be the author of SplitFspBin.py, which is the
utility that coreboot uses for splitting up the FSP image.

Due to the technicality of the licensing, the FSP shall now
be scrubbed from releases, and re-inserted.

Coreboot was inserting the -S component with LZ4 compression,
which is bad news for ./mk inject beacuse the act of compression
is currently not reproducible. Therefore, coreboot has been
modified not to compress this section, and the inject command
doesn't compress it either. This means that the S file is using
about 180KB in flash, instead of about 140KB. This is totally OK.

The _fsp targets are retained, but set to release=n, because these
targets *still* don't scrub fsp.bin; if released, they would
include fsp files, so they've been set to release=n. These can
be used on older Libreboot release archives, for compatibility.

The new ROM images released for the affected machines are:

t480_vfsp_16mb
t480s_vfsp_16mb
dell3050micro_vfsp_16mb

Note the use of _vfsp instead of _fsp. These images are released,
unlike _fsp, and they lack fspm/fsps in the image. FSP S/M must
be inserted using ./mk inject.

This has been tested and confirmed to boot just fine.
The 20241206 images will be re-compiled and re-uploaded with this
and other recent changes, to make Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:05:16 +00:00
Leah Rowe
7813205146 Remove legacy update/vendor commands
We only use ./mk now.

./build still exists for now. This will be removed
in a future revision, when the trees script is removed
and merged with the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-25 09:10:57 +00:00
Leah Rowe
07037561bd lbmk: remove use of deprecated ./vendor command
use ./mk instead, because in a future change to lbmk,
only ./mk will be used and the other commands will
be removed.

with this change, the ./vendor, ./build and ./update
commands are no longer used. these commands still work,
for backwards compatibility, but they are deprecated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 16:58:23 +00:00
Leah Rowe
5d1f182306 vendor.sh: Safer exit when vendorfiles not needed
When vendor files were not needed on a given board,
the script would directly exit. This is bad, because
the inject functions are called directly from the main
script, which means the parent instance of lbmk.

This means that the lock file and temporary files were
not being removed on exit. On a subsequent run, this
would cause the error stating that a lock file is present,
which would cause further error, making the user believe
something is broken in lbmk.

Modify the behaviour accordingly; exits are now returns,
and these are handled in the calling functions, in such
a way that a proper exit occurs, whereby temporary files
and the lock file are deleted.

For context, please read the main "build" script where
it calls vendor_inject and vendor_download. At the end
of that script, it calls tmp_cleanup, which removes the
TMPDIR that was created, and the lock file. In lbmk,
the TMPDIR is not /tmp, but rather a subdirectory
under /tmp, so that further calls to mktemp create
everything under one single temporary directory, which
lbmk automatically removes on exit.

Therefore, this patch also avoids leaving temporary files
laying around on the disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 14:09:29 +00:00
Leah Rowe
a18175a5df data/deguard: Remove unused patch
The appdir.patch file was used on the older deguard
version, prior to Mate Kukri's rewrite. This patch is
no longer required, and no longer used, so it can be
removed safely from lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:40:53 +00:00
Leah Rowe
ee8f53b96f lib.sh: Safer exit from ./mk dependencies
The exit was dependent upon install_packages returning
zero status, which it always would in practise, due to
its design, but this exit must always be observed, so
the code has been modified to honour this design.

A direct exit violates lbmk's design in most instances,
where a temporary directory and lock file has already
been created; at this stage, no such act was performed,
so a direct exit is perfectly acceptable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:39:05 +00:00
Leah Rowe
a8b35c88cf remove geteltorito and mtools from lbmk
we needed these for extracting intel vga roms from
lenovoo updates, for t480, very briefly. about an hour
after i pushed that patch, mate kukri fixed libgfxinit
and then i removed the vgarom integration because it
wasn't needed anymore.

however, i forgot to remove geteltorito/mtools from
dependencies. some distros like fedora were problematic
about it.

the best thing about bugs is when you don't have to fix them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-22 23:13:43 +00:00
Leah Rowe
1dd32ea548 rom.sh: support grub-first setups
in this setup, seabios is never the default payload, grub is,
but only if grub is enabled.

set this in target.cfg:

payload_grubsea="y"

if payload_grub isn't enabled, this is auto-set to n

ditto if initmode=normal

NOTE: if flashing libgfx setups, you should make sure
that you're not booting with a graphics card, only intel
graphics. this setting will intentionally not be documented,
because it's not recommended, but is being implemented for
testing purposes (and i implemented it for some guy who i
think is cool). i'll probably also use this myself, since
i already do grub-only setups on all my own machines.

seagrub is the default on x86 because of past instabilities
with grub. to mitigate in case of future issues, since seabios
is always stable, we reduce the chance of bricks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 07:15:18 +00:00
Leah Rowe
f7801ef477 vendor.sh: delete old tb.bin first, just in case
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 03:49:58 +00:00
Leah Rowe
02cbf8a729 vendor.sh: make TBFW pad size configurable
we encountered 1MB flash so far, but we may encounter other
sizes on other machines when added to libreboot later on

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 03:42:45 +00:00
Leah Rowe
9884e5ed1b T480/T480S: Support fetching ThunderBolt firmware
Though not used in coreboot builds, and not injected into the
builds in any way, these files are now created seperately when
handling T480/T480s vendor files:

vendorfiles/t480/tb.bin
vendorfiles/t480s/tb.bin

These are created by extracting Lenovo's ThunderBolt firmware
from update files. The updated firmware fixes a bug; older firmware
enabled debug commands that wrote logs to the TB controller's
own flash IC, and it'd get full up with logs, bricking the controller.
If you've already been screwed by this, you must flash externally,
using a padded firmware from Lenovo's updates.

Lenovo's own updater requires creating a boot CD or booting
Windows. This patch in lbmk auto-downloads just the firmware,
and you can flash it externally.

You could simply do this as a matter of course, when installing
Libreboot. You are recommended to update the Lenovo UEFI/EC firmwares
first, before installing Libreboot; please look at the Libreboot
documentation to know exactly which versions.

Then dump the ThunderBolt firmware first, to be sure, and then you
can flash these files. Flashing these updates will prevent the bug
described here:

https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/20l5/solutions/ht508988

You can download Lenovo's installers for various ThinkPad models
there, including T480s/T480s. It is these downloads that this lbmk
patch uses, to extract those files directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 02:28:29 +00:00
Leah Rowe
36b42dd1c1 also de-rainbow the u-boot menu
boring is good

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 13:02:37 +00:00
Leah Rowe
eafc82028a Revert "use rainbow deer on the grub background"
libreboot has a lot of users worldwide, some of whom live in
countries that punish being gay; if they look at libreboot or
boot it and it has the pride colours on it, it could actually
get them in trouble.

this fact occured to me, and i've decided therefore to revert
back to the boring plain logo.

though, perhaps we could actually properly design a new logo?
a new, modern logo, and a nicer website.

we'll see!

This reverts commit 401efb24b2.
2024-12-17 12:32:17 +00:00
Leah Rowe
44969c73bd rom.sh: insert grub background in cbfs not memdisk
for some reason, when the background is in memdisk, inserting
it into cbfs afterward doesn't override, despite this
being the behaviour in grub.cfg

put it in cbfs explicitly, and skip inserting into memdisk

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 01:02:03 +00:00
Leah Rowe
401efb24b2 use rainbow deer on the grub background
same as on u-boot recently

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 00:57:05 +00:00
Leah Rowe
dc27cb9178 add some scripts to .gitignore
f/m are scripts i'm gradually working on. easy flash scripts
for lbmk. no promises when/if i push them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-13 06:28:05 +00:00
Leah Rowe
3b6b283eab disable 3050micro nvme hotplug
see patch for rationale. this should prevent instability caused
when the nvme randomly replugs under linux. sometimes e.g. nvme0n1
becomes nvme0n2 while the system is running.

in my case, that caused my raid1 to become unsynced every few days.
this issue was fixed on t480 by disabling pcie hotplug for its nvme
device, so the same fix has been applied for dell optiplex 3050 micro.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-11 01:11:08 +00:00
Leah Rowe
c202392189 fix t480 spd size (512, not 256)
this was done with the following command:

./mk -u coreboot t480s_fsp_16mb t480_fsp_16mb

it was set to 256 but should be 512. the SPD is what
contains configuration data for raminit, which training
code uses so that the timings will be correct. if the SPD
size is wrong, the machine won't boot

in practise, lbmk always runs "make oldconfig" on
a coreboot config, before building it, so this was
already being corrected automatically at build time.

however, if that fact ever changes in the future, this
wrong configuration would cause the machines not to boot.

therefore, this can be considered a preventative or perhaps
pre-emptive bug fix.

this fix does not need to be applied to the 20241206 release,
because of the behaviour described above. the final ROM images
do have the spd size set correctly to 512, because of this
design feature in lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-10 23:48:41 +00:00
Leah Rowe
da527459b6 add tarballs and signatures to gitignore
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 21:31:06 +00:00
Leah Rowe
b910424b5d fix another very stupid mistake
the last revision disabled building arm64 images!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 18:24:57 +00:00
Leah Rowe
e3b77b132e fix the stupidest bug ever
no context given, but every rom needs to be re-built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 18:04:51 +00:00
Leah Rowe
e80261dd54 Revert "vendor.sh: avoid unnecessary directory copy"
Nope. It was correct before. fml

This reverts commit 2d96fe2a1d.
2024-12-06 10:34:36 +00:00
Leah Rowe
ec581bde47 Libreboot 20241206 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 10:06:38 +00:00
Leah Rowe
2d96fe2a1d vendor.sh: avoid unnecessary directory copy
the previous commit changed an mv to a cp. what it hacked
was actually a relic of the vgarom download patch that i
did for t480, before mate got native video init working.

this patch is the better fix. i double checked to be sure,
and nothing was using the files at the copied location.
the _extracted directory under cache gets deleted later on,
so it's perfectly acceptable to keep.

the other alternative would have been to simply change
the path in the sch5545 function to appdir, instead of
the cache dir, but who really cares?

this patch removes bloat from lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 01:53:44 +00:00
Leah Rowe
2dc7c5fa72 vendor.sh: fix minor release bug
I should have copied the extract directory, in cases
where it appears as filename_extracted/ under cache/,
but I was moving it instead.

Both locations (cache/file/*_extracted/
and vendorfiles/appdir/) get deleted, on every run of
the vendor script, per target, so this is OK.

The only sin is additional use of disk space, for
archives that are mostly very small and get immediately
deleted anyway.

This one lbmk bug, minor though it may be, prevented
the Libreboot 20241205 release, which (since it's now
the 6th of December) will become Libreboot 20241206
instead - and that gives me time to contemplate whether
I want to do one more change that I had planned for the 5th!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 01:24:35 +00:00
Leah Rowe
56b35bd9d8 Libreboot 20241205 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 23:45:01 +00:00
Leah Rowe
07983c1d88 Revert "Revert "disable u-boot on thinkpad t480""
Nope! Bootflow menu is cursed on this machine.

Too many issues in U-Boot on this machine. I did however
boot a Debian installer after it booted, using bootflow.

The installed system wouldn't boot with bootflow, but I could
then boot it with "bootefi bootmgr".

I'll rig up a uart on the T480 when I get round to it and
start investigating U-Boot bugs on this board.

I don't want people flashing something that doesn't work.
GRUB and SeaBIOS work, so ship those, and don't ship U-Boot.

This reverts commit 19ec440a6f.
2024-12-05 13:01:31 +00:00
Leah Rowe
19ec440a6f Revert "disable u-boot on thinkpad t480"
u-boot does work after a few reboots. it just boot loops.

let it run. it should be able to boot from nvme. sata still needs
some work (sata only works in grub, on this machine)

This reverts commit cd9baca5d6.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:55:06 +00:00
Leah Rowe
99513c3bf6 add patch from mkukri fixing t480 sata
nvme worked but not sata. with this, t480 users with sata
ssds should be able to boot linux nicely

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:33:51 +00:00
Leah Rowe
cd9baca5d6 disable u-boot on thinkpad t480
it just bootloops and doesn't seem reliable at the moment

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:29:59 +00:00
Leah Rowe
8065b9842b remove the purple patch on arm64 u-boot
it's green there. different colour scheme apparently.

still works on x86. alper said his kevin chromebook was green!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 22:17:34 +00:00
Leah Rowe
5cc91d8e40 Merge pull request 'u-boot: Use bootflow menu by default for ARM64 boards' (#254) from alpernebbi/lbmk:u-boot-arm64-bootflow-menu into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/254
2024-12-04 20:16:01 +00:00
Leah Rowe
bef2890233 i made u-boot purple
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 20:14:59 +00:00
Alper Nebi Yasak
f26752fd85 u-boot: Use bootflow menu by default for ARM64 boards
The bootflow menu is already the default boot command on x86. Switch
arm64 boards to that as well, so instead of booting the first thing we
find, we can easily choose what to boot.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-12-04 22:51:45 +03:00
Leah Rowe
965f9bd033 Add bootflow/branding patches to arm64 U-Boot too
U-Boot on ARM64 also enables the bootflow menu.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 18:57:24 +00:00
Leah Rowe
44e6a0c090 Add libreboot branding/version to U-Boot bootflow
Show it in the bootflow menu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 18:51:45 +00:00
Leah Rowe
c038b653ac Add auto-boot timeout for U-Boot's bootflow menu
Otherwise, you have to press enter to boot your distro.

With this, a timeout is created. After a number of seconds,
which can be reconfigured, the first option selected will be booted,
when generating a bootflow menu.

The timeout is disabled when you navigate the menu; it only
kicks in if you don't input anything on the keyboard.

More information about how this works is in the U-Boot patches,
within this patch. I've set the timeout to 8 seconds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 07:23:51 +00:00
Leah Rowe
7a6e47c24f 8-sec auto-boot timeout for U-Boot's bootflow menu
Otherwise, you have to press enter to boot, which is unacceptable
for headless operation.

Pressing anything other than enter an an option, such as the arrow
keys, will disable the timeout.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 21:40:15 +00:00
Leah Rowe
90850eb859 fix board name for coreboot/dell7010sff
i'd copied the t1650 config and reselected the board lazily.

this fixes the issue:

https://codeberg.org/libreboot/lbmk/issues/242

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 15:33:27 +00:00
Leah Rowe
8314fbc67e add /dump/ to .gitignore
this is used for factoryy bios dumps, in cases where
boards require extraction of ME and so on,
instead of downloading online.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 15:15:24 +00:00
Leah Rowe
efebfa992b Revert "trees: Allow using a custom clean command"
This reverts commit 5b4c9158e5.
2024-12-02 21:22:36 +00:00
Leah Rowe
5b4c9158e5 trees: Allow using a custom clean command
On coreboot for example, as Mate has told me, if you're
making Kconfig changes and re-compiling, sometimes the
actual image that you build might still have the old one
in it, due to how coreboot's build system works.

To mitigate this, you can just always run distclean before
doing the build, but lbmk was doing just clean.

In practise, we did not find any issues, but this change should
be harmless, and might prevent such issues in the future. It's
even possible that we might have already encountered this before
and not realised, and we were just lucky that no noticeable issues
were caused.

It's *also* possible that the reverse is true: an issue that
was previously covered up, then that issue will now be exposed.
However, if that turns out to be true, then that is good because
we are exposing said bugs and then we will know to fix them!

Anyway, the variable in target.cfg is:

cleancmd="whatever_you_want"

e.g.

cleancmd="distclean"

You may also specify this in global mkhelper.cfg files, per
project; I've already done this for SeaBIOS, coreboot
and U-Boot, since all of these use Kconfig files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 20:41:05 +00:00
Leah Rowe
b95a411a36 Add SPD support for onboard ThinkPad T480S RAM
Patchset 20 from:

https://review.coreboot.org/c/coreboot/+/83274/18..20

Updated to that. A bunch of changes I made locally have been
copied here, thus removed from lbmk.

The previous setup in lbmk was to have only the DIMM slot work,
on the ThinkPad T480S, without setting up SPD for the onboard RAM>

Mate Kukri reverse engineered the scheme by which the SPDs are
chosen at boot, based on the wiring of the board. This should
just about match the way Lenovo did it in their firmware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 16:32:15 +00:00
Leah Rowe
046529abd9 Disable m2 caddy hotplug on T480S
This fixes an error where nvme disappears and gets renamed
on s3 resume. Mate Kukri told me to test that and it worked.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 11:29:19 +00:00
Leah Rowe
9dc3c86ae3 vendor.sh: Remove T480 VGA ROM download handling
Libreboot's binary blob reduction policy is crystal clear:

If a blob can be avoided, it must be avoided.

The ThinkPad T480 was using Intel's VGA ROM for graphics
initialisation very briefly, before Mate fixed libgfxinit.

Since libgfxinit is fixed, the Intel VGA ROM is obsolete,
so we should not be handling this at all.

Similarly, the Nvidia ROM handling has been removed, because
Mate is hard-disabling that in the coreboot code anyway, since
the Nvidia dGPU didn't work when tested anyway.

Even if it did, Libreboot's blob policy makes it clear
that Intel graphics with native init from coreboot is to
be the preferred option.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:12:59 +00:00
Leah Rowe
33efe45b14 Enable legacy 8254 timer on ThinkPad T480
I also enabled this on T480S, because otherwise SeaBIOS hung.

Enabling it shouldn't cause any harm on the T480, though Mate
did say that his machine seemed to work with my setup.

However, I believe that was when I gave him the ones that lbmk
built with the VGA ROM. Now it builds with libgfxinit, because
Mate was able to fix libgfxinit on this machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:09:03 +00:00
Leah Rowe
cde9594aab libgfxinit on Thinkpad T480
was previously using the VGA ROM.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:05:41 +00:00
Leah Rowe
c1b7326972 NEW MAINBOARD: ThinkPad T480S
Added t480s delta to deguard, for MFS config.

Updated coreboot/next to latest t480 patch set,
which includes t480s. This porting was done by
Mate Kukri.

also includes experimental t480s support

Also added a data.vbt file (not in the gerrit patch)
for the T480s.

I had to turn on 8254 legacy timer on t480s, otherwise
SeaBIOS would hang. Same issue I saw on OptiPlex 3050 Micro.

Minor issue:

On S3 resume, nvme0n1 for example got renamed to nvme0n2.
This caused a crash if running Linux from the nvme. I confirmed
this via live USB distro. So this port will need some tweaking
before it can be considered stable.

Also uses libgfxinit, which Mate recently fixed. I'm
going to enable libgfxinit on regular T480 next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 05:57:34 +00:00
Leah Rowe
264928c6cd NEW MAINBOARD: ThinkPad T480
This uses the excellent deguard utility, written by
the excellent Mate Kukri.

A few bugs but it mostly works. Documentation to come
shortly, in lbwww.git.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-01 23:51:20 +00:00
Leah Rowe
597b45fdbd Merge pull request 'Update U-Boot to v2024.10' (#253) from alpernebbi/lbmk:uboot-v2024.10 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/253
2024-12-01 17:03:08 +00:00
Leah Rowe
28d8dc93a5 vendor.sh: Use the new deguard for 3050micro
I'm adding ThinkPad T480 support next, which requires
the new revision of deguard. Mate Kukri changed the way
deguard is used, in a rewrite of the project, so lbmk
has to change too.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-01 01:44:45 +00:00
Alper Nebi Yasak
3dd77b33a7 u-boot: Enable USB with a preboot command
We need to initialize the USB subsystem before we can use USB devices
like keyboards and external disks, by running `usb start`. Use the
PREBOOT config option to run the necessary command before U-Boot tries
to automatically boot anything. It's already enabled for boards other
than gru_kevin and gru_bob, so just update those two configs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-11-30 22:31:16 +03:00
Alper Nebi Yasak
ba772eb6ac u-boot: Update ARM64 boards to v2024.10
Set default U-Boot revision to v2024.10 and rebase patches on top of
that. The video subsystem now has switched to using the 'cyclic'
mechanism, so the code around one of the video patches changed a bit.

x86 boards were already switched to v2024.10. Update U-Boot for the
remaining ARM64 boards as usual:

- Turn old configs into defconfigs (./update trees -s u-boot)
- Save the diff from old upstream defconfig (diffconfig $theirs $ours)
- Update U-Boot revision, rebase patches, and clean old trees
- Prepare new U-Boot tree (./update trees -f u-boot)
- Review the diffconfigs to see if any options were renamed upstream
- Copy over the new upstream defconfigs and apply earlier diff
- Turn new defconfigs into configs (./update trees -l u-boot)

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-11-30 22:24:29 +03:00
Leah Rowe
7f6e47d27c trees: reset PATH per-target
Otherwise, if PATH was set before, it will be re-used
again in the next pass. We previously unset CROSS_COMPILE
to avoid using the wrong cross-compiler when switching to
another target within a multi-tree project such as U-Boot.

Well, PATH was also being set, to use coreboot xgcc first.
This is fine, but the next target may not use the same one.

This patch solves a similar problem to the following patch
which was mentioned above:

commit 637c0a1521
Author: Leah Rowe <leah@libreboot.org>
Date:   Tue Nov 19 02:52:28 2024 +0000

    trees: unset CROSS_COMPILE per target

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-29 00:39:35 +00:00
Leah Rowe
f4b6aeea28 rom.sh: Add U-Boot before SeaBIOS and GRUB (x86)
Since U-Boot must be inserted at a specific offset, it's
theoretically possible that other files might overlap, but
cbfstool will work around wherever U-Boot was inserted if
it was inserted first; we don't use specific offsets for
the other files.

This is technically a preventative bug fix, but it fixes
a bug that would probably never occur in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-27 02:41:39 +00:00
Leah Rowe
7014b303f9 rom.sh: Remove unnecessary shebang
This is not a main script, and should not be treated as such;
it must never be directly executed by the user.

This script was only ever used inside other scripts, so the
shebang didn't seem to do much at all, but it shouldn't be
there anyway.

Remove it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-26 23:28:42 +00:00
Leah Rowe
a3accd39a0 Merge pull request 'config/deps/fedora41: Add openssl-devel-engine to dependency list' (#251) from mkukri/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/251
2024-11-24 15:17:48 +00:00
Mate Kukri
98c5e43628 config/deps/fedora41: Add openssl-devel-engine to dependency list
openssl-devel was split up in Fedora 41, and this package is required to build libreboot
on Fedora 41.

This was reported by "tweezers" on #libreboot.

Signed-off-by: Mate Kukri <km@mkukri.xyz>
2024-11-24 11:59:46 +00:00
Leah Rowe
ef7db20546 e6400nvidia: Disable U-Boot
This uses the "normal" config. Previous changes prevent
U-Boot images being built for this anyway, but it does
yield a warning message.

Remove the warning at the source.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:35:59 +00:00
Leah Rowe
eea9fc4097 rom.sh: unset displaymode on normal initmode
Otherwise, you get "normal_normal" in the image name.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:34:08 +00:00
Leah Rowe
f312e6026f rom.sh: Don't build U-Boot on normal initmode
The "normal" mode in lbmk is where no built-in GPU exists,
or no libgfxinit is used, and SeaBIOS is the first payload,
and SeaBIOS executes VGA ROMs (can't know if it'll start
in VESA or text mode).

U-Boot needs a VESA framebuffer or native coreboot
framebuffer to work correctly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:24:50 +00:00
Leah Rowe
587d588fe4 rom.sh: Don't build txtmode U-Boot images
U-Boot needs a VESA framebuffer or native coreboot
framebuffer to work properly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:07:33 +00:00
Leah Rowe
7d1fd1cc6a rom.sh: Support SeaUBoot for 64-bit x86 U-Boot
Same concept as SeaGRUB, but for U-Boot. SeaBIOS starts, but
has a bootorder file loading U-Boot first, from flash.

You can interrupt it with the ESC menu, to boot something else
in SeaBIOS, including GRUB.

With this, we can effectively provide extremely user-friendly
UEFI-first setups in Libreboot.

Take that, edk2!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 12:29:05 +00:00
Leah Rowe
02e66ae01a U-Boot x86: Avoid clearing the VESA display
This is a patch from Simon Glass. U-Boot clears the display
when it starts up, but was asking the VESA driver to do the
same, needlessly; this patch avoids the latter.

A further patch is also included, which provides a better
message when jumping into long mode on the SPL (64-bit) target,
dumping it on the serial console instead of using printf.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 15:44:35 +00:00
Leah Rowe
32dced8cd8 disable U-Boot for now on HP EliteBook 8560w
dGPU only, and starts in text mode.

will have to test with vesa framebuffer later on.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 13:24:14 +00:00
Leah Rowe
a68b468964 enable serial debug on HP EliteBook 8460p
there's a uart on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 12:07:18 +00:00
Leah Rowe
b79bd736e7 enable serial debug on hp elite 8200 sff
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 12:05:37 +00:00
Leah Rowe
b109617752 enable the serial console on thinkpad x60
it has one on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 11:31:37 +00:00
Leah Rowe
0c7fb21a06 enable the serial console on thinkpad t60
it has one on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 11:29:53 +00:00
Leah Rowe
eb14a176bc Only boot 32-bit u-boot from grub, 64 from seabios
For some reason, 32-bit U-Boot only works when executed from
GRUB, but not SeaBIOS; 64-bit U-Boot only works from SeaBIOS!

This will have to be investigated. Standalone U-Boot, where
U-Boot is the primary payload, has not yet been tested in
Libreboot, and will not be provided for some time due to
stability concerns. More testing is needed!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 01:19:27 +00:00
Leah Rowe
279e69172f make the u-boot grub menuentry more useful
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 23:26:28 +00:00
Leah Rowe
fdbdf0449b Re-enable U-Boot x86 on real mainboards
The previous stability issues were resolved, thanks to
the previous revision which added a fix courtesy Simon Glass.

This reverts commit eba73c778a.
2024-11-19 22:48:21 +00:00
Leah Rowe
b549d1e5f3 u-boot x86 serial/ns16550: disable UART as needed
U-Boot was hanging on hardware, but not Qemu. This is because on
the machines tested, namely the X200 and E6230 laptops supported
in Libreboot, the UART was disabled from coreboot.

This U-Boot patch from Simon Glass works around the issue by
silently disabling the UART when it isn't there. Instead,
output is sent to the display and U-Boot no longer hangs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 22:46:29 +00:00
Leah Rowe
eba73c778a Disable U-Boot x86 except on Qemu
It's really buggy on hardware. Disable for now.

I've contacted Simon Glass on IRC, asking about hardware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 16:22:14 +00:00
Leah Rowe
4bc6ca545e fix U-Boot hotkey mention in grub.cfg
it's u, not b, for the U-Boot hotkey

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 10:56:54 +00:00
Leah Rowe
6d629a8496 Update x86 U-Boot to v2024.10 (was v2024.07)
It's a new experimental payload in Libreboot, so we may aswell
start with the very latest release of U-Boot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 09:52:40 +00:00
Leah Rowe
709bbebdcf grub.cfg: mark U-Boot as experimental in the menu
it's important that we maintain realistic expectations.
x86 u-boot is not yet fully stable, so mark it as such.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 04:55:46 +00:00
Leah Rowe
637c0a1521 trees: unset CROSS_COMPILE per target
When building a coreboot image, if they enable the
x86 U-Boot payloads, sometimes what happens is you
have CROSS_COMPILE set, for i386-elf, but then it's
still set to that when later building 64-bit U-Boot,
which needs x86_64-elf.

We currently rely on hostcc to build U-Boot.

To mitigate this, unset CROSS_COMPILE in the main
loop of the trees script, for building project targets.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:52:28 +00:00
Leah Rowe
f13819386b Enable x86 U-Boot payload on every x86 board
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:28:18 +00:00
Leah Rowe
747b6514ea Add U-Boot x86_64 payload
Currently seems to stall when booted from the GRUB
payload, but works when booted from the SeaBIOS menu.

I also tested it as a standalone payload and it seems
to boot. Will test on hardware next, and start adding
it to more mainboards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:04:50 +00:00
Leah Rowe
3bf3ef557e add arm-none-eabi-gcc-cs-c++ to fedora dependency
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-09 15:36:36 +00:00
Leah Rowe
2deab8572d clean up the coreboot submodules
also bring the coreboot/next modules in line with
the recent merge that did away with coreboot/dell7

the submodules for coreboot/haswell were still there,
and have now been deleted; the haswell tree was used
for the NRI patches, which were moved to /default some
time ago

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-07 00:26:59 +00:00
Leah Rowe
9abddb82b9 Bump coreboot/next and merge coreboot/dell7
coreboot/dell7 is now part of coreboot/next, which in turn
has been updated, to accomodate 3050 micro patchset 18:

https://review.coreboot.org/c/coreboot/+/82053/18

It incorporates my Verb/VBT patches, which are therefore
no longer included separately.

Mate has fixed the USB config; see diff for details.
The configuration of USB ports was wrong, before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-06 22:32:45 +00:00
Leah Rowe
8c4cacba27 data/coreboot: add missing variable
payload_uboot_i386 must be defined here, or the
build will fail for coreboot targets

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-05 19:33:49 +00:00
Leah Rowe
cdd8cb9086 coreboot/default: remove unnecessary module
The fsp module is unnecessary on coreboot/default, and
therefore constitutes a waste of disk space.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-04 05:44:39 +00:00
Leah Rowe
c0017c7357 Experimental U-Boot payload (32-bit dtb, U-Boot)
NOTE: Support added for xarch target x86_64-elf,
but U-Boot failed to build with this error:

OBJCOPY lib/efi_loader/helloworld.efi
x86_64-elf-objcopy: lib/efi_loader/helloworld_efi.so: invalid bfd target
make[2]: *** [scripts/Makefile.lib:476: lib/efi_loader/helloworld.efi] Error 1

Since I'm building U-Boot for x86_64 *on* an x86-64
host, and since that is currently the recommended type
of machine to use for lbmk development, and since the
other x86 payloads currently don't cross compile anyway,
this is an acceptable compromise for now. This is because
at present, I'm not making U-Boot the primary payload on x86,
instead preferring to chain it from GRUB and SeaBIOS.

The target.cfg file for x86 u-boot shows xarch/xtree commented.
Uncomment these to compile on crossgcc instead of hostcc.

I mention 64-bit because I initially did this first, but decided
to do 32-bit first. I'll work on the 64-bit one next (SPL).

It's only enabled in QEMU for now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-03 09:22:52 +00:00
Leah Rowe
14b4838d49 coreboot/default: Re-base all patches
There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-01 15:59:30 +00:00
Leah Rowe
67c92889a8 NEW MAINBOARD: Dell OptiPlex 780 USFF
Thanks go to Nicholas Chin and Lorenzo Aloe for working on
and testing this code. Based on the 780 MT port.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-31 05:30:10 +00:00
Leah Rowe
38006cb2bc coreboot/dell3050micro: enable coffeelake CPUs
pin mod needed (soldering) but according to mate, you
can use some coffeelake CPUs on these machines, despite
them being intel 7th gen. this includes 8-core chips.

this patch enables the software configuration in coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-31 02:38:01 +00:00
Leah Rowe
97054498e9 NEW MAINBOARD: Dell OptiPlex 780 MT
Thanks go to Lorenzo Aloe and Nicholas Chin for working on
and testing this code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-28 05:03:17 +00:00
Leah Rowe
f3170fb06e coreboot/dell7: add missing ifdtool nuke patch
This is for blanking the ME region on release builds.

This is required for lbmk when doing Libreboot releases,
on images that use an Intel ME region.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-28 01:16:25 +00:00
Leah Rowe
19795bf980 re-update seabios to latest revision
I reset it temporarily back to 1.16.3 when testing the
SeaBIOS hanging bug on 3050 micro, but the revision had
no effect; the bug was caused by a bad coreboot config

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 20:06:16 +00:00
Leah Rowe
9bdec645a3 3050micro: Re-enable SeaGRUB
Remove what is now unnecessary bloat, for ensuring that
GRUB is the primary payload; SeaGRUB is the only preference,
as per lbmk design.

The SeaBIOS hanging issue was fixed, so SeaGRUB is OK now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 19:32:36 +00:00
Leah Rowe
6c78942290 Merge pull request 'config/coreboot/default: Update MEC5035 patches' (#244) from nic3-14159/lbmk:mec5035-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/244
2024-10-27 18:44:41 +00:00
Leah Rowe
237fa1e3c1 3050micro: don't set static option table
Again, I'm adapting the config to be as close to the
coreboot one as possible. I compiled directly from coreboot
earlier, and got SeaBIOS to work on my 3050.

I'm matching the setup as closely as possible. Once it works,
I can use that in a Libreboot release but then debug why the
old config wasn't working.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 18:35:29 +00:00
Leah Rowe
d1743d1f64 3050micro: Use alt century byte +legacy 8254 timer
I'm eliminating as many differences as possible between lbmk's
setup, and the setup that is default when simply building from
the gerrit patch, directly in coreboot, by just picking the
mainboard; in this way, coreboot picks SeaBIOS as payload. I
already changed the SeaBIOS configs, in the previous patch.

Upon testing, this seems to have fixed the SeaBIOS hanging. I
need to have both of these options selected, or SeaBIOS hangs
just after it says "Press ESC" for the boot menu.

With this config change, SeaBIOS does not hang; instead, it shows
the list of devices as normal, and boots your machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 18:34:43 +00:00
Leah Rowe
c56f698713 Use SeaBIOS 1.16.3 and enable debugging
This diff matches the setup currently used in coreboot.

I'm eliminating as many differences as possible, while
I test the SeaBIOS hanging issue on Dell Optiplex 3050 Micro.

The actual SeaBIOS configs have also been modified, to match
the coreboot config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 16:07:56 +00:00
Nicholas Chin
b257662e55
config/coreboot/default: Update MEC5035 patches
- Update the MEC5035 S3 patches to the versions that were sent upstream
  to prevent conflicts with subsequent patches for that EC.
- Update the patch that enables the S3 SMI handler in mainboard code so
  that all Latitudes use the handler.
- Add a new patch that tells the EC to route power button events to the
  host so that the OS can decide what to do. Without it, the EC powers
  off the system without letting the OS cleanly shut down.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-10-26 20:55:18 -06:00
Leah Rowe
d8ac9d53b6 Switch Dell 3050 Micro to newer coreboot revision
Specifically, use the same revision that Mate used in patchset 15.

This will ensure that any issues are *not* caused by the coreboot
revision; this is being done, because the old coreboot revision was
from July, but patchset 15 from Mate is based on a September revision
of coreboot.

I've been eliminating as many variables as possible, trying to fix
SeaBIOS payload on this machine, because it hangs in Libreboot, but
not when building from gerrit directly, which means the coreboot
revision may be a factor (since I'm using his patches on an older
revision so upstream might have made some changes since then that
the port relies on).

For this, a new coreboot tree is used, called "dell7", referring to
the fact that Kabylake is Intel's 7th generation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 01:15:24 +00:00
Leah Rowe
99a88ebfa2 Update dell 3050 patch to patch 15 (pwm fix)
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch

Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch

We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14

Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15

Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.

I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.

Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.

I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-26 06:26:25 +01:00
Leah Rowe
3f63c6d12f rom.sh: remove unnecessary logic from copyps1bios
the .git directory never exists anyway, when doing a release,
so the purpose this is intended is defeated by lbmk's design.

individual headers say "pcsx-redux team" as copyright anyway,
and the code for generating that COPYING file, with MIT license
and correct years (matching the entire source code for the
open bios) remains correct.

a mitigation instead of this patch might be to maintain a hardcoded
list of authors, and manually update it over time, but this is not
required. however, it may be good practise for upstream to maintain
such a file. perhaps i should contact them?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-20 00:13:35 +01:00
Leah Rowe
56495c61e6 use redundant mirrors for recent utils imports
i mirrored riku's utils int, mxmdump and gpio-scripts
to the codeberg and disroot libreboot sites.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:48:32 +01:00
Leah Rowe
38d37a340f remove end slashes on repos in config/git/
Due to quirks in how caching works in lbmk, this may be
error-prone. I'll properly address it in the next audit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:37:05 +01:00
Leah Rowe
6eb2e98c0f import Riku's int tool
Riku used this for debugging, when adding the MXM support
to the HP EliteBook 8560w port. It will be useful for other
work that I have planned, so I'm archiving this too!

Riku has a lot of useful code, that I meant to import ages ago.
Once I'm done importing these in lbmk, I'll add backup repos.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:33:48 +01:00
Leah Rowe
441d21dc13 import Riku's gpio-scripts
Based on hell's code, but parses inteltool logs.

This will be useful for ports that I have planned, so
I'd like this to be included with Libreboot releases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:30:51 +01:00
Leah Rowe
e8957b0833 import Riku's mxmdump utility
Used to dump MXM config for a given mainboard. We used this
for the HP EliteBook 8560w.

I meant to import this via config/git/ ages ago.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:28:18 +01:00
Leah Rowe
91a26ec361 bump seabios
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:22:44 +01:00
Leah Rowe
34f851742e vendor.sh: Don't use x_ for image MAC address mod
The path might contain spaces and such, which breaks when
using the x_ prefix.

Call err instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-16 15:48:43 +01:00
Leah Rowe
c7a3a607f3 bump flashprog revision to d128a0a
This brings in the following important fix:

commit d128a0ae87086b37c0e5d7a8d934bcdee173402f
Author: Nicholas Chin <nic.c3.14@gmail.com>
Date:   Fri Sep 27 22:57:22 2024 -0600

    flashchips: Remove unsupported erase blocks for Winbond W25X{16,32,64}

    This family of chips does not support the 0x52 (32 KiB block erase) and
    0x60 (chip erase) opcodes according to their datasheet.

The full list of changes this brings in is as follows:

* d128a0a flashchips: Remove unsupported erase blocks for Winbond W25X{16,32,64}
* c6a924a Don't mention writing when erasing only (-E)
* dac4239 ch347_spi: Add 'spimode' parameter
* 56d236b chipset_enable: Add some newer AMD code names
* 3b9f152 chipset_enable: Probe AMD SPIBAR first and bail on ff
* 522160f meson: Add ft4222_spi

Nicholas Chin's patch fixes a bug on GM45 ThinkPads, where WX25
ICs (Winbond) could be read, but writes would fail in certain
cases because flashchips.c provided incorrect block erase commands.

This is unrelated to the --workaround-mx patch, for Macronix ICs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-14 16:26:01 +01:00
Leah Rowe
3b92b7b723 vendor.sh: Handle error status on RUNME.sh
The deguard utility is executed within a subshell, and
the subshell does not handle error status. This patch
fixes that, so that the main shell also exits non-zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-14 01:15:44 +01:00
Leah Rowe
147e034341 dependencies/fedora40: add python3-devel
I was build-testing gru_bob on an arm64 host, and got a
build error when compiling U-Boot.

Python.h missing - installing python3-devel fixes it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-13 06:31:36 +01:00
Leah Rowe
c1ff438c90 Libreboot 20241008 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 19:50:44 +01:00
Leah Rowe
6b40616a40 build: actually build pcsx-redux bios on release
I added support earlier, on rom.sh, but the main build script
specifically defines which projects are to be compiled. I've
modified it so that pcsx-redux (just the BIOS part) will also
be compiled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 16:16:30 +01:00
Leah Rowe
d845791d6f rom.sh: support making pcsx-redux bios release
I also checked the copyright declarations in the
directory src/mips/openbios where the PCSX-Redux BIOS
is, gleaning all the copyright years: 2019-2024 at this
time.

The years will be updated as and when PCSX-Redux is
updated in lbmk. Their BIOS is under MIT so I made lbmk
generate an appropriate COPYING file alongside the binary,
containing:

Copyright (c) 2019-2024 PCSX-Redux authors

Along with the actual text of the MIT license. With all
of this, the PCSX-Redux BIOS can now be included in
Libreboot releases.

No actual tarball is created. The release script in lbmk
simply copies the bin/ directory to ../roms

I'm leaving the PCSX-Redux BIOS release uncompressed,
because, and this will sound patronising because that is
my precise intention: Windows users don't know how to do
anything. If I provide a tarball to Windows users, they
won't know what to do. Libreboot releases always go on rsync
mirrors, which also have HTTP servers with indexing enabled,
for browsing release files.

I mention Windows users, because most people who use the PCSX
Redux BIOS will probably use it on a PlayStation emulator, and
most emulator users are on Windows. I can't really be bothered
to provide it as a .zip archive, and it's only 512kb, so just
provide it uncompressed in Libreboot releases!

Releases were already possible under this scheme, so this
patch really just adds the COPYING file. It's simply a courtesy
to the PCSX-Redux developers, providing proper credit to them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 13:27:08 +01:00
Leah Rowe
09a8f2ea83 coreboot/dell3050micro: Add data.vbt file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-07 00:32:31 +01:00
Leah Rowe
217aa1735a Add verb patch for Dell OptiPlex 3050 Micro
Thanks go to Nicholas Chin for helping me with this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 22:37:19 +01:00
Leah Rowe
f4de640e45 rom.sh: disable seabios-as-primary if grub is main
on 3050micro, we disable seabios as a primary payload,
making grub a pribary payload instead.

the way it worked, the roms were still named seagrub
and the seabios rom would be compiled, but with the wrong
path, so seabios wouldn't be executed; seabios would hang
anyway, on this board.

instead, engineer it in such a way as to disable seabios_
images on this board. also, rename seagrub_ to grub_.

i normally only permit seagrub, and not grub, but i make an
exception for 3050micro because we know grub works, but seabios
currently hangs on this board (which means no bsd).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 10:31:36 +01:00
Leah Rowe
c99dced5b1 dell3050micro: make GRUB the primary payload
SeaBIOS is known to hang on this board. It is being investigated.

Add two variable options for target.cfg files:

* seabiosname
* grubname

This string defines where it would be located in CBFS.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 09:22:21 +01:00
Leah Rowe
ed8178e83b disable dram clear on dell 3050 micro
otherwise it takes ages to boot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 19:04:57 +01:00
Leah Rowe
d2939231ac 3050micro: disable TPM to mitagate seabios hanging
SeaBIOS hangs without this. Thanks go to Mate Kukri who
suggested this workaround.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:59:14 +01:00
Leah Rowe
809e1d97ab fix 3050 config (./mk -u coreboot)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:57:06 +01:00
Leah Rowe
44473d6832 git.sh: fix error with cache re-download
in some cases, on a fresh clone, the cached repo already
exists but lbmk tries to download it again. work around
this by checking that the directory exists; it's in the
main if statement, so that the "else" still applies. as
a result, the fallback to a live repo would un-fall back
to doing git-pull if the cached directory exists exists.

if it doesn't seem to make sense, it's because it doesn't.
this whole function needs to be rewritten better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:52:50 +01:00
Leah Rowe
c3ef0a8639 Add config for Dell OptiPlex 3050 Micro
This is using Mate Kukri's port, which was added in
previous lbmk revisions. I've added an IFD that sets
the HAP bit, and unlocks regions as standard.

vcfg is set to 3050micro, which defines downloading
of the MEv11 image and it will run deguard automatically.

I made a small adjustment to vendor.sh, because the hotpatch
logic for deguard uses -C in git, and when doing that, the
specified directory path is relative to that Git repository;
the .patch path has been adjusted accordingly.

Also add 3rdparty/fsp to coreboot/default modules.

This board requires the ifdtool option: -p sklkbl

The -p option tells flashrom what quirks are present in a
given IFD. We don't normally need this on other Libreboot
targets that we currently support. The -p option was needed
for creating this modified IFD, and it is therefore needed in
the inject script. Therefore, an "IFD_platform" option is
specified in a given board's target.cfg file. If this is set,
another variable is set that makes -p be used.

In this case, 3050's target.cfg says:

IFD_platform="sklkbl"

This option enables quirks for skylake/kabylake descriptors,
as required when using ifdtool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:32:06 +01:00
Leah Rowe
23e64192ed Add Dell OptiPlex 7010/9010 SFF support
Pretty much just copied the T1650 directory in config/,
then changed the board to 9010 SFF in menuconfig.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-04 22:24:57 +01:00
Leah Rowe
02e76d09c1 add swig to fedora dependencies
needed when compiling u-boot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-30 09:35:46 +01:00
Leah Rowe
a42fe72c93 Merge pull request 'config/coreboot: Add Dell Latitude E4300' (#236) from nic3-14159/lbmk:e4300 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/236
2024-09-30 03:11:04 +00:00
Nicholas Chin
e0e9c6ab3e config/coreboot: Add Dell Latitude E4300
Add patches to convert the E6400 port into a GM45 Latitude variant and
add the E4300 as another variant, and create a config for the E4300.
Tested on my E6400 and E4300.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-09-27 20:39:27 -06:00
Leah Rowe
ff9c250a3e Add Sony PlayStation support to Libreboot
I also added a "cleanargs" argument, similar to the makeargs
argument, to work around a build error.

This builds the PCSX-Redux PS1 BIOS. They reverse engineered
the Sony PS1 BIOS and wrote a free one under MIT license.

Run this:

./mk -b pcsx-redux

The file will appear: bin/playstation/openbios.bin

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-26 00:35:18 +01:00
Leah Rowe
2b0fe39acb config/git: Import pcsx-redux
We don't need the entire emulator, but we will be using
a specific part: src/mips/openbios

third_party/uC-sdk submodule is included, because it
contains the necessary header files when building open bios.

I will be adding Sony Playstation support to Libreboot,
alongside a new emulator project to be announced soon.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-25 23:21:15 +01:00
Leah Rowe
c723ce56d2 coreboot/default: Import mkukri's 3050 micro port
Dell OptiPlex 3050 Micro

I ran ./mk -u coreboot, to update existing configs
after merging. Actualy IFD and coreboot configs will
be done in the next revision. I've already added logic
for handling deguard, in preparation for this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 20:31:12 +01:00
Leah Rowe
e7c0109f5d Add deguard logic for Dell OptiPlex 3050 Micro
Copy the downloaded deguard source code into appdir,
and patch it to run as part of lbmk, instead of
standalone. The archived one in src/ is not directly
used; instead, the hotpatched version is used.

This is because the standalone version already has
download logic for the .zip file, but we already
cache that file in cache/ and use that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 16:53:48 +01:00
Leah Rowe
0266a48913 Add Mate Kukri's deguard utility
This program disables the Intel Boot Guard on Dell
OptiPlex 3050 Micro, via Intel ME modification.

Using this hack, you can run unsigned code on the ME.
Mate disabled BootGuard this way.

This will be used to add Dell OptiPlex 3050 Micro
support in Libreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 13:41:01 +01:00
Leah Rowe
242b79aa25 Revert "vendor.sh: print extract errors to /dev/null"
This reverts commit 72fa467cb7.
2024-09-05 19:46:37 +01:00
Leah Rowe
72fa467cb7 vendor.sh: print extract errors to /dev/null
the output isn't really super critical, because it pertains
to files that would just result in a coreboot build error
if they didn't extract, which would still allow me to know
if a given extract function failed.

however, the extract function shows a lot of error output
because it literally bruteforces various extract methods,
when dealing with vendor files.

mitigate this by just printing the errors to /dev/null. this
will prevent users from erroneously thinking that lbmk is
operating under error condition, when it isn't. we do sometimes
get questions about it on irc.

fewer questions on irc is better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-31 01:17:57 +01:00
Leah Rowe
66755f73ca Merge pull request 'Add remaining SNB/IVB Latitude ports' (#217) from nic3-14159/lbmk:latitude-ports into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/217
2024-08-14 13:34:52 +00:00
Nicholas Chin
4702e568c3
config/coreboot: Fix INTEL_GMA_VBT_FILE in Latitude configs
Commit 3ee4cc9dde (fix typo in dell
latitude coreboot coreboot config) fixed a typo from ${VARIANT_DIR) to
$(CONFIG_VARIANT_DIR). While this does work, since CONFIG_VARIANT_DIR is
a valid variable, it is not technically correct, as the default VBT path
set by coreboot's Kconfig files uses $(VARIANT_DIR), which is the same
as CONFIG_VARIANT_DIR, but with quotes stripped out.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 22:28:05 -06:00
Nicholas Chin
73484d98ac
config/coreboot: Add config for Dell Latitude E6230
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:09 -06:00
Nicholas Chin
f51a9dee95
config/coreboot: Add config for Dell Latitude E6330
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:09 -06:00
Nicholas Chin
0240be1833
config/coreboot: Add config for Dell Latitude E6320
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:08 -06:00
Nicholas Chin
875e9cb255
config/coreboot: Add config for Dell Latitude E6220
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:08 -06:00
Leah Rowe
3f9d575ceb coreboot/x4x: fix build error
see relevant patch added in the diff

set the clock on x4x boards to 96MHz like on GM45

fixes the following build error on x4x boards:

hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-12 02:23:12 +01:00
Leah Rowe
8ca56f96c1 coreboot/default: fix build issue with DDR2 fix
some of my DDR2 checks were unnecessary, as nicholas pointed
out on irc, because they were in places that only ran if
DDR2 memory was used anyway.

in another, valid place, I was checking the wrong variable for
knowing what memory type is used.

this patch fixes build errors in lbmk:

src/northbridge/intel/gm45/raminit.c: In function 'dram_program_timings':
src/northbridge/intel/gm45/raminit.c:1120:29: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'?
 1120 |                         if (sysinfo->spd_type == DDR2)
      |                             ^~~~~~~
      |                             sysinfo_t
src/northbridge/intel/gm45/raminit.c:1120:29: note: each undeclared identifier is reported only once for each function it appears in
src/northbridge/intel/gm45/raminit.c: In function 'ddr2_odt_setup':
src/northbridge/intel/gm45/raminit.c:1291:21: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'?
 1291 |                 if (sysinfo->spd_type == DDR2) {
      |                     ^~~~~~~
      |                     sysinfo_t
make: *** [Makefile:423: build/romstage/northbridge/intel/gm45/raminit.o] Error 1

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 23:09:25 +01:00
Leah Rowe
3ee4cc9dde fix typo in dell latitude coreboot coreboot config
these configs were otherwise correct, but i typo'd a variable
in them when manually rebasing the old configs, after switching
to nicholas's new ports implemented as variants, where the old
ones in lbmk were individual board ports for those same boards.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 22:06:19 +01:00
Leah Rowe
7ab22503ab vendor.sh: use readkconfig on inject too
same as the last change. we must avoid use of make variables,
in sh specifically, when handling these configuration files.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 22:06:18 +01:00
Leah Rowe
d66f6e0d5b vendor.sh: don't load entire coreboot configs
instead, only grep for the entries required, such
as Intel ME paths.

some variables in coreboot configs use $(), which
is used in *make*, on the coreboot build system, and
there refers to variables.

here, we are sourcing them from sh, which treats this
as a mini subshell to run a command; for example
CONFIG_FOO would be executed, which is bad.

The current logic still theoretically has this problem,
with this patch, but the entries we scan from the configs
do not currently have variable names in the strings.

So: filter out just what we need, into a temporary config,
when scanning for vendor files in coreboot configs, and
use the temporary config.

This fixes a build error when compiling for e5520_6mb.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 21:22:26 +01:00
Leah Rowe
aae8cabe73 lib.sh: more verbose error in x_
part of the command was cut off in the output

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 21:22:23 +01:00
Leah Rowe
3a5a179379 flashprog: bump to 639d563 (2024-08-02)
The workaround-mx patch was rebased on one section in spi.c,
because that part in upstream added QPI support; in the newly
rebase mx patch, the workaround_mx behaviour is only
honoured if QPI (Quad SPI) is not in use.

Quad SPI is not used in practise, on the machines where this
workaround is intended (GM45 ThinkPads with Macronix chips).

This imports the following upstream changes:

* 639d563 README: Update flashprog.org URLs
* cbbd601 README: Update dependency list and Linux package names
* 79451f1 README: Rename "Packaging" -> "Source Packaging"
* 5b4695c README: Dial laptop warning down a little
* 7224085 udev rules: Add some more IDs
* 448457a ch347_spi: Add CH347F ID and loop over the entries
* e39549b ch347_spi: Search for compatible USB interface
* dfd0647 ich_descriptors: Refactor component density handling
* b2ad9fd ich_descriptors: Make use of SPI_ENGINE_PCH100 marker
* 140e22f chipset_enable: Make use of SPI_ENGINE_PCH100 marker
* 869f0e7 ichspi: Use `swseq_data' on ICH7 paths too
* eeee91b ichspi: Replace all switch/case on `ich_generation'
* ecba1d8 ichspi: Drop redundant bail-out cases in ich_set_bbar()
* e8babf4 ichspi: Use a single check to enable hwseq for PCH100+
* fda324b ichspi: Introduce SPI_ENGINE_PCH100 marker
* a1f6476 ichspi: Split ICH7 init out
* 3f75d44 ich_descriptors: Remove `Dual Output Fast Read' for newer gens
* 2862011 spi25: Try to set volatile quad-enable (QE) automatically
* 4ac536b spi25_statusreg: Allow to write (non-)volatile bits specifically
* b1d2bae dediprog: Fix and enable 4BA modes for SF600Plus-G2
* d0afeef dediprog: Disable 4BA modes for SF100 w/ protocol v2
* 1b1deda Implement QPI support
* a1b7f35 dediprog: Implement multi-i/o reads
* 008a44f dediprog: Split read/write command preparation by protocol
* 4760b6e spi25: Implement multi-i/o reads
* 0c9af0a spi25: Check quad-enable (QE) bit
* 930d421 spi25: Introduce generic spi_prepare_io()/spi_finish_io()
* 8d0f465 spi25: Extract 4BA preparations into new `spi25_prepare.c`
* 044c9dc Add FT4222H support
* fc7c13c linux_gpio2_spi: Implement multi i/o
* 5fc3154 bitbang_spi: Implement multi-i/o
* d16a911 bitbang_spi: Move API into its own header file
* 226bb87 flashchips: Add missing QE-bit definitions
* 4fa39c5 flashchips: Fill multi-i/o gaps in MX25U family
* 5f50999 flashchips: Fill multi-i/o gaps in MX25R family
* 46552c8 flashchips: Fill multi-i/o gaps in MX25L family
* 96786d0 flashchips: Fill quad-i/o gaps in XM25Q family
* a26a3c6 flashchips: Fill dual-i/o gaps in W25X family
* 2133f59 flashchips: Fill quad-i/o gaps in W25Q family
* 68573af flashchips: Split GD25Q127C and GD25Q128C
* 4da971f flashchips: Fill quad-i/o gaps in GD25*Q families
* f7e2d97 spi: Allow to define a quad-enable (QE) configuration bit
* 1412d9f spi: Rework FEATURE_QPI
* d518563 spi: Prepare for multi i/o and dummy bytes
* bd72a47 spi25_statusreg: support reading/writing configuration register
* 3d728e7 spi25_statusreg.c: support reading security register
* a358b14 flashchips: Split W25Q64.W -> W25Q64DW | W25Q64FW/W25Q64JW...Q
* 3127db1 manibuilder: Drop legacy flashrom tag collections
* 619d9c0 manibuilder: Use `test_build.sh'
* 6560bba manibuilder/almalinux: Install `diffutils' for new `test_build.sh'
* c7b549e test_build.sh: Compare output for -L of Make and Meson builds
* 72b30a0 test_build.sh: Don't try to run cross-compiled programs
* 3d2f212 test_build.sh: Allow to override Make and Meson commands
* 4eb9748 test_build.sh: Run tests for both Make and Meson builds
* 8279457 manibuilder: Add Alpine Linux 3.18 & 3.19 images
* 15e9b10 manibuilder/alpine: Install libjaylink-dev when available
* b8b3593 manibuilder: Add images for Fedora 38..40
* 7b05f09 manibuilder: Add images for Ubuntu 24.04 "Noble Numbat"
* 5e8b339 manibuilder/anita: Add NetBSD 10.0 i386 & amd64 images
* 61da8c7 manibuilder/anita: Export library path for libusb
* 39152af manibuilder: Set sourcearcade.org as default source
* 20073e7 Properly clear erase-block selection when bigger block is chosen
* 3824c8d ichspi: Allow all opcodes when the "opmenu" isn't locked
* 0d4354e flashchips: Add W25Q32JV-.M

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 18:18:21 +01:00
Leah Rowe
c3f6dd03cc seabios/default: bump to ec0bc256 (2024-06-24)
This brings in a single change:

commit ec0bc256ae0ea08a32d3e854e329cfbc141f07ad
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Jun 24 10:44:09 2024 +0200

    limit address space used for pci devices, part two

This increases compatibility with i686 hosts, when allocating
memory for pci devices.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 16:43:22 +01:00
Leah Rowe
5b353a2290 grub/*: Bump to rev b53ec06a1 (2024-06-17)
Of note: upstream has made several improvements to memory
management, and several fixes to file systems.

User-friendly change to LUKS: if the passphrase input failed,
the user is prompted again for the correct passphrase, instead
of GRUB just failing. Similar to cryptsetup luksOpen behaviour
under Linux.

This pulls in the following changes from upstream (gnu.org):

* b53ec06a1 util/grub-mkrescue: Check existence of option arguments
* ab9fe8030 loader/efi/fdt: Add fdtdump command to access device tree
* 0cfec355d osdep/devmapper/getroot: Unmark 2 strings for translation
* f171122f0 loader/emu/linux: Fix determination of program name
* 828717833 disk/cryptodisk: Fix translatable message
* 9a2134a70 tests: Add test for ZFS zstd
* f96df6fe9 fs/zfs/zfs: Add support for zstd compression
* 55d35d628 kern/efi/mm: Detect calls to grub_efi_drop_alloc() with wrong page counts
* 61f1d0a61 kern/efi/mm: Change grub_efi_allocate_pages_real() to call semantically correct free function
* dc0a3a27d kern/efi/mm: Change grub_efi_mm_add_regions() to keep track of map allocation size
* b990df0be tests/util/grub-fs-tester: Fix EROFS label tests in grub-fs-tester
* d41c64811 tests: Switch to requiring exfatprogs from exfat-utils
* c1ee4da6a tests/util/grub-shell-luks-tester: Fix detached header test getting wrong header path
* c22e052fe tests/util/grub-shell: Add flexibility in QEMU firmware handling
* d2fc9dfcd tests/util/grub-shell: Use pflash instead of -bios to load UEFI firmware
* 88a7e64c2 tests/util/grub-shell: Print gdbinfo if on EFI platform
* b8d29f114 configure: Add Debian/Ubuntu DejaVu font path
* 13b315c0a term/ns8250-spcr: Add one more 16550 debug type
* 8abec8e15 loader/i386/multiboot_mbi: Fix handling of errors in broken aout-kludge
* d35ff2251 net/drivers/ieee1275/ofnet: Remove 200 ms timeout in get_card_packet() to reduce input latency
* 86df79275 commands/efi/tpm: Re-enable measurements on confidential computing platforms
* 0b4d01794 util/grub-mkpasswd-pbkdf2: Simplify the main function implementation
* fa36f6376 kern/ieee1275/init: Add IEEE 1275 Radix support for KVM on Power
* c464f1ec3 fs/zfs/zfs: Mark vdev_zaps_v2 and head_errlog as supported
* 2ffc14ba9 types: Add missing casts in compile-time byteswaps
* c6ac49120 font: Add Fedora-specific font paths
* 5e8989e4e fs/bfs: Fix improper grub_free() on non-existing files
* c806e4dc8 io/gzio: Properly init a table
* 243682baa io/gzio: Abort early when get_byte() reads nothing
* bb65d81fe cli_lock: Add build option to block command line interface
* 56e58828c fs/erofs: Add tests for EROFS in grub-fs-tester
* 9d603061a fs/erofs: Add support for the EROFS
* 1ba39de62 safemath: Add ALIGN_UP_OVF() which checks for an overflow
* d291449ba docs: Fix spelling mistakes
* 6cc2e4481 util/grub.d/00_header.in: Quote background image pathname in output
* f456add5f disk/lvm: GRUB fails to detect LVM volumes due to an incorrect computation of mda_end
* 386b59ddb disk/cryptodisk: Allow user to retry failed passphrase
* 99b4c0c38 disk/mdraid1x_linux: Prevent infinite recursion
* b272ed230 efi: Fix stack protector issues
* 6744840b1 build: Track explicit module dependencies in Makefile.core.def

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 16:13:31 +01:00
Leah Rowe
80c3f9395d coreboot/fam15h: only use this, for amd boards
it is identical to fam15h_rdimm, with _udimm now removed;
the latter had a patch that added certain behaviour only
intended for rdimm, but the patch in question breaks various
configurations.

raminit has always been unreliable on these boards. i'd rather
simplify it all, in lbmk. i'll probably update this to the dasharo
tree later on, specificalyl for kgpe-d16

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 18:24:31 +01:00
Leah Rowe
0f7c0aa1c5 coreboot/default: re-merge coreboot/i945
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 17:53:10 +01:00
Leah Rowe
877f5d6aeb coreboot/default: merge coreboot/haswell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 14:48:01 +01:00
Leah Rowe
a15347ef1e coreboot/dell: merge into coreboot/default
The libgfxinit patch and other patches e.g. DDR2 fix, are
now provided in coreboot/default. The Latitude E6400 is now
using the newer coreboot revision from late July 2024.

Some other configs had to change because of this, relating to
the new way that Nicholas handles timing on LVDS displays
with the E6400 port; a default 96MHz clock is still used for
pixel reference clock, overridden with a value of 100MHz on
other GM45 machines, where 96MHz was previously hardcoded.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-09 20:55:42 +01:00
Leah Rowe
dbe24b039d coreboot/default: Update to 97bc693ab (2024-07-29)
Several patches are now merged upstream and no longer needed
in lbmk, such as the HP EliteBook 8560w patch, and related
patches. Some patches were changed, for example the Dell Latitude
ivb/snb laptops are now variants in coreboot, instead of being
individual ports; now they re-use the same base code.

This this, the corresponding files under config/submodules
have changed, for things like 3rdparty submodules e.g. libgfxinit,
and tarballs e.g. crossgcc.

This is long overdue, and will enable more boards to be added.
This newer revision will be used in the next release, and some
follow-up patches will merge these trees into default:

* coreboot/haswell
* coreboot/dell

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-09 20:50:37 +01:00
Leah Rowe
1b55fc790c fix hp8200sff_4mb ifd file (pd region)
see bug report:

https://codeberg.org/libreboot/lbmk/issues/228

The layout specified incorrect boundaries for the pd region.
With this change, it should flash and boot reliably.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 18:24:12 +01:00
Leah Rowe
490a94d7bc uefitool: Only define ACCESSPERMS on *nix
I re-read the modified code, and it has defines in place
for building on Windows; I was defining ACCESSPERMS
universally, but it should only be defined for non-Windows
systems, which the context in this code means Linux/BSD.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 16:38:48 +01:00
Leah Rowe
a78eaac883 uefitool: Add patch working around musl libc issue
musl libc is very conservative in what it implements,
preferring a very "pure" libc implementation. this means
that it lacks many of the niceties found in others like
the GNU C Library; the latter implements many BSD libc
extensions, for example.

ACCESSPERMS is a #define in BSD libc that does:
S_IRWXU | S_IRWXG | S_IRWXO

Essentially, it provides a bitwise OR providing chmod 0777,
which can be used as shorthand in calls to functions such
as mkdir() available in all libc implementations.

In the case of uefitool, this define is indeed used on mkdir.
Conditionally re-define ACCESSPERMS, if undefined, so that musl
libc can be used when building uefitool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 16:09:35 +01:00
Leah Rowe
59894ed555 lib.sh: new function mk() to handle trees in bulk
single-tree projects cannot be handled in bulk, e.g.
./mk -f project1 project2 project3

that is still the case, from the shell, but internally
it is now possible:
mk -f project1 project2 project3

mk() is a function that simply handles the given flag,
and all projects specified.

it does not handle cases without argument, for example
you cannot do:
mk -f

arguments must be provided. it can be used internally,
to simplify cases where multiple single-tree projects
must be handled, but *also* allows multi-tree projects
to be specified, without being able to actually handle
trees within that multi-tree project; so for example,
you can only specify coreboot, and then it would run
on every coreboot tree.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 13:35:31 +01:00
Leah Rowe
7fa6052de0 general code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-26 15:49:49 +01:00
Leah Rowe
3bd290f6a6 rom.sh: don't dry-run mkcoreboottar
same as the last change. make the main function a wrapper
that dry-runs the real function.

if the "dry" variable is blank, it executes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:46:53 +01:00
Leah Rowe
a91751a86b rom.sh: don't run mkcorebootbin on trees -d
don't let it execute during dry builds

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:39:36 +01:00
Leah Rowe
38b65af5b5 support ./mk in place of ./update trees
it's a shortcut command. a new symlink.

./update trees -b flashprog

can instead do:

./mk -b flashprog

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:36:04 +01:00
Leah Rowe
f5ba40200f trees: initialise badhash no n, not empty string
this is another alternative to the previous fix. this one
is therefore now a pre-emptive fix, in case other code is
written in the future that makes use of badhash.

the badhash variable in a y/n variable, so initialise to n.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 19:40:46 +01:00
Leah Rowe
faefcdf3df rom.sh: fix buggy deletion of cbutils
when badhash=y, the utils should be deleted, but
the check is deleting if badhash isn't n. if the
hash check isn't being performed, then this will
always be the case and the utils are always deleted.

make it positively delete the file only if badhash=y,
not when it isn't n. while this may not sound very
different, it will prevent the utils being deleted and
re-build endlessly in other cases, like when building
release archives and running the inject --nuke mode
on every image that gets built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 19:34:19 +01:00
Leah Rowe
40dd0a7cf3 rom.sh: also add grub to seabios images
we want multiple seagrub images made, with different
keymaps, but we only want one non-seagrub image.

however, we also want grub in the non-seagrub image.
it just means that seabios is primarily what the user
wants, and they might occasionally use grub, whereas
the seagrub images are for people who primarily want
grub but may occasionally access the seabios menu.

right now, the seabios images really only contain seabios,
but there's no harm in adding grub to them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 18:47:38 +01:00
Leah Rowe
d070eb1fef rom.sh: copy tmprom to TMPDIR for modification
don't rely on build/coreboot.rom staying in place,
because sometimes it can get purged under certain
conditions, due to idiosyncrasies in the coreboot
build system, even when we don't explicitly clean it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 18:40:42 +01:00
Leah Rowe
f85cb69ce0 rom.sh: re-add seabios-only roms and grub keymaps
this time, only handle multiple keymaps on seagrub
images. for images where seabios is first but does
not immediately load grub, whether grub is still
available in flash, just do one image (US Qwerty)

this still results in fewer images per target than
Libreboot 20240612, but should prevent most users
from being annoyed. i got a few people asking
repeatedly, and i hadn't documented yet how to add
keymap.gkb or how to remove bootorder, to get a
different keymap or disable seagrub respectively.

i anticipate that i'll get such questions a lot, even
if i do document it, so i'm reversing that decision.

it doesn't result in much extra code. the new design
in lbmk makes this sort of thing much simpler.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 09:30:47 +01:00
Leah Rowe
490e0186a2 emphasis on readme that lbmk isn't a coreboot fork
i actually only made this change so that the revision changes,
so that the release directory changes when doing:
./update release

this is to test whether such location change affects the build
time when using ccache.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 02:00:26 +01:00
Leah Rowe
ba4278e0c6 include/rom.sh: use ccache when building coreboot
ccache now required, in build dependencies

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-21 07:39:47 +01:00
Leah Rowe
31f1e4dadf vendor.sh: don't use XBMK_CACHE for appdir
the me_extract function prefixes it with PWD in
some cases, but we can't predict where appdir
will point to.

the "app" directory is not intended to be a cache
anyway, so it doesn't make sense to put it in
the cache directory.

it's essentially scratch memory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-19 00:48:09 +01:00
Leah Rowe
2b50b3ea9a put cachedir in environmental variable
XBMK_CACHE is now used, instead of hardcoding cache/

this is exported initialised to cache/, if unset.
this means you can set your own directory, and it means
./update release will use the same directory.

this means bandwidth wastage is further avoided.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-19 00:37:11 +01:00
Leah Rowe
0e0b12a630 git.sh: warn when a cached clone fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:23:50 +01:00
Leah Rowe
9b1b955767 git.sh: fix typo in git command
the || : condition should be used, whereas i just
wrote : by mistake. this was done in a previous change.

fix it now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:11:45 +01:00
Leah Rowe
82bdf27072 git.sh: fix lack of error exits on fault
a previous change made it more redundant, falling back
on old behaviour (direct downloading, not cached), but
the way it's done means that the function never returns
an error condition in practise.

this patch fixes it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:09:59 +01:00
Leah Rowe
64283a1fb1 build: remove tmp/ on release archives
i overlooked this before. remove it. the directory
happened to be empty when i tested archives, but it's
still not a good thing that we have it. remove it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 14:13:11 +01:00
Leah Rowe
bf85246c4c trees: hardcode makeargs for xgcc
if coreboot itself is being handled, crossgcc has the
correct makeargs, setting the number of build threads.

however, other projects can specify "xtree" pointing to
a given coreboot tree, and build crossgcc for it.

one workaround may be to use trees -d coreboot TREE,
but then extra code would have to be written to make
it avoid other things like building cbfstool, which is
not required for just building crossgcc.

the cleanest way to do it is to simply hardcode it. the
value is set exactly the same as regular coreboot makeargs.

this fixes a bug, where some builds of crossgcc are made
on a single thread, rather than using XBMK_THREADS. this
patch forces it to always use CPUS=$XBMK_THREADS

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 23:25:44 +01:00
Leah Rowe
c6e6d96ce1 allow using coreboot's build system to add payload
lbmk must still define payloads, but specific configs
may use coreboot's build system instead.

you might use this to add your own config with, say,
tianocore payload, using coreboot.git to build it,
rather than using lbmk's choice of payloads.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 19:06:53 +01:00
Leah Rowe
78cdc56ae1 trees: remove unnecessary command
we no longer need to remove cache/ per project, because
it's removed in bulk at the end, in the main build script,
when generating release archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:55:18 +01:00
Leah Rowe
e699037890 build: remove cache/ on making releases
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:52:58 +01:00
Leah Rowe
79f50b3791 unify caching of files into cache/
hash/ becomes cache/hash/

repo/ becomes cache/repo/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:39:42 +01:00
Leah Rowe
a9f9de885c unified cache file handling for vendorfile/subfile
lib.sh download() is used by subfile handling in git.sh,
e.g. crossgcc tarballs, and also the vendor scripts.

vendor files are cached, but not subfiles for repos.

cache both, under cache/file/, saved with the name equal
to the checksum, so: cache/file/CHECKSUM

also move vendorfiles/app/ to cache/app/ in this change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:15:52 +01:00
Leah Rowe
ef867eccca git.sh: remove previous tmprepo if args>5
if doing a retry, the directory may still exist, which
would make git clone yield an error response; the existing
directory will have been the one that failed to reset, so
let's delete it.

the one deleted is not the cache (repo/PROJECT/), thus
otherwise maintaining current behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 17:28:27 +01:00
Leah Rowe
4d5385a14d git.sh: try direct clone if cached git fails
normally, a project is cached at repo/PROJECT/, and
cloned from there to the final destination.

errors lead to a calling of $err, but this will result
in a return if done from inside a subshell, of non-zero
value, so use this to re-try with a 6th argument when
calling tmpclone().

in most cases, this fallback will never kick in, but
it will kick in resetting or patching the cached clone
fails; specifically, we are interested in the reset part.

a given project name may change repositories in lbmk at
a given time. if this happens, and the old one is cached,
the overall result of this patch is that lbmk will fall
back to the old behaviour, where git urls are tried
directly, without caching.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 17:09:34 +01:00
Leah Rowe
0cd52fc7fd git.sh: re-try git pull three times
mitigate jittery internet connections

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 16:55:05 +01:00
Leah Rowe
0b9cd77fe7 trees: auto-delete+auto-rebuild if project changes
actual source code is not scanned, but config directories are
scanned. simply get the checksum of each file under config/
pertaining to a given project/tree, and also for the given
target. coreboot utilities are also handled.

if it changes, in any way, delete and re-build automatically.

such deletions should probably still be done manually, as part
of understanding the build system, but this change should make
the build system much easier to use during development.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 16:34:34 +01:00
Leah Rowe
4438368c0c trees: also remove single-tree repo/p/
single-tree repos were not previously cached, but now
they are and they have to be handled.

this, as also alluded to in the previous commit, is done
when preparing release archives (XBMK_RELEASE=y)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:27:50 +01:00
Leah Rowe
570e3abb24 trees: remove repo/p, not src/p/p
repo/p/ does not have its revision reset, so it
changes unpredictably, and it's not used in builds.

this used to be src/p/p/ - the context here is multi-tree
projects, in source archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:24:21 +01:00
Leah Rowe
583502027e git.sh: don't download to src/project/project/
re-use repo/project/

this means that single- and multi-tree projects now
have a unified cached git repo location, as per the
new rules, thus saving on disk space usage.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:20:51 +01:00
Leah Rowe
9f09728aca git.sh: cache git downloads to repo/
do it based on the URL, e.g. https://review.coreboot.org/coreboot
becomes repo/coreboot

the downside is if you have two projects with repo urls specifying
the same string at the end, but this isn't the case at the moment
and likely won't be the case, but it's a theoretical issue.

this saves on bandwidth when downloading identical submodule repos
between multiple trees within the same multi-tree project

for example, coreboot 3rdparty/vboot is no longer downloaded more
than once, instead cloned locally on subsequent downloads.

if repo/DIR exists, git-pull is attempted, but errors do not result
in a non-zero exit, by design.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:01:12 +01:00
Leah Rowe
f367afabc1 remove util/autoport
upstream has merged all of the changes that it contained,
so we don't need this anymore. we'll have the newer upstream
changes on the next general revision updates for coreboot,
within config/coreboot/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-16 03:57:08 +01:00
Leah Rowe
373c2eb23d trees: move dependency building to new function
configure_project is a bit big. move the dependencies
build logic to a new function.

it may be desirable in future to make the way that
function works the way all build commands are done.

for example:

./update trees -b coreboot x230_12mb

would become:

./update trees -b coreboot/x230_12mb

this would enable to mix and match multi/single tree
projects. for now, leave things as they are.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-13 23:07:45 +01:00
Leah Rowe
12c3956f59 Merge pull request 'Update U-Boot to v2024.07' (#225) from alpernebbi/lbmk:uboot-v2024.07 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/225
2024-07-11 22:03:18 +00:00
Alper Nebi Yasak
708fc14c60 u-boot: Fix display initialization on gru boards
U-Boot has migrated to using upstream device-tree files for gru boards,
but the clock driver doesn't yet support setting rates for a certain
clock that upstream uses for the eDP display. It happens to work without
it, so for now remove the clock setting until the driver is fixed.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 23:16:42 +03:00
Alper Nebi Yasak
0cc7736b40 u-boot: Avoid breaking build for U-Boot-only binman images
Commit 46e01c0e1d ("u-boot: Avoid building U-Boot-only binman images")
added a patch that prevents an error while building U-Boot, due to some
U-Boot images needing a copy of BL31 that we are not passing in.

Removing build instructions for these images isn't really necessary,
when we can instead tell the build tool that it shouldn't exit with an
error. It checks a BINMAN_ALLOW_MISSING environment variable for this,
but just unconditionally replace the check with the argument.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 22:40:33 +03:00
Alper Nebi Yasak
2ecec55af7 u-boot: Update to v2024.07
Set default U-Boot revision to v2024.07 and rebase patches on top of
that. One patch that fixes drawing box characters (UTF-8 to CP437) had
an alternative merged, another hack we have to fix regulator issues is
no longer neccessary as the issue is fixed, and my QEMU patches were
merged upstream, so drop these patches. One patch we have to disable
binman images can be replaced by a simpler alternative so drop it too.

Upstream kconfig status is still unstable, so updating configs with
`make oldconfig` would miss important upstream changes, since they rely
on carrying defaults via upstream defconfigs. Update the configs as
such, like before:

- Turn old configs into defconfigs (./update trees -s u-boot)
- Save the diff from old upstream defconfig (diffconfig $theirs $ours)
- Update U-Boot revision, rebase patches, and clean old trees
- Prepare new U-Boot tree (./update trees -f u-boot)
- Review the diffconfigs to see if any options were renamed upstream
- Copy over the new upstream defconfigs and apply earlier diff
- Turn new defconfigs into configs (./update trees -l u-boot)

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 22:29:58 +03:00
Leah Rowe
090cf7ad54 trees: fix bad comparison in configure_project()
we used to set cmd only to these values:
build_project
build_targets

however, now we set them to:
build_project
build_targets $@

the latter cannot be measured reliably, but
we were checking whether cmd equalled:
build_targets

now we instead check that it does not equal:
build_project

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-11 01:14:28 +01:00
Leah Rowe
e37779c11d trees: don't continue if no argument given
main() used to be the only function executed from
outside of main(), in this script, but now we source
a config file and then run the build afterward.

when a flag is provided without OPTARG, this means
that we are continuing such action erroneously. to
mitigate this, return 1 in that instance, and handle
it in the line that calls main(), making it exit with
zero status (success).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-11 00:28:32 +01:00
Leah Rowe
3263eeb6b6 trees: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 23:11:23 +01:00
Leah Rowe
17f3e61a0e trees: merge build_targets() with handle_targets()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 21:43:13 +01:00
Leah Rowe
c0a4df688c trees: use wrapper for dry-running make commands
instead of using lots of if/else conditions, do that once
and set a variable, dry, to :

if not doing a dry run, the variable is empty. prefix this
variable in places where you don't want a certain action to
be performed, on dry runs.

more specifically, : does *nothing* and always returns with
zero status (success).

this results in cleaner code, and a small sloccount reduction.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 21:00:16 +01:00
Leah Rowe
459db1cc2e trees: remove project-specific hacks
move the coreboot-specific includes into mkhelper.cfg
for that project.

on some projects, we need variables from mkhelper.cfg
to be global, so I was including serprog and coreboot
mkhelper.cfg files in this script.

instead, set a new variable "mkhelpercfg" pointing to
the config file. if it doesn't exist, create and then
point to a temporary (empty) mkhelper.cfg file.

the rom.sh include has been moved to coreboot mkhelper.cfg

The only remaining project-specific logic, in this trees
script, is now the coreboot crossgcc handling, but this
needs to be there as it's also used to build U-Boot.

The way this now works, certain includes are done twice.
For example, include/rom.sh will be included once globally,
outside of main(), and then again in configure_project().

This means that certain functions will be defined twice.
I'm uncertain if shell has anything equivalent to an ifdef
guard as in C, but we actually want this here anyway, and
it shouldn't cause any problems. It's a bit of a hack, but
otherwise results in much cleaner code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 13:41:15 +01:00
Leah Rowe
e9f66ec4a8 remove executable permission on include/
files under include/ should never be executed directly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 02:14:25 +01:00
Leah Rowe
91994b7852 rom.sh: actually say if a cbutil exists
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 02:04:25 +01:00
Leah Rowe
97b777715b rom.sh: avoid re-building cbutils if built
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:37:27 +01:00
Leah Rowe
494b94799e rom.sh: only before cbutils before coreboot
otherwise, due to the idiosyncratic nature of the coreboot
build system, the coreboot.rom gets wiped out.

cbutils is still handled by premake. ensure that payloads are
only inserted just after running the coreboot make command.

fixes a build issues introduced on 9020sff, previously unhandled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:24:05 +01:00
Leah Rowe
469cc64f99 trees: fix bad comparison
pro-tip: don't do this at 3AM

do massive changes like this, no later than 1AM.

the intent anyway is for -d to cause no build dependencies
to be handled, but the current logic says to only handle
them if -d is set! fix it by removing the ! part

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:11:14 +01:00
Leah Rowe
5a1d2401c2 minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-09 03:09:49 +01:00
Leah Rowe
9646172145 trees: support -d (dry run) for custom build logic
-d does the same as -b, except for actually building
anything! in effect, it does the same as -f (fetch)
except that the resulting variable assignments will
not be recursive (as with -f).

if -d is passed, configuration is still loaded, defconfig
files are still cycled through, and more importantly:

helper functions are still processed.

the grub, serprog and coreboot helper functions have
been modified to return early (zero status) if -d is
passed.

this behaviour will be used to integrate vendor.sh
logic in with the trees script, for cases where the
user wants to only handle vendor files. e.g.:

./update trees -b coreboot x230_12mb

this would download the files as usual, build coreboot,
with those files, and then build the payloads. but:

./update trees -d coreboot x230_12mb

this would download the files, NOT build coreboot, and
NOT build the payloads.

this change increases the sloccount a bit, but i'm relying
on the fact that the vendor.sh script already re-implements
config handling wastefully; the plan is to only use trees.

for now, simply stub the same ./vendor download command.

there is one additional benefit to doing it this way:

this method is *per-kconfig* rather than per-target.
this way, one kconfig might specify a given vendor file
that is not specified in the other. although the stub
still simply handles this per target, it's done in premake,
which means that the given .config file has been copied.

this means that when i properly re-integrate the logic
into script/trees, i'll be able to go for it per-kconfig.

the utils command has been removed, e.g.
./update trees -b coreboot utils default

the equivalent is now:
./update trees -d coreboot default

this would technically download vendor files, but here
we are specifying a target for which no kconfigs exist;
a check is also in place, to avoid running the vendor file
download logic if tree==target

the overall effect of this change is that the trees script
no longer contains any project-specific logic, except for
the crossgcc build logic.

it does include some config/data mkhelper files at the top,
for serprog and coreboot, so that those variables defined in
those files can be global, but another solution to mitigate
that will also be implemented in a future commit.

the purpose of this and other revisions (in the final push
to complete lbmk audit 6 / cbmk audit 2) is to generalise as
much logic as possible, removing various ugly hacks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-09 02:55:20 +01:00
Leah Rowe
e850c06bd2 rom.sh: only make rom tarball if release=y
Signed-off-by: Leah Rowe <info@minifree.org>
2024-07-08 02:22:22 +01:00
Leah Rowe
2f3cc5d379 rom.sh: new file, to replace script/roms
stub it from the trees script. the way it works now,
there is less code in the build system.

./build roms

this is no longer a thing

./build roms serprog

this is also no longer a thing. instead, do:

./update trees -b coreboot targetnamehere

./update trees -b pico-serprog

./update trees -b stm32-vserprog

the old commands still works, which causes the new
commands to run

coreboot roms now appear in elf/, not bin/, as before,
but those images now contain payloads.

NOTE: to contradict the above: ./build roms is no
longer a thing, in that it's now deprecated, but
backward compatibility is present for now. it will
be removed in a future release.

./build roms list also still works! it will do:
./update trees -b coreboot list

also:
./update trees -b grub list
this is now possible too

if a target "list" is provided, for multi-tree sources,
the targets are shown.

there is another difference: seagrub roms are now seagrub_,
instead of seabios_withgrub.

seabios-only roms are no longer provided, where grub is also
enabled; only seagrub is used. the user can easily remove
the bootorder file, if they want seabios to not try grub first.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-07 21:25:07 +01:00
Leah Rowe
889afe1689 roms: remove unnecessary trees checks
we no longer need to call trees -b for payloads, because
build_depend is set in coreboot target.cfg files

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe
c241a3ef48 coreboot: set build_depend on target.cfg files
set a default one in mkhelper.cfg

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe
6d4fb200ac trees: rename load_target_config()
rename it to configure_project, because the function now
also handles building (a little bit), not just mere loading
of configuration files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe
87df6ae369 trees: support build dependencies, not just fetch
We already have this to an extent, e.g. the xtree variable.

The xtree variable could probably be removed, in favour of
this, and used for the same purpose.

It works like this, for example:

build_depend="coreboot/default grub/xhci seabios u-boot/gru_bob flashprog"

the "/" denotes a tree, if it's a multi-tree project. However, specifying
the entire multi-tree project without slash is possible, for example:

build_depend="coreboot"

this would specify that all coreboot trees must be built.

This functionality will be used in follow-up commits, centralising
script/trees into mk on the main directory, repacing "build".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:19 +01:00
Leah Rowe
23ca49bee8 GRUB: only load xhci from grub.cfg
don't put it in the install modules.

this works around a hanging issue on haswell thinkpads.

when any usb device is inserted, GRUB will sometimes
hang if started from the SeaBIOS payload, *while* the
USB device is plugged in.

plugging in the USB device after GRUB starts worked.
it will have to be investigated more at a later date,
but this simply configuration change works.

the xhci module is already loaded explicitly, in grub.cfg

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 02:04:14 +01:00
Leah Rowe
065453b72e trees: just do makeargs on coreboot, not cbmakearg
stick the makeargs in mkhelper

i previously did cbmakeargs because the old revisions
had to define makeargs per-target otherwise. mkhelper
was done specifically to solve that problem.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-05 18:17:23 +01:00
Leah Rowe
2ab1d99490 trees: fix bad rm -Rf command (-Rf, not Rf)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 13:03:04 +01:00
Leah Rowe
d6ff009e20 roms: fix bad comparison in configure_target()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 03:34:09 +01:00
Leah Rowe
3ee045f9ad GRUB: use mkhelper.cfg for common variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 03:32:35 +01:00
Leah Rowe
3ef84af9fd trees: allow global config on multi-tree projects
config/data/PROJECT/mkhelper.cfg can be provided, for
configuration, and it is loaded *before* target.cfg

there are certain instances where we repeat a lot of
config per tree, in multi-tree projects.

for example, we have the exact same config per grub
tree, besides tree name and revision number, for things
like autoconf arguments.

this last problem will be addressed, in a follow-up
patch, and then expanded upon for other projects.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 22:22:15 +01:00
Leah Rowe
2b49714a6a trees: handle all projects if project undefined
e.g. ./update trees -f

if passed, this command would download every tree

similarly, the -c option can be used in this way. this
solves a longstanding issue: on the current, much more
efficient design, it was not possible to systematically
clean every project.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 21:33:30 +01:00
Leah Rowe
b7f12ade03 vendor.sh: remove mkdirs()
merge it into the only calling function

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 19:22:58 +01:00
Leah Rowe
0018600d6e git.sh: simpler for loop in git_am_patches()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:23:15 +01:00
Leah Rowe
5882056a27 git.sh: merge for loops in git_am_patches()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:16:34 +01:00
Leah Rowe
67421a21fd trees and git.sh: tidy up global variables
some of the variables only initialised in git.sh are
also used in the trees script, which is technically ok
because git.sh is included from the trees script, but
it makes more sense to declare them in the latter.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:10:22 +01:00
Leah Rowe
55dbd72aaf git.sh: simplified initialisation of "loc"
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:56:32 +01:00
Leah Rowe
0cb84a8dd1 trees: simplified distclean directory check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:13:49 +01:00
Leah Rowe
5ba0433b5f git.sh: condense fetch_targets() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:04:24 +01:00
Leah Rowe
4772186b19 git.sh: short git_prep command in fetch_targets()
loc is already set, and will correspond to the same
path, so we can quite conveniently use it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:02:44 +01:00
Leah Rowe
c62dbdbe82 trees: only do bare multi-tree clone on git
i forgot to add the check for CHANGELOG

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 16:23:32 +01:00
Leah Rowe
89a81a2910 trees: simplified multi-tree bare repo clone
the git_prep function already creates the given
directory where source code goes, so we don't
need to do it from the trees script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 16:16:07 +01:00
Leah Rowe
017fd8259e git.sh: merge prepare_new_tree with fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:49:35 +01:00
Leah Rowe
f937a1142d trees run_make_command: simpler distclean handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:46:03 +01:00
Leah Rowe
88f741db92 trees: condense copy_elf() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:39:41 +01:00
Leah Rowe
d5928c9ba8 trees: add return to handle_defconfig()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:39:20 +01:00
Leah Rowe
1a7c8acb0e trees: rename check_config to check_defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:13:52 +01:00
Leah Rowe
ba7b3a3b21 trees: remove variable "config_name"
it's only ever used once, so just use the value that
it's set to, without declaring the variable itself

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:10:49 +01:00
Leah Rowe
030f1afd8e trees: rename variable "config" to defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:08:22 +01:00
Leah Rowe
7394960619 git.sh: remove duplicate "xtree" variable
it's already defined inside the trees script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:00:19 +01:00
Leah Rowe
0c4ad24b05 trees: remove unnecessary commonts
behaviour described there is obvious just
from analysing the while loop condition

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:46:31 +01:00
Leah Rowe
eacc41e82a trees: condense run_make_command() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:42:42 +01:00
Leah Rowe
5639481419 trees: condense handle_makefile() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:30:35 +01:00
Leah Rowe
1ec9fc3368 trees: mv load_project_config load_target_config
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 01:07:59 +01:00
Leah Rowe
789631ccb8 trees, multi: download bare project *before* trees
when downloading multi-tree projects, the rev can be reset
to HEAD instead of the actual rev for a given target. this
occurs when the bare repo (e.g. src/coreboot/coreboot) does
not exist and has to be downloaded first.

bare repository downloading does not rely on target.cfg, in
this context, only pkg.cfg, but it uses the same variable
names (e.g. "rev").

instead of using a separate variable name, thus increasing
code complexity (which is the exact opposite of what i want
to do), do the bare repository download first.

this means that the git.sh script is much cleaner now, for
multi-tree projects, in that it *only* copies the bare repo
then runs git_prep; in that context, the bare repo is cloned
directly by calling the relevant function from script/trees,
which is the same behaviour as when cloning single-tree
project sources.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 00:40:30 +01:00
Leah Rowe
a5e724e51e trees: unified multi-tree configuration handling
the same function that loads configurations for single-tree
projects has been merged with the function for multi-tree
configs in git.sh, and that functionality has been removed
from git.sh; now it is all unified in the trees script.

as the saying goes: write one program to do one thing well.

the purpose of git.sh is to download source code, but not
to handle configuration files; the latter is meant to be
handled by the trees script, which then calls into git.sh
before running the build logic for that given project.

additionally: the "seen" files are no longer handled, at all.
the logic there was added ages ago, because at the time, i was
considering whether to separate configuration into a new
repository, so that users could more easily make their own
configuration, so it was a guard against misconfiguration.
however, that decision was canceled and we're always very
careful not to introduce a loop; if a loop does occur, the
worst that can possibly happen is you waste some CPU cycles.

Instead, print (on standard output) what config file is being
used, so the operator can see when an infinite loop occurs.

ALSO:

remove _setcfgarg in load_project_config()

it was used to skip when a target.cfg file didn't exist,
specifically on single-tree projects, but this is now
handled using -f instead, on the while loop inside that
function, so _setcfgarg is now a redundant variable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 00:02:03 +01:00
Leah Rowe
cfc9f62ffe trees: unified handling of source downloads
run it from load_project_config()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 22:25:54 +01:00
Leah Rowe
7bf2835207 git.sh: rename Fetch_project_trees fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:59:16 +01:00
Leah Rowe
e0c244f37b git.sh: rename fetch_project_repo to fetch_project
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:58:03 +01:00
Leah Rowe
02f7417952 trees: better skip-clean string in handle_src_tree
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:47:25 +01:00
Leah Rowe
f7ec42d379 trees: add return to check_coreboot_utils()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:46:07 +01:00
Leah Rowe
8d02adfbb5 trees: simplify "utilmode" variable initialisation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:44:47 +01:00
Leah Rowe
d1b7882c5a vendor.sh readcfg: split the -b coreboot command
just add a line break to make the code more readable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 18:55:41 +01:00
Leah Rowe
fbe36b01ac trees mkpayload_grub: remove unnecessary check
these variables are initialised empty, then populated
by reading a configuration file.

it may be that in some cases, we want these variables
to be empty. besides that, the "setcfg" command before
it will throw an error if the module file is missing,
and it is assumed that the variables would be set there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 18:39:25 +01:00
Leah Rowe
088a79918b vendor.sh: remove unnecessary check
the next command is a copy, which would give us the error
if the file doesn't exist, and an appropriate message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:47:57 +01:00
Leah Rowe
8c5f78d3d3 vendor.sh: condense inject() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:27:31 +01:00
Leah Rowe
42925ce79f vendor.sh extract_kbc1126: use quote on file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:09:03 +01:00
Leah Rowe
ddcc74777e vendor.sh extract_kbc1126ec: simplify build check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:06:58 +01:00
Leah Rowe
7a12cd7704 vendor.sh: simplify e6400 vga rom file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:25:22 +01:00
Leah Rowe
163bcfcdfd vendor.sh: simplify variable checks for e6400vga
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:23:02 +01:00
Leah Rowe
cbac2087cc vendor.sh: condense fetch() a bit more
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:21:00 +01:00
Leah Rowe
675d2c0376 vendor.sh: remove unnecessary check
this is over-engineering, because we do not allow just
about any path to be provided; it's not provided as an
argument in a command, for example.

this is dictated by a configuration file, which we control.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:14:00 +01:00
Leah Rowe
5e46b9f434 vendor.sh: simplify kbc1126 util handling
we don't need to check whether the binary exists, because
make already does that for us.

we still need to check that the directory exists, because
older versions of coreboot did not include kbc1126, and we
do still use older coreboot revisions on some boards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:12:40 +01:00
Leah Rowe
7086b68685 vendor.sh: simplify bootstrap() utils handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:07:16 +01:00
Leah Rowe
6a05487ef3 vendor.sh: simplified initialisation of _7ztest
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:57:03 +01:00
Leah Rowe
972e61070b vendor.sh: condense detect_board() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:47:14 +01:00
Leah Rowe
bf5acedb12 vendor.sh: condense patch_rom() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:41:48 +01:00
Leah Rowe
8b8cf070d3 vendor.sh: add return to end of bootstrap()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:27:42 +01:00
Leah Rowe
d85b9de2d9 vendor.sh: rename getcfg() to readkconfig()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:26:31 +01:00
Leah Rowe
53b69f673c vendor.sh: merge cfgutils() into readcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:24:13 +01:00
Leah Rowe
55677d8217 vendor.sh: remove build_dependencies_inject()
merge it into vendor_inject()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:22:28 +01:00
Leah Rowe
c764198619 vendor.sh: simplify initialisation of variables
also unify handling of cbutils

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:19:29 +01:00
Leah Rowe
d63da943c1 vendor.sh inject: skip serprog targets
this is to prevent a fault condition during automated testing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 00:33:31 +01:00
Leah Rowe
c6df9666af vendor.sh: don't inject /dev/null
if injection is attempted, verification comes next,
and verification fails.

this happens for kcma/kgpe amd boards, where pike2008
fake roms are inserted by inserting the correct pci
ids using /dev/null as a source. an empty pike2008 rom
prevents seabios from loading the real pci rom, and this
is done because the real one hangs SeaBIOS.

a similar fix was made for ./vendor download, but
overlooked for ./vendor inject. this patch fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 00:23:26 +01:00
Leah Rowe
f7ab70f60e vendor.sh: simplify inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:53:29 +01:00
Leah Rowe
ee5bab2c9a vendor.sh: clean up GbE handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:33:31 +01:00
Leah Rowe
f2d53eb842 vendor.sh: condense fetch() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:10:22 +01:00
Leah Rowe
85c2eb0f7c vendor.sh: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:49:59 +01:00
Leah Rowe
a8f272536d lib.sh: stricter check in chkvars()
testing +x is all well and good, but the variable string
may be empty, even if set. some of the checks in the build
system are relying on the latter, so handle it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:32:03 +01:00
Leah Rowe
fa5af956c4 vendor.sh: simplified modify_gbe handling
we don't need the "modifygbe" variable. we only need to
know that new_mac was set.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:31:09 +01:00
Leah Rowe
155ce49b17 vendor.sh: simplify modify_gbe()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 21:43:23 +01:00
Leah Rowe
08bce7ad3b vendor.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 21:31:40 +01:00
Leah Rowe
636b86237f vendor.sh: re-add modify_gbe()
i accidentally deleted it in an earlier code purge

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 16:24:07 +01:00
Leah Rowe
2eb0163cc7 Revert "vendor.sh: remove unnecessary check"
This reverts commit 8196ce6ddf.
2024-06-28 15:24:42 +01:00
Leah Rowe
3f37c3788b tidy up some setvars lists
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 15:02:11 +01:00
Leah Rowe
ed3cce84bc roms: explicitly shift by 1 on the "all" target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:57:07 +01:00
Leah Rowe
359d00bd56 roms: add return value for the list command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:56:30 +01:00
Leah Rowe
3f540e7565 roms: build u-boot *before* checking ubootelf
the current check is flawed, because if u-boot doesn't
exist, but a given build would be the file verified by
the first check, the check would still fail even after
then building u-boot.

building it first will make this check pass, under such
a condition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:52:08 +01:00
Leah Rowe
afc0030682 remove more unnecessary checks on trees commands
the trees script already performs these checks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:51:32 +01:00
Leah Rowe
35c487106a vendor.sh: remove unnecessary checks
again: the trees script already checks binaries,
and already checks sources. if they exist, the
relevant action is skipped entirely.

we don't need to check it in vendor.sh, because the
trees script already performs the same check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:45:20 +01:00
Leah Rowe
ce03786f69 vendor.sh: remove unnecessary command
we don't need to download the entire coreboot tree here,
because the next command after it builds utils from that
tree, using the trees script which would then go and
download that tree anyway; this is part of the design.

if a given elf binary exists, it won't be re-built, but
the missing sources will still be downloaded automatically.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:18:01 +01:00
Leah Rowe
e01b5c9744 vendor.sh: remove unnecesessary cbutils check
the trees script already does this same check, so don't
do it in here. defer to the trees script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:16:17 +01:00
Leah Rowe
8196ce6ddf vendor.sh: remove unnecessary check
mktemp will never return empty output, and the next
command after it is an mkdir, which would throw an
error anyway, if the string is empty.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:15:28 +01:00
Leah Rowe
8f50131e1e vendor.sh: condense check_board() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:59:26 +01:00
Leah Rowe
d12a686015 vendor fetch(): condense variable initialisation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:50:35 +01:00
Leah Rowe
708e306e5f vendor.sh: remove unnecessary cbfstool check
the trees script already performs this check

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:49:44 +01:00
Leah Rowe
75951c4690 vendor.sh: simplified cbfstoolref check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:49:08 +01:00
Leah Rowe
d36c07847d lib.sh: keep versiondate check to 80 characters
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:44:13 +01:00
Leah Rowe
40d3bb19be lib.sh: condense for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:42:19 +01:00
Leah Rowe
5725e3c4ee lib.sh: condense err_() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:41:22 +01:00
Leah Rowe
e3546f77b8 lib.sh: add a return to the end of chkvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:40:50 +01:00
Leah Rowe
d0f68a0fbf vendor.sh: rename release to vrelease
also remove inject_vendorfiles() and merge it
into vendor_download()

the "release" variable is included in some target.cfg
files, which we put in config/coreboot/ and handle
here, so they could conflict with the release variable
used in vendor.sh, used for a different purpose. therefore,
rename it to "vrelease".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:38:43 +01:00
Leah Rowe
473f277845 vendor.sh: unified reading of board configs
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:33:50 +01:00
Leah Rowe
a2f4eba581 vendor.sh: simplify variable check in getcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:24:47 +01:00
Leah Rowe
4afcbcb641 vendor.sh: remove unnecessary cbdir check
we don't need to check this, because the trees script
already checks it. avoid unnecessary work.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:22:37 +01:00
Leah Rowe
fd037722ad remove use of _xm variable in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 22:18:01 +01:00
Leah Rowe
136787185d trees: don't hardcode use of mkpayload_grub
instead, make it a helper function, defined in target.cfg

this means that we can also do the same with other projects
in the future, and it is expected that we will have to.

these helper functions are used in cases where we want
additional actions to be performed.

actually, the helper could be anything. for example, you
could write:

mkhelper="./build foo bar"

and it would do that (at the point of execution, PWD
is the root directory of the build system)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:51:48 +01:00
Leah Rowe
c59fbb3651 trees: simplify single/multi handling in main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:43:35 +01:00
Leah Rowe
902b98d1ac trees: rename build_projects to build_project
the script used to support building multiple single-tree
projects, but this behaviour was buggy and unused, so it
was removed.

rename the build_projects variable accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:41:23 +01:00
Leah Rowe
e1e04aa80d trees: err if target.cfg not given if multi-tree
it was always by design that an error should occur, if a
target.cfg file does not exist on multi-tree projects,
but we previously did not support target.cfg files on
single-tree projects.

single-tree target.cfg support was later added, and it was
done by making target.cfg optional there, but i accidentally
made it optional on multi-tree projects.

in practise, all multi-tree projects included target.cfg,
but this was not being enforced in code.

this patch should fix the issue.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:38:49 +01:00
Leah Rowe
93ff80d96d trees: set btype if target.cfg doesn't exist
set it to "auto", because otherwise it'll be unset,
which means that kconfig type is assumed.

the build system is designed in such a way that multi-tree
is assumed, if the target build system uses kconfig files.

target.cfg is optional on single-tree but not multi-tree,
so it's ok to set something here.

basically, kconfig-type projects will never be single-tree.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:33:30 +01:00
Leah Rowe
732c5908df lib.sh: remove unused cbdir variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:12:30 +01:00
Leah Rowe
119cebc4d8 roms: remove unnecessary assignment to cbdir
cbdir isn't used in this script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:10:09 +01:00
Leah Rowe
7a15ba18cb trees: avoid kconfig make commands generically
don't hardcode the check based on whether the current
project is grub. instead, define "btype" in target.cfg

if unset, we assume kconfig and permit kconfig commands
e.g. make menuconfig, make silentoldconfig, etc

this is to avoid the deadliest of sins:
project-specific hacks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 15:55:56 +01:00
Leah Rowe
eb9c1872b6 git.sh: remove unnecessary check
the trees script itself will check that the directory
exists, and exit with zero status if it does, without
doing anything else other than the return.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:52:28 +01:00
Leah Rowe
9aec992ff2 lib.sh: move git_err() to build
it's only used in the main build script, so move it there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:32:20 +01:00
Leah Rowe
6fc7cd3c17 lib.sh: condense singletree() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:06:41 +01:00
Leah Rowe
35d09e426a lib.sh: add a return to the end of check_defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:06:08 +01:00
Leah Rowe
144b3c93a4 trees: condense elfcheck() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:05:19 +01:00
Leah Rowe
7b8c2bd412 lib.sh: condense e() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:41:30 +01:00
Leah Rowe
ffdecb0ce1 trees: shorten the final confirmation message
must stay below 80 characters per line

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:36:32 +01:00
Leah Rowe
ed6acfee84 lib.sh: make elf/coreboot* a dot directory
we don't want the user to flash coreboot from elf/, because
those images do not contain payloads. the user must flash from
bin/

ample warning is given, at build time, but the warning is written
in english. therefore, some people may not understand it, because
they may not even speak english.

hide the coreboot elf/ directory, to mitigate this possibility.
in most cases, this will probably prevent the average user from
flashing those images, since they likely won't see it.

the "DO NOT FLASH" warning is still included in that directory
name, while creating it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:23:31 +01:00
Leah Rowe
44fb987363 build: don't rm TMPDIR if it's /tmp
we override TMPDIR, setting it to /tmp/xbmk*C

if it's just set to tmp, that means we didn't set it properly,
which is a bug.

this patch protects against deletion of /tmp under such a
fault condition, if it were ever to occur in the future.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:20:18 +01:00
Leah Rowe
fac74cd60a lib.sh: simplified TMPDIR handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:18:23 +01:00
Leah Rowe
671893a802 lib.sh: condense setcfg() if/else logic
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:52:46 +01:00
Leah Rowe
19bc5845a6 trees: remove redundant space in printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:45:11 +01:00
Leah Rowe
9154ba5b85 trees: explicitly err if OPTARG is not set
we currently rely on -e to make this happen

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:44:01 +01:00
Leah Rowe
f383b1ad70 trees: only permit one single-tree project
the current logic for handling multiple single-tree projects
is quite error-prone, and uses recursion.

since we don't actually use it this way, remove that feature.

the most correct way to do it is with a for loop.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:42:59 +01:00
Leah Rowe
a64e2db589 trees: call err if multiple flags are provided
this script is designed to only run a single flag.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:33:45 +01:00
Leah Rowe
0e97e98fe1 trees: explicitly set mode for -b
doing nothing means that if a flag is passed, and then
another flag overriding it, the resulting action will
not be correct; only one flag should be provided anyway,
but some users may feel a bit more adventurous.

mitigate it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:31:54 +01:00
Leah Rowe
7f7b640d3a roms: re-add compression of coreboot images
i accidentally removed this feature, during prior cleanup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:05:29 +01:00
Leah Rowe
1ab9189cbd roms: build coreboot *after* checking variables
otherwise, release=n is ignored and an image is built in
the elf/ directory, even if it's still skipped for bin/

avoid doing unnecessary work per-release by checking the
variables before building coreboot via script/trees

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 09:54:22 +01:00
Leah Rowe
2b4c6ee5ca lib.sh: introduce mandatory check of projectname
error out if it's not set. ditto projectsite.

that way, if the files are accidentally deleted, or not
added in a derivative of the build system, you'll know.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:24:59 +01:00
Leah Rowe
c79fb125eb lib.sh: condense setvars() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:22:42 +01:00
Leah Rowe
1387dc0ae2 simplified lock message
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:20:06 +01:00
Leah Rowe
20ac7ec67b lib.sh: simplify reading of version files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:18:12 +01:00
Leah Rowe
4e48fa808e lib.sh: simplify use of environment variables
don't have a separate variable for them.

just export them directly and use them directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:12:18 +01:00
Leah Rowe
b4fb251008 roms main(): confirm what serprog images are built
just like we do for coreboot images, do it for serprog.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:39:53 +01:00
Leah Rowe
5e2308ce05 roms: remove unused variable name
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:35:32 +01:00
Leah Rowe
2960abd008 roms: remove redundant printf
we don't need this message here, because the final confirmation
at the end of main() says which targets were built. saying what
individual rom images were built is just needless bloat,
especially with the new simplified lbmk design; we no longer
provide lots of rom images with different keymaps, because we
now expect the user to insert a gkb file themselves with cbfstool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:32:18 +01:00
Leah Rowe
c661eca6b9 roms: optimise u-boot elf check
because we use crossgcc here, blindly running trees -f
means needlessly re-running buildgcc, which then checks
for gcc binaries, even though we already know that the
u-boot binary exists. skip this check if u-boot exists.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:30:48 +01:00
Leah Rowe
8af9f904c4 roms: simplify build_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:24:50 +01:00
Leah Rowe
c9f26dbc94 roms: make the bin/elf message more polite
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:42:58 +01:00
Leah Rowe
9484eda5a7 roms: re-add final confirmation of targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:41:43 +01:00
Leah Rowe
2b7df7ab2c roms: rename functions for extra clarity
the names of these functions do not match their true
intent. fix that by renaming them appropriately.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:35:44 +01:00
Leah Rowe
6753222d0e roms: build coreboot early to avoid duplicate work
we're building it per coreboot configuration file, rather
than per-target; the latter is more appropriate, and saves
on compilation time.

do it per-target.cfg, not per coreboot configuration.

this works because the trees script compiles all images
per target, for each given coreboot configuration within
that target, e.g. libgfxinit _corebootfb and _txtmode.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:28:25 +01:00
Leah Rowe
19e7c1eabb trees: try xgcc build twice if first attempt fails
sometimes buildgcc just fails for like no reason. we had this
the other day and another fix was made to the trees script, to
mitigate; the user ran it again and buildgcc worked just fine.

run it twice, and then call err only if the second one fails.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 14:23:56 +01:00
Leah Rowe
6468bdb3aa trees: don't check if xgcc is already built
just run the make crossgcc command anyway.
coreboot's own build system checks itself, and much
more reliably, but the check is more thorough and a bit
slower.

in rare cases, lbmk may come into build issues with xgcc,
and if you run the build again, it will always fail every
time because the checks is based on whether the xgcc
directory exists, rather than checking each
individual crossgcc binary.

checking every binary is also possible, but as i said,
the coreboot build system already does that, so let's defer
to coreboot's own handling of it.

remove the directory check. this will slow down the build
process a little bit, but should improve reliability under
fault conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 17:24:28 +01:00
Leah Rowe
d5baaff0ec lib.sh: fix error running ./build dependencies
the e() and setvars() functions need to be declared before
the dependencies function.

also: after calling install_packages, it was doing a return
when it should have done an exit.

this is all fixed now. i apologise to anyone who previously
ran into trouble with this!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 12:34:26 +01:00
Leah Rowe
0158a08111 roms: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 01:10:11 +01:00
Leah Rowe
e67cd17164 roms: only support SeaBIOS/SeaGRUB on x86
Never, ever build images where GRUB is the primary payload.

These options have been removed from target.cfg handling:

* seabios_withgrub
* grub_withseabios

The "payload_grub" variable now does the same thing as
the old "seabios_withgrub" variable, if set.

The "grubonly" configuration is retained, and enabled by
default when SeaGRUB is enabled (non-grubonly also available).

Due to lbmk issue #216, it is no longer Libreboot policy to
make GRUB the primary payload on any board. GRUB's sheer size
and complexity, plus the large number of memory corruption issues
similar to it that *have* been fixed over the years, tells me
that GRUB is a liability when it is the primary payload.

SeaBIOS is a much safer payload to run as primary, on x86, due
to its smaller size and much more conservative development; it
is simply far less likely to break.

If GRUB breaks in the future, the user's machine is not
bricked. This is because SeaBIOS is the default payload.

Since I no longer wish to ever provide GRUB as a primary
payload, supporting it in lbmk adds needless bloat that
will later probably break anyway due to lack of testing,
so let's just assume SeaGRUB in all cases where the user
wants to use a GRUB payload.

You can mitigate potential security issues with SeaBIOS
by disabling option ROM execution, which can be done at
runtime by inserting integers into CBFS. The SeaBIOS
documentation says how to do this.

Libreboot's GRUB hardening guide still says how to add
a bootorder file in CBFS, making SeaBIOS only load GRUB
from CBFS, and nothing else. This, combined with the
disablement of option ROM execution (if using Intel
graphics), pretty much provides the same security benefits
as GRUB-as-primary, for example when setting a GRUB password
and GPG checks, with encrypted /boot as in the hardening guide.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 22:57:39 +01:00
Leah Rowe
71137b12b4 roms: remove support for "grubonly" seabios
due to lbmk issue #216, it is now unwise to use grub as the
primary payload on any machine; the sheer complexity of grub
and the number of memory corruption bugs that have been fixed
due to auditing over the years, means more such bugs exist.

we now provide seabios as the primary payload on all x86 ports,
but provide a "grubfirst" configuration where a bootorder file
in seabios can be added via cbfs, which tells seabios to load
grub from cbfs first, while still allowing use of the boot select
menu by pressing esc in seabios.

well, the "grubonly" option also disables the seabios esc menu,
so that *only* grub runs. there is no point in using this unless
you want to harden your setup, for example if you want to set up
encrypted /boot and boot that from grub, and have a grub password
disallowing unauthorised bootup of your machine.

see grub hardening guide;
https://libreboot.org/docs/linux/grub_hardening.html

at least as of today, 22 June 2024, that page already says
how to manually disable the seabios menu in the same way, if that
is the setup you want. alternatively, a user may be wily
enough to edit target.cfg for their board and compile a rom
that only has the grub payload in it, if that is what the user
wishes to do.

regardless, the default configurations provided by lbmk must never
be unsafe, norc should the build system support such unsafe
settings;

yes, grub as primary payload is technically still supported in
lbmk. actually, at the time of this revision, i have half a mind
to remove that functionality altogether, so that only seabios is
allowed as primary payload, when compiling a rom image that also
has grub, chainloading grub from the seabios menu instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 21:44:49 +01:00
Leah Rowe
d4d5d2902c use backticks on eval commands, not subshells
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:46:20 +01:00
Leah Rowe
c1527b6114 lib.sh: remove badcmd()
it's bloat. telling the user to rtfm is something that
we already do on irc; they will still ask how to do
everything, and ignore the message from badcmd(), or
they will automatically know to rtfm.

i'm on a massive purge, removing bloat from lbmk as
part of Libreboot Build System Audit 6.

all bloat must go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:46:20 +01:00
Leah Rowe
fc7ae3e590 lib.sh: more unified config handling
replace it with logic that simply uses "." to load
files directly. for this, "vcfg" is added as a variable
in coreboot target.cfg files, referring to a directory
in config/vendor/ containing a file named pkg.cfg, and
this file then contains the same variables as the
erstwhile config/vendor/sources

config/git files are now directories, also containing
pkg.cfg files each with the same variables as before,
such as repository link and commit hash

this change results in a noticeable reduction in code
complexity within the build system.

unified reading of config files: new function setcfg()
added to lib.sh

setcfg checks if a config exists. if a 2nd argument is
passed, it is used as a return value for eval, otherwise
a string calling err is passed. setcfg output is passed
through eval, to set strings based on config; eval must
be used, so that the variables are set within the same
scope, otherwise they'd be set within setcfg which could
lead to some whacky results.

there's still a bit more more to do, but this single change
results in a substantial reduction in code complexity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:44:27 +01:00
Leah Rowe
ad1602569e trees: more robust check to avoid "make fetch"
do not use shorthand here. the test was failing to
produce the desired result under some circumstances,
for example when i did "./update release" i got this:

make: Entering directory '/home/lbdev/lbmk/release/20240612-62-ga6b1a6bd/libreboot-20240612-62-ga6b1a6bd_src/src/stm32-vserprog'
make: *** No rule to make target 'fetch'.  Stop.
make: Leaving directory '/home/lbdev/lbmk/release/20240612-62-ga6b1a6bd/libreboot-20240612-62-ga6b1a6bd_src/src/stm32-vserprog'
ERROR script/trees: !mk src/stm32-vserprog fetch
ERROR ./update: excmd: script/trees -f
ERROR script/roms: Unhandled non-zero exit: ./update
ERROR ./build: excmd: script/roms serprog
ERROR ./update: build_release release/20240612-62-ga6b1a6bd: stm32
ERROR ./update: can't build rom images

in the above circumstance, run_make_command was executed,
which is not the desired behaviour; rather, fetch_project_trees
or fetch_project_repo should be called, and then the script
should immediately exit. it should also exit, without downloading
anything, if a changelog file exists as in release archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-21 03:10:46 +01:00
Leah Rowe
a6b1a6bddb roms: fix lack of backslash on multi-line command
Signed-off-by: Leah Rowe <info@minifree.org>
2024-06-20 22:39:28 +01:00
Leah Rowe
8c4a918500 vendor.sh: more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 04:04:42 +01:00
Leah Rowe
4711296841 Revert "roms: remove build_payloads() and split it up"
This reverts commit 3610667e3d.

The output of some functions in the roms script are used as
an argument in cp and mv commands, also cbfstool. I overlooked
this fact in a previous code optimisation.

Revert it. The change only reduced sloccount by a few lines
anyway.
2024-06-20 02:58:59 +01:00
Leah Rowe
5a4fc97c63 vendor.sh: correction (s/scancfg/scan_config)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 02:07:35 +01:00
Leah Rowe
d65e4fac1d git.sh: revert modification to for loop
i tried to be clever with this one, but it just made
the script exit with an error.

revert back to the old check (check whether one of
either repo or repo backup is set)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:42:10 +01:00
Leah Rowe
bc61c39ec8 vendor.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:23:37 +01:00
Leah Rowe
808458ced5 minor code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:15:06 +01:00
Leah Rowe
4ab99d546e git.sh: general code cleanup in fetch_submodule()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:57:10 +01:00
Leah Rowe
cd1d847898 git.sh: reduced indentation on repo/file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:51:04 +01:00
Leah Rowe
4f6dda1366 git.sh: simplified repo/backup check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:46:51 +01:00
Leah Rowe
185d76f57e roms: merge mkserprog() into main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:46:43 +01:00
Leah Rowe
893e88bc81 roms: don't insert timeout.cfg
this is bloat, because it's something the user can already
do at runtime configuration anyway.

set it to a reasonable default of 8 seconds instead of 5,
and don't honour the timeout variable in target.cfg.

this will be documented in the next release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:32:42 +01:00
Leah Rowe
abfc799fd5 correction
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:20:09 +01:00
Leah Rowe
a0da8fdef1 roms: reduce indentation in build_grub_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:11:54 +01:00
Leah Rowe
383433d4f6 roms: re-introduce accidentally disabled check
i disabled a check in the script, while testing a prior
modification. re-introoduce the check, which is put there
to yield an error condition if no targets were compiled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 01:29:26 +01:00
Leah Rowe
3610667e3d roms: remove build_payloads() and split it up
payloads are compiled before coreboot, but it doesn't matter
to the build speed whether this is done first.

reduce the lines of code by checking payload builds *while*
adding them to the coreboot images. this means that coreboot
is now compiled first, before the payloads.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:42:01 +01:00
Leah Rowe
29a7123c0c roms: group some commands that are similar
this makes the build_payloads() function nicer to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:06:36 +01:00
Leah Rowe
2d6946775e roms: remove mt86bin variable
it's only meaningfully used once, so just hardcode
the string, which is not set dynamically anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:03:16 +01:00
Leah Rowe
920e5ba2d9 roms: merge build_uboot_payload to build_payloads
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 23:56:39 +01:00
Leah Rowe
a96c4b59fd roms: simplify payload_uboot y/n check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 23:49:28 +01:00
Leah Rowe
28682b1a4b roms: simplify the check for serprog srcdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:15:25 +01:00
Leah Rowe
b61dd4c258 roms: simplify the loop for building serprog roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:09:26 +01:00
Leah Rowe
6df17860e2 roms: shorten variable serprog_boards_dir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:00:47 +01:00
Leah Rowe
ea5b5b0720 roms: simplified serprog image copy
use eval to avoid having two mv commands

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:50:40 +01:00
Leah Rowe
ea9bdfce4b roms: rename picosrc variable to rp2040src
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:44:25 +01:00
Leah Rowe
1a4f97ffd1 roms: remove useless confirmation in mkserprogfw
the user knows where to look. replace it with a single
declaration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:22:48 +01:00
Leah Rowe
1881d34dbc roms: merge serprog build into one function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:20:40 +01:00
Leah Rowe
f7e28964ac roms: remind the user about gkb files
nowadays, we don't insert GRUB keymaps automatically, for
sake of efficiency; without one, the default is US QWERTY.

a user will only want one keymap in particular, so this
is more efficient. in practise, they're either building
from source anyway, or using the inject scripts which
compile cbfstool anyway, so the user will already have
cbfstool.

also output this message from the inject script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-17 15:50:22 +01:00
Leah Rowe
f928ac5c70 roms: rename x variable to it in for loop
there are two for loops that use x as a variable anme,
and an idiosyncrasy of certain sh implementations is
that these become global;

the result in this case was that when you finish building
every target in "./build roms", it would print "libgfxinit"
repeatedly, comma separated, instead of a comma-separated
list of the targets that were built.

work around it by renaming the variable in one of the loops.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-17 01:05:28 +01:00
Leah Rowe
58a451865b roms: don't use x_ to call cproms()
cproms() never returns non-zero, so it doesn't make
sense to use x_ here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:56:41 +01:00
Leah Rowe
bc853fbb89 roms build_uboot_roms(): move rom, don't copy
that way, we don't have to delete the temporary file.
just move it entirely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:50:42 +01:00
Leah Rowe
12b26f207f roms cproms(): allow other commands besides cp
e.g. the operator might specify mv instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:50:13 +01:00
Leah Rowe
e67628c6a5 unify coreboot elfdir (DO_NOT_FLASH)
use a common string when setting this path

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:46:58 +01:00
Leah Rowe
8b58c1eac6 roms: merge mkUbootRom() into build_uboot_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:42:34 +01:00
Leah Rowe
c3f0a109c3 roms: simplify mkSeabiosRom()
remove variables that are not meaningfully used

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:54:07 +01:00
Leah Rowe
c8944f1ca8 roms: simplify mkUbootRom()
remove variables that are not meaningfully used

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:51:47 +01:00
Leah Rowe
92aa83a236 roms: simplify build_roms()
cbcfg is already a global variable, so there's no reason
to set it again at the start of this function.

remove the check for whether the given coreboot config
exists, to the calling function instead of build_roms().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:46:03 +01:00
Leah Rowe
d3e7886450 roms: remove unnecessary check
uboot_config is later only used if payload_uboot is set

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:42:57 +01:00
Leah Rowe
ef411c596a build: remove unused variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:38:47 +01:00
Leah Rowe
6dc0515583 roms: further clean up build_grub_roms()
the tmpcfg variable will be useful elsewhere, for
the same kind of change as before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:11:46 +01:00
Leah Rowe
0e9b36c581 roms: simplify timeout/scandisk insertion
we don't need to call mktemp everytime.
just use a staticly named file in tmpdir
and keep overwriting it.

these files are only small, and they get deleted
when the build system exits later on.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:08:40 +01:00
Leah Rowe
3a7b3660f9 roms: simplify seagrub check in build_grub_roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:05:28 +01:00
Leah Rowe
4b764d26fd roms: simplify mkserprog()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:53:21 +01:00
Leah Rowe
167e7447a5 roms: simplify the serprog build functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:48:36 +01:00
Leah Rowe
7bc9fcc342 script/roms: fix serprog build commands
forgot to shift

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:40:57 +01:00
Leah Rowe
0dfe3aed91 roms: simplified ubootelf check
we check it twice, which we don't need to do.

we only need to check it once!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:58:27 +01:00
Leah Rowe
a9166898d2 roms: simplify grubonly check in configure_target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:43:02 +01:00
Leah Rowe
90017cdc56 roms: simplify seagrub check in configure_target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:38:19 +01:00
Leah Rowe
817004e151 roms: don't use x_ to call build_grub_roms
build_grub_roms never returns a non-zero value

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:31:26 +01:00
Leah Rowe
0812d53212 trees: simplify copy_elf()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe
331c4097ff trees: remove unnecessary check in copy_elf
we don't need to check whether this variable is set,
because checking an empty path will also cause the
same return in the next line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe
340eea0b1c grub: insert background in memdisk instead
the background is only a few kb. the whole rationale
before was to limit the space used in memdisk, but this
decision was made when the background was much bigger;
it has since been optimised greatly, and the grub modules
were heavily reduce, so it should be safe.

grub's memdisk breaks when you add too much data to it.
as part of simplifying the rest of lbmk, this change removes
some more bloat from the rest of lbmk. handling this in the
memdisk is much simpler than handling it with cbfstool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe
ed9c90e59d roms: unify all add-payload commands
add a generic function that can insert payloads with lzma
compression, or raw files without compression

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:25 +01:00
Leah Rowe
26451775d5 roms: don't add grub keymaps at all
if not inserted, the default keymap is usqwerty.

don't waste ssd write cycles copying so many images,
or cpu time compressing so many. the user can simply
add a keymap.gkb file to cbfs and it will work fine.

this will be documented in the next release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 18:35:20 +01:00
Leah Rowe
af8296ce6b roms: merge handle_coreboot_target into main()
rely on return status per each of the three main rom
functions, to then update the "targets" variable.

use this as the basis to determine which targets were
built, during final confirmation when the script exits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 16:34:05 +01:00
Leah Rowe
d1c0c34642 roms: simplify target check (whether roms built)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 16:26:49 +01:00
Leah Rowe
f626b25db3 roms: simplify main() again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:30 +01:00
Leah Rowe
eb9a688ee3 roms: remove redundant check on grub_scan_disk
the current validation check is extremely over-engineered,
because the user override is no longer available and we're
always very careful in how we modify target.cfg per board.

remove the redundant code. trust that target.cfg is correct.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:30 +01:00
Leah Rowe
a4328cb11f roms: remove dangerous runtime p/s/d options
p = payload

s = grub_scan_disk

d = displaymode

setting the payload is no longer safe, due to issue 216
and similar issues that might pop up in the future; it's
best left only to target.cfg, per board, so that we know
what config is safe/tested. don't let the user override it.

scandisk isn't safe to override because the given machine
may not have the type of device that the user specifies

displaymode is actually ok to set, because it simply whitelists
what configs pre-existing to actually use, but it's bloat

basically, the rule is this:

don't make it easy for the user to brick their hardware.
make it harder instead.

a user wily enough to go modifying their payload will probably
have read docs/maintain/ anyway and knows how to edit target.cfg
if they want another board configuration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:27 +01:00
Leah Rowe
167e1a0fbe unified checks for variable initialisation
new function chkvars() does the job

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 13:37:03 +01:00
Leah Rowe
98724d701b lib.sh: remove the items() function
it's pretty much just doing the same thing as ls -1

remove it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 13:19:25 +01:00
Leah Rowe
baea03c672 roms: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 09:11:07 +01:00
773 changed files with 51944 additions and 38928 deletions

13
.gitignore vendored
View file

@ -1,6 +1,8 @@
*~
*.o
/cache/
/lbmk.err.log
/repo/
/docs/
/pciroms/
/util/dell-flash-unlock/dell_flash_unlock
@ -22,6 +24,8 @@
/push
/version
/versiondate
/.version
/.versiondate
/vendorfiles/
*me.bin
*sch5545ec.bin
@ -31,3 +35,12 @@
/CHANGELOG
/todo.txt
/lock
/hash/
/dump/
/qrun*.sh
*.tar.*
/m
/f
/r
/e
/xbmkpath/

144
README.md
View file

@ -1,123 +1,57 @@
Libreboot
=========
Find libreboot documentation at <https://libreboot.org/>
Documentation: [libreboot.org](https://libreboot.org)\
Support: [\#libreboot](https://web.libera.chat/#libreboot) on
[Libera](https://libera.chat/) IRC
The `libreboot` project provides
[libre](https://libreboot.org/freedom-status.html) *boot
firmware* that initializes the hardware (e.g. memory controller, CPU,
peripherals) on specific Intel/AMD x86 and ARM targets, which
then starts a bootloader for your operating system. Linux/BSD are
well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
via [\#libreboot IRC](https://web.libera.chat/#libreboot)
on [Libera](https://libera.chat/) IRC.
Libreboot provides
[libre](https://libreboot.org/freedom-status.html)
boot firmware on
[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
* ... which loads your operating system's boot loader (BSD and Linux-based
[systems](systems) are supported).
Why use Libreboot?
==================
Why use Libreboot, and what is coreboot?
----------------------------------------
Why should you use *libreboot*?
----------------------------
A lot of users who use libre operating systems still use proprietary boot
firmware, which often contain backdoors and bugs, hampering
[user freedom](https://writefreesoftware.org) and
[right to repair](https://www.eff.org/issues/right-to-repair).
Libreboot gives you freedoms that you otherwise can't get with most other
boot firmware. It's extremely powerful and configurable for many use cases.
[coreboot](https://coreboot.org) provides libre boot firmware by initializing
the hardware then running a payload. However, coreboot is notoriously difficult
to configure and install for most non-technical users, requiring detailed
technical knowledge of hardware.
You have rights. The right to privacy, freedom of thought, freedom of speech
and the right to read. In this context, Libreboot gives you these rights.
Your freedom matters.
[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
Many people use proprietary (non-libre)
boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
Proprietary firmware often contains backdoors (more info on the FAQ), and it
and can be buggy. The libreboot project was founded in December 2013,
with the express purpose of making coreboot firmware accessible for
non-technical users.
Libreboot solves this by being **a coreboot distribution** (in the same way
that Alpine Linux is a Linux distribution). It provides a fully automated build
system that downloads and compiles pre-configured ROM images for supported
motherboards, so end-users could easily fetch images to flash onto their
devices.
The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
initialisation](https://doc.coreboot.org/getting_started/architecture.html).
Coreboot is notoriously difficult to install for most non-technical users; it
handles only basic initialization and jumps to a separate
[payload](https://doc.coreboot.org/payloads.html) program (e.g.
[GRUB](https://www.gnu.org/software/grub/),
[Tianocore](https://www.tianocore.org/)), which must also be configured.
*The libreboot software solves this problem*; it is a *coreboot distribution* with
an automated build system (named *lbmk*) that builds complete *ROM images*, for
more robust installation. Documentation is provided.
Libreboot also produces documentation aimed at non-technical users and
excellent user support via IRC.
How does Libreboot differ from coreboot?
========================================
In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
a *coreboot distribution*. If you want to build a ROM image from scratch, you
otherwise have to perform expert-level configuration of coreboot, GRUB and
whatever other software you need, to prepare the ROM image. With *libreboot*,
you can literally download from Git or a source archive, and run `make`, and it
will build entire ROM images. An automated build system, named `lbmk`
(Libreboot MaKe), builds these ROM images automatically, without any user input
or intervention required. Configuration has already been performed in advance.
If you were to build regular coreboot, without using libreboot's automated
build system, it would require a lot more intervention and decent technical
knowledge to produce a working configuration.
Regular binary releases of `libreboot` provide these
ROM images pre-compiled, and you can simply install them, with no special
knowledge or skill except the ability to follow installation instructions
and run commands BSD/Linux.
Project goals
=============
- *Support as much hardware as possible!* Libreboot aims to eventually
have *maintainers* for every board supported by coreboot, at every
point in time.
- *Make coreboot easy to use*. Coreboot is notoriously difficult
to install, due to an overall lack of user-focused documentation
and support. Most people will simply give up before attempting to
install coreboot. Libreboot's automated build system and user-friendly
installation instructions solves this problem.
Libreboot attempts to bridge this divide by providing a build system
automating much of the coreboot image creation and customization.
Secondly, the project produces documentation aimed at non-technical users.
Thirdly, the project attempts to provide excellent user support via IRC.
Libreboot already comes with a payload (GRUB), flashprog and other
needed parts. Everything is fully integrated, in a way where most of
the complicated steps that are otherwise required, are instead done
for the user in advance.
You can download ROM images for your libreboot system and install
them without having to build anything from source. If, however, you are
interested in building your own image, the build system makes it relatively
easy to do so.
Not a coreboot fork!
--------------------
Libreboot is not a fork of coreboot. Every so often, the project
re-bases on the latest version of coreboot, with the number of custom
patches in use minimized. Tested, *stable* (static) releases are then provided
in Libreboot, based on specific coreboot revisions.
How to help
===========
Contribute
----------
You can check bugs listed on
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
If you spot a bug and have a fix, the website has instructions for how to send
patches, and you can also report it. Also, this entire website is
written in Markdown and hosted in a [separate
repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
You may use Codeberg pull requests to send patches with bug fixes or other
improvements. This repository hosts the code for the main build system.
The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
Any and all development discussion and user support are all done on the IRC
channel. More information is on <https://libreboot.org/contact.html>.
Development is also done on the IRC channel.
LICENSE FOR THIS README
=======================
License for this README
-----------------------
It's just a README file. This README file is released under the terms of the
Creative Commons Zero license, version 1.0 of the license, which you can
read here:
It's just a README file. It is released under
[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>

143
build
View file

@ -1,143 +0,0 @@
#!/usr/bin/env sh
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
set -u -e
if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
printf "You must run this in the proper work directory.\n" 1>&2
exit 1
fi
. "include/lib.sh"
. "include/vendor.sh"
. "include/mrc.sh"
eval "$(setvars "" vdir src_dirname srcdir _xm mode xp)"
err="fail"
linkpath="${0}"
linkname="${linkpath##*/}"
main()
{
[ $# -lt 1 ] && badcmd
spath="script/$1"
for g in "which git" "git config --global user.name" \
"git config --global user.email" "git_init"; do
eval "$g 1>/dev/null 2>/dev/null || git_err \"$g\""
done
case "${1}" in
version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
release) shift 1; mkrelease $@ ;;
inject) shift 1; vendor_inject $@ ;;
download) shift 1; vendor_download $@ ;;
*)
[ -f "$spath" ] || badcmd
shift 1; "$spath" $@ || $err "excmd: $spath $@" ;;
esac
set -u -e # some commands disable them. turn them on!
}
git_init()
{
[ -L ".git" ] && return 1
[ -e ".git" ] && return 0
eval "$(setvars "$(date -Rud @$versiondate)" cdate _nogit)"
git init || return 1
git add -A . || return 1
git commit -m "$projectname $version" --date "$cdate" \
--author="xbmk <xbmk@example.com>" || return 1
git tag -a "$version" -m "$projectname $version" || return 1
}
mkrelease()
{
export XBMK_RELEASE="y"
vdir="release"
while getopts d:m: option; do
[ -z "$OPTARG" ] && badcmd "empty argument not allowed"
case "$option" in
d) vdir="$OPTARG" ;;
m) mode="$OPTARG" ;;
*) badcmd "invalid option '-$option'" ;;
esac
done
vdir="$vdir/$version"
src_dirname="${relname}_src"
srcdir="$vdir/$src_dirname"
[ -e "$vdir" ] && $err "already exists: \"$vdir\""
mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
build_release
printf "\n\nDONE! Check release files under %s\n" "$vdir"
}
build_release()
{
_xm="build_release $vdir"
(
cd "$srcdir" || $err "$_xm: !cd \"$srcdir\""
fetch_trees
x_ mv src/docs docs
) || $err "can't create release files"
git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
--abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
(
cd "${srcdir%/*}" || $err "$_xm: mktarball \"$srcdir\""
mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$_xm: mksrc"
) || $err "can't create src tarball"
[ "$mode" = "src" ] && return 0
touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
(
cd "$srcdir" || $err "$_xm: 2 !cd \"$srcdir\""
./build roms all || $err "$_xm: roms-all"
./build roms serprog rp2040 || $err "$_xm: rp2040"
./build roms serprog stm32 || $err "$_xm: stm32"
x_ mv bin ../roms
) || $err "can't build rom images"
rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
}
fetch_trees()
{
for x in $(items config/git); do
./update trees -f "$x" || $err "$_xm: fetch $x"
singletree "$x" || x_ rm -Rf "src/$x/$x"
done
rmgit .
}
fail()
{
tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$tmpdir" 1>&2
err_ "${1}"
}
tmp_cleanup()
{
[ "$tmpdir_was_set" = "n" ] || return 0
rm -Rf "$tmpdir" || return 1
rm -f lock || return 1
}
main $@
tmp_cleanup || err_ "can't rm tmpdir upon non-zero exit: $tmpdir"

View file

@ -1,56 +0,0 @@
From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.huber@secunet.com>
Date: Tue, 22 Jun 2021 13:49:44 +0000
Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
util/cbfstool/common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index e2ed38ffc4..539d0baccf 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -168,10 +168,10 @@ void print_supported_architectures(void)
void print_supported_filetypes(void)
{
- int i, number = ARRAY_SIZE(filetypes);
+ int i;
- for (i=0; i<number; i++) {
- printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
+ for (i=0; filetypes[i].name; i++) {
+ printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
if ((i%8) == 7)
printf("\n");
}
@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
uint64_t intfiletype(const char *name)
{
size_t i;
- for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
+ for (i = 0; filetypes[i].name; i++)
if (strcmp(filetypes[i].name, name) == 0)
return filetypes[i].type;
return -1;
--
2.39.2

View file

@ -1,2 +0,0 @@
tree="coreboot413"
rev="5c186c6777c9438ff4681929c9c25c98dee28bef"

View file

@ -6,19 +6,19 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -55,10 +54,11 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@ -67,23 +67,30 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@ -93,6 +100,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -103,7 +111,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@ -119,22 +129,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@ -150,8 +164,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -159,7 +171,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -178,6 +192,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@ -193,6 +208,11 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@ -200,17 +220,19 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -250,6 +272,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -258,13 +281,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
@ -293,6 +316,8 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -347,6 +372,8 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
# CONFIG_GOOGLE_PVMFW_CBMEM is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@ -370,6 +397,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@ -386,6 +417,7 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
@ -419,6 +451,7 @@ CONFIG_USE_DDR2=y
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@ -436,6 +469,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@ -457,6 +491,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -509,7 +545,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -584,7 +619,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@ -598,6 +632,13 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y

View file

@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_memtest="y"
release="n"
build_depend="seabios/default memtest86plus"

View file

@ -6,19 +6,19 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@ -37,7 +37,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -55,10 +54,11 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@ -67,23 +67,30 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@ -93,6 +100,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -103,7 +111,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@ -119,22 +129,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@ -150,8 +164,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -159,7 +171,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -178,6 +192,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@ -193,6 +208,11 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@ -200,17 +220,19 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -250,6 +272,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -258,13 +281,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
@ -293,6 +316,8 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -347,6 +372,8 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
# CONFIG_GOOGLE_PVMFW_CBMEM is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@ -370,6 +397,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@ -386,6 +417,7 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
@ -419,6 +451,7 @@ CONFIG_USE_DDR2=y
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@ -436,6 +469,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@ -457,6 +491,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -509,7 +545,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -584,7 +619,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@ -598,6 +632,13 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y

View file

@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_seabios_withgrub="y"
payload_grub="y"
payload_memtest="y"
release="n"

View file

@ -6,19 +6,19 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@ -37,7 +37,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -55,10 +54,11 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@ -67,23 +67,30 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@ -93,6 +100,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -103,7 +111,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@ -119,23 +129,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@ -151,8 +165,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -160,7 +172,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -179,6 +193,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@ -194,6 +209,11 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@ -201,15 +221,17 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
@ -249,6 +271,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -257,13 +280,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
@ -292,6 +315,8 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -346,6 +371,8 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
# CONFIG_GOOGLE_PVMFW_CBMEM is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@ -369,6 +396,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@ -385,6 +416,7 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
@ -414,6 +446,7 @@ CONFIG_USE_DDR2=y
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@ -431,6 +464,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@ -451,6 +485,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -503,7 +539,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -582,7 +617,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@ -597,6 +631,13 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y

View file

@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
release="n"
build_depend="seabios/default"

View file

@ -6,19 +6,19 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@ -37,7 +37,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@ -55,10 +54,11 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@ -67,23 +67,30 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@ -93,6 +100,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@ -103,7 +111,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@ -119,23 +129,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@ -151,8 +165,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@ -160,7 +172,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@ -179,6 +193,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@ -194,6 +209,11 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@ -201,15 +221,17 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@ -249,6 +271,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@ -257,13 +280,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
@ -292,6 +315,8 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@ -346,6 +371,8 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
# CONFIG_GOOGLE_PVMFW_CBMEM is not set
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@ -369,6 +396,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@ -385,6 +416,7 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
@ -414,6 +446,7 @@ CONFIG_USE_DDR2=y
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@ -431,6 +464,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@ -451,6 +485,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@ -503,7 +539,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@ -582,7 +617,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@ -597,6 +631,13 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y

View file

@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_seabios_withgrub="y"
payload_grub="y"
release="n"
build_depend="seabios/default grub/default"

View file

@ -0,0 +1,19 @@
3rdparty/fsp/EagleStreamFspBinPkg
3rdparty/fsp/AlderLakeFspBinPkg
3rdparty/fsp/MeteorLakeFspBinPkg
3rdparty/fsp/IceLakeFspBinPkg
3rdparty/fsp/AmberLakeFspBinPkg
3rdparty/fsp/DenvertonNSFspBinPkg
3rdparty/fsp/TigerLakeFspBinPkg
3rdparty/fsp/CedarIslandFspBinPkg
3rdparty/fsp/ElkhartLakeFspBinPkg
3rdparty/fsp/CometLakeFspBinPkg
3rdparty/fsp/WhitleyFspBinPkg
3rdparty/fsp/ArrowLakeFspBinPkg
3rdparty/fsp/IdavilleFspBinPkg
3rdparty/fsp/BraswellFspBinPkg
3rdparty/fsp/CoffeeLakeFspBinPkg
3rdparty/fsp/RaptorLakeFspBinPkg
3rdparty/fsp/ApolloLakeFspBinPkg
3rdparty/fsp/SkylakeFspBinPkg
3rdparty/vboot/tests

View file

@ -1,7 +1,7 @@
From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
From bd959c38f6ee21db1ff8f4fbb0675e38bfbe1147 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@ -10,10 +10,10 @@ Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 5f5ffde588..27377b737c 100644
index 330d8efae2..cf10343554 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
end
end
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
src/mainboard/apple/macbook21/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index cf1bc4566e..dc0df3b6d6 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -5,4 +5,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
From e5eab4c8043b89a325b4a28bf7da456d68475144 Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
Subject: [PATCH 02/37] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
register "sata_traffic_monitor" = "0"
--
2.39.2
2.39.5

View file

@ -1,7 +1,7 @@
From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
From fd398cc10600cccce3dd4931651a5294ffebde9a Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
Subject: [PATCH 03/37] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@ -23,16 +23,15 @@ Date: Thu Nov 21 21:47:31 2019 +0300
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 2e315d4521..3585cbd58b 100644
index 732e214b32..8454f0eac0 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -15,5 +15,5 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
gfx_uma_size=224M
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
src/mainboard/lenovo/x60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 5c3576d1f3..88170a1aab 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

View file

@ -1,22 +0,0 @@
From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index af865f16da..7f03157df7 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
From 74230d8123cb7c31afd084658720084b1a5ac5d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
Subject: [PATCH 04/37] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@ -20,103 +20,105 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
index 681c40e78b..57cdcf9162 100644
index be08e0a342..b8970efa46 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index 8244071b8a..c011867916 100644
index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index 8244071b8a..c011867916 100644
index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 26795fe5cf..55e1e6c04e 100644
index c896eadec1..6d1e172056 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
index 52dbf70377..b16800ca9e 100644
index 286fb0ae8c..5a05c73721 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
@@ -16,4 +16,4 @@ backlight=Both
@@ -18,4 +18,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index cf79b391e2..b66f7034dc 100644
index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index cf79b391e2..b66f7034dc 100644
index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 6d1d57a795..52f303dfdb 100644
index ef706c1303..b318ab9772 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -13,4 +13,4 @@ usb_always_on=Disable
@@ -15,4 +15,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
index 62715bc6ba..129b5fd121 100644
index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/protectli/vault_cml/cmos.default
+++ b/src/mainboard/protectli/vault_cml/cmos.default
@@ -1,3 +1,3 @@
@@ -2,4 +2,4 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
index 62715bc6ba..129b5fd121 100644
index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/system76/tgl-u/cmos.default
+++ b/src/mainboard/system76/tgl-u/cmos.default
@@ -1,3 +1,3 @@
@@ -2,4 +2,4 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/t400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
index a326e315b1..b907a3e2df 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -13,4 +13,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
From f592ac32892d7f99fa2e68504bb147e5d06184ca Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region)
Subject: [PATCH 05/37] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@ -16,14 +16,14 @@ Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++-----------
1 file changed, 82 insertions(+), 31 deletions(-)
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
1 file changed, 83 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 516570e0a3..1638e1710e 100644
index b21a89c0e1..fc91d4c239 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2143,6 +2143,7 @@ static void print_usage(const char *name)
@@ -2230,6 +2230,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
@ -31,7 +31,7 @@ index 516570e0a3..1638e1710e 100644
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -2151,6 +2152,60 @@ static void print_usage(const char *name)
@@ -2238,6 +2239,60 @@ static void print_usage(const char *name)
"\n");
}
@ -92,15 +92,15 @@ index 516570e0a3..1638e1710e 100644
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[])
@@ -2245,6 +2300,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0, mode_gpr0_enable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[])
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
char *new_filename = NULL;
@@ -2279,6 +2335,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
@ -108,7 +108,7 @@ index 516570e0a3..1638e1710e 100644
{0, 0, 0, 0}
};
@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[])
@@ -2328,35 +2385,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
@ -146,7 +146,7 @@ index 516570e0a3..1638e1710e 100644
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[])
@@ -2533,6 +2563,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
@ -169,26 +169,27 @@ index 516570e0a3..1638e1710e 100644
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[])
@@ -2552,7 +2598,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- (mode_gpr0_disable | mode_gpr0_enable)) > 1) {
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) {
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
+ mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[])
@@ -2561,7 +2608,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) {
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) +
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
+ mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[])
@@ -2674,6 +2722,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
@ -200,5 +201,5 @@ index 516570e0a3..1638e1710e 100644
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/x200/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
index bb4323836e..458b3f19c5 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -12,4 +12,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
From 18069af7c0c6beedfadb615cca9127e82a0d8007 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
Subject: [PATCH 06/37] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2
2.39.5

View file

@ -1,7 +1,7 @@
From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
From 9563c107a4b40e66b610d7205a21590c7c181c78 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 19/30] Remove warning for coreboot images built without a
Subject: [PATCH 07/37] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
index 5f988dac1b..516133880f 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
@@ -50,16 +50,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
@ -35,5 +35,5 @@ index a2336aa876..4f1692a873 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
index 8372032119..bedad54d2a 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
From 7f650a19d30fe6157b150c5248d6086007323d72 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
Subject: [PATCH 08/37] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index 538d254ace..18e451d63c 100644
index f54c6d22fc..b075abfd42 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
@ -24,5 +24,5 @@ index 538d254ace..18e451d63c 100644
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
2.39.2
2.39.5

View file

@ -1,23 +0,0 @@
From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
index 706f5dd551..e8b45ea22c 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2

View file

@ -1,7 +1,7 @@
From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
From 3f6f65ed6a435fe49534c8a0b5cb98c3eac71150 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 11:41:41 +0000
Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
Subject: [PATCH 09/37] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6430/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
index 2a5b30f2b7..279415dfd1 100644
--- a/src/mainboard/dell/e6430/cmos.default
+++ b/src/mainboard/dell/e6430/cmos.default
--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
@@ -6,4 +6,4 @@ bluetooth=Enable
wwan=Enable
wlan=Enable
@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
-me_state=Normal
+me_state=Disabled
--
2.39.2
2.39.5

View file

@ -1,22 +0,0 @@
From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 7314066c2b..2e315d4521 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.39.2

View file

@ -1,7 +1,7 @@
From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
From b4d48233a8d829d7285501f662d999aad898be21 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 23 Dec 2023 19:02:10 +0200
Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
Subject: [PATCH 10/37] mb/hp: Add Compaq Elite 8300 CMT port
Based on autoport and Z220 SuperIO code.
@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
.../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++
.../hp/compaq_elite_8300_cmt/Kconfig.name | 2 +
.../hp/compaq_elite_8300_cmt/Makefile.inc | 7 +
.../hp/compaq_elite_8300_cmt/Makefile.mk | 7 +
.../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 +
.../compaq_elite_8300_cmt/acpi/platform.asl | 10 +
.../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++
@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
.../hp/compaq_elite_8300_cmt/cmos.default | 7 +
.../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++
.../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes
.../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++
.../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++
.../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++
.../hp/compaq_elite_8300_cmt/early_init.c | 31 +++
.../hp/compaq_elite_8300_cmt/early_init.c | 14 ++
.../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++
src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
.../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++
.../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++
18 files changed, 661 insertions(+)
18 files changed, 660 insertions(+)
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
@ -121,11 +121,11 @@ index 0000000000..bd399b1e76
@@ -0,0 +1,2 @@
+config BOARD_HP_COMPAQ_ELITE_8300_CMT
+ bool "Compaq Elite 8300 CMT"
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
new file mode 100644
index 0000000000..fb492d3583
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
@ -353,10 +353,10 @@ HcmV?d00001
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
new file mode 100644
index 0000000000..f4efabd792
index 0000000000..3d21739b72
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
@@ -0,0 +1,161 @@
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
@ -386,6 +386,22 @@ index 0000000000..f4efabd792
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ register "usb_port_config" = "{
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 }
+ }"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
@ -405,7 +421,7 @@ index 0000000000..f4efabd792
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
+
@ -552,10 +568,10 @@ index 0000000000..e8e2b3a3e5
+}
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
new file mode 100644
index 0000000000..99b7891c70
index 0000000000..8d10c6317c
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
@@ -0,0 +1,31 @@
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
@ -565,23 +581,6 @@ index 0000000000..99b7891c70
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (CONFIG(CONSOLE_SERIAL))
@ -869,5 +868,5 @@ index 0000000000..8dbd95ef96
+ .enable_dev = mainboard_enable,
+};
--
2.39.2
2.39.5

View file

@ -1,7 +1,7 @@
From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001
From a16ff494adb1f706d402a2e167d0d53c775d0897 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 22:51:09 +0000
Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option
Subject: [PATCH 11/37] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless
@ -101,16 +101,16 @@ index c9ba76c78f..95ee3d36fb 100644
checksums
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index cd4046f1ab..c974022472 100644
index 6c4a2a1be7..8000eea8c0 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -3,3 +3,4 @@ boot_option=Fallback
debug_level=Debug
@@ -4,3 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
fan_full_speed=Disable
+iommu=Enable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
index c9ba76c78f..72ff9c4bee 100644
index d10ad95b23..4a1496a878 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -21,6 +21,9 @@ entries
@ -118,12 +118,12 @@ index c9ba76c78f..72ff9c4bee 100644
409 2 e 5 power_on_after_fail
+# turn iommu on or off
+412 1 e 6 iommu
+411 1 e 6 iommu
+
# coreboot config options: check sums
984 16 h 0 check_sum
# coreboot config options: EC
412 1 e 1 fan_full_speed
@@ -52,6 +55,9 @@ enumerations
@@ -55,6 +58,9 @@ enumerations
5 1 Enable
5 2 Keep
@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
if (capid0_a & VTD_DISABLE)
return;
--
2.39.2
2.39.5

View file

@ -1,7 +1,7 @@
From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001
From 4b0536ce7cd55eedc52d13497bea59d91e8924d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 23:00:09 +0000
Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default
Subject: [PATCH 12/37] dell/optiplex_9020: Disable IOMMU by default
Needed to make graphics cards work. Turning it on is
recommended if only using iGPU, otherwise leave it off
@ -15,15 +15,15 @@ Signed-off-by: Leah Rowe <info@minifree.org>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index 8253570f19..7bccc80e51 100644
index 8000eea8c0..0700f971ee 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
@@ -4,4 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
fan_full_speed=Disable
-iommu=Enable
+iommu=Disable
--
2.39.2
2.39.5

View file

@ -1,7 +1,7 @@
From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001
From c8329f84b2d06581dcbeecedc38b7c4715a9cba7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 6 Apr 2024 01:22:47 +0100
Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used
Subject: [PATCH 13/37] nb/haswell: Fully disable iGPU when dGPU is used
My earlier patch disabled decode *and* disabled the iGPU itself, but
a subsequent revision disabled only VGA decode. Upon revisiting, I
@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 48a0ba54c7..f0b848852d 100644
index f7fad3183d..1b188e92e1 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev)
@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
{
/* Disable VGA decode */
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
@ -47,5 +47,5 @@ index 48a0ba54c7..f0b848852d 100644
static struct device_operations gma_func0_ops = {
--
2.39.2
2.39.5

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@ -1,16 +1,37 @@
From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
From 73dbf291631fdbae2d8e8a761c147523c8d9e65c Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 11:03:32 -0600
Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
Subject: [PATCH 14/37] ec/dell/mec5035: Add S3 suspend SMI handler
This is necessary for S3 resume to work on SNB and newer Dell Latitude
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
preventing the system from resuming. These commands were found using an
FPGA to log all LPC bus transactions between the host and the EC and
then narrowing down which ones were actually necessary.
Interestingly, the command IDs appear to be identical to those in
ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
implements a similar S3 SMI handler as the one implemented in this
commit. The Wilco EC Kconfig does suggest that its firmware is a
modified version of Dell's usual Latitude EC firmware, so the
similarities seem to be intentional.
These similarities also identified a command to enable or disable wake
sources like the power button and lid switch, and this was added to the
SMI handler to disable lid wake as the system does not yet resume
properly from a like wake with coreboot.
Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
(Haswell, not yet pushed).
Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/Makefile.mk | 1 +
src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++
src/ec/dell/mec5035/mec5035.h | 19 +++++++++++++++++++
src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++
src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
4 files changed, 51 insertions(+)
4 files changed, 54 insertions(+)
create mode 100644 src/ec/dell/mec5035/smihandler.c
diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
@ -25,35 +46,35 @@ index 4ebdd811f9..be557e4599 100644
endif
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 68b6b2f7fb..33bf046634 100644
index dffbb7960c..85c2ab0140 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
ec_command(CMD_RADIO_CTRL);
}
+void mec5035_sleep_enable(void)
+{
+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
+ ec_command(CMD_SLEEP_ENABLE);
+}
+
+void mec5035_change_wake(u8 source, enum ec_wake_change change)
+{
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
+ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
+ ec_command(CMD_ACPI_WAKEUP_CHANGE);
+}
+
+void mec5035_sleep_enable(void)
+{
+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
+ ec_command(CMD_SLEEP_ENABLE);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index fa15a9d621..069616fbc5 100644
index 32f791cb01..8d4fded28b 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -4,6 +4,7 @@
@@ -4,12 +4,15 @@
#define _EC_DELL_MEC5035_H_
#include <stdint.h>
@ -61,37 +82,46 @@ index fa15a9d621..069616fbc5 100644
#define NUM_REGISTERS 32
@@ -29,9 +30,27 @@ enum ec_radio_state {
enum mec5035_cmd {
CMD_MOUSE_TP = 0x1a,
CMD_RADIO_CTRL = 0x2b,
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
+ CMD_SLEEP_ENABLE = 0x64,
CMD_CPU_OK = 0xc2,
};
@@ -33,9 +36,28 @@ enum ec_radio_state {
RADIO_ON
};
+#define CMD_ACPI_WAKEUP_CHANGE 0x4a
+#define ACPI_WAKEUP_NUM_ARGS 4
+enum ec_wake_change {
+ WAKE_OFF = 0,
+ WAKE_ON
+};
+
+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
+enum ec_acpi_wake_events {
+ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */
+ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */
+ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */
+};
+
+#define CMD_SLEEP_ENABLE 0x64
+#define SLEEP_EN_NUM_ARGS 2
+
u8 mec5035_mouse_touchpad(u8 setting);
u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
+void mec5035_sleep(int slp_type);
+void mec5035_change_wake(u8 source, enum ec_wake_change change);
+void mec5035_sleep_enable(void);
+
+void mec5035_smi_sleep(int slp_type);
#endif /* _EC_DELL_MEC5035_H_ */
diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
new file mode 100644
index 0000000000..1db834773d
index 0000000000..958733bf97
--- /dev/null
+++ b/src/ec/dell/mec5035/smihandler.c
@@ -0,0 +1,17 @@
@ -102,7 +132,7 @@ index 0000000000..1db834773d
+#include <ec/acpi/ec.h>
+#include "mec5035.h"
+
+void mec5035_sleep(int slp_type)
+void mec5035_smi_sleep(int slp_type)
+{
+ switch (slp_type) {
+ case ACPI_S3:
@ -113,5 +143,5 @@ index 0000000000..1db834773d
+ }
+}
--
2.44.0
2.39.5

View file

@ -1,7 +1,7 @@
From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001
From a507fe609a2e99c95218ec430916eaf4c3cb61d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 4 May 2024 02:00:53 +0100
Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU
Subject: [PATCH 15/37] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016
@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
--
2.39.2
2.39.5

View file

@ -1,203 +0,0 @@
From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
Example:
./ifdtool --nuke gbe coreboot.rom
./ifdtool --nuke bios coreboot.com
./ifdtool --nuke me coreboot.com
Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
1 file changed, 81 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 191b3216de..38132b4a28 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
+ if (!strcasecmp("Descriptor", region_type_string))
+ return 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ return 1;
+ else if (!strcasecmp("ME", region_type_string))
+ return 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ return 3;
+ else if (!strcasecmp("Platform Data", region_type_string))
+ return 4;
+ else if (!strcasecmp("Device Exp1", region_type_string))
+ return 5;
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
+ return 6;
+ else if (!strcasecmp("Reserved", region_type_string))
+ return 7;
+ else if (!strcasecmp("EC", region_type_string))
+ return 8;
+ else if (!strcasecmp("Device Exp2", region_type_string))
+ return 9;
+ else if (!strcasecmp("IE", region_type_string))
+ return 10;
+ else if (!strcasecmp("10GbE_0", region_type_string))
+ return 11;
+ else if (!strcasecmp("10GbE_1", region_type_string))
+ return 12;
+ else if (!strcasecmp("PTT", region_type_string))
+ return 15;
+ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
+ int i;
+ struct region region;
+ const struct frba *frba = find_frba(image, size);
+ if (!frba)
+ exit(EXIT_FAILURE);
+
+ region = get_region(frba, region_type);
+ if (region.size > 0) {
+ for (i = region.base; i <= region.limit; i++) {
+ if ((i + 1) > (size))
+ break;
+ image[i] = 0xFF;
+ }
+ write_image(filename, image, size);
+ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
- if (!strcasecmp("Descriptor", region_type_string))
- region_type = 0;
- else if (!strcasecmp("BIOS", region_type_string))
- region_type = 1;
- else if (!strcasecmp("ME", region_type_string))
- region_type = 2;
- else if (!strcasecmp("GbE", region_type_string))
- region_type = 3;
- else if (!strcasecmp("Platform Data", region_type_string))
- region_type = 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
- region_type = 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
- region_type = 6;
- else if (!strcasecmp("Reserved", region_type_string))
- region_type = 7;
- else if (!strcasecmp("EC", region_type_string))
- region_type = 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
- region_type = 9;
- else if (!strcasecmp("IE", region_type_string))
- region_type = 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
- region_type = 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
- region_type = 12;
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
+ fprintf(stderr, "No region specified\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_nuke = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- mode_gpr0_disable) > 1) {
+ mode_gpr0_disable + mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + mode_gpr0_disable) == 0) {
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2

View file

@ -1,47 +0,0 @@
From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2

View file

@ -1,7 +1,7 @@
From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
From 9e0a6aa376db81f9409eda92b6783a8262c1fedb Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
Subject: [PATCH 16/37] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index d929533d92..997f8a0e5a 100644
index 5d9ac56606..338260ea7a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
--
2.39.2
2.39.5

View file

@ -1,173 +0,0 @@
From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2

View file

@ -0,0 +1,240 @@
From 6acc310c1d695d47c148296da9da189de21d58be Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 6 Aug 2024 00:50:24 +0100
Subject: [PATCH 17/37] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:
commit commit_id_here
Author: Angel Pons <th3fanbus@gmail.com>
Date: Mon May 10 22:40:59 2021 +0200
nb/intel/gm45: Make DDR2 raminit work
This patch was original applied, in lbmk, only on coreboot/dell,
separately from coreboot/default, which was wasteful because it
meant having an entire coreboot tree just for a single board. We
did this, because the DDR2 RCOMP fix happened to break DDR3 init
on other boards.
What *this* new patch does on top of Angel's patch, is make sure
that their changes only apply to DDR2, while DDR3 behaviour remains
unchanged. This means that the Dell Latitude E6400 can be supported
in the main coreboot tree, within lbmk.
Essentially, this patch restores the old behaviour, prior to applying
Angel's patch, only when DDR3 memory is used.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
.../intel/gm45/raminit_rcomp_calibration.c | 9 +-
2 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index df8f46fbbc..433db3a68c 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
reg = (reg & ~(0xf << 10)) | (2 << 10);
else
reg = (reg & ~(0xf << 10)) | (3 << 10);
- reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ if (spd_type == DDR2)
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ else
+ reg = (reg & ~(0x7 << 5)) | (3 << 5);
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
- /*
- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
- * after receiver enable calibration, otherwise raminit sometimes
- * completes with non-working memory.
- */
- mchbar_write32(0x0530, 0x06060005);
- mchbar_write32(0x0680, 0x06060606);
- mchbar_write32(0x0684, 0x08070606);
- mchbar_write32(0x0688, 0x0e0e0c0a);
- mchbar_write32(0x068c, 0x0e0e0e0e);
- mchbar_write32(0x0698, 0x06060606);
- mchbar_write32(0x069c, 0x08070606);
- mchbar_write32(0x06a0, 0x0c0c0b0a);
- mchbar_write32(0x06a4, 0x0c0c0c0c);
-
- mchbar_write32(0x06c0, 0x02020202);
- mchbar_write32(0x06c4, 0x03020202);
- mchbar_write32(0x06c8, 0x04040403);
- mchbar_write32(0x06cc, 0x04040404);
- mchbar_write32(0x06d8, 0x02020202);
- mchbar_write32(0x06dc, 0x03020202);
- mchbar_write32(0x06e0, 0x04040403);
- mchbar_write32(0x06e4, 0x04040404);
-
- mchbar_write32(0x0700, 0x02020202);
- mchbar_write32(0x0704, 0x03020202);
- mchbar_write32(0x0708, 0x04040403);
- mchbar_write32(0x070c, 0x04040404);
- mchbar_write32(0x0718, 0x02020202);
- mchbar_write32(0x071c, 0x03020202);
- mchbar_write32(0x0720, 0x04040403);
- mchbar_write32(0x0724, 0x04040404);
-
- mchbar_write32(0x0740, 0x02020202);
- mchbar_write32(0x0744, 0x03020202);
- mchbar_write32(0x0748, 0x04040403);
- mchbar_write32(0x074c, 0x04040404);
- mchbar_write32(0x0758, 0x02020202);
- mchbar_write32(0x075c, 0x03020202);
- mchbar_write32(0x0760, 0x04040403);
- mchbar_write32(0x0764, 0x04040404);
-
- mchbar_write32(0x0780, 0x06060606);
- mchbar_write32(0x0784, 0x09070606);
- mchbar_write32(0x0788, 0x0e0e0c0b);
- mchbar_write32(0x078c, 0x0e0e0e0e);
- mchbar_write32(0x0798, 0x06060606);
- mchbar_write32(0x079c, 0x09070606);
- mchbar_write32(0x07a0, 0x0d0d0c0b);
- mchbar_write32(0x07a4, 0x0d0d0d0d);
-
- mchbar_write32(0x07c0, 0x06060606);
- mchbar_write32(0x07c4, 0x09070606);
- mchbar_write32(0x07c8, 0x0e0e0c0b);
- mchbar_write32(0x07cc, 0x0e0e0e0e);
- mchbar_write32(0x07d8, 0x06060606);
- mchbar_write32(0x07dc, 0x09070606);
- mchbar_write32(0x07e0, 0x0d0d0c0b);
- mchbar_write32(0x07e4, 0x0d0d0d0d);
-
- mchbar_write32(0x0840, 0x06060606);
- mchbar_write32(0x0844, 0x08070606);
- mchbar_write32(0x0848, 0x0e0e0c0a);
- mchbar_write32(0x084c, 0x0e0e0e0e);
- mchbar_write32(0x0858, 0x06060606);
- mchbar_write32(0x085c, 0x08070606);
- mchbar_write32(0x0860, 0x0c0c0b0a);
- mchbar_write32(0x0864, 0x0c0c0c0c);
-
- mchbar_write32(0x0880, 0x02020202);
- mchbar_write32(0x0884, 0x03020202);
- mchbar_write32(0x0888, 0x04040403);
- mchbar_write32(0x088c, 0x04040404);
- mchbar_write32(0x0898, 0x02020202);
- mchbar_write32(0x089c, 0x03020202);
- mchbar_write32(0x08a0, 0x04040403);
- mchbar_write32(0x08a4, 0x04040404);
+ if (sysinfo->spd_type == DDR2) {
+ /*
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
+ * after receiver enable calibration, otherwise raminit sometimes
+ * completes with non-working memory.
+ */
+ mchbar_write32(0x0530, 0x06060005);
+ mchbar_write32(0x0680, 0x06060606);
+ mchbar_write32(0x0684, 0x08070606);
+ mchbar_write32(0x0688, 0x0e0e0c0a);
+ mchbar_write32(0x068c, 0x0e0e0e0e);
+ mchbar_write32(0x0698, 0x06060606);
+ mchbar_write32(0x069c, 0x08070606);
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
+
+ mchbar_write32(0x06c0, 0x02020202);
+ mchbar_write32(0x06c4, 0x03020202);
+ mchbar_write32(0x06c8, 0x04040403);
+ mchbar_write32(0x06cc, 0x04040404);
+ mchbar_write32(0x06d8, 0x02020202);
+ mchbar_write32(0x06dc, 0x03020202);
+ mchbar_write32(0x06e0, 0x04040403);
+ mchbar_write32(0x06e4, 0x04040404);
+
+ mchbar_write32(0x0700, 0x02020202);
+ mchbar_write32(0x0704, 0x03020202);
+ mchbar_write32(0x0708, 0x04040403);
+ mchbar_write32(0x070c, 0x04040404);
+ mchbar_write32(0x0718, 0x02020202);
+ mchbar_write32(0x071c, 0x03020202);
+ mchbar_write32(0x0720, 0x04040403);
+ mchbar_write32(0x0724, 0x04040404);
+
+ mchbar_write32(0x0740, 0x02020202);
+ mchbar_write32(0x0744, 0x03020202);
+ mchbar_write32(0x0748, 0x04040403);
+ mchbar_write32(0x074c, 0x04040404);
+ mchbar_write32(0x0758, 0x02020202);
+ mchbar_write32(0x075c, 0x03020202);
+ mchbar_write32(0x0760, 0x04040403);
+ mchbar_write32(0x0764, 0x04040404);
+
+ mchbar_write32(0x0780, 0x06060606);
+ mchbar_write32(0x0784, 0x09070606);
+ mchbar_write32(0x0788, 0x0e0e0c0b);
+ mchbar_write32(0x078c, 0x0e0e0e0e);
+ mchbar_write32(0x0798, 0x06060606);
+ mchbar_write32(0x079c, 0x09070606);
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
+
+ mchbar_write32(0x07c0, 0x06060606);
+ mchbar_write32(0x07c4, 0x09070606);
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
+ mchbar_write32(0x07d8, 0x06060606);
+ mchbar_write32(0x07dc, 0x09070606);
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
+
+ mchbar_write32(0x0840, 0x06060606);
+ mchbar_write32(0x0844, 0x08070606);
+ mchbar_write32(0x0848, 0x0e0e0c0a);
+ mchbar_write32(0x084c, 0x0e0e0e0e);
+ mchbar_write32(0x0858, 0x06060606);
+ mchbar_write32(0x085c, 0x08070606);
+ mchbar_write32(0x0860, 0x0c0c0b0a);
+ mchbar_write32(0x0864, 0x0c0c0c0c);
+
+ mchbar_write32(0x0880, 0x02020202);
+ mchbar_write32(0x0884, 0x03020202);
+ mchbar_write32(0x0888, 0x04040403);
+ mchbar_write32(0x088c, 0x04040404);
+ mchbar_write32(0x0898, 0x02020202);
+ mchbar_write32(0x089c, 0x03020202);
+ mchbar_write32(0x08a0, 0x04040403);
+ mchbar_write32(0x08a4, 0x04040404);
+ }
igd_compute_ggc(sysinfo);
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index b74765fd9c..5d4505e063 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
reg = mchbar_read32(0x518);
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
- if (i == 1) {
+ if ((i == 1) && (ddr_type == DDR2)) {
magic_comp[0] = (reg >> 8) & 0x3f;
magic_comp[1] = (reg >> 0) & 0x3f;
}
@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
}
mchbar += 0x0040;
}
-
- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ if (ddr_type == DDR2) {
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ }
}
--
2.39.5

View file

@ -1,7 +1,7 @@
From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
From 7461210ecc7c8e41f3f941bd5ce7943e5f66c711 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
Subject: [PATCH 18/37] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2 files changed, 7 insertions(+)
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
index 034de4be2b..4cb16af697 100644
index 417d95fd5d..6fe1b1c456 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
@ -33,10 +33,10 @@ index 034de4be2b..4cb16af697 100644
default "dell/e6400"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 2a266b9771..2432c9d78e 100644
index fef0d735b3..fc5df8b11a 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
if NORTHBRIDGE_INTEL_GM45
@ -48,5 +48,5 @@ index 2a266b9771..2432c9d78e 100644
select VBOOT_STARTS_IN_BOOTBLOCK
--
2.45.1
2.39.5

View file

@ -0,0 +1,52 @@
From a683dffd774dbbe25cc77c0f7d3853232c17c2bf Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 12 Aug 2024 02:15:24 +0100
Subject: [PATCH 19/37] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:
hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
this error was introduced when merging coreboot/dell
into coreboot/default in lbmk. nicholas chin's fix in lbmk
was as follows:
commit 8629873a6043067affc137be275b7aa69cb1f10c
Author: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon May 20 10:46:25 2024 -0600
Fix E6400 display issue with 1440 x 900 panel
this currently corresponds to the patch in lbmk,
as of 12 august 2024:
0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
The assumption prior to Nicholas's fix was 96MHz, so set
it accordingly on x4x northbridge.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/x4x/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 097e11126c..6430319f6a 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
if NORTHBRIDGE_INTEL_X4X
+config INTEL_GMA_DPLL_REF_FREQ
+ int
+ default 96000000
+
config CBFS_SIZE
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
--
2.39.5

View file

@ -1,826 +0,0 @@
From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
is based on the autoport output with some manual tweaks. The flash is
8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
can also be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Working:
- Libgfxinit
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
right side is HCD index 1)
- Keyboard
- Touchpad/trackpoint
- ExpressCard
- Audio
- Ethernet
- SD card reader
- mPCIe WiFi
- SeaBIOS 1.16.2
- edk2 (MrChromebox' fork, uefipayload_202306)
- Internal flashing using dell-flash-unlock
Not working:
- S3 suspend: Possibly EC related
- Physical wireless switch - this triggers an SMI handler in the vendor
firmware which sends commands to the EC to enable/disable wireless
devices
- Battery reporting - needs ACPI code for the EC
- Brightness hotkeys - probably EC related
Unknown/untested:
- Dock
- eSATA
- TPM
- dGPU on non-UMA model
- Bluetooth module (not included on my system)
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6430/Kconfig | 44 +++++
src/mainboard/dell/e6430/Kconfig.name | 2 +
src/mainboard/dell/e6430/Makefile.inc | 6 +
src/mainboard/dell/e6430/acpi/ec.asl | 9 +
src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
src/mainboard/dell/e6430/acpi/superio.asl | 3 +
src/mainboard/dell/e6430/acpi_tables.c | 16 ++
src/mainboard/dell/e6430/board_info.txt | 6 +
src/mainboard/dell/e6430/cmos.default | 9 +
src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++
src/mainboard/dell/e6430/dsdt.asl | 30 ++++
src/mainboard/dell/e6430/early_init.c | 32 ++++
src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6430/hda_verb.c | 33 ++++
src/mainboard/dell/e6430/mainboard.c | 21 +++
18 files changed, 593 insertions(+)
create mode 100644 src/mainboard/dell/e6430/Kconfig
create mode 100644 src/mainboard/dell/e6430/Kconfig.name
create mode 100644 src/mainboard/dell/e6430/Makefile.inc
create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
create mode 100644 src/mainboard/dell/e6430/board_info.txt
create mode 100644 src/mainboard/dell/e6430/cmos.default
create mode 100644 src/mainboard/dell/e6430/cmos.layout
create mode 100644 src/mainboard/dell/e6430/data.vbt
create mode 100644 src/mainboard/dell/e6430/devicetree.cb
create mode 100644 src/mainboard/dell/e6430/dsdt.asl
create mode 100644 src/mainboard/dell/e6430/early_init.c
create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6430/gpio.c
create mode 100644 src/mainboard/dell/e6430/hda_verb.c
create mode 100644 src/mainboard/dell/e6430/mainboard.c
diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
new file mode 100644
index 0000000000..e4c799803e
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig
@@ -0,0 +1,44 @@
+if BOARD_DELL_LATITUDE_E6430
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6430"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6430"
+
+config PS2K_EISAID
+ default "PNP0303"
+
+config PS2M_EISAID
+ default "PNP0F13"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+endif
diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
new file mode 100644
index 0000000000..f866b03585
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6430
+ bool "Latitude E6430"
diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6430/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6430/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
new file mode 100644
index 0000000000..2a5b30f2b7
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Normal
diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
GIT binary patch
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diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
new file mode 100644
index 0000000000..054b01c5ac
--- /dev/null
+++ b/src/mainboard/dell/e6430/devicetree.cb
@@ -0,0 +1,70 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0534 inherit
+
+ device ref host_bridge on end
+ device ref peg10 off end
+ device ref igd on end
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt on end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end # WWAN Slot
+ device ref pcie_rp2 on end # SLAN Slot
+ device ref pcie_rp3 on end # ExpressCard
+ device ref pcie_rp4 on end # E-Module (optical bay)
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
+ device ref pcie_rp6 on end # SD/MMC Card Reader
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6430/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
new file mode 100644
index 0000000000..d882c3d78b
--- /dev/null
+++ b/src/mainboard/dell/e6430/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6430/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
new file mode 100644
index 0000000000..56ada95c58
--- /dev/null
+++ b/src/mainboard/dell/e6430/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280534, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280534),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6430/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.39.2

View file

@ -0,0 +1,243 @@
From a48ba23bb4a24730fa49b5a10b56c9de873dea8a Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:48:26 -0600
Subject: [PATCH 20/37] mb/dell: Convert E6400 into a variant
All the GM45 Dell Latitudes should be nearly identical, so convert the
E6400 port into a variant so that future ports for the other systems can
share code with each other.
Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/Makefile.mk | 10 --------
.../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++-----
.../{e6400 => gm45_latitude}/Kconfig.name | 0
src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++
.../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0
.../acpi/ich9_pci_irqs.asl | 0
.../{e6400 => gm45_latitude}/acpi/superio.asl | 0
.../dell/{e6400 => gm45_latitude}/blc.c | 0
.../{e6400 => gm45_latitude}/board_info.txt | 0
.../dell/{e6400 => gm45_latitude}/bootblock.c | 0
.../{e6400 => gm45_latitude}/cmos.default | 0
.../dell/{e6400 => gm45_latitude}/cmos.layout | 0
.../dell/{e6400 => gm45_latitude}/cstates.c | 0
.../{e6400 => gm45_latitude}/devicetree.cb | 1 -
.../dell/{e6400 => gm45_latitude}/dsdt.asl | 0
.../dell/{e6400 => gm45_latitude}/mainboard.c | 0
.../dell/{e6400 => gm45_latitude}/romstage.c | 0
.../variants}/e6400/data.vbt | Bin
.../variants}/e6400/gma-mainboard.ads | 0
.../{ => gm45_latitude/variants}/e6400/gpio.c | 0
.../variants}/e6400/hda_verb.c | 0
.../variants/e6400/overridetree.cb | 7 ++++++
22 files changed, 34 insertions(+), 17 deletions(-)
delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
deleted file mode 100644
index ca3a82db48..0000000000
--- a/src/mainboard/dell/e6400/Makefile.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += gpio.c
-
-ramstage-y += cstates.c
-ramstage-y += blc.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
similarity index 64%
rename from src/mainboard/dell/e6400/Kconfig
rename to src/mainboard/dell/gm45_latitude/Kconfig
index 6fe1b1c456..ba76fb6e8c 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -1,9 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
-if BOARD_DELL_E6400
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
+config BOARD_DELL_GM45_LATITUDE_COMMON
+ def_bool n
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_P
select NORTHBRIDGE_INTEL_GM45
@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
+
+config BOARD_DELL_E6400
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
+if BOARD_DELL_GM45_LATITUDE_COMMON
+
config INTEL_GMA_DPLL_REF_FREQ
default 100000000
config MAINBOARD_DIR
- default "dell/e6400"
+ default "dell/gm45_latitude"
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VARIANT_DIR
+ default "e6400" if BOARD_DELL_E6400
+
config USBDEBUG_HCD_INDEX
default 1
config CBFS_SIZE
default 0x1A0000
-endif # BOARD_DELL_E6400
+endif # BOARD_DELL_GM45_LATITUDE_COMMON
diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
similarity index 100%
rename from src/mainboard/dell/e6400/Kconfig.name
rename to src/mainboard/dell/gm45_latitude/Kconfig.name
diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
new file mode 100644
index 0000000000..5295d5be22
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+ramstage-y += cstates.c
+ramstage-y += blc.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ec.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/superio.asl
rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
similarity index 100%
rename from src/mainboard/dell/e6400/blc.c
rename to src/mainboard/dell/gm45_latitude/blc.c
diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
similarity index 100%
rename from src/mainboard/dell/e6400/board_info.txt
rename to src/mainboard/dell/gm45_latitude/board_info.txt
diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
similarity index 100%
rename from src/mainboard/dell/e6400/bootblock.c
rename to src/mainboard/dell/gm45_latitude/bootblock.c
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.default
rename to src/mainboard/dell/gm45_latitude/cmos.default
diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.layout
rename to src/mainboard/dell/gm45_latitude/cmos.layout
diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
similarity index 100%
rename from src/mainboard/dell/e6400/cstates.c
rename to src/mainboard/dell/gm45_latitude/cstates.c
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
similarity index 98%
rename from src/mainboard/dell/e6400/devicetree.cb
rename to src/mainboard/dell/gm45_latitude/devicetree.cb
index e9f3915d17..76dae87153 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
register "pci_mmio_size" = "2048"
device domain 0 on
- subsystemid 0x1028 0x0233 inherit
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
similarity index 100%
rename from src/mainboard/dell/e6400/dsdt.asl
rename to src/mainboard/dell/gm45_latitude/dsdt.asl
diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
similarity index 100%
rename from src/mainboard/dell/e6400/mainboard.c
rename to src/mainboard/dell/gm45_latitude/mainboard.c
diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
similarity index 100%
rename from src/mainboard/dell/e6400/romstage.c
rename to src/mainboard/dell/gm45_latitude/romstage.c
diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
similarity index 100%
rename from src/mainboard/dell/e6400/data.vbt
rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/dell/e6400/gma-mainboard.ads
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
similarity index 100%
rename from src/mainboard/dell/e6400/gpio.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
similarity index 100%
rename from src/mainboard/dell/e6400/hda_verb.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
new file mode 100644
index 0000000000..acc34a2252
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+ device domain 0 on
+ subsystemid 0x1028 0x0233 inherit
+ end
+end
--
2.39.5

View file

@ -0,0 +1,332 @@
From b87e6774f0407ea48610c83ea54ab6a4b4a78a24 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:51:25 -0600
Subject: [PATCH 21/37] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/gm45_latitude/Kconfig | 5 +
src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
.../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
.../variants/e4300/gma-mainboard.ads | 17 +++
.../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
.../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
.../variants/e4300/overridetree.cb | 10 ++
7 files changed, 210 insertions(+)
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index ba76fb6e8c..144f9bcdf0 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
config BOARD_DELL_E6400
select BOARD_DELL_GM45_LATITUDE_COMMON
+config BOARD_DELL_E4300
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
if BOARD_DELL_GM45_LATITUDE_COMMON
config INTEL_GMA_DPLL_REF_FREQ
@@ -31,12 +34,14 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
+ default "Latitude E4300" if BOARD_DELL_E4300
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VARIANT_DIR
default "e6400" if BOARD_DELL_E6400
+ default "e4300" if BOARD_DELL_E4300
config USBDEBUG_HCD_INDEX
default 1
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
index aefe777109..4dc95f46be 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
@@ -1,4 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_E4300
+ bool "Latitude E4300"
+
config BOARD_DELL_E6400
bool "Latitude E6400"
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
GIT binary patch
literal 3881
zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M?
z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9
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zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a
zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P
zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!?
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zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7
zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr
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zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
new file mode 100644
index 0000000000..89b81b3d69
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP2, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
new file mode 100644
index 0000000000..b50f8da0b5
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
new file mode 100644
index 0000000000..a9948a93dd
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x111d76b2, /* IDT 92HD71B7X */
+ 0x1028024d, /* Subsystem ID */
+ 13, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00d70500, /* power up speakers */
+ 0x00d70102, /* select mixer (input 0x2) for speakers */
+ 0x00d70740, /* enable speakers output */
+ 0x02770720, /* enable beep input */
+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
+ 0x00d37000, /* unmute speakers */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
new file mode 100644
index 0000000000..20dfa245fb
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+ device domain 0 on
+ subsystemid 0x1028 0x024d inherit
+ chip southbridge/intel/i82801ix
+ device pci 1c.2 off end # PCIe Port #3
+ end
+ end
+end
--
2.39.5

View file

@ -1,39 +0,0 @@
From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 22/30] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

View file

@ -0,0 +1,70 @@
From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
Integrate the previously added mec5035_smi_sleep() function into
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
The E6400 does not require the EC command to sucessfully suspend and
resume from S3, though sending it does enable the breathing effect on
the power LED while in S3. Without it, all LEDs turn off during S3.
Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e7240/smihandler.c | 9 +++++++++
src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
3 files changed, 27 insertions(+)
create mode 100644 src/mainboard/dell/e7240/smihandler.c
create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/e7240/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
--
2.39.5

View file

@ -1,142 +0,0 @@
From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 31 Oct 2023 18:24:39 +0000
Subject: [PATCH 23/30] crank up vram allocation on more intel boards
these were added to libreboot, and it's a policy of
libreboot to max out the vram settings. this was
overlooked, in prior revisions and releases.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
src/mainboard/lenovo/t420/cmos.default | 1 +
src/mainboard/lenovo/t420s/cmos.default | 1 +
src/mainboard/lenovo/t430/cmos.default | 1 +
src/mainboard/lenovo/t520/cmos.default | 1 +
src/mainboard/lenovo/t530/cmos.default | 1 +
src/mainboard/lenovo/x201/cmos.default | 1 +
src/mainboard/lenovo/x220/cmos.default | 1 +
12 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
index ccc7e64625..7c97b84baf 100644
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=128M
+gfx_uma_size=224M
fan_full_speed=Disable
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
index 6d27a79c66..4517ffc7c2 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
psu_fan_lvl=3
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
index 6f3cec735e..9fc4db2990 100644
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
index ad822d5043..89418a4cfc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
@@ -3,3 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 55e1e6c04e..a72108f47e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
index 2cf484fd5a..46294d91ca 100644
--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
@@ -15,3 +15,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
usb_always_on=Disable
+gfx_uma_size=128M
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 52f303dfdb..92a2026542 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
me_state=Disabled
+gfx_uma_size=224M
--
2.39.2

View file

@ -0,0 +1,92 @@
From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 18 Jun 2024 21:31:08 -0600
Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
power button results in the EC powering off the system without letting
the OS cleanly shutting itself down. This command and argument tells the
EC to route power button events to the host so that it can determine
what to do.
The EC command was identified from the ec/google/wilco code, which is
used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
Kconfig help text, those ECs run a modified version of Dell's typical
Latitude EC firmware, so it is likely that the two firmware
implementations use similar commands. Examining LPC traffic between the
host and the EC on the Latitude E6400 did reveal that the same command
was being sent by the vendor firmware to the EC, but this does not
confirm that it has the same meaning as the command from the Wilco code.
Sending the command using inb/outb calls in a userspace C program while
running coreboot without this patch did allow subsequent power button
events to be handled by the host, confirming that the command was indeed
the same.
Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 8 ++++++++
src/ec/dell/mec5035/mec5035.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 85c2ab0140..bdae929a27 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
ec_command(CMD_RADIO_CTRL);
}
+void mec5035_power_button_route(enum ec_power_button_route target)
+{
+ u8 buf = (u8)target;
+ write_mailbox_regs(&buf, 2, 1);
+ ec_command(CMD_POWER_BUTTON_TO_HOST);
+}
+
void mec5035_change_wake(u8 source, enum ec_wake_change change)
{
u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
/* Unconditionally use this argument for now as this setting
is probably the most sensible default out of the 3 choices. */
mec5035_mouse_touchpad(TP_PS2_MOUSE);
+ mec5035_power_button_route(HOST);
pc_keyboard_init(NO_AUX_DEVICE);
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 8d4fded28b..51422598c4 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -11,6 +11,7 @@
enum mec5035_cmd {
CMD_MOUSE_TP = 0x1a,
CMD_RADIO_CTRL = 0x2b,
+ CMD_POWER_BUTTON_TO_HOST = 0x3e,
CMD_ACPI_WAKEUP_CHANGE = 0x4a,
CMD_SLEEP_ENABLE = 0x64,
CMD_CPU_OK = 0xc2,
@@ -36,6 +37,11 @@ enum ec_radio_state {
RADIO_ON
};
+enum ec_power_button_route {
+ EC = 0,
+ HOST
+};
+
#define ACPI_WAKEUP_NUM_ARGS 4
enum ec_wake_change {
WAKE_OFF = 0,
@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
+void mec5035_power_button_route(enum ec_power_button_route target);
void mec5035_change_wake(u8 source, enum ec_wake_change change);
void mec5035_sleep_enable(void);
--
2.39.5

View file

@ -0,0 +1,31 @@
From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 31 Dec 2024 14:42:24 +0000
Subject: [PATCH 24/37] Disable compression on refcode insertion
Compression is not reliably reproducible. In an lbmk release
context, this means we cannot rely on vendorfile insertion.
Therefore, use uncompressed refcode.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.mk b/Makefile.mk
index 3969bfbd05..15346569f8 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1392,7 +1392,7 @@ endif
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
--
2.39.5

View file

@ -0,0 +1,187 @@
From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 02:58:47 +0100
Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/e7505/Kconfig | 9 +++++++++
src/northbridge/intel/gm45/Kconfig | 9 +++++++++
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
src/northbridge/intel/i945/Kconfig | 9 +++++++++
src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
src/northbridge/intel/pineview/Kconfig | 9 +++++++++
src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
9 files changed, 85 insertions(+)
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
index 039a7396f8..ddcb986f10 100644
--- a/src/northbridge/intel/e7505/Kconfig
+++ b/src/northbridge/intel/e7505/Kconfig
@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
select NO_CBFS_MCACHE
select SMM_TSEG
select NEED_SMALL_2MB_PAGE_TABLES
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index fc5df8b11a..95e3644b73 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 6191cb6ccf..0f5b5c7241 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config USE_NATIVE_RAMINIT
bool "[NOT COMPLETE] Use native raminit"
default n
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index dbb2d7436b..5e9418b6a9 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
+
+if NORTHBRIDGE_INTEL_I440BX
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
+endif
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 32eff1a611..9479d75c07 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 2bafebf92e..16b81705bb 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 59cfcd5e0a..a3ad8d3425 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 973eed8bbd..6387cf926d 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
default 2 if IGD_DEFAULT_UMA_SIZE_96MB
default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 6430319f6a..1803ef5733 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
--
2.39.5

View file

@ -1,36 +0,0 @@
From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

View file

@ -1,792 +0,0 @@
From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
is based on the autoport output with some manual tweaks. The flash is
8MiB + 4MiB. It can be internally flashed by sending a command to the
EC, which causes the EC to pull the FDO pin low and the firmware to skip
setting up any chipset based write protections. [1] The EC is the SMSC
MEC5055, which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6530/Kconfig | 37 ++++
src/mainboard/dell/e6530/Kconfig.name | 2 +
src/mainboard/dell/e6530/Makefile.inc | 6 +
src/mainboard/dell/e6530/acpi/ec.asl | 9 +
src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
src/mainboard/dell/e6530/acpi/superio.asl | 3 +
src/mainboard/dell/e6530/acpi_tables.c | 16 ++
src/mainboard/dell/e6530/board_info.txt | 6 +
src/mainboard/dell/e6530/cmos.default | 9 +
src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
src/mainboard/dell/e6530/dsdt.asl | 30 ++++
src/mainboard/dell/e6530/early_init.c | 38 ++++
src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6530/hda_verb.c | 33 ++++
src/mainboard/dell/e6530/mainboard.c | 21 +++
18 files changed, 590 insertions(+)
create mode 100644 src/mainboard/dell/e6530/Kconfig
create mode 100644 src/mainboard/dell/e6530/Kconfig.name
create mode 100644 src/mainboard/dell/e6530/Makefile.inc
create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
create mode 100644 src/mainboard/dell/e6530/board_info.txt
create mode 100644 src/mainboard/dell/e6530/cmos.default
create mode 100644 src/mainboard/dell/e6530/cmos.layout
create mode 100644 src/mainboard/dell/e6530/data.vbt
create mode 100644 src/mainboard/dell/e6530/devicetree.cb
create mode 100644 src/mainboard/dell/e6530/dsdt.asl
create mode 100644 src/mainboard/dell/e6530/early_init.c
create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6530/gpio.c
create mode 100644 src/mainboard/dell/e6530/hda_verb.c
create mode 100644 src/mainboard/dell/e6530/mainboard.c
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
new file mode 100644
index 0000000000..582adddbd4
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E6530
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ default "dell/e6530"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6530"
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config USBDEBUG_HCD_INDEX
+ default 2
+endif
diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
new file mode 100644
index 0000000000..01ed76d107
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6530
+ bool "Latitude E6530"
diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6530/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
new file mode 100644
index 0000000000..e85ea4c661
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+415 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
GIT binary patch
literal 4280
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
new file mode 100644
index 0000000000..96eed178c5
--- /dev/null
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000251"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0535 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x007c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt on end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6530/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
new file mode 100644
index 0000000000..d57f48e7f1
--- /dev/null
+++ b/src/mainboard/dell/e6530/early_init.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ mec5035_early_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6530/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
new file mode 100644
index 0000000000..9de7e34311
--- /dev/null
+++ b/src/mainboard/dell/e6530/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280535, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280535),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6530/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.39.2

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@ -0,0 +1,94 @@
From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
From: Felix Singer <felixsinger@posteo.net>
Date: Wed, 26 Jun 2024 04:24:31 +0200
Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
src/soc/intel/skylake/Kconfig | 1 +
src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 4ad33496b2..9191ed0ff8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
+ select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
index 6538a1475b..dfb81d496e 100644
--- a/src/soc/intel/skylake/chipset.cb
+++ b/src/soc/intel/skylake/chipset.cb
@@ -13,7 +13,61 @@ chip soc/intel/skylake
device pci 07.0 alias chap off end
device pci 08.0 alias gmm off end # Gaussian Mixture Model
device pci 13.0 alias ish off end # SensorHub
- device pci 14.0 alias south_xhci off ops usb_xhci_ops end
+ device pci 14.0 alias south_xhci off ops usb_xhci_ops
+ chip drivers/usb/acpi
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 alias xhci_root_hub off
+ chip drivers/usb/acpi
+ device usb 2.0 alias usb2_port1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.1 alias usb2_port2 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.2 alias usb2_port3 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.3 alias usb2_port4 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.4 alias usb2_port5 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.5 alias usb2_port6 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.6 alias usb2_port7 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.7 alias usb2_port8 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.8 alias usb2_port9 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.9 alias usb2_port10 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.0 alias usb3_port1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.1 alias usb3_port2 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.2 alias usb3_port3 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.3 alias usb3_port4 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.4 alias usb3_port5 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.5 alias usb3_port6 off end
+ end
+ end
+ end
+ end
device pci 14.1 alias south_xdci off ops usb_xdci_ops end
device pci 14.2 alias thermal off end
device pci 14.3 alias cio off end
--
2.39.5

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@ -1,145 +0,0 @@
From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 25 Jan 2024 14:30:03 +0000
Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
i diffed nicholas's current e6430 patch, versus the old one,
prior to this revision update in lbmk, also cross referencing
the original e6430 and e6530 patches, diffing them, and the
result in this patch. most notably, spd data is now defined in
the devicetree, instead of early_init.c as per:
commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
Author: Keith Hui <buurin@gmail.com>
Date: Sat Jul 22 12:49:05 2023 -0400
mb/*: Update SPD mapping for sandybridge boards
This should work fine. Will test after this builds.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/e6530/Kconfig | 15 +++++++++++----
src/mainboard/dell/e6530/cmos.layout | 2 +-
src/mainboard/dell/e6530/devicetree.cb | 8 +++++---
src/mainboard/dell/e6530/early_init.c | 12 +++---------
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
index 582adddbd4..a104566890 100644
--- a/src/mainboard/dell/e6530/Kconfig
+++ b/src/mainboard/dell/e6530/Kconfig
@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config DRAM_RESET_GATE_GPIO
+ default 60
+
config MAINBOARD_DIR
default "dell/e6530"
config MAINBOARD_PART_NUMBER
default "Latitude E6530"
-config VGA_BIOS_ID
- default "8086,0166"
+config PS2K_EISAID
+ default "PNP0303"
-config DRAM_RESET_GATE_GPIO
- default 60
+config PS2M_EISAID
+ default "PNP0F13"
config USBDEBUG_HCD_INDEX
default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
endif
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
index e85ea4c661..1aa7e77bce 100644
--- a/src/mainboard/dell/e6530/cmos.layout
+++ b/src/mainboard/dell/e6530/cmos.layout
@@ -25,7 +25,7 @@ entries
# coreboot config options: EC
412 1 e 1 bluetooth
413 1 e 1 wwan
-415 1 e 1 wlan
+414 1 e 1 wlan
# coreboot config options: ME
424 1 e 14 me_state
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
index 96eed178c5..37135bcf0f 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "gpu_panel_power_up_delay" = "400"
register "gpu_pch_backlight" = "0x13121312"
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
device domain 0x0 on
subsystemid 0x1028 0x0535 inherit
@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "gen1_dec" = "0x007c0681"
register "gen2_dec" = "0x005c0921"
register "gen3_dec" = "0x003c07e1"
- register "gen4_dec" = "0x007c0901"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
register "gpi0_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end # USB 3.0 Controller
- device ref mei1 off end # Management Engine Interface 1
+ device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
device ref me_kt on end # Management Engine KT
@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
device ref pcie_rp2 on end # PCIe Port #2
device ref pcie_rp3 on end # PCIe Port #3
device ref pcie_rp4 on end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp5 on end # PCIe Port #5
device ref pcie_rp6 on end # PCIe Port #6
device ref pcie_rp7 off end # PCIe Port #7
device ref pcie_rp8 off end # PCIe Port #8
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
index d57f48e7f1..2b40f6963f 100644
--- a/src/mainboard/dell/e6530/early_init.c
+++ b/src/mainboard/dell/e6530/early_init.c
@@ -4,7 +4,6 @@
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <ec/dell/mec5035/mec5035.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
void bootblock_mainboard_early_init(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[2], 0x52, id_only);
-}
--
2.39.2

View file

@ -0,0 +1,30 @@
From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
From: Mate Kukri <km@mkukri.xyz>
Date: Fri, 22 Nov 2024 21:26:48 +0000
Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
bootblock
Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
Signed-off-by: Mate Kukri <km@mkukri.xyz>
---
src/soc/intel/skylake/bootblock/pch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index df00bb85a9..beaece960b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
void pch_early_iorange_init(void)
{
- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
- LPC_IOE_EC_62_66;
+ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
+ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
const config_t *config = config_of_soc();
--
2.39.5

View file

@ -1,54 +0,0 @@
From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 25 Jan 2024 14:37:30 +0000
Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
we neuter anyway. disabling it in devicetree will prevent linux
from ever trying to use it or load a driver for it, and thus
might prevent benign error messages from appearing in dmesg.
this change was suggested by nicholas when asked on irc.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/e6430/devicetree.cb | 4 ++--
src/mainboard/dell/e6530/devicetree.cb | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
index 054b01c5ac..2b8574c984 100644
--- a/src/mainboard/dell/e6430/devicetree.cb
+++ b/src/mainboard/dell/e6430/devicetree.cb
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end
- device ref mei1 on end
+ device ref mei1 off end
device ref mei2 off end
device ref me_ide_r off end
- device ref me_kt on end
+ device ref me_kt off end
device ref gbe on end
device ref ehci2 on end
device ref hda on end
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
index 37135bcf0f..010200bb6d 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end # USB 3.0 Controller
- device ref mei1 on end # Management Engine Interface 1
+ device ref mei1 off end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt on end # Management Engine KT
+ device ref me_kt off end # Management Engine KT
device ref gbe on end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on end # High Definition Audio
--
2.39.2

View file

@ -0,0 +1,708 @@
From 75cc0ea09234064318046624845b0afc5afb0ce5 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 30 Sep 2024 20:44:38 -0400
Subject: [PATCH 29/37] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/optiplex_780/Kconfig | 40 ++++
src/mainboard/dell/optiplex_780/Kconfig.name | 4 +
src/mainboard/dell/optiplex_780/Makefile.mk | 10 +
src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 +
.../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++
.../dell/optiplex_780/acpi/superio.asl | 18 ++
.../dell/optiplex_780/board_info.txt | 6 +
src/mainboard/dell/optiplex_780/cmos.default | 8 +
src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++
src/mainboard/dell/optiplex_780/cstates.c | 8 +
src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++
src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++
.../dell/optiplex_780/gma-mainboard.ads | 16 ++
.../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes
.../optiplex_780/variants/780_mt/early_init.c | 12 ++
.../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++
.../optiplex_780/variants/780_mt/hda_verb.c | 26 +++
.../variants/780_mt/overridetree.cb | 10 +
18 files changed, 530 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
new file mode 100644
index 0000000000..2d06c75c9a
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -0,0 +1,40 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_780_COMMON
+ def_bool n
+ select BOARD_ROMSIZE_KB_8192
+ select CPU_INTEL_SOCKET_LGA775
+ select DRIVERS_I2C_CK505
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_X4X
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select SOUTHBRIDGE_INTEL_I82801JX
+
+config BOARD_DELL_OPTIPLEX_780_MT
+ select BOARD_DELL_OPTIPLEX_780_COMMON
+
+if BOARD_DELL_OPTIPLEX_780_COMMON
+
+config VGA_BIOS_ID
+ default "8086,2e22"
+
+config MAINBOARD_DIR
+ default "dell/optiplex_780"
+
+config MAINBOARD_PART_NUMBER
+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
+
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VARIANT_DIR
+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
+
+endif # BOARD_DELL_OPTIPLEX_780_COMMON
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
new file mode 100644
index 0000000000..db7f2e8fe3
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_780_MT
+ bool "OptiPlex 780 MT"
diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
new file mode 100644
index 0000000000..d462995d75
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += cstates.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
new file mode 100644
index 0000000000..479296cb76
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
+
+/* dummy */
diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000000..b7588dcc41
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+ Return (Package() {
+ /* PCI slot */
+ Package() { 0x0001ffff, 0, 0, 0x14},
+ Package() { 0x0001ffff, 1, 0, 0x15},
+ Package() { 0x0001ffff, 2, 0, 0x16},
+ Package() { 0x0001ffff, 3, 0, 0x17},
+
+ Package() { 0x0002ffff, 0, 0, 0x15},
+ Package() { 0x0002ffff, 1, 0, 0x16},
+ Package() { 0x0002ffff, 2, 0, 0x17},
+ Package() { 0x0002ffff, 3, 0, 0x14},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
new file mode 100644
index 0000000000..9f3900b86c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8720F_SHOW_SP1
+#undef IT8720F_SHOW_SP2
+#undef IT8720F_SHOW_EC
+#undef IT8720F_SHOW_KBCK
+#undef IT8720F_SHOW_KBCM
+#undef IT8720F_SHOW_GPIO
+#undef IT8720F_SHOW_CIR
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8720F_SHOW_EC 1
+#define IT8720F_SHOW_KBCK 1
+#define IT8720F_SHOW_KBCM 1
+#define IT8720F_SHOW_GPIO 1
+#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
new file mode 100644
index 0000000000..aaf657b583
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
new file mode 100644
index 0000000000..23f0e55f3e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cmos.default
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
new file mode 100644
index 0000000000..9f5012adb4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cmos.layout
@@ -0,0 +1,72 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 10 sata_mode
+409 2 e 7 power_on_after_fail
+411 1 e 1 nmi
+
+# coreboot config options: cpu
+
+# coreboot config options: northbridge
+432 4 e 11 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+10 0 AHCI
+10 1 Compatible
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+11 7 128M
+11 8 256M
+11 9 96M
+11 10 160M
+11 11 224M
+11 12 352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
new file mode 100644
index 0000000000..4adf0edc63
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cstates.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+int get_cst_entries(const acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
new file mode 100644
index 0000000000..95e3bd517c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
+ device domain 0 on
+ ops x4x_pci_domain_ops # PCI domain
+ subsystemid 0x8086 0x0028 inherit
+ device pci 0.0 on end # Host Bridge
+ device pci 1.0 on end # PCIe x16 2.0 slot
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 on end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801jx # ICH10
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x3f"
+ register "sata_clock_request" = "1"
+
+ # Enable PCIe ports 0,1 as slots.
+ register "pcie_slot_implemented" = "0x3"
+
+ device pci 19.0 on end # GBE
+ device pci 1a.0 on end # USB
+ device pci 1a.1 on end # USB
+ device pci 1a.2 on end # USB
+ device pci 1a.7 on end # USB
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 off end # PCIe 1
+ device pci 1c.1 off end # PCIe 2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
+ device pci 1f.3 on # SMBus
+ chip drivers/i2c/ck505 # IDT CV194
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff }"
+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
+ 0xff, 0x00, 0x00, 0x95,
+ 0x00, 0x65, 0x7d, 0x56,
+ 0x13, 0xc0, 0x00, 0x07,
+ 0x01, 0x0a, 0x64 }"
+ device i2c 69 on end
+ end
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
+ device pci 1f.6 off end # Thermal Subsystem
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
new file mode 100644
index 0000000000..9ad70469de
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20090811 // OEM revision
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ OSYS = 2002
+ // global NVS and variables
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
new file mode 100644
index 0000000000..bc81cf4a40
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP2,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
GIT binary patch
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diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
new file mode 100644
index 0000000000..e2fa05cd8f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/x4x/x4x.h>
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+ // BTX form factor
+ spd_map[0] = 0x53;
+ spd_map[1] = 0x52;
+ spd_map[2] = 0x51;
+ spd_map[3] = 0x50;
+}
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
new file mode 100644
index 0000000000..9993f17c55
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_NATIVE,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
new file mode 100644
index 0000000000..4158bcf899
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11d4194a, /* Analog Devices AD1984A */
+ 0xbfd40000, /* Subsystem ID */
+ 10, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
+ AZALIA_PIN_CFG(0, 0x12, 0x21214010),
+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
new file mode 100644
index 0000000000..555b1c1f5c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device domain 0 on
+ chip southbridge/intel/i82801jx
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ end
+ end
+end
--
2.39.5

View file

@ -0,0 +1,326 @@
From 6725ec0bb976c61cbe87e61bf0e8b02e38d14de9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 30 Oct 2024 20:55:25 -0600
Subject: [PATCH 30/37] mb/dell/optiplex_780: Add USFF variant
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/optiplex_780/Kconfig | 5 +
src/mainboard/dell/optiplex_780/Kconfig.name | 3 +
.../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes
.../variants/780_usff/early_init.c | 9 +
.../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++
.../optiplex_780/variants/780_usff/hda_verb.c | 26 +++
.../variants/780_usff/overridetree.cb | 10 ++
7 files changed, 219 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
index 2d06c75c9a..fc649e35d5 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON
config BOARD_DELL_OPTIPLEX_780_MT
select BOARD_DELL_OPTIPLEX_780_COMMON
+config BOARD_DELL_OPTIPLEX_780_USFF
+ select BOARD_DELL_OPTIPLEX_780_COMMON
+
if BOARD_DELL_OPTIPLEX_780_COMMON
config VGA_BIOS_ID
@@ -30,11 +33,13 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VARIANT_DIR
default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF
endif # BOARD_DELL_OPTIPLEX_780_COMMON
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
index db7f2e8fe3..bc84c82a79 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig.name
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
@@ -2,3 +2,6 @@
config BOARD_DELL_OPTIPLEX_780_MT
bool "OptiPlex 780 MT"
+
+config BOARD_DELL_OPTIPLEX_780_USFF
+ bool "OptiPlex 780 USFF"
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7
GIT binary patch
literal 1917
zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;|
zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G
z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX
zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv
zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB
zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^
zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1#
zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU
zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T
z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4
zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c
z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8
zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE
zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb
zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn
z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D(
z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a=
T#w3FFBiyj<XAh$hb(enud`r7S
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
new file mode 100644
index 0000000000..2a55fc3a6e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/x4x/x4x.h>
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+ spd_map[0] = 0x50;
+ spd_map[2] = 0x52;
+}
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
new file mode 100644
index 0000000000..389f4077d7
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_NATIVE,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
new file mode 100644
index 0000000000..c94e06b156
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11d4194a, /* Analog Devices AD1984A */
+ 0x10280420, /* Subsystem ID */
+ 10, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x11, 0x02214040),
+ AZALIA_PIN_CFG(0, 0x12, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020),
+ AZALIA_PIN_CFG(0, 0x15, 0x01813030),
+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0),
+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
new file mode 100644
index 0000000000..555b1c1f5c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device domain 0 on
+ chip southbridge/intel/i82801jx
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ end
+ end
+end
--
2.39.5

View file

@ -0,0 +1,49 @@
From 4ffaddc37d30d39f25faeaef73046a6e2ce525e8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 11 Dec 2024 01:06:01 +0000
Subject: [PATCH 31/37] dell/3050micro: disable nvme hotplug
in my testing, when running my 3050micro for a few days,
the nvme would sometimes randomly rename.
e.g. nvme0n1 renamed to nvme0n2
this might cause crashes in linux, if booting only from the
nvme. in my case, i was booting from mdraid (sata+nvme) and
every few days, the nvme would rename at least once, causing
my RAID to become unsynced. since i'm using RAID1, this was
OK and I could simply re-sync the array, but this is quite
precarious indeed. if you're using raid0, that will potentially
corrupt your RAID array indefinitely.
this same issue manifested on the T480/T480 thinkpads, and
S3 resume would break because of that, when booting from nvme,
because the nvme would be "unplugged" and appear to linux as a
new device (the one that you booted from).
the fix there was to disable hotplugging on that pci-e slot
for the nvme, so apply the same fix here for 3050 micro
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
index da11085ab6..2a97306c5d 100644
--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
@@ -45,7 +45,9 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieRpClkSrcNumber[20]" = "3"
- register "PcieRpHotPlug[20]" = "1"
+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2,
+# which could cause crashes in linux if booting from nvme
+ register "PcieRpHotPlug[20]" = "0"
end
# Realtek LAN
--
2.39.5

View file

@ -1,923 +0,0 @@
From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
From: Mate Kukri <kukri.mate@gmail.com>
Date: Mon, 4 Dec 2023 21:34:18 +0000
Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The OptiPlex 7020 and 9020 use physically identical motherboards.
Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT
(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
mic inputs untested
- Ethernet: tested, works
(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
---
src/mainboard/dell/optiplex_9020/Kconfig | 34 +++
src/mainboard/dell/optiplex_9020/Kconfig.name | 11 +
src/mainboard/dell/optiplex_9020/Makefile.inc | 5 +
src/mainboard/dell/optiplex_9020/acpi/ec.asl | 3 +
.../dell/optiplex_9020/acpi/platform.asl | 11 +
.../dell/optiplex_9020/acpi/superio.asl | 3 +
.../dell/optiplex_9020/board_info.txt | 8 +
src/mainboard/dell/optiplex_9020/bootblock.c | 116 ++++++++++
src/mainboard/dell/optiplex_9020/cmos.default | 4 +
src/mainboard/dell/optiplex_9020/cmos.layout | 58 +++++
src/mainboard/dell/optiplex_9020/data.vbt | Bin 0 -> 4409 bytes
.../dell/optiplex_9020/devicetree.cb | 80 +++++++
src/mainboard/dell/optiplex_9020/dsdt.asl | 25 ++
.../dell/optiplex_9020/gma-mainboard.ads | 18 ++
src/mainboard/dell/optiplex_9020/gpio.c | 217 ++++++++++++++++++
src/mainboard/dell/optiplex_9020/hda_verb.c | 27 +++
src/mainboard/dell/optiplex_9020/mainboard.c | 15 ++
.../dell/optiplex_9020/overridetree_mt.cb | 10 +
src/mainboard/dell/optiplex_9020/romstage.c | 53 +++++
19 files changed, 698 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
new file mode 100644
index 0000000000..774a72f161
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_HASWELL
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
+ select SUPERIO_SMSC_SCH555x
+
+config CBFS_SIZE
+ default 0x600000
+
+config MAINBOARD_DIR
+ default "dell/optiplex_9020"
+
+config MAINBOARD_PART_NUMBER
+ default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
+ default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
+
+config OVERRIDE_DEVICETREE
+ default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
+
+endif
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
new file mode 100644
index 0000000000..c25c330a44
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_9020_SFF
+ bool "OptiPlex 7020/9020 SFF"
+ help
+ The 7020 SFF and 9020 SFF mainboards are physically identical.
+
+config BOARD_DELL_OPTIPLEX_9020_MT
+ bool "OptiPlex 7020/9020 MT"
+ help
+ The 7020 MT and 9020 MT mainboards are physically identical.
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
new file mode 100644
index 0000000000..6ca2f2afaa
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += bootblock.c
diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
new file mode 100644
index 0000000000..cda7682e3e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ Return(Package() { 0, 0 })
+}
+
+Method(_PTS, 1)
+{
+
+}
diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
new file mode 100644
index 0000000000..e30cf9c41f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Dell Inc.
+Board name: OptiPlex 7020/9020
+Release year: 2014
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
new file mode 100644
index 0000000000..2837cf9cf1
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <superio/smsc/sch555x/sch555x.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+{
+ // Clear EC-to-Host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // Send address and value to the EC
+ sch555x_emi_write16(0, (addr1 * 2) | 0x101);
+ sch555x_emi_write32(4, val | (addr2 << 16));
+
+ // Wait for acknowledgement message from EC
+ outb(1, SCH555x_EMI_IOBASE);
+ size_t timeout = 0;
+ do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
+}
+
+struct ec_init_entry {
+ uint16_t addr;
+ uint8_t val;
+};
+
+static void ec_init(void)
+{
+ /*
+ * Tables from CORE_PEI
+ */
+
+ static const struct ec_init_entry init_table1[] = {
+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
+ ec_write(2, init_table1[i].addr, init_table1[i].val);
+
+ static const struct ec_init_entry init_table2[] = {
+ {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
+ {0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
+ {0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
+ {0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
+ {0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
+ {0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
+ {0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
+ {0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
+ {0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
+ {0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
+ {0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
+ {0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
+ ec_write(1, init_table2[i].addr, init_table2[i].val);
+
+ /*
+ * Table from PeiHwmInit
+ */
+
+ static const struct ec_init_entry hwm_init_table[] = {
+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
+ ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
+}
+
+#define SCH555x_IOBASE 0x2e
+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
+
+void mainboard_config_superio(void)
+{
+ // Super I/O early init will map Runtime and EMI registers
+ sch555x_early_init(GLOBAL_DEV);
+
+ // Changes LED color among a few other things (extracted from Dell's FW)
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
+ outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
+ outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
+ outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
+
+ // Magic EC init
+ ec_init();
+
+ // Magic EC init is needed for UART1 initialization to work
+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
new file mode 100644
index 0000000000..b159660aa8
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
new file mode 100644
index 0000000000..c9ba76c78f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -0,0 +1,58 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 4 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 5 power_on_after_fail
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+3 0 Fallback
+3 1 Normal
+
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
GIT binary patch
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diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
new file mode 100644
index 0000000000..c0b17a15ff
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -0,0 +1,80 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/haswell
+ # This mainboard has VGA
+ register "gpu_ddi_e_connected" = "1"
+
+ chip cpu/intel/haswell
+ device cpu_cluster 0 on ops haswell_cpu_bus_ops end
+ end
+
+ device domain 0 on
+ ops haswell_pci_domain_ops
+
+ subsystemid 0x1028 0x05a5 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe graphics
+ device pci 02.0 on end # VGA controller
+ device pci 03.0 on end # Mini-HD audio
+
+ chip southbridge/intel/lynxpoint
+ register "gen1_dec" = "0x007c0a01"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "sata_port_map" = "0x33"
+
+ device pci 14.0 on end # xHCI controller
+ device pci 16.0 on end # Management Engine interface 1
+ device pci 16.1 off end # Management Engine interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 on end # Management Engine KT
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x1028 0x05a4
+ end
+ device pci 1a.0 on end # EHCI controller #2
+ device pci 1b.0 on end # HD audio controller
+ device pci 1c.0 off end
+ device pci 1c.1 off end
+ device pci 1c.2 off end
+ device pci 1c.3 off end
+ device pci 1c.4 on end # PCIe 4x slot
+ device pci 1c.5 off end
+ device pci 1c.6 off end
+ device pci 1c.7 off end
+ device pci 1d.0 on end # EHCI controller #1
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/sch555x
+ device pnp 2e.0 on # EMI
+ io 0x60 = 0xa00
+ end
+ device pnp 2e.1 on # 8042
+ io 0x60 = 0x60
+ irq 0x0f = 0
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.7 on # UART1
+ io 0x60 = 0x3f8
+ irq 0x0f = 2
+ irq 0x70 = 4
+ end
+ device pnp 2e.8 off end # UART2
+ device pnp 2e.c on # LPC interface
+ io 0x60 = 0x2e
+ end
+ device pnp 2e.a on # Runtime registers
+ io 0x60 = 0xa40
+ end
+ device pnp 2e.b off end # Floppy Controller
+ device pnp 2e.11 off end # Parallel Port
+ end
+ end
+ device pci 1f.2 on end # SATA controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
new file mode 100644
index 0000000000..7ec1e9775a
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20181031 /* OEM Revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/hostbridge.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
new file mode 100644
index 0000000000..173f2f1d0d
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
new file mode 100644
index 0000000000..48b7707e2c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/gpio.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio13 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio18 = GPIO_BLINK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio8 = GPIO_INVERT,
+ .gpio9 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio26 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_OUTPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio66 = GPIO_LEVEL_HIGH,
+ .gpio72 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
new file mode 100644
index 0000000000..df43ade3e6
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0280, /* Realtek ALC3220 */
+ 0x102805a5, /* Subsystem ID */
+ 13, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x102805a5),
+ AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
+ AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
+ AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
new file mode 100644
index 0000000000..c834fea5d3
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
new file mode 100644
index 0000000000..90205c2d68
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/haswell
+ device domain 0 on
+ chip southbridge/intel/lynxpoint
+ device pci 1c.1 on end # PCI (via XIO2001 bridge)
+ device pci 1c.2 on end # PCIe 1x slot
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
new file mode 100644
index 0000000000..2b9cdaa5fd
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/romstage.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
+ RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
+ RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
+ RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
+ RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
+ RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
+ RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
+ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+ spdi->addresses[0] = 0x50;
+ spdi->addresses[1] = 0x51;
+ spdi->addresses[2] = 0x52;
+ spdi->addresses[3] = 0x53;
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
+ {0x0040, 1, 1, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 2, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 6, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 7, USB_PORT_BACK_PANEL},
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ {1, 6},
+ {1, 7},
+ {0, USB_OC_PIN_SKIP},
+ {0, USB_OC_PIN_SKIP},
+ {1, 1},
+ {1, 2},
+};
--
2.39.2

View file

@ -0,0 +1,78 @@
From 5d8930edfa1d9537ba80e24c0cf8f0c9e4e9ec72 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 18 Dec 2024 02:06:18 +0000
Subject: [PATCH 32/37] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
This is used by lbmk to know where a tb.bin file goes,
when extracting and padding TBT.bin from Lenovo ThunderBolt
firmware updates on T480/T480s and other machines, grabbing
Lenovo update files.
Not used in any builds, so it's not relevant for ./mk inject
However, the ThunderBolt firmware is now auto-downloaded on
T480/T480s. This is not inserted, because it doesn't go in
the main flash, but the resulting ROM image can be flashed
on the TB controller's separate flash chip.
Locations are as follows:
vendorfiles/t480s/tb.bin
vendorfiles/t480/tb.bin
This can be used for other affected ThinkPads when they're
added to Libreboot, but note that Lenovo provides different
TB firmware files for each machine.
Since I assume it's the same TB controller on all of those
machines, I have to wonder: what difference is there between
the various TBT.bin files provided by Lenovo, and how do they
differ in terms of actual flashed configuration?
We simply flash the padded TBT.bin when updating the firmware,
flashing externally. That's what this patch is for, so that
lbmk can auto-download them.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 2ffbaab85f..512b326381 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY
string
default MAINBOARD_PART_NUMBER
+config LENOVO_TBFW_BIN
+ string "Lenovo ThunderBolt firmware bin file"
+ default ""
+ help
+ ThunderBolt firmware for certain ThinkPad models e.g. T480.
+ Not used in the actual build. Libreboot's build system uses this
+ along with config/vendor/*/pkg.cfg entries defining a URL to the
+ Lenovo download link and hash. The resulting file when processed by
+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device.
+ Earlier versions of this firmware had debug commands enabled that
+ sent logs to said flash IC, and it would quickly fill up, bricking
+ the ThunderBolt controller. With these updates, flashed externally,
+ you can fix the issue if present or otherwise prevent it. The benefit
+ here is that you then don't need to use Windows or a boot disk. You
+ can flash the TB firmware while flashing Libreboot firmware. Easy!
+ Look for these variables in lbmk:
+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and
+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file.
+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting
+ the firmware, putting it at that desired location. In this way, lbmk
+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb
+ and it appears at vendorfiles/t480/tb.bin fully padded and everything!
+
+ Just leave this blank if you don't care about this option. It's not
+ useful for every ThinkPad, only certain models.
+
endif # VENDOR_LENOVO
--
2.39.5

View file

@ -1,774 +0,0 @@
From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 26 Nov 2023 17:08:52 -0700
Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6420/Kconfig | 38 ++++
src/mainboard/dell/e6420/Kconfig.name | 2 +
src/mainboard/dell/e6420/Makefile.inc | 6 +
src/mainboard/dell/e6420/acpi/ec.asl | 9 +
src/mainboard/dell/e6420/acpi/platform.asl | 12 ++
src/mainboard/dell/e6420/acpi/superio.asl | 3 +
src/mainboard/dell/e6420/acpi_tables.c | 16 ++
src/mainboard/dell/e6420/board_info.txt | 6 +
src/mainboard/dell/e6420/cmos.default | 9 +
src/mainboard/dell/e6420/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6420/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6420/devicetree.cb | 66 +++++++
src/mainboard/dell/e6420/dsdt.asl | 30 ++++
src/mainboard/dell/e6420/early_init.c | 32 ++++
src/mainboard/dell/e6420/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6420/gpio.c | 191 +++++++++++++++++++++
src/mainboard/dell/e6420/hda_verb.c | 33 ++++
src/mainboard/dell/e6420/mainboard.c | 21 +++
18 files changed, 582 insertions(+)
create mode 100644 src/mainboard/dell/e6420/Kconfig
create mode 100644 src/mainboard/dell/e6420/Kconfig.name
create mode 100644 src/mainboard/dell/e6420/Makefile.inc
create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
create mode 100644 src/mainboard/dell/e6420/board_info.txt
create mode 100644 src/mainboard/dell/e6420/cmos.default
create mode 100644 src/mainboard/dell/e6420/cmos.layout
create mode 100644 src/mainboard/dell/e6420/data.vbt
create mode 100644 src/mainboard/dell/e6420/devicetree.cb
create mode 100644 src/mainboard/dell/e6420/dsdt.asl
create mode 100644 src/mainboard/dell/e6420/early_init.c
create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6420/gpio.c
create mode 100644 src/mainboard/dell/e6420/hda_verb.c
create mode 100644 src/mainboard/dell/e6420/mainboard.c
diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
new file mode 100644
index 0000000000..cff62bf70c
--- /dev/null
+++ b/src/mainboard/dell/e6420/Kconfig
@@ -0,0 +1,38 @@
+if BOARD_DELL_LATITUDE_E6420
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_10240
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6420"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6420"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0126"
+
+endif # BOARD_DELL_LATITUDE_E6420
diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
new file mode 100644
index 0000000000..1722891e7b
--- /dev/null
+++ b/src/mainboard/dell/e6420/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6420
+ bool "Latitude E6420"
diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6420/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e6420/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6420/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6420/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
GIT binary patch
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diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
new file mode 100644
index 0000000000..f9259f7175
--- /dev/null
+++ b/src/mainboard/dell/e6420/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x0000054f"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0493 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6420/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
new file mode 100644
index 0000000000..0682441ed6
--- /dev/null
+++ b/src/mainboard/dell/e6420/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e6420/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
new file mode 100644
index 0000000000..943c743f48
--- /dev/null
+++ b/src/mainboard/dell/e6420/gpio.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
new file mode 100644
index 0000000000..b3803b7c65
--- /dev/null
+++ b/src/mainboard/dell/e6420/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280493, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280493),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6420/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0

View file

@ -1,773 +0,0 @@
From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:07:25 -0700
Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6520/Kconfig | 38 +++++
src/mainboard/dell/e6520/Kconfig.name | 2 +
src/mainboard/dell/e6520/Makefile.inc | 6 +
src/mainboard/dell/e6520/acpi/ec.asl | 9 +
src/mainboard/dell/e6520/acpi/platform.asl | 12 ++
src/mainboard/dell/e6520/acpi/superio.asl | 3 +
src/mainboard/dell/e6520/acpi_tables.c | 16 ++
src/mainboard/dell/e6520/board_info.txt | 6 +
src/mainboard/dell/e6520/cmos.default | 9 +
src/mainboard/dell/e6520/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6520/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6520/devicetree.cb | 66 +++++++
src/mainboard/dell/e6520/dsdt.asl | 30 ++++
src/mainboard/dell/e6520/early_init.c | 32 ++++
src/mainboard/dell/e6520/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6520/gpio.c | 190 +++++++++++++++++++++
src/mainboard/dell/e6520/hda_verb.c | 33 ++++
src/mainboard/dell/e6520/mainboard.c | 21 +++
18 files changed, 581 insertions(+)
create mode 100644 src/mainboard/dell/e6520/Kconfig
create mode 100644 src/mainboard/dell/e6520/Kconfig.name
create mode 100644 src/mainboard/dell/e6520/Makefile.inc
create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
create mode 100644 src/mainboard/dell/e6520/board_info.txt
create mode 100644 src/mainboard/dell/e6520/cmos.default
create mode 100644 src/mainboard/dell/e6520/cmos.layout
create mode 100644 src/mainboard/dell/e6520/data.vbt
create mode 100644 src/mainboard/dell/e6520/devicetree.cb
create mode 100644 src/mainboard/dell/e6520/dsdt.asl
create mode 100644 src/mainboard/dell/e6520/early_init.c
create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6520/gpio.c
create mode 100644 src/mainboard/dell/e6520/hda_verb.c
create mode 100644 src/mainboard/dell/e6520/mainboard.c
diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
new file mode 100644
index 0000000000..db9f25b4ac
--- /dev/null
+++ b/src/mainboard/dell/e6520/Kconfig
@@ -0,0 +1,38 @@
+if BOARD_DELL_LATITUDE_E6520
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_10240
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6520"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6520"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0116"
+
+endif # BOARD_DELL_LATITUDE_E6520
diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
new file mode 100644
index 0000000000..25968e80e5
--- /dev/null
+++ b/src/mainboard/dell/e6520/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6520
+ bool "Latitude E6520"
diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6520/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e6520/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6520/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6520/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
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z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
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zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
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z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
new file mode 100644
index 0000000000..cfba8ef4e7
--- /dev/null
+++ b/src/mainboard/dell/e6520/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0494 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6520/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
new file mode 100644
index 0000000000..2a37091df6
--- /dev/null
+++ b/src/mainboard/dell/e6520/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e6520/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
new file mode 100644
index 0000000000..61f01816c4
--- /dev/null
+++ b/src/mainboard/dell/e6520/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
new file mode 100644
index 0000000000..d33eb3b4c5
--- /dev/null
+++ b/src/mainboard/dell/e6520/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280494, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280494),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6520/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0

View file

@ -0,0 +1,36 @@
From 49cee334bc7fe9a78b9355b5256a37984bac385a Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 26 Dec 2024 19:45:20 +0000
Subject: [PATCH 33/37] soc/intel/skylake: Don't compress FSP-S
Build systems like lbmk need to reproducibly insert
certain vendor files on release images.
Compression isn't always reproducible, and making it
so costs a lot more time than simply disabling compression.
With this change, the FSP-S module will now be inserted
without compression, which means that there will now be
about 40KB of extra space used in the flash.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/soc/intel/skylake/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 9191ed0ff8..d51ffaef7b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
+# select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
--
2.39.5

View file

@ -1,780 +0,0 @@
From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:57:07 -0700
Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5530/Kconfig | 37 ++++
src/mainboard/dell/e5530/Kconfig.name | 2 +
src/mainboard/dell/e5530/Makefile.inc | 6 +
src/mainboard/dell/e5530/acpi/ec.asl | 9 +
src/mainboard/dell/e5530/acpi/platform.asl | 12 ++
src/mainboard/dell/e5530/acpi/superio.asl | 3 +
src/mainboard/dell/e5530/acpi_tables.c | 16 ++
src/mainboard/dell/e5530/board_info.txt | 6 +
src/mainboard/dell/e5530/cmos.default | 9 +
src/mainboard/dell/e5530/cmos.layout | 88 ++++++++++
src/mainboard/dell/e5530/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e5530/devicetree.cb | 70 ++++++++
src/mainboard/dell/e5530/dsdt.asl | 30 ++++
src/mainboard/dell/e5530/early_init.c | 32 ++++
src/mainboard/dell/e5530/gma-mainboard.ads | 20 +++
src/mainboard/dell/e5530/gpio.c | 194 +++++++++++++++++++++
src/mainboard/dell/e5530/hda_verb.c | 33 ++++
src/mainboard/dell/e5530/mainboard.c | 21 +++
18 files changed, 588 insertions(+)
create mode 100644 src/mainboard/dell/e5530/Kconfig
create mode 100644 src/mainboard/dell/e5530/Kconfig.name
create mode 100644 src/mainboard/dell/e5530/Makefile.inc
create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
create mode 100644 src/mainboard/dell/e5530/board_info.txt
create mode 100644 src/mainboard/dell/e5530/cmos.default
create mode 100644 src/mainboard/dell/e5530/cmos.layout
create mode 100644 src/mainboard/dell/e5530/data.vbt
create mode 100644 src/mainboard/dell/e5530/devicetree.cb
create mode 100644 src/mainboard/dell/e5530/dsdt.asl
create mode 100644 src/mainboard/dell/e5530/early_init.c
create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e5530/gpio.c
create mode 100644 src/mainboard/dell/e5530/hda_verb.c
create mode 100644 src/mainboard/dell/e5530/mainboard.c
diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
new file mode 100644
index 0000000000..3faae4ee50
--- /dev/null
+++ b/src/mainboard/dell/e5530/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E5530
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e5530"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E5530"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+endif # BOARD_DELL_LATITUDE_E5530
diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
new file mode 100644
index 0000000000..775963204a
--- /dev/null
+++ b/src/mainboard/dell/e5530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E5530
+ bool "Latitude E5530"
diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e5530/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e5530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e5530/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e5530/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
new file mode 100644
index 0000000000..2af748cf27
--- /dev/null
+++ b/src/mainboard/dell/e5530/devicetree.cb
@@ -0,0 +1,70 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x03d003d0"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x053d inherit
+
+ device ref host_bridge on end
+ device ref peg10 off end
+ device ref igd on end
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end # WWAN Slot
+ device ref pcie_rp2 on end # SLAN Slot
+ device ref pcie_rp3 on end # ExpressCard
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
+ device ref pcie_rp6 on end # SD/MMC Card Reader
+ device ref pcie_rp7 on end # BCM5761 Ethernet
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e5530/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
new file mode 100644
index 0000000000..00fd5f6795
--- /dev/null
+++ b/src/mainboard/dell/e5530/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 0, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 0, 6 },
+ { 1, 1, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e5530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
new file mode 100644
index 0000000000..0599f13921
--- /dev/null
+++ b/src/mainboard/dell/e5530/gpio.c
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
new file mode 100644
index 0000000000..4c7c36ee05
--- /dev/null
+++ b/src/mainboard/dell/e5530/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x1028053d, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028053d),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e5530/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0

View file

@ -0,0 +1,82 @@
From 09740dc9d43a8dc24b7416b70476796515af6581 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 31 Dec 2024 01:40:42 +0000
Subject: [PATCH 34/37] soc/intel/pmc: Hardcoded poweroff after power fail
Coreboot can set the power state for power on after previous
power failure, based on the option table. On the ThinkPad T480,
we have no nvram and, due to coreboot's design, we therefore
have no option table, so the default setting is enabled.
In my testing, this seems to be that the system will turn on
after a power failure. If your ThinkPad was previously in a state
where it wouldn't turn on when plugging in the power, it'd be fine.
If your battery ran out later on, this would be triggered and
your ThinkPad would permanently turn on, when plugging in a charger,
and there is currently no way to configure this behaviour.
We currently only use the common SoC PMC code on the ThinkPad
T480, T480s and the Dell OptiPlex 3050 Micro, at the time of
this patch, and it is desirable that the system be set to power
off after power fail anyway.
In some cases, you might want the opposite, for example if you're
running a server. This will be documented on the website, for that
reason.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/soc/intel/common/block/pmc/pmclib.c | 36 +++----------------------
1 file changed, 4 insertions(+), 32 deletions(-)
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 64b9bb997c..7823775bcb 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -776,38 +776,10 @@ void pmc_clear_pmcon_sts(void)
void pmc_set_power_failure_state(const bool target_on)
{
- const unsigned int state = get_uint_option("power_on_after_fail",
- CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-
- /*
- * On the shutdown path (target_on == false), we only need to
- * update the register for MAINBOARD_POWER_STATE_PREVIOUS. For
- * all other cases, we don't write the register to avoid clob-
- * bering the value set on the boot path. This is necessary,
- * for instance, when we can't access the option backend in SMM.
- */
-
- switch (state) {
- case MAINBOARD_POWER_STATE_OFF:
- if (!target_on)
- break;
- printk(BIOS_INFO, "Set power off after power failure.\n");
- pmc_soc_set_afterg3_en(false);
- break;
- case MAINBOARD_POWER_STATE_ON:
- if (!target_on)
- break;
- printk(BIOS_INFO, "Set power on after power failure.\n");
- pmc_soc_set_afterg3_en(true);
- break;
- case MAINBOARD_POWER_STATE_PREVIOUS:
- printk(BIOS_INFO, "Keep power state after power failure.\n");
- pmc_soc_set_afterg3_en(target_on);
- break;
- default:
- printk(BIOS_WARNING, "Unknown power-failure state: %d\n", state);
- break;
- }
+ if (!target_on)
+ return;
+ printk(BIOS_INFO, "Set power off after power failure.\n");
+ pmc_soc_set_afterg3_en(false);
}
/* This function returns the highest assertion duration of the SLP_Sx assertion widths */
--
2.39.5

View file

@ -1,41 +0,0 @@
From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sun, 11 Feb 2024 19:02:20 +0200
Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
src/mainboard/hp/snb_ivb_laptops/Makefile.mk | 6 ++++++
.../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis | Bin 0 -> 129 bytes
2 files changed, 6 insertions(+)
create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
index c007bb68cd..7950abbc4e 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
# FIXME: Other variants with same size onboard RAM may exist.
SPD_SOURCES = hynix_4g
+
+ifeq ($(CONFIG_BOARD_HP_8560W),y)
+cbfs-files-y += mxm-30-sis
+mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
+mxm-30-sis-type := raw
+endif
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
new file mode 100644
index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
GIT binary patch
literal 129
zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
literal 0
HcmV?d00001
--
2.43.1

View file

@ -1,775 +0,0 @@
From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 10:23:38 -0700
Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5520/Kconfig | 37 ++++
src/mainboard/dell/e5520/Kconfig.name | 2 +
src/mainboard/dell/e5520/Makefile.inc | 5 +
src/mainboard/dell/e5520/acpi/ec.asl | 9 +
src/mainboard/dell/e5520/acpi/platform.asl | 12 ++
src/mainboard/dell/e5520/acpi/superio.asl | 3 +
src/mainboard/dell/e5520/acpi_tables.c | 16 ++
src/mainboard/dell/e5520/board_info.txt | 6 +
src/mainboard/dell/e5520/cmos.default | 9 +
src/mainboard/dell/e5520/cmos.layout | 88 ++++++++++
src/mainboard/dell/e5520/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e5520/devicetree.cb | 66 +++++++
src/mainboard/dell/e5520/dsdt.asl | 30 ++++
src/mainboard/dell/e5520/early_init.c | 32 ++++
src/mainboard/dell/e5520/gma-mainboard.ads | 20 +++
src/mainboard/dell/e5520/gpio.c | 195 +++++++++++++++++++++
src/mainboard/dell/e5520/hda_verb.c | 33 ++++
src/mainboard/dell/e5520/mainboard.c | 21 +++
18 files changed, 584 insertions(+)
create mode 100644 src/mainboard/dell/e5520/Kconfig
create mode 100644 src/mainboard/dell/e5520/Kconfig.name
create mode 100644 src/mainboard/dell/e5520/Makefile.inc
create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
create mode 100644 src/mainboard/dell/e5520/board_info.txt
create mode 100644 src/mainboard/dell/e5520/cmos.default
create mode 100644 src/mainboard/dell/e5520/cmos.layout
create mode 100644 src/mainboard/dell/e5520/data.vbt
create mode 100644 src/mainboard/dell/e5520/devicetree.cb
create mode 100644 src/mainboard/dell/e5520/dsdt.asl
create mode 100644 src/mainboard/dell/e5520/early_init.c
create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e5520/gpio.c
create mode 100644 src/mainboard/dell/e5520/hda_verb.c
create mode 100644 src/mainboard/dell/e5520/mainboard.c
diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
new file mode 100644
index 0000000000..213c54cf5c
--- /dev/null
+++ b/src/mainboard/dell/e5520/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E5520
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_6144
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e5520"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E5520"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0126"
+
+endif # BOARD_DELL_LATITUDE_E5520
diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
new file mode 100644
index 0000000000..c88913e8b3
--- /dev/null
+++ b/src/mainboard/dell/e5520/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E5520
+ bool "Latitude E5520"
diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
new file mode 100644
index 0000000000..18391d8b18
--- /dev/null
+++ b/src/mainboard/dell/e5520/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e5520/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e5520/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e5520/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
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z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
H=7E0zE^L4Z
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
new file mode 100644
index 0000000000..bef96ac14c
--- /dev/null
+++ b/src/mainboard/dell/e5520/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000218"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x049a inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e5520/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
new file mode 100644
index 0000000000..7297921546
--- /dev/null
+++ b/src/mainboard/dell/e5520/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e5520/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
new file mode 100644
index 0000000000..f76b93d9f0
--- /dev/null
+++ b/src/mainboard/dell/e5520/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
new file mode 100644
index 0000000000..e2efee3646
--- /dev/null
+++ b/src/mainboard/dell/e5520/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x1028049a, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028049a),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e5520/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0

View file

@ -0,0 +1,61 @@
From 18f4e970ebda43dd538f74398aea463a67040dd3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:36:23 +0000
Subject: [PATCH 35/37] src/intel/skylake: Disable stack overflow debug options
The option was appearing in T480/3050micro configs of lbmk,
after updating on the coreboot/next uprev for 20241206 rev8:
CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
I did some digging. See coreboot commit:
commit 51cc2bacb6b07279b97e9934d079060475481fb6
Author: Subrata Banik <subratabanik@google.com>
Date: Fri Dec 13 13:07:28 2024 +0530
soc/intel/pantherlake: Disable stack overflow debug options
Well now:
I'm disabling this behaviour on Skylake, for the same
behaviour, because I want as few behaviour changes in general,
as possible, for the rev8 release.
According to Subrata's patch, which was for Pantherlake,
without this change, stack corruption can occur on verstage
and romstage early on. Please look at that coreboot patch,
referenced above, for clarity.
I see no harm in disabling this option for Skylake, since
the behaviour that it otherwise enables was not present
before.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/skylake/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d51ffaef7b..42af82a5d8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x20400 if FSP_USES_CB_STACK
--
2.39.5

View file

@ -1,292 +0,0 @@
From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 22:51:09 +0000
Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless
I set iommu=off on the Linux cmdline.
Coreboot's current behaviour is to check whether the CPU
has vt-d support and, if it does, initialise the IOMMU.
This patch maintains the current behaviour by default, but
allows the user to turn *off* the IOMMU, even if vt-d is
supported by the host CPU.
If iommu=Disable is specified, the check will not be
performed, and the IOMMU will be left disabled. This option
has been added to all current Haswell boards, though it is
recommended to leave the IOMMU turned on in most setups.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
src/mainboard/google/beltino/cmos.layout | 5 +++++
src/mainboard/google/slippy/cmos.layout | 5 +++++
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
src/mainboard/lenovo/haswell/cmos.default | 1 +
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
src/northbridge/intel/haswell/early_init.c | 5 +++++
14 files changed, 48 insertions(+)
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
index c51001c03c..1c5c17f841 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
@@ -2,3 +2,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
+iommu=Enable
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
index efdc333fc2..c9883ea71d 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
@@ -11,6 +11,7 @@
395 4 e 4 debug_level
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+ 412 1 e 6 iommu
984 16 h 0 check_sum
# -----------------------------------------------------------------
@@ -38,6 +39,8 @@
5 0 Disable
5 1 Enable
5 2 Keep
+ 6 0 Disable
+ 6 1 Enable
# -----------------------------------------------------------------
# -----------------------------------------------------------------
diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
index c51001c03c..1c5c17f841 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.default
+++ b/src/mainboard/asrock/h81m-hds/cmos.default
@@ -2,3 +2,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
+iommu=Enable
diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
index c9ba76c78f..95ee3d36fb 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# enable or disable iommu
+412 1 e 6 iommu
+
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -52,6 +55,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index b159660aa8..8253570f19 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -2,3 +2,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
+iommu=Enable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
index c9ba76c78f..72ff9c4bee 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# turn iommu on or off
+412 1 e 6 iommu
+
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -52,6 +55,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/beltino/cmos.layout
+++ b/src/mainboard/google/beltino/cmos.layout
@@ -19,6 +19,9 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+# enable or disable iommu
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +50,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/slippy/cmos.layout
+++ b/src/mainboard/google/slippy/cmos.layout
@@ -19,6 +19,9 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+# enable or disable iommu
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +50,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
index 78d44c1415..f2c602f541 100644
--- a/src/mainboard/intel/baskingridge/cmos.layout
+++ b/src/mainboard/intel/baskingridge/cmos.layout
@@ -19,6 +19,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +49,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
index bb8626d48b..051658d757 100644
--- a/src/mainboard/lenovo/haswell/cmos.default
+++ b/src/mainboard/lenovo/haswell/cmos.default
@@ -12,3 +12,4 @@ trackpoint=Enable
backlight=Keyboard
enable_dual_graphics=Disable
usb_always_on=Disable
+iommu=Enable
diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
index 27915d3ab7..59df76b64c 100644
--- a/src/mainboard/lenovo/haswell/cmos.layout
+++ b/src/mainboard/lenovo/haswell/cmos.layout
@@ -23,6 +23,7 @@ entries
# coreboot config options: EC
411 1 e 8 first_battery
+413 1 e 14 iommu
415 1 e 1 wlan
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
@@ -72,6 +73,8 @@ enumerations
13 0 Disable
13 1 AC and battery
13 2 AC only
+14 0 Disable
+14 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
index f4047147f7..eea2c36b88 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
@@ -3,3 +3,4 @@ debug_level=Debug
nmi=Enable
power_on_after_fail=Keep
hide_ast2400=Disable
+iommu=Enable
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
index 38ba87aa45..24d39e97ee 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# enable or disable iommu
+412 1 e 6 iommu
+
# coreboot config options: mainboard
416 1 e 1 hide_ast2400
@@ -55,6 +58,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index e47deb5da6..1a7e0b1076 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <option.h>
#include "haswell.h"
@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
static void haswell_setup_iommu(void)
{
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
+ u8 enable_iommu = get_uint_option("iommu", 1);
+
+ if (!enable_iommu)
+ return;
if (capid0_a & VTD_DISABLE)
return;
--
2.39.2

View file

@ -0,0 +1,33 @@
From 8dcd86c34d92b9b17bcfe4c7c61793042dc97268 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:53:53 +0000
Subject: [PATCH 36/37] src/intel/x4x: Disable stack overflow debug
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 1803ef5733..7129aabf72 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
int
default 256
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
# This number must be equal or lower than what's reported in ACPI PCI _CRS
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
--
2.39.5

View file

@ -0,0 +1,37 @@
From 9b547c2029611793f895117a807fa2d2c22a5332 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 05:14:45 +0100
Subject: [PATCH 37/37] Conditional TBFW setting for T480/T480S
Otherwise, other boards will define it, which
might trigger the vendor download script, and
lead to a non-zero exit.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 512b326381..3d3490b35d 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
string
default MAINBOARD_PART_NUMBER
+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S
+
config LENOVO_TBFW_BIN
string "Lenovo ThunderBolt firmware bin file"
default ""
@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
Just leave this blank if you don't care about this option. It's not
useful for every ThinkPad, only certain models.
+endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S
+
endif # VENDOR_LENOVO
--
2.39.5

View file

@ -0,0 +1,153 @@
From 49204919e885dca2be45ffbaf2f5af62109ec3a7 Mon Sep 17 00:00:00 2001
From: gaspar-ilom <gasparilom@riseup.net>
Date: Thu, 6 Mar 2025 23:00:00 +0000
Subject: [PATCH 1/1] do not break building other thinkpads with the hacks for
the t480/s made Mate Kukri
still not fixing things properly but at least it should now be possible to build older thinkpads without regressions.
prior, some code was just commented or unreachable. now we make this explicit with preprocessor directives.
heads should build all boards on this coreboot version from the same coreboot tree.
Signed-off-by: gaspar-ilom <gasparilom@riseup.net>
---
src/device/pci_rom.c | 9 ++++++---
src/ec/lenovo/h8/acpi/ec.asl | 4 +++-
src/ec/lenovo/h8/bluetooth.c | 14 ++++++++++----
src/ec/lenovo/h8/wwan.c | 14 ++++++++++----
4 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index bba98d9dea..db3dbbe2ce 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -396,16 +396,19 @@ void pci_rom_ssdt(const struct device *device)
rom = cbrom;
}
-#if 0
+
+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+ const char *scope = "\\_SB.PCI0.RP01.PEGP";
+ #else
const char *scope = acpi_device_path(device);
+ #endif
if (!scope) {
printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
return;
}
-#endif
/* write _ROM method */
- acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
+ acpigen_write_scope(scope);
acpigen_write_rom((void *)rom, rom->size * 512);
acpigen_pop_len(); /* pop scope */
}
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 8f4a8e1986..f80c15106c 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -331,7 +331,9 @@ Device(EC)
#include "sleepbutton.asl"
#include "lid.asl"
#include "beep.asl"
-//#include "thermal.asl"
+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+#include "thermal.asl"
+#endif
#include "systemstatus.asl"
#include "thinkpad.asl"
}
diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
index be71a24ced..e60b6c088c 100644
--- a/src/ec/lenovo/h8/bluetooth.c
+++ b/src/ec/lenovo/h8/bluetooth.c
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// #include <southbridge/intel/common/gpio.h>
+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+#include <southbridge/intel/common/gpio.h>
+#endif
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
@@ -26,23 +28,27 @@ void h8_bluetooth_enable(int on)
*/
bool h8_has_bdc(const struct device *dev)
{
+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+ printk(BIOS_INFO, "H8: BDC detection not implemented. "
+ "Assuming BDC installed\n");
+ return true;
+ #else
struct ec_lenovo_h8_config *conf = dev->chip_info;
- if (1 || !conf->has_bdc_detection) {
+ if (!conf->has_bdc_detection) {
printk(BIOS_INFO, "H8: BDC detection not implemented. "
"Assuming BDC installed\n");
return true;
}
-#if 0
if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
printk(BIOS_INFO, "H8: BDC installed\n");
return true;
}
-#endif
printk(BIOS_INFO, "H8: BDC not installed\n");
return false;
+ #endif
}
/*
diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
index 5cdcf77406..b4f5787e01 100644
--- a/src/ec/lenovo/h8/wwan.c
+++ b/src/ec/lenovo/h8/wwan.c
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-// #include <southbridge/intel/common/gpio.h>
+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+#include <southbridge/intel/common/gpio.h>
+#endif
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
@@ -24,23 +26,27 @@ void h8_wwan_enable(int on)
*/
bool h8_has_wwan(const struct device *dev)
{
+ #if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
+ printk(BIOS_INFO, "H8: WWAN detection not implemented. "
+ "Assuming WWAN installed\n");
+ return true;
+ #else
struct ec_lenovo_h8_config *conf = dev->chip_info;
- if (1 || !conf->has_wwan_detection) {
+ if (!conf->has_wwan_detection) {
printk(BIOS_INFO, "H8: WWAN detection not implemented. "
"Assuming WWAN installed\n");
return true;
}
-#if 0
if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
printk(BIOS_INFO, "H8: WWAN installed\n");
return true;
}
-#endif
printk(BIOS_INFO, "H8: WWAN not installed\n");
return false;
+ #endif
}
/*
--
2.39.5

View file

@ -1,774 +0,0 @@
From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 4 Mar 2024 18:05:43 -0700
Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge)
---
src/mainboard/dell/e5420/Kconfig | 37 ++++
src/mainboard/dell/e5420/Kconfig.name | 2 +
src/mainboard/dell/e5420/Makefile.mk | 5 +
src/mainboard/dell/e5420/acpi/ec.asl | 9 +
src/mainboard/dell/e5420/acpi/platform.asl | 12 ++
src/mainboard/dell/e5420/acpi/superio.asl | 3 +
src/mainboard/dell/e5420/acpi_tables.c | 16 ++
src/mainboard/dell/e5420/board_info.txt | 6 +
src/mainboard/dell/e5420/cmos.default | 9 +
src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++
src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e5420/devicetree.cb | 66 +++++++
src/mainboard/dell/e5420/dsdt.asl | 30 ++++
src/mainboard/dell/e5420/early_init.c | 32 ++++
src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++
src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++
src/mainboard/dell/e5420/hda_verb.c | 33 ++++
src/mainboard/dell/e5420/mainboard.c | 21 +++
18 files changed, 584 insertions(+)
create mode 100644 src/mainboard/dell/e5420/Kconfig
create mode 100644 src/mainboard/dell/e5420/Kconfig.name
create mode 100644 src/mainboard/dell/e5420/Makefile.mk
create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl
create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl
create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl
create mode 100644 src/mainboard/dell/e5420/acpi_tables.c
create mode 100644 src/mainboard/dell/e5420/board_info.txt
create mode 100644 src/mainboard/dell/e5420/cmos.default
create mode 100644 src/mainboard/dell/e5420/cmos.layout
create mode 100755 src/mainboard/dell/e5420/data.vbt
create mode 100644 src/mainboard/dell/e5420/devicetree.cb
create mode 100644 src/mainboard/dell/e5420/dsdt.asl
create mode 100644 src/mainboard/dell/e5420/early_init.c
create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e5420/gpio.c
create mode 100644 src/mainboard/dell/e5420/hda_verb.c
create mode 100644 src/mainboard/dell/e5420/mainboard.c
diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig
new file mode 100644
index 0000000000..f4385045ae
--- /dev/null
+++ b/src/mainboard/dell/e5420/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E5420
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_6144
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e5420"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E5420"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0116"
+
+endif # BOARD_DELL_LATITUDE_E5420
diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name
new file mode 100644
index 0000000000..eb495fb705
--- /dev/null
+++ b/src/mainboard/dell/e5420/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E5420
+ bool "Latitude E5420"
diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk
new file mode 100644
index 0000000000..18391d8b18
--- /dev/null
+++ b/src/mainboard/dell/e5420/Makefile.mk
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e5420/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e5420/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e5420/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e5420/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e5420/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e5420/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e5420/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt
new file mode 100755
index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
GIT binary patch
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z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb
new file mode 100644
index 0000000000..f26413557d
--- /dev/null
+++ b/src/mainboard/dell/e5420/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000c31"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x049b inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e5420/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c
new file mode 100644
index 0000000000..7297921546
--- /dev/null
+++ b/src/mainboard/dell/e5420/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e5420/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c
new file mode 100644
index 0000000000..f76b93d9f0
--- /dev/null
+++ b/src/mainboard/dell/e5420/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c
new file mode 100644
index 0000000000..70e7c2e79a
--- /dev/null
+++ b/src/mainboard/dell/e5420/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x1028049b, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028049b),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e5420/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.44.0

View file

@ -1,66 +0,0 @@
From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 30 Mar 2024 05:57:54 +0000
Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt
mate kukri has a patch under review on coreboot that sets
sata port map to 0x7 on sff and 0xf on mt.
see: intel 8 series pch datasheet, section 13.1.35
basically, the 6 least significant bits enable the sata
slots; 1 for enable and 0 for disable. there can be up
to 6 ports. least significant bit is port 0, then next
is port 1, and so on.
coreboot currently enables ports 0, 1, 4 and 5, making this
value 0x33 (converted to binary: 00110011). sff has ports
0, 1 and 2 wired, so mate changed that to 0x7 (00000111).
on mt, the blue ports are ports 0 and 1, but the two white
ports don't work, but coreboot enables 4 and 5; it is
likely that the blue ports are in fact 0 and 1, and the
white ports are 2 and 3, but we've not tested this!
it could be that the blue ports are ports 4 and 5, and
the white ports are 2 and 3! we have not yet determined
this, but mate set it to 0xf, meaning ports 0 1 2 and 3
are enabled, in his patch under review. the chance that
it's 2, 3, 4 and 5 on the board is unlikely, but it is
theoretically possible and has not been confirmed.
therefore, for now, i will set the value to 0x3f, which
in binary is 00111111, thus enabling all 6 slots. the two
that aren't physically wired don't really matter. enabling
ports (from the pch) that electrically aren't there and
then powering on is electrically equivalent to those ports
being actually being wired, but with no devices plugged
into them. therefore, 0x3f is an effective shotgun fix.
i'll remove this patch and use mate's fix when the latter
has been tested on MT; it has already been tested on SFF.
this patch fixes the 3rd sata slot on 9020 sff, and the 3rd
and 4th sata slots on 9020 MT
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
index c0b17a15ff..7bfa6736a6 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -23,7 +23,7 @@ chip northbridge/intel/haswell
register "gen2_dec" = "0x007c0901"
register "gen3_dec" = "0x003c07e1"
register "gen4_dec" = "0x001c0901"
- register "sata_port_map" = "0x33"
+ register "sata_port_map" = "0x3f"
device pci 14.0 on end # xHCI controller
device pci 16.0 on end # Management Engine interface 1
--
2.39.2

View file

@ -0,0 +1,42 @@
From b313c1d4bae17fc6eb3a8217c503187d1cd5453d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 22 Apr 2025 10:21:59 +0100
Subject: [PATCH 1/1] hp/8300cmt: remove xhci_overcurrent_mapping
No longer needed, as per the following commit:
commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
Author: Keith Hui <buurin@gmail.com>
Date: Tue Dec 31 18:19:31 2024 -0500
sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
Removing this from the devicetree also allows the
board to compile, otherwise an error is thrown:
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
147 | .xhci_overcurrent_mapping = 0x00000c03,
| ^~~~~~~~~~~~~~~~~~~~~~~~
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
147 | .xhci_overcurrent_mapping = 0x00000c03,
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
index 3d21739b72..3a0b6d5c59 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
- register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },
--
2.39.5

View file

@ -0,0 +1,62 @@
From 281151d85240bd8a60545b6415e0f44ce6a2af33 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Tue, 29 Apr 2025 17:31:13 +0300
Subject: [PATCH] WIP: Fix build with GCC 15 as host compiler
GCC 15 now considers the unterminated-string-initialization warning as
part of -Werror by default. Coreboot compiles host utilities with the
system compiler, which results in getting this error in some files.
Mark a hexadecimal translation table in cbfstool code as "nonstring" to
avoid the warning-turned-error.
The bios log prefixes are non-null-terminated as well, but I couldn't
figure out how to mark them as non-strings. Temporarily disable the
warning with a pragma to avoid the error. That pragma causes an error on
GCC 14, so disable pragma warnings along with it to avoid that as well.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
---
src/commonlib/include/commonlib/loglevel.h | 4 ++++
util/cbfstool/common.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
index 79fbcfc6d92b..31438c945ff5 100644
--- a/src/commonlib/include/commonlib/loglevel.h
+++ b/src/commonlib/include/commonlib/loglevel.h
@@ -163,6 +163,9 @@
* When printing logs, lines should be printed with the following prefixes in
* front of them according to the BIOS_LOG_PREFIX_PATTERN printf() pattern.
*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpragmas"
+#pragma GCC diagnostic ignored "-Wunterminated-string-initialization"
#define BIOS_LOG_PREFIX_PATTERN "[%.5s] "
#define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW
static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
@@ -177,6 +180,7 @@ static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
[BIOS_DEBUG] = "DEBUG",
[BIOS_SPEW] = "SPEW ",
};
+#pragma GCC diagnostic pop
/*
* When printing to terminals supporting ANSI escape sequences, the following
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 7154bc9d5425..cb08c9e8ec11 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -192,7 +192,7 @@ uint64_t intfiletype(const char *name)
char *bintohex(uint8_t *data, size_t len)
{
- static const char translate[16] = "0123456789abcdef";
+ static const char translate[16] __attribute__((__nonstring__)) = "0123456789abcdef";
char *result = malloc(len * 2 + 1);
if (result == NULL)
--
2.49.0

View file

@ -1,54 +0,0 @@
From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 23 Feb 2024 13:33:31 +0000
Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info@minifree.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
src/northbridge/intel/haswell/gma.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6e6948b70f..48a0ba54c7 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev)
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
+static void gma_func0_disable(struct device *dev)
+{
+ /* Disable VGA decode */
+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
+}
+
static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.acpi_fill_ssdt = gma_generate_ssdt,
+ .vga_disable = gma_func0_disable,
.ops_pci = &pci_dev_ops_pci,
};
--
2.39.2

View file

@ -0,0 +1,71 @@
From ee3925486f3567b9fe45cb98a88b9acc64991127 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 29 Apr 2025 21:15:22 +0100
Subject: [PATCH 1/1] crossgcc/gmp: Add upstream fix for GCC 15
See:
https://gmplib.org/list-archives/gmp-devel/2025-January/006279.html
by default, upstream GCC-15 now defaults to -std=c23, instead
of -std=c17, which can cause some build issues.
GMP has this patch on their mailing list for GCC-15 (see link).
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
.../gmp-6.3.0_acinclude-m4-fix-std-c23.patch | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
diff --git a/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
new file mode 100644
index 0000000000..b884b62df7
--- /dev/null
+++ b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
@@ -0,0 +1,43 @@
+From b1b61bc8ab19659f0fb8c0f87edcd79ae1bfef7e Mon Sep 17 00:00:00 2001
+From: Rudi Heitbaum <rudi@heitbaum.com>
+Date: Wed, 22 Jan 2025 02:34:09 +0100
+Subject: [PATCH 1/1] acinclude.m4: fix -std=c23 build failure
+
+Add prototype to configure test function as c23 removes unprototyped
+functions.
+
+gcc-15 switched to -std=c23 by default:
+
+ https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=55e3bd376b2214e200fa76d12b67ff259b06c212
+
+As a result `configure` fails with:
+ conftest.c: In function 'f':
+ conftest.c:12:48: error: too many arguments to function 'g'; expected 0, have 6
+ 12 | for(i=0;i<1;i++){if(e(got,got,9,d[i].n)==0)h();g(i,d[i].src,d[i].n,got,d[i].want,9);if(d[i].n)h();}}
+ | ^ ~
+ conftest.c:7:6: note: declared here
+ 7 | void g(){}
+ | ^
+
+Link: https://gmplib.org/list-archives/gmp-bugs/2024-November/005550.html
+Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
+---
+ acinclude.m4 | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/acinclude.m4 b/acinclude.m4
+index 9cf9483..1eed843 100644
+--- a/acinclude.m4
++++ b/acinclude.m4
+@@ -609,7 +609,7 @@ GMP_PROG_CC_WORKS_PART([$1], [long long reliability test 1],
+
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+ typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
++void g(int,const t1 *,t1,t1 *,const t1 *,int){}
+ void h(){}
+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+--
+2.39.5
+
--
2.39.5

View file

@ -0,0 +1,54 @@
From 983835d1470dde4559d9ee58c60e65c0bb3873c2 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 29 Apr 2025 23:13:42 +0100
Subject: [PATCH 1/1] further gcc-15 fix for compiling gmp
same as the previous fix, but we needed to apply
the exact same change to the configure file, in
the appropriate place.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
...6.3.0_acinclude-m4-fix-std-c23-extra.patch | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
diff --git a/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
new file mode 100644
index 0000000000..bee0159abf
--- /dev/null
+++ b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
@@ -0,0 +1,30 @@
+From f1da82325f91ccf8f3a251c0f94388acf091c1fe Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 29 Apr 2025 23:11:25 +0100
+Subject: [PATCH 1/1] further gcc-15 -std=23 mitigation
+
+the same fix as in the previous revision, also needs
+to be applied here. this make the coreboot build process
+pass, when compiling gmp.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ configure | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configure b/configure
+index 7910aa0..bd4342d 100755
+--- a/configure
++++ b/configure
+@@ -6568,7 +6568,7 @@ if test "$gmp_prog_cc_works" = yes; then
+
+ #if defined (__GNUC__) && ! defined (__cplusplus)
+ typedef unsigned long long t1;typedef t1*t2;
+-void g(){}
++void g(int,const t1 *,t1,t1 *,const t1 *,int){}
+ void h(){}
+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
+--
+2.39.5
+
--
2.39.5

View file

@ -1,602 +0,0 @@
From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001
From: Mate Kukri <kukri.mate@gmail.com>
Date: Thu, 18 Apr 2024 20:28:45 +0100
Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.
The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 1.
Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.
This was tested to make fan control work on my OptiPlex 7020 SFF.
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
---
src/mainboard/dell/optiplex_9020/Makefile.inc | 3 +-
src/mainboard/dell/optiplex_9020/bootblock.c | 25 +-
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
src/mainboard/dell/optiplex_9020/cmos.layout | 5 +-
src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++
src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++
src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 +
7 files changed, 463 insertions(+), 22 deletions(-)
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
index 6ca2f2afaa..08e2e53577 100644
--- a/src/mainboard/dell/optiplex_9020/Makefile.inc
+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
@@ -2,4 +2,5 @@
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += bootblock.c
+ramstage-y += sch5555_ec.c
+bootblock-y += bootblock.c sch5555_ec.c
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
index 2837cf9cf1..e5e759273e 100644
--- a/src/mainboard/dell/optiplex_9020/bootblock.c
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
@@ -4,29 +4,14 @@
#include <device/pnp_ops.h>
#include <superio/smsc/sch555x/sch555x.h>
#include <southbridge/intel/lynxpoint/pch.h>
-
-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
-{
- // Clear EC-to-Host mailbox
- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
- outb(tmp, SCH555x_EMI_IOBASE + 1);
-
- // Send address and value to the EC
- sch555x_emi_write16(0, (addr1 * 2) | 0x101);
- sch555x_emi_write32(4, val | (addr2 << 16));
-
- // Wait for acknowledgement message from EC
- outb(1, SCH555x_EMI_IOBASE);
- size_t timeout = 0;
- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
-}
+#include "sch5555_ec.h"
struct ec_init_entry {
uint16_t addr;
uint8_t val;
};
-static void ec_init(void)
+static void bootblock_ec_init(void)
{
/*
* Tables from CORE_PEI
@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
- // Magic EC init
- ec_init();
+ // Perform bootblock EC initialization
+ bootblock_ec_init();
- // Magic EC init is needed for UART1 initialization to work
+ // Bootblock EC initialization is required for UART1 to work
sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index 7bccc80e51..1909abcb9f 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -3,3 +3,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
iommu=Disable
+fan_full_speed=Disable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
index 72ff9c4bee..4a1496a878 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -22,7 +22,10 @@ entries
409 2 e 5 power_on_after_fail
# turn iommu on or off
-412 1 e 6 iommu
+411 1 e 6 iommu
+
+# coreboot config options: EC
+412 1 e 1 fan_full_speed
# coreboot config options: check sums
984 16 h 0 check_sum
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
index c834fea5d3..0b7829c736 100644
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -1,7 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <bootstate.h>
+#include <cpu/x86/msr.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
+#include <option.h>
+#include <southbridge/intel/common/gpio.h>
+#include "sch5555_ec.h"
static void mainboard_enable(struct device *dev)
{
@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
+
+#define HWM_TAB_ADD_TEMP_TARGET 1
+#define HWM_TAB_PKG_POWER_ANY 0xffff
+#define CHASSIS_TYPE_UNKNOWN 0xff
+
+struct hwm_tab_entry {
+ uint16_t addr;
+ uint8_t val;
+ uint8_t flags;
+ uint16_t pkg_power;
+};
+
+struct hwm_tab_entry HWM_TAB3[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x8a, 0, 0x0010 },
+ { 0x086, 0x4c, 0, 0x0010 },
+ { 0x08a, 0x66, 0, 0x0010 },
+ { 0x08b, 0x5b, 0, 0x0010 },
+ { 0x090, 0x65, 0, 0xffff },
+ { 0x091, 0x70, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa4, 0, 0xffff },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0e, 0, 0xffff },
+ { 0x0a1, 0x0e, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x86, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x9a, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x99, 0, 0xffff },
+ { 0x280, 0xa0, 0, 0x0010 },
+ { 0x281, 0x0f, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x68, 0, 0x0010 },
+ { 0x289, 0x10, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB4[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x99, 0, 0x0020 },
+ { 0x085, 0xad, 0, 0x0010 },
+ { 0x086, 0x1c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x41, 0, 0x0010 },
+ { 0x08b, 0x76, 0, 0x0020 },
+ { 0x08b, 0x8b, 0, 0x0010 },
+ { 0x090, 0x5e, 0, 0xffff },
+ { 0x091, 0x5e, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa4, 0, 0xffff },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0a, 0, 0xffff },
+ { 0x0a1, 0x0a, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x7c, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x90, 0, 0xffff },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x28, 0, 0x0020 },
+ { 0x289, 0x0a, 0, 0x0020 },
+ { 0x288, 0x28, 0, 0x0010 },
+ { 0x289, 0x0a, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB5[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x66, 0, 0x0020 },
+ { 0x085, 0x5d, 0, 0x0010 },
+ { 0x086, 0x1c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x41, 0, 0x0010 },
+ { 0x08b, 0x76, 0, 0x0020 },
+ { 0x08b, 0x80, 0, 0x0010 },
+ { 0x090, 0x5d, 0, 0x0020 },
+ { 0x090, 0x5e, 0, 0x0010 },
+ { 0x091, 0x5e, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa3, 0, 0x0020 },
+ { 0x098, 0xa4, 0, 0x0010 },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x08, 0, 0xffff },
+ { 0x0a1, 0x0a, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x7c, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x98, 0, 0x0020 },
+ { 0x1be, 0x90, 0, 0x0010 },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x28, 0, 0x0020 },
+ { 0x289, 0x0a, 0, 0x0020 },
+ { 0x288, 0x28, 0, 0x0010 },
+ { 0x289, 0x0a, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB6[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x98, 0, 0xffff },
+ { 0x086, 0x3c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x3d, 0, 0x0010 },
+ { 0x08b, 0x44, 0, 0x0020 },
+ { 0x08b, 0x51, 0, 0x0010 },
+ { 0x090, 0x61, 0, 0xffff },
+ { 0x091, 0x6d, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0x9f, 0, 0x0020 },
+ { 0x098, 0xa4, 0, 0x0010 },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0e, 0, 0xffff },
+ { 0x0a1, 0x0e, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9b, 0, 0x0020 },
+ { 0x0b0, 0x98, 0, 0x0010 },
+ { 0x0b3, 0x9a, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x9a, 0, 0x0020 },
+ { 0x1be, 0x96, 0, 0x0010 },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x94, 0, 0x0020 },
+ { 0x289, 0x11, 0, 0x0020 },
+ { 0x288, 0x94, 0, 0x0010 },
+ { 0x289, 0x11, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+static uint8_t get_chassis_type(void)
+{
+ uint8_t gpio_chassis_type;
+
+ // Read chassis type from GPIO
+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
+ get_gpio(17) << 1 | get_gpio(1);
+
+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
+
+ // Turn it into internal chassis index
+ switch (gpio_chassis_type) {
+ case 0x08:
+ case 0x0a:
+ return 4;
+ case 0x0b:
+ return 3;
+ case 0x0c:
+ return 5;
+ case 0x0d: // SFF
+ case 0x0e:
+ case 0x0f:
+ return 6;
+ default:
+ return CHASSIS_TYPE_UNKNOWN;
+ }
+
+}
+
+static uint8_t get_temp_target(void)
+{
+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
+ if (!val)
+ val = 20;
+ return 0x95 - val;
+}
+
+static uint16_t get_pkg_power(void)
+{
+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
+ if (rapl_power_unit)
+ rapl_power_unit = 2 << (rapl_power_unit - 1);
+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
+ if (pkg_power_info / rapl_power_unit > 0x41)
+ return 32;
+ else
+ return 16;
+}
+
+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
+{
+ uint8_t temp_target = get_temp_target();
+ uint16_t pkg_power = get_pkg_power();
+
+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
+
+ for (size_t i = 0; i < size; ++i) {
+ // Skip entry if it doesn't apply for this package power
+ if (arr[i].pkg_power != pkg_power &&
+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
+ continue;
+
+ uint8_t val = arr[i].val;
+
+ // Add temp target to value if requested (current tables never do)
+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
+ val += temp_target;
+
+ // Perform write
+ ec_write(1, arr[i].addr, val);
+
+ }
+}
+
+static void sch5555_ec_hwm_init(void *arg)
+{
+ uint8_t chassis_type, saved_2fc;
+
+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
+
+ saved_2fc = ec_read(1, 0x2fc);
+ ec_write(1, 0x2fc, 0xa0);
+ ec_write(1, 0x2fd, 0x32);
+
+ chassis_type = get_chassis_type();
+
+ if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
+ } else {
+ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
+ }
+
+ // Apply HWM table based on chassis type
+ switch (chassis_type) {
+ case 3:
+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
+ break;
+ case 4:
+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
+ break;
+ case 5:
+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
+ break;
+ case 6:
+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
+ break;
+ }
+
+ // NOTE: vendor firmware applies these when "max core address" > 2
+ // i think this is always the case
+ ec_write(1, 0x9e, 0x30);
+ ec_write(1, 0xeb, ec_read(1, 0xea));
+
+ ec_write(1, 0x2fc, saved_2fc);
+
+ // Apply full speed fan config if requested or if the chassis type is unknown
+ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
+ printk(BIOS_DEBUG, "Setting full fan speed\n");
+ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
+ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
+ }
+
+ ec_read(1, 0xb8);
+
+ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
+ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
+ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
+ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
+ ec_write(1, 0x8a, 0x99);
+ ec_write(1, 0x8b, 0x47);
+ ec_write(1, 0x8c, 0x91);
+ }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
new file mode 100644
index 0000000000..a1067ac063
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <superio/smsc/sch555x/sch555x.h>
+#include "sch5555_ec.h"
+
+uint8_t ec_read(uint8_t addr1, uint16_t addr2)
+{
+ // clear ec-to-host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // send address
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
+
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
+
+ // send message to ec
+ outb(1, SCH555x_EMI_IOBASE);
+
+ // wait for ack
+ for (size_t retry = 0; retry < 0xfff; ++retry)
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
+ break;
+
+ // read result
+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
+ return inb(SCH555x_EMI_IOBASE + 4);
+}
+
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+{
+ // clear ec-to-host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // send address and value
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
+
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
+
+ // send message to ec
+ outb(1, SCH555x_EMI_IOBASE);
+
+ // wait for ack
+ for (size_t retry = 0; retry < 0xfff; ++retry)
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
+ break;
+}
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
new file mode 100644
index 0000000000..7e399e8e74
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SCH5555_EC_H__
+#define __SCH5555_EC_H__
+
+uint8_t ec_read(uint8_t addr1, uint16_t addr2);
+
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
+
+#endif
--
2.39.2

View file

@ -1,49 +0,0 @@
From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001
From: Mate Kukri <kukri.mate@gmail.com>
Date: Wed, 10 Apr 2024 20:31:35 +0100
Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device
These machines come with a TPM1.2 device by default. It is somewhat
obsolete these days, but there is no harm in enabling it.
Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
src/mainboard/dell/optiplex_9020/Kconfig | 2 ++
src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++
2 files changed, 5 insertions(+)
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
index 774a72f161..296938aa8d 100644
--- a/src/mainboard/dell/optiplex_9020/Kconfig
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
+ select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
index 7bfa6736a6..e5cbd64127 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -70,6 +70,9 @@ chip northbridge/intel/haswell
device pnp 2e.b off end # Floppy Controller
device pnp 2e.11 off end # Parallel Port
end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
end
device pci 1f.2 on end # SATA controller 1
device pci 1f.3 on end # SMBus
--
2.39.2

View file

@ -1,47 +0,0 @@
From 4ccef4fffd98071c339cb4135e2d8c805e554378 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Fri, 3 May 2024 17:45:52 +0100
Subject: [PATCH 1/1] hp/8560w: turn on wifi
according to angel pons, this gpio is WLAN_TRN_OFF#
and setting it high will make wifi work. testing with
this change as suggested by angel. see:
https://review.coreboot.org/c/coreboot/+/39398/4/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c#158
if it makes it into a libreboot release, you can assume
the fix works. right now we have this problem:
https://codeberg.org/libreboot/lbmk/issues/201
Riku reported:
[ 333.890080] atkbd serio0: Unknown key pressed (translated set 2, code 0xf8 on isa0060/serio0).
[ 333.890102] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
[ 334.104069] atkbd serio0: Unknown key released (translated set 2, code 0xf8 on isa0060/serio0).
[ 334.104090] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
The wifi stays to hardblocked in rfkill. When the wireless button
is pressed, nothing changes except for these lines in dmesg.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
index 560d668d6f..10cd11ce48 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
@@ -155,7 +155,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio37 = GPIO_LEVEL_LOW,
.gpio49 = GPIO_LEVEL_LOW,
.gpio53 = GPIO_LEVEL_HIGH,
- .gpio57 = GPIO_LEVEL_LOW,
+ .gpio57 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio61 = GPIO_LEVEL_HIGH,
};
--
2.39.2

View file

@ -1,133 +0,0 @@
From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
This should fix S3 suspend on these systems
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5420/smihandler.c | 9 +++++++++
src/mainboard/dell/e5520/smihandler.c | 9 +++++++++
src/mainboard/dell/e5530/smihandler.c | 9 +++++++++
src/mainboard/dell/e6420/smihandler.c | 9 +++++++++
src/mainboard/dell/e6430/smihandler.c | 9 +++++++++
src/mainboard/dell/e6520/smihandler.c | 9 +++++++++
src/mainboard/dell/e6530/smihandler.c | 9 +++++++++
7 files changed, 63 insertions(+)
create mode 100644 src/mainboard/dell/e5420/smihandler.c
create mode 100644 src/mainboard/dell/e5520/smihandler.c
create mode 100644 src/mainboard/dell/e5530/smihandler.c
create mode 100644 src/mainboard/dell/e6420/smihandler.c
create mode 100644 src/mainboard/dell/e6430/smihandler.c
create mode 100644 src/mainboard/dell/e6520/smihandler.c
create mode 100644 src/mainboard/dell/e6530/smihandler.c
diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5420/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5520/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e5530/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6420/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6430/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6520/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c
new file mode 100644
index 0000000000..334d7b1a5f
--- /dev/null
+++ b/src/mainboard/dell/e6530/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_sleep(slp_typ);
+}
--
2.44.0

View file

@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
rev="c247f62749b967143e58c33aa0e5e234711a628f"

View file

@ -1,203 +0,0 @@
From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
Example:
./ifdtool --nuke gbe coreboot.rom
./ifdtool --nuke bios coreboot.com
./ifdtool --nuke me coreboot.com
Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
1 file changed, 81 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 191b3216de..38132b4a28 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
+ if (!strcasecmp("Descriptor", region_type_string))
+ return 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ return 1;
+ else if (!strcasecmp("ME", region_type_string))
+ return 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ return 3;
+ else if (!strcasecmp("Platform Data", region_type_string))
+ return 4;
+ else if (!strcasecmp("Device Exp1", region_type_string))
+ return 5;
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
+ return 6;
+ else if (!strcasecmp("Reserved", region_type_string))
+ return 7;
+ else if (!strcasecmp("EC", region_type_string))
+ return 8;
+ else if (!strcasecmp("Device Exp2", region_type_string))
+ return 9;
+ else if (!strcasecmp("IE", region_type_string))
+ return 10;
+ else if (!strcasecmp("10GbE_0", region_type_string))
+ return 11;
+ else if (!strcasecmp("10GbE_1", region_type_string))
+ return 12;
+ else if (!strcasecmp("PTT", region_type_string))
+ return 15;
+ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
+ int i;
+ struct region region;
+ const struct frba *frba = find_frba(image, size);
+ if (!frba)
+ exit(EXIT_FAILURE);
+
+ region = get_region(frba, region_type);
+ if (region.size > 0) {
+ for (i = region.base; i <= region.limit; i++) {
+ if ((i + 1) > (size))
+ break;
+ image[i] = 0xFF;
+ }
+ write_image(filename, image, size);
+ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
- if (!strcasecmp("Descriptor", region_type_string))
- region_type = 0;
- else if (!strcasecmp("BIOS", region_type_string))
- region_type = 1;
- else if (!strcasecmp("ME", region_type_string))
- region_type = 2;
- else if (!strcasecmp("GbE", region_type_string))
- region_type = 3;
- else if (!strcasecmp("Platform Data", region_type_string))
- region_type = 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
- region_type = 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
- region_type = 6;
- else if (!strcasecmp("Reserved", region_type_string))
- region_type = 7;
- else if (!strcasecmp("EC", region_type_string))
- region_type = 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
- region_type = 9;
- else if (!strcasecmp("IE", region_type_string))
- region_type = 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
- region_type = 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
- region_type = 12;
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
+ fprintf(stderr, "No region specified\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_nuke = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- mode_gpr0_disable) > 1) {
+ mode_gpr0_disable + mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + mode_gpr0_disable) == 0) {
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2

View file

@ -1,47 +0,0 @@
From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2

View file

@ -1,173 +0,0 @@
From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2

View file

@ -1,28 +0,0 @@
From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
- device pci 01.0 off end
+ device pci 01.0 on end
device pci 02.0 on end # VGA
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2

View file

@ -1,39 +0,0 @@
From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 5/9] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.mk | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2

View file

@ -1,39 +0,0 @@
From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 6/9] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

View file

@ -1,36 +0,0 @@
From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2

View file

@ -1,23 +0,0 @@
From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Nov 2023 16:33:11 +0000
Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2

View file

@ -1,4 +0,0 @@
tree="dell"
tree_depend="default"
xtree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

View file

@ -0,0 +1,825 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
# CONFIG_USE_OPTION_TABLE is not set
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xEEE000
CONFIG_CONSOLE_SERIAL=y
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
CONFIG_MAX_CPUS=16
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_USE_PM_ACPI_TIMER=y
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x40000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_TTYS0_BAUD=115200
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_SMM_MODULE_STACK_SIZE=0x800
CONFIG_ACPI_BERT_SIZE=0x0
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IFD_CHIPSET="sklkbl"
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_MAX_ROOT_PORTS=24
CONFIG_PCR_BASE_ADDRESS=0xfd000000
CONFIG_CPU_BCLK_MHZ=100
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
CONFIG_CPU_XTAL_HZ=24000000
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
# CONFIG_ENABLE_SATA_TEST_MODE is not set
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_FSP_PUBLISH_MBP_HOB=y
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
CONFIG_MAX_HECI_DEVICES=5
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_HAVE_PAM0_REGISTER=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_SOC_INTEL_COMMON=y
#
# Intel SoC Common Code for IP blocks
#
CONFIG_SOC_INTEL_COMMON_BLOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
# CONFIG_USE_COREBOOT_MP_INIT is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
CONFIG_SA_ENABLE_DPR=y
CONFIG_HAVE_CAPID_A_REGISTER=y
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
#
# Intel SoC Common PCH Code
#
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
#
# Intel SoC Common coreboot stages and non-IP blocks
#
CONFIG_SOC_INTEL_COMMON_BASECODE=y
CONFIG_SOC_INTEL_COMMON_RESET=y
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
CONFIG_PAVP=y
# CONFIG_MMA is not set
CONFIG_SOC_INTEL_COMMON_NHLT=y
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
#
# CPU
#
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_PARALLEL_MP=y
CONFIG_PARALLEL_MP_AP_WORK=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_SCH555x=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
# CONFIG_GOOGLE_PVMFW_CBMEM is not set
CONFIG_UDK_BASE=y
CONFIG_UDK_2017_BINDING=y
CONFIG_UDK_2013_VERSION=2013
CONFIG_UDK_2017_VERSION=2017
CONFIG_UDK_202005_VERSION=202005
CONFIG_UDK_202111_VERSION=202111
CONFIG_UDK_202302_VERSION=202302
CONFIG_UDK_202305_VERSION=202305
CONFIG_UDK_VERSION=2017
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_HAVE_FSP_GOP=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_RUN_FSP_GOP is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_DRIVERS_EFI_FW_INFO is not set
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
CONFIG_INTEL_GMA_ACPI=y
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Skylake"
CONFIG_GFX_GMA_PCH="Sunrise_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_USB_ACPI=y
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
# end of Memory initialization
# CONFIG_STM is not set
# CONFIG_INTEL_CBNT_SUPPORT is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_ACPI_LPIT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
#
# I/O mapped, 8250-compatible
#
CONFIG_TTYS0_BASE=0x3f8
#
# Serial port base address = 0x3f8
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_LCS=3
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_ACPI_S1_NOT_SUPPORTED=y
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_ACPI_NHLT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# Vendorcode Debug Settings
#
#
# BLOB Debug Settings
#
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
# CONFIG_DISPLAY_FSP_HEADER is not set
# CONFIG_VERIFY_HOBS is not set
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
CONFIG_HAVE_DEBUG_GPIO=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y

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