diff --git a/.gitignore b/.gitignore
index d6c27f5d..4979e1f9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,8 @@
*~
*.o
+/cache/
/lbmk.err.log
+/repo/
/docs/
/pciroms/
/util/dell-flash-unlock/dell_flash_unlock
@@ -22,6 +24,8 @@
/push
/version
/versiondate
+/.version
+/.versiondate
/vendorfiles/
*me.bin
*sch5545ec.bin
@@ -31,3 +35,12 @@
/CHANGELOG
/todo.txt
/lock
+/hash/
+/dump/
+/qrun*.sh
+*.tar.*
+/m
+/f
+/r
+/e
+/xbmkpath/
diff --git a/README.md b/README.md
index 7f73a3e2..e6452dbd 100644
--- a/README.md
+++ b/README.md
@@ -1,123 +1,57 @@
Libreboot
=========
-Find libreboot documentation at
+Documentation: [libreboot.org](https://libreboot.org)\
+Support: [\#libreboot](https://web.libera.chat/#libreboot) on
+ [Libera](https://libera.chat/) IRC
-The `libreboot` project provides
-[libre](https://libreboot.org/freedom-status.html) *boot
-firmware* that initializes the hardware (e.g. memory controller, CPU,
-peripherals) on specific Intel/AMD x86 and ARM targets, which
-then starts a bootloader for your operating system. Linux/BSD are
-well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
-via [\#libreboot IRC](https://web.libera.chat/#libreboot)
-on [Libera](https://libera.chat/) IRC.
+Libreboot provides
+[libre](https://libreboot.org/freedom-status.html)
+boot firmware on
+[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
+* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
+ minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
+* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
+* ... which loads your operating system's boot loader (BSD and Linux-based
+ [systems](systems) are supported).
-Why use Libreboot?
-==================
+Why use Libreboot, and what is coreboot?
+----------------------------------------
-Why should you use *libreboot*?
-----------------------------
+A lot of users who use libre operating systems still use proprietary boot
+firmware, which often contain backdoors and bugs, hampering
+[user freedom](https://writefreesoftware.org) and
+[right to repair](https://www.eff.org/issues/right-to-repair).
-Libreboot gives you freedoms that you otherwise can't get with most other
-boot firmware. It's extremely powerful and configurable for many use cases.
+[coreboot](https://coreboot.org) provides libre boot firmware by initializing
+the hardware then running a payload. However, coreboot is notoriously difficult
+to configure and install for most non-technical users, requiring detailed
+technical knowledge of hardware.
-You have rights. The right to privacy, freedom of thought, freedom of speech
-and the right to read. In this context, Libreboot gives you these rights.
-Your freedom matters.
-[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
-Many people use proprietary (non-libre)
-boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
-Proprietary firmware often contains backdoors (more info on the FAQ), and it
-and can be buggy. The libreboot project was founded in December 2013,
-with the express purpose of making coreboot firmware accessible for
-non-technical users.
+Libreboot solves this by being **a coreboot distribution** (in the same way
+that Alpine Linux is a Linux distribution). It provides a fully automated build
+system that downloads and compiles pre-configured ROM images for supported
+motherboards, so end-users could easily fetch images to flash onto their
+devices.
-The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
-initialisation](https://doc.coreboot.org/getting_started/architecture.html).
-Coreboot is notoriously difficult to install for most non-technical users; it
-handles only basic initialization and jumps to a separate
-[payload](https://doc.coreboot.org/payloads.html) program (e.g.
-[GRUB](https://www.gnu.org/software/grub/),
-[Tianocore](https://www.tianocore.org/)), which must also be configured.
-*The libreboot software solves this problem*; it is a *coreboot distribution* with
-an automated build system (named *lbmk*) that builds complete *ROM images*, for
-more robust installation. Documentation is provided.
+Libreboot also produces documentation aimed at non-technical users and
+excellent user support via IRC.
-How does Libreboot differ from coreboot?
-========================================
-
-In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
-a *coreboot distribution*. If you want to build a ROM image from scratch, you
-otherwise have to perform expert-level configuration of coreboot, GRUB and
-whatever other software you need, to prepare the ROM image. With *libreboot*,
-you can literally download from Git or a source archive, and run `make`, and it
-will build entire ROM images. An automated build system, named `lbmk`
-(Libreboot MaKe), builds these ROM images automatically, without any user input
-or intervention required. Configuration has already been performed in advance.
-
-If you were to build regular coreboot, without using libreboot's automated
-build system, it would require a lot more intervention and decent technical
-knowledge to produce a working configuration.
-
-Regular binary releases of `libreboot` provide these
-ROM images pre-compiled, and you can simply install them, with no special
-knowledge or skill except the ability to follow installation instructions
-and run commands BSD/Linux.
-
-Project goals
-=============
-
-- *Support as much hardware as possible!* Libreboot aims to eventually
- have *maintainers* for every board supported by coreboot, at every
- point in time.
-- *Make coreboot easy to use*. Coreboot is notoriously difficult
- to install, due to an overall lack of user-focused documentation
- and support. Most people will simply give up before attempting to
- install coreboot. Libreboot's automated build system and user-friendly
- installation instructions solves this problem.
-
-Libreboot attempts to bridge this divide by providing a build system
-automating much of the coreboot image creation and customization.
-Secondly, the project produces documentation aimed at non-technical users.
-Thirdly, the project attempts to provide excellent user support via IRC.
-
-Libreboot already comes with a payload (GRUB), flashprog and other
-needed parts. Everything is fully integrated, in a way where most of
-the complicated steps that are otherwise required, are instead done
-for the user in advance.
-
-You can download ROM images for your libreboot system and install
-them without having to build anything from source. If, however, you are
-interested in building your own image, the build system makes it relatively
-easy to do so.
-
-Not a coreboot fork!
---------------------
-
-Libreboot is not a fork of coreboot. Every so often, the project
-re-bases on the latest version of coreboot, with the number of custom
-patches in use minimized. Tested, *stable* (static) releases are then provided
-in Libreboot, based on specific coreboot revisions.
-
-How to help
-===========
+Contribute
+----------
You can check bugs listed on
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
-If you spot a bug and have a fix, the website has instructions for how to send
-patches, and you can also report it. Also, this entire website is
-written in Markdown and hosted in a [separate
-repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
+You may use Codeberg pull requests to send patches with bug fixes or other
+improvements. This repository hosts the code for the main build system.
+The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
-Any and all development discussion and user support are all done on the IRC
-channel. More information is on .
+Development is also done on the IRC channel.
-LICENSE FOR THIS README
-=======================
+License for this README
+-----------------------
-It's just a README file. This README file is released under the terms of the
-Creative Commons Zero license, version 1.0 of the license, which you can
-read here:
+It's just a README file. It is released under
+[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
-
diff --git a/build b/build
deleted file mode 100755
index 19ed8875..00000000
--- a/build
+++ /dev/null
@@ -1,143 +0,0 @@
-#!/usr/bin/env sh
-# SPDX-License-Identifier: GPL-3.0-or-later
-# Copyright (c) 2014-2015,2020-2024 Leah Rowe
-# Copyright (c) 2015 Patrick "P. J." McDermott
-# Copyright (c) 2015-2016 Klemens Nanni
-# Copyright (c) 2022 Caleb La Grange
-
-set -u -e
-
-if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
- printf "You must run this in the proper work directory.\n" 1>&2
- exit 1
-fi
-
-. "include/lib.sh"
-. "include/vendor.sh"
-. "include/mrc.sh"
-
-eval "$(setvars "" vdir src_dirname srcdir _xm mode xp)"
-err="fail"
-
-linkpath="${0}"
-linkname="${linkpath##*/}"
-
-main()
-{
- [ $# -lt 1 ] && badcmd
- spath="script/$1"
-
- for g in "which git" "git config --global user.name" \
- "git config --global user.email" "git_init"; do
- eval "$g 1>/dev/null 2>/dev/null || git_err \"$g\""
- done
-
- case "${1}" in
- version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
- release) shift 1; mkrelease $@ ;;
- inject) shift 1; vendor_inject $@ ;;
- download) shift 1; vendor_download $@ ;;
- *)
- [ -f "$spath" ] || badcmd
- shift 1; "$spath" $@ || $err "excmd: $spath $@" ;;
- esac
- set -u -e # some commands disable them. turn them on!
-}
-
-git_init()
-{
- [ -L ".git" ] && return 1
- [ -e ".git" ] && return 0
- eval "$(setvars "$(date -Rud @$versiondate)" cdate _nogit)"
-
- git init || return 1
- git add -A . || return 1
- git commit -m "$projectname $version" --date "$cdate" \
- --author="xbmk " || return 1
- git tag -a "$version" -m "$projectname $version" || return 1
-}
-
-mkrelease()
-{
- export XBMK_RELEASE="y"
-
- vdir="release"
- while getopts d:m: option; do
- [ -z "$OPTARG" ] && badcmd "empty argument not allowed"
- case "$option" in
- d) vdir="$OPTARG" ;;
- m) mode="$OPTARG" ;;
- *) badcmd "invalid option '-$option'" ;;
- esac
- done
-
- vdir="$vdir/$version"
- src_dirname="${relname}_src"
- srcdir="$vdir/$src_dirname"
-
- [ -e "$vdir" ] && $err "already exists: \"$vdir\""
- mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
- git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
- touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
-
- build_release
-
- printf "\n\nDONE! Check release files under %s\n" "$vdir"
-}
-
-build_release()
-{
- _xm="build_release $vdir"
- (
- cd "$srcdir" || $err "$_xm: !cd \"$srcdir\""
- fetch_trees
- x_ mv src/docs docs
- ) || $err "can't create release files"
-
- git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
- --abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
- rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
-
- (
- cd "${srcdir%/*}" || $err "$_xm: mktarball \"$srcdir\""
- mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$_xm: mksrc"
- ) || $err "can't create src tarball"
- [ "$mode" = "src" ] && return 0
-
- touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
-
- (
- cd "$srcdir" || $err "$_xm: 2 !cd \"$srcdir\""
- ./build roms all || $err "$_xm: roms-all"
- ./build roms serprog rp2040 || $err "$_xm: rp2040"
- ./build roms serprog stm32 || $err "$_xm: stm32"
- x_ mv bin ../roms
- ) || $err "can't build rom images"
-
- rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
-}
-
-fetch_trees()
-{
- for x in $(items config/git); do
- ./update trees -f "$x" || $err "$_xm: fetch $x"
- singletree "$x" || x_ rm -Rf "src/$x/$x"
- done
- rmgit .
-}
-
-fail()
-{
- tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$tmpdir" 1>&2
- err_ "${1}"
-}
-
-tmp_cleanup()
-{
- [ "$tmpdir_was_set" = "n" ] || return 0
- rm -Rf "$tmpdir" || return 1
- rm -f lock || return 1
-}
-
-main $@
-tmp_cleanup || err_ "can't rm tmpdir upon non-zero exit: $tmpdir"
diff --git a/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch b/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch
deleted file mode 100644
index dfc684e1..00000000
--- a/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
-From: Nico Huber
-Date: Tue, 22 Jun 2021 13:49:44 +0000
-Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
-
-The null-termination of `filetypes` was added after the code was
-written, obviously resulting in NULL dereferences. As some more
-code has grown around the termination, it's hard to revert the
-regression, so let's update the code that still used the array
-length.
-
-This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
-which actually did fix something, but only one path while it broke
-two others. We should be careful with fixes, they can always break
-something else. Especially when a dumb tool triggered the patching
-it seems likely that fewer people looked into related code.
-
-Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
-Signed-off-by: Nico Huber
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
-Tested-by: build bot (Jenkins)
-Reviewed-by: Julius Werner
----
- util/cbfstool/common.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
-index e2ed38ffc4..539d0baccf 100644
---- a/util/cbfstool/common.c
-+++ b/util/cbfstool/common.c
-@@ -168,10 +168,10 @@ void print_supported_architectures(void)
-
- void print_supported_filetypes(void)
- {
-- int i, number = ARRAY_SIZE(filetypes);
-+ int i;
-
-- for (i=0; i
Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -10,10 +10,10 @@ Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index 5f5ffde588..27377b737c 100644
+index 330d8efae2..cf10343554 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
end
end
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
deleted file mode 100644
index d2bae2e4..00000000
--- a/config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
- 8MiB
-
----
- src/mainboard/apple/macbook21/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
-index cf1bc4566e..dc0df3b6d6 100644
---- a/src/mainboard/apple/macbook21/cmos.default
-+++ b/src/mainboard/apple/macbook21/cmos.default
-@@ -5,4 +5,4 @@ boot_devices=''
- boot_default=0x40
- cmos_defaults_loaded=Yes
- lpt=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
similarity index 89%
rename from config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
rename to config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
index 332b870e..0c2b080f 100644
--- a/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
+++ b/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
@@ -1,7 +1,7 @@
-From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
+From e5eab4c8043b89a325b4a28bf7da456d68475144 Mon Sep 17 00:00:00 2001
From: persmule
Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 02/37] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
register "sata_traffic_monitor" = "0"
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
similarity index 83%
rename from config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
rename to config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
index dc3a33ca..4ccde9a6 100644
--- a/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
+++ b/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
@@ -1,7 +1,7 @@
-From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
+From fd398cc10600cccce3dd4931651a5294ffebde9a Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 03/37] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@@ -23,16 +23,15 @@ Date: Thu Nov 21 21:47:31 2019 +0300
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 2e315d4521..3585cbd58b 100644
+index 732e214b32..8454f0eac0 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -15,5 +15,5 @@ trackpoint=Enable
+@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
- gfx_uma_size=224M
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
deleted file mode 100644
index 34e12a6b..00000000
--- a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
- (previously it was 8MiB)
-
----
- src/mainboard/lenovo/x60/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
-index 5c3576d1f3..88170a1aab 100644
---- a/src/mainboard/lenovo/x60/cmos.default
-+++ b/src/mainboard/lenovo/x60/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
deleted file mode 100644
index ee90dd63..00000000
--- a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
-
----
- src/mainboard/lenovo/t60/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
-index af865f16da..7f03157df7 100644
---- a/src/mainboard/lenovo/t60/cmos.default
-+++ b/src/mainboard/lenovo/t60/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
similarity index 81%
rename from config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
rename to config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
index 49f4db9b..39319d58 100644
--- a/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
+++ b/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
@@ -1,7 +1,7 @@
-From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
+From 74230d8123cb7c31afd084658720084b1a5ac5d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 04/37] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@@ -20,103 +20,105 @@ Signed-off-by: Leah Rowe
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
-index 681c40e78b..57cdcf9162 100644
+index be08e0a342..b8970efa46 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
+@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 8244071b8a..c011867916 100644
+index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
+@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 8244071b8a..c011867916 100644
+index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
+@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index 26795fe5cf..55e1e6c04e 100644
+index c896eadec1..6d1e172056 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
+@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
-index 52dbf70377..b16800ca9e 100644
+index 286fb0ae8c..5a05c73721 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
-@@ -16,4 +16,4 @@ backlight=Both
+@@ -18,4 +18,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index cf79b391e2..b66f7034dc 100644
+index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
+@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index cf79b391e2..b66f7034dc 100644
+index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
+@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index 6d1d57a795..52f303dfdb 100644
+index ef706c1303..b318ab9772 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -13,4 +13,4 @@ usb_always_on=Disable
+@@ -15,4 +15,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
-index 62715bc6ba..129b5fd121 100644
+index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/protectli/vault_cml/cmos.default
+++ b/src/mainboard/protectli/vault_cml/cmos.default
-@@ -1,3 +1,3 @@
+@@ -2,4 +2,4 @@
+
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
-index 62715bc6ba..129b5fd121 100644
+index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/system76/tgl-u/cmos.default
+++ b/src/mainboard/system76/tgl-u/cmos.default
-@@ -1,3 +1,3 @@
+@@ -2,4 +2,4 @@
+
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
deleted file mode 100644
index 35d74c75..00000000
--- a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/lenovo/t400/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index a326e315b1..b907a3e2df 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,4 +13,4 @@ power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
- hybrid_graphics_mode=Integrated Only
--gfx_uma_size=32M
-+gfx_uma_size=256M
---
-2.39.2
-
diff --git a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
similarity index 83%
rename from config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
rename to config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
index 60490608..9c00ab79 100644
--- a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
+++ b/config/coreboot/default/patches/0005-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -1,7 +1,7 @@
-From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001
-From: Leah Rowe
+From f592ac32892d7f99fa2e68504bb147e5d06184ca Mon Sep 17 00:00:00 2001
+From: Leah Rowe
Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 05/37] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@@ -16,14 +16,14 @@ Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe
---
- util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 82 insertions(+), 31 deletions(-)
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 516570e0a3..1638e1710e 100644
+index b21a89c0e1..fc91d4c239 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
-@@ -2143,6 +2143,7 @@ static void print_usage(const char *name)
+@@ -2230,6 +2230,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
@@ -31,7 +31,7 @@ index 516570e0a3..1638e1710e 100644
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
-@@ -2151,6 +2152,60 @@ static void print_usage(const char *name)
+@@ -2238,6 +2239,60 @@ static void print_usage(const char *name)
"\n");
}
@@ -92,15 +92,15 @@ index 516570e0a3..1638e1710e 100644
int main(int argc, char *argv[])
{
int opt, option_index = 0;
-@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[])
+@@ -2245,6 +2300,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
- int mode_gpr0_disable = 0, mode_gpr0_enable = 0;
- char *region_type_string = NULL, *region_fname = NULL;
- const char *layout_fname = NULL;
-@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[])
+ int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
+ char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
+ char *new_filename = NULL;
+@@ -2279,6 +2335,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index 516570e0a3..1638e1710e 100644
{0, 0, 0, 0}
};
-@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[])
+@@ -2328,35 +2385,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
@@ -146,7 +146,7 @@ index 516570e0a3..1638e1710e 100644
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[])
+@@ -2533,6 +2563,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
@@ -169,26 +169,27 @@ index 516570e0a3..1638e1710e 100644
case 'v':
print_version();
exit(EXIT_SUCCESS);
-@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[])
+@@ -2552,7 +2598,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-- (mode_gpr0_disable | mode_gpr0_enable)) > 1) {
-+ (mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) {
+- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
++ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
++ mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
-@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[])
+@@ -2561,7 +2608,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-- mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) {
-+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) +
+- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
++ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
+ mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
-@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[])
+@@ -2674,6 +2722,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
@@ -200,5 +201,5 @@ index 516570e0a3..1638e1710e 100644
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
deleted file mode 100644
index cc6abb00..00000000
--- a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/lenovo/x200/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index bb4323836e..458b3f19c5 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -12,4 +12,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-+gfx_uma_size=256M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
similarity index 85%
rename from config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
rename to config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
index bfc9231a..ee60c3c8 100644
--- a/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
+++ b/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -1,7 +1,7 @@
-From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
+From 18069af7c0c6beedfadb615cca9127e82a0d8007 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 06/37] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
similarity index 85%
rename from config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
rename to config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
index 090f2629..525bd366 100644
--- a/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
+++ b/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -1,7 +1,7 @@
-From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
+From 9563c107a4b40e66b610d7205a21590c7c181c78 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/30] Remove warning for coreboot images built without a
+Subject: [PATCH 07/37] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index a2336aa876..4f1692a873 100644
+index 5f988dac1b..516133880f 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
-@@ -49,16 +49,5 @@ distclean-payloads:
+@@ -50,16 +50,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
@@ -35,5 +35,5 @@ index a2336aa876..4f1692a873 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
deleted file mode 100644
index c4840ecc..00000000
--- a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-index 8372032119..bedad54d2a 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- power_on_after_fail=Enable
- nmi=Enable
--gfx_uma_size=64M
-+gfx_uma_size=256M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
similarity index 77%
rename from config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch
rename to config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
index 40e1ccee..bd2c56bd 100644
--- a/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch
+++ b/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
@@ -1,7 +1,7 @@
-From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
+From 7f650a19d30fe6157b150c5248d6086007323d72 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak
Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 08/37] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index 538d254ace..18e451d63c 100644
+index f54c6d22fc..b075abfd42 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
-@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
@@ -24,5 +24,5 @@ index 538d254ace..18e451d63c 100644
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
deleted file mode 100644
index 19977870..00000000
--- a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/acer/g43t-am3/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
-index 706f5dd551..e8b45ea22c 100644
---- a/src/mainboard/acer/g43t-am3/cmos.default
-+++ b/src/mainboard/acer/g43t-am3/cmos.default
-@@ -3,4 +3,4 @@ debug_level=Debug
- power_on_after_fail=Disable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=64M
-+gfx_uma_size=256M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
similarity index 58%
rename from config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch
rename to config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
index 79ee4b6c..ca3b6264 100644
--- a/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch
+++ b/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
@@ -1,7 +1,7 @@
-From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
+From 3f6f65ed6a435fe49534c8a0b5cb98c3eac71150 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 09/37] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
@@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
Signed-off-by: Leah Rowe
---
- src/mainboard/dell/e6430/cmos.default | 2 +-
+ src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
+diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
index 2a5b30f2b7..279415dfd1 100644
---- a/src/mainboard/dell/e6430/cmos.default
-+++ b/src/mainboard/dell/e6430/cmos.default
+--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
++++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
@@ -6,4 +6,4 @@ bluetooth=Enable
wwan=Enable
wlan=Enable
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
-me_state=Normal
+me_state=Disabled
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
deleted file mode 100644
index 12917ed8..00000000
--- a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Mon, 20 Dec 2021 01:29:31 +0000
-Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
- default
-
----
- src/mainboard/lenovo/x230/cmos.default | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 7314066c2b..2e315d4521 100644
---- a/src/mainboard/lenovo/x230/cmos.default
-+++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -16,3 +16,4 @@ backlight=Both
- usb_always_on=Disable
- f1_to_f12_as_primary=Enable
- me_state=Normal
-+gfx_uma_size=224M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
similarity index 96%
rename from config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
rename to config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
index e0af8372..2a7d5c17 100644
--- a/config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
+++ b/config/coreboot/default/patches/0010-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch
@@ -1,7 +1,7 @@
-From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
+From b4d48233a8d829d7285501f662d999aad898be21 Mon Sep 17 00:00:00 2001
From: Riku Viitanen
Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 10/37] mb/hp: Add Compaq Elite 8300 CMT port
Based on autoport and Z220 SuperIO code.
@@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen
---
.../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++
.../hp/compaq_elite_8300_cmt/Kconfig.name | 2 +
- .../hp/compaq_elite_8300_cmt/Makefile.inc | 7 +
+ .../hp/compaq_elite_8300_cmt/Makefile.mk | 7 +
.../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 +
.../compaq_elite_8300_cmt/acpi/platform.asl | 10 +
.../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++
@@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen
.../hp/compaq_elite_8300_cmt/cmos.default | 7 +
.../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++
.../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes
- .../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++
+ .../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++
.../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++
- .../hp/compaq_elite_8300_cmt/early_init.c | 31 +++
+ .../hp/compaq_elite_8300_cmt/early_init.c | 14 ++
.../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++
src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
.../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++
.../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++
- 18 files changed, 661 insertions(+)
+ 18 files changed, 660 insertions(+)
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
@@ -121,11 +121,11 @@ index 0000000000..bd399b1e76
@@ -0,0 +1,2 @@
+config BOARD_HP_COMPAQ_ELITE_8300_CMT
+ bool "Compaq Elite 8300 CMT"
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
+diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
new file mode 100644
index 0000000000..fb492d3583
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
@@ -353,10 +353,10 @@ HcmV?d00001
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
new file mode 100644
-index 0000000000..f4efabd792
+index 0000000000..3d21739b72
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -0,0 +1,161 @@
+@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
@@ -386,6 +386,22 @@ index 0000000000..f4efabd792
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
++ register "usb_port_config" = "{
++ { 1, 0, 0 },
++ { 1, 0, 0 },
++ { 1, 0, 1 },
++ { 1, 0, 1 },
++ { 1, 0, 2 },
++ { 1, 0, 2 },
++ { 1, 0, 3 },
++ { 1, 0, 3 },
++ { 1, 0, 4 },
++ { 1, 0, 4 },
++ { 1, 0, 6 },
++ { 1, 0, 5 },
++ { 1, 0, 5 },
++ { 1, 0, 6 }
++ }"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
@@ -405,7 +421,7 @@ index 0000000000..f4efabd792
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 on end
-+ device ref pcie_rp5 on end
++ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
+
@@ -552,10 +568,10 @@ index 0000000000..e8e2b3a3e5
+}
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
new file mode 100644
-index 0000000000..99b7891c70
+index 0000000000..8d10c6317c
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
-@@ -0,0 +1,31 @@
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include
@@ -565,23 +581,6 @@ index 0000000000..99b7891c70
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+ { 1, 0, 0 },
-+ { 1, 0, 0 },
-+ { 1, 0, 1 },
-+ { 1, 0, 1 },
-+ { 1, 0, 2 },
-+ { 1, 0, 2 },
-+ { 1, 0, 3 },
-+ { 1, 0, 3 },
-+ { 1, 0, 4 },
-+ { 1, 0, 4 },
-+ { 1, 0, 6 },
-+ { 1, 0, 5 },
-+ { 1, 0, 5 },
-+ { 1, 0, 6 },
-+};
-+
+void bootblock_mainboard_early_init(void)
+{
+ if (CONFIG(CONSOLE_SERIAL))
@@ -869,5 +868,5 @@ index 0000000000..8dbd95ef96
+ .enable_dev = mainboard_enable,
+};
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
similarity index 95%
rename from config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
rename to config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
index 81b8e839..f8c56155 100644
--- a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
+++ b/config/coreboot/default/patches/0011-nb-intel-haswell-make-IOMMU-a-runtime-option.patch
@@ -1,7 +1,7 @@
-From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001
+From a16ff494adb1f706d402a2e167d0d53c775d0897 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option
+Subject: [PATCH 11/37] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -101,16 +101,16 @@ index c9ba76c78f..95ee3d36fb 100644
checksums
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index cd4046f1ab..c974022472 100644
+index 6c4a2a1be7..8000eea8c0 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -3,3 +3,4 @@ boot_option=Fallback
- debug_level=Debug
+@@ -4,3 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
+ fan_full_speed=Disable
+iommu=Enable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
-index c9ba76c78f..72ff9c4bee 100644
+index d10ad95b23..4a1496a878 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -21,6 +21,9 @@ entries
@@ -118,12 +118,12 @@ index c9ba76c78f..72ff9c4bee 100644
409 2 e 5 power_on_after_fail
+# turn iommu on or off
-+412 1 e 6 iommu
++411 1 e 6 iommu
+
- # coreboot config options: check sums
- 984 16 h 0 check_sum
+ # coreboot config options: EC
+ 412 1 e 1 fan_full_speed
-@@ -52,6 +55,9 @@ enumerations
+@@ -55,6 +58,9 @@ enumerations
5 1 Enable
5 2 Keep
@@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
if (capid0_a & VTD_DISABLE)
return;
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
similarity index 77%
rename from config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch
rename to config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
index c8cde72e..e578d22a 100644
--- a/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch
+++ b/config/coreboot/default/patches/0012-dell-optiplex_9020-Disable-IOMMU-by-default.patch
@@ -1,7 +1,7 @@
-From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001
+From 4b0536ce7cd55eedc52d13497bea59d91e8924d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 12/37] dell/optiplex_9020: Disable IOMMU by default
Needed to make graphics cards work. Turning it on is
recommended if only using iGPU, otherwise leave it off
@@ -15,15 +15,15 @@ Signed-off-by: Leah Rowe
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 8253570f19..7bccc80e51 100644
+index 8000eea8c0..0700f971ee 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
+@@ -4,4 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
+ fan_full_speed=Disable
-iommu=Enable
+iommu=Disable
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
similarity index 85%
rename from config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
rename to config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
index bc8fd55c..89584d95 100644
--- a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
+++ b/config/coreboot/default/patches/0013-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch
@@ -1,7 +1,7 @@
-From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001
+From c8329f84b2d06581dcbeecedc38b7c4715a9cba7 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 13/37] nb/haswell: Fully disable iGPU when dGPU is used
My earlier patch disabled decode *and* disabled the iGPU itself, but
a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
-index 48a0ba54c7..f0b848852d 100644
+index f7fad3183d..1b188e92e1 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
-@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev)
+@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
{
/* Disable VGA decode */
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
@@ -47,5 +47,5 @@ index 48a0ba54c7..f0b848852d 100644
static struct device_operations gma_func0_ops = {
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
similarity index 61%
rename from config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
rename to config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
index 97f14314..70556090 100644
--- a/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
+++ b/config/coreboot/default/patches/0014-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch
@@ -1,16 +1,37 @@
-From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
+From 73dbf291631fdbae2d8e8a761c147523c8d9e65c Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
+Subject: [PATCH 14/37] ec/dell/mec5035: Add S3 suspend SMI handler
+
+This is necessary for S3 resume to work on SNB and newer Dell Latitude
+laptops. If a command isn't sent, the EC cuts power to the DIMMs,
+preventing the system from resuming. These commands were found using an
+FPGA to log all LPC bus transactions between the host and the EC and
+then narrowing down which ones were actually necessary.
+
+Interestingly, the command IDs appear to be identical to those in
+ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
+implements a similar S3 SMI handler as the one implemented in this
+commit. The Wilco EC Kconfig does suggest that its firmware is a
+modified version of Dell's usual Latitude EC firmware, so the
+similarities seem to be intentional.
+
+These similarities also identified a command to enable or disable wake
+sources like the power button and lid switch, and this was added to the
+SMI handler to disable lid wake as the system does not yet resume
+properly from a like wake with coreboot.
+
+Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
+(Haswell, not yet pushed).
Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
Signed-off-by: Nicholas Chin
---
src/ec/dell/mec5035/Makefile.mk | 1 +
src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++
- src/ec/dell/mec5035/mec5035.h | 19 +++++++++++++++++++
+ src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++
src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
- 4 files changed, 51 insertions(+)
+ 4 files changed, 54 insertions(+)
create mode 100644 src/ec/dell/mec5035/smihandler.c
diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
@@ -25,35 +46,35 @@ index 4ebdd811f9..be557e4599 100644
endif
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 68b6b2f7fb..33bf046634 100644
+index dffbb7960c..85c2ab0140 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
ec_command(CMD_RADIO_CTRL);
}
-+void mec5035_sleep_enable(void)
-+{
-+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
-+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
-+ ec_command(CMD_SLEEP_ENABLE);
-+}
-+
+void mec5035_change_wake(u8 source, enum ec_wake_change change)
+{
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
+ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
+ ec_command(CMD_ACPI_WAKEUP_CHANGE);
+}
++
++void mec5035_sleep_enable(void)
++{
++ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
++ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
++ ec_command(CMD_SLEEP_ENABLE);
++}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index fa15a9d621..069616fbc5 100644
+index 32f791cb01..8d4fded28b 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -4,6 +4,7 @@
+@@ -4,12 +4,15 @@
#define _EC_DELL_MEC5035_H_
#include
@@ -61,37 +82,46 @@ index fa15a9d621..069616fbc5 100644
#define NUM_REGISTERS 32
-@@ -29,9 +30,27 @@ enum ec_radio_state {
+ enum mec5035_cmd {
+ CMD_MOUSE_TP = 0x1a,
+ CMD_RADIO_CTRL = 0x2b,
++ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
++ CMD_SLEEP_ENABLE = 0x64,
+ CMD_CPU_OK = 0xc2,
+ };
+
+@@ -33,9 +36,28 @@ enum ec_radio_state {
RADIO_ON
};
-+#define CMD_ACPI_WAKEUP_CHANGE 0x4a
+#define ACPI_WAKEUP_NUM_ARGS 4
+enum ec_wake_change {
+ WAKE_OFF = 0,
+ WAKE_ON
+};
++
++/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
+enum ec_acpi_wake_events {
+ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */
+ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */
+ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */
+};
+
-+#define CMD_SLEEP_ENABLE 0x64
+#define SLEEP_EN_NUM_ARGS 2
+
- u8 mec5035_mouse_touchpad(u8 setting);
+ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_sleep(int slp_type);
+void mec5035_change_wake(u8 source, enum ec_wake_change change);
+void mec5035_sleep_enable(void);
++
++void mec5035_smi_sleep(int slp_type);
#endif /* _EC_DELL_MEC5035_H_ */
diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
new file mode 100644
-index 0000000000..1db834773d
+index 0000000000..958733bf97
--- /dev/null
+++ b/src/ec/dell/mec5035/smihandler.c
@@ -0,0 +1,17 @@
@@ -102,7 +132,7 @@ index 0000000000..1db834773d
+#include
+#include "mec5035.h"
+
-+void mec5035_sleep(int slp_type)
++void mec5035_smi_sleep(int slp_type)
+{
+ switch (slp_type) {
+ case ACPI_S3:
@@ -113,5 +143,5 @@ index 0000000000..1db834773d
+ }
+}
--
-2.44.0
+2.39.5
diff --git a/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
similarity index 93%
rename from config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
rename to config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
index a7af707e..9525b8ce 100644
--- a/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
+++ b/config/coreboot/default/patches/0015-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch
@@ -1,7 +1,7 @@
-From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001
+From a507fe609a2e99c95218ec430916eaf4c3cb61d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 15/37] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
deleted file mode 100644
index a71324db..00000000
--- a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
+++ /dev/null
@@ -1,203 +0,0 @@
-From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
-
-When this option is used, the region's contents are overwritten
-with all ones (0xFF).
-
-Example:
-
-./ifdtool --nuke gbe coreboot.rom
-./ifdtool --nuke bios coreboot.com
-./ifdtool --nuke me coreboot.com
-
-Rebased since the last revision update in lbmk.
-
-Signed-off-by: Leah Rowe
----
- util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
- 1 file changed, 81 insertions(+), 31 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 191b3216de..38132b4a28 100644
---- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
- " tgl - Tiger Lake\n"
- " wbg - Wellsburg\n"
- " -S | --setpchstrap Write a PCH strap\n"
-+ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n"
- " -V | --newvalue The new value to write into PCH strap specified by -S\n"
- " -v | --version: print the version\n"
- " -h | --help: print this help\n\n"
-@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
- "\n");
- }
-
-+static int
-+get_region_type_string(const char *region_type_string)
-+{
-+ if (!strcasecmp("Descriptor", region_type_string))
-+ return 0;
-+ else if (!strcasecmp("BIOS", region_type_string))
-+ return 1;
-+ else if (!strcasecmp("ME", region_type_string))
-+ return 2;
-+ else if (!strcasecmp("GbE", region_type_string))
-+ return 3;
-+ else if (!strcasecmp("Platform Data", region_type_string))
-+ return 4;
-+ else if (!strcasecmp("Device Exp1", region_type_string))
-+ return 5;
-+ else if (!strcasecmp("Secondary BIOS", region_type_string))
-+ return 6;
-+ else if (!strcasecmp("Reserved", region_type_string))
-+ return 7;
-+ else if (!strcasecmp("EC", region_type_string))
-+ return 8;
-+ else if (!strcasecmp("Device Exp2", region_type_string))
-+ return 9;
-+ else if (!strcasecmp("IE", region_type_string))
-+ return 10;
-+ else if (!strcasecmp("10GbE_0", region_type_string))
-+ return 11;
-+ else if (!strcasecmp("10GbE_1", region_type_string))
-+ return 12;
-+ else if (!strcasecmp("PTT", region_type_string))
-+ return 15;
-+ return -1;
-+}
-+
-+static void
-+nuke(const char *filename, char *image, int size, int region_type)
-+{
-+ int i;
-+ struct region region;
-+ const struct frba *frba = find_frba(image, size);
-+ if (!frba)
-+ exit(EXIT_FAILURE);
-+
-+ region = get_region(frba, region_type);
-+ if (region.size > 0) {
-+ for (i = region.base; i <= region.limit; i++) {
-+ if ((i + 1) > (size))
-+ break;
-+ image[i] = 0xFF;
-+ }
-+ write_image(filename, image, size);
-+ }
-+}
-+
- int main(int argc, char *argv[])
- {
- int opt, option_index = 0;
-@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
- int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
- int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
- int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
-+ int mode_nuke = 0;
- int mode_gpr0_disable = 0;
- char *region_type_string = NULL, *region_fname = NULL;
- const char *layout_fname = NULL;
-@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
- {"validate", 0, NULL, 't'},
- {"setpchstrap", 1, NULL, 'S'},
- {"newvalue", 1, NULL, 'V'},
-+ {"nuke", 1, NULL, 'N'},
- {0, 0, 0, 0}
- };
-
-@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
- region_fname++;
- // Descriptor, BIOS, ME, GbE, Platform
- // valid type?
-- if (!strcasecmp("Descriptor", region_type_string))
-- region_type = 0;
-- else if (!strcasecmp("BIOS", region_type_string))
-- region_type = 1;
-- else if (!strcasecmp("ME", region_type_string))
-- region_type = 2;
-- else if (!strcasecmp("GbE", region_type_string))
-- region_type = 3;
-- else if (!strcasecmp("Platform Data", region_type_string))
-- region_type = 4;
-- else if (!strcasecmp("Device Exp1", region_type_string))
-- region_type = 5;
-- else if (!strcasecmp("Secondary BIOS", region_type_string))
-- region_type = 6;
-- else if (!strcasecmp("Reserved", region_type_string))
-- region_type = 7;
-- else if (!strcasecmp("EC", region_type_string))
-- region_type = 8;
-- else if (!strcasecmp("Device Exp2", region_type_string))
-- region_type = 9;
-- else if (!strcasecmp("IE", region_type_string))
-- region_type = 10;
-- else if (!strcasecmp("10GbE_0", region_type_string))
-- region_type = 11;
-- else if (!strcasecmp("10GbE_1", region_type_string))
-- region_type = 12;
-- else if (!strcasecmp("PTT", region_type_string))
-- region_type = 15;
-- if (region_type == -1) {
-+ if ((region_type =
-+ get_region_type_string(region_type_string)) == -1) {
- fprintf(stderr, "No such region type: '%s'\n\n",
- region_type_string);
- fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
- case 't':
- mode_validate = 1;
- break;
-+ case 'N':
-+ region_type_string = strdup(optarg);
-+ if (!region_type_string) {
-+ fprintf(stderr, "No region specified\n");
-+ print_usage(argv[0]);
-+ exit(EXIT_FAILURE);
-+ }
-+ if ((region_type =
-+ get_region_type_string(region_type_string)) == -1) {
-+ fprintf(stderr, "No such region type: '%s'\n\n",
-+ region_type_string);
-+ print_usage(argv[0]);
-+ exit(EXIT_FAILURE);
-+ }
-+ mode_nuke = 1;
-+ break;
- case 'v':
- print_version();
- exit(EXIT_SUCCESS);
-@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
- if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-- mode_gpr0_disable) > 1) {
-+ mode_gpr0_disable + mode_nuke) > 1) {
- fprintf(stderr, "You may not specify more than one mode.\n\n");
- fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- exit(EXIT_FAILURE);
-@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
- if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-- mode_validate + mode_gpr0_disable) == 0) {
-+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
- fprintf(stderr, "You need to specify a mode.\n\n");
- fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- exit(EXIT_FAILURE);
-@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
- write_image(new_filename, image, size);
- }
-
-+ if (mode_nuke) {
-+ nuke(new_filename, image, size, region_type);
-+ }
-+
- if (mode_altmedisable) {
- struct fpsba *fpsba = find_fpsba(image, size);
- struct fmsba *fmsba = find_fmsba(image, size);
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
deleted file mode 100644
index 279fdad1..00000000
--- a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
- "cpu/intel/model_1067x: enable PECI"
-
-This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
-
-Enabling PECI without microcode updates loaded causes the CPUID feature set
-to become corrupted. And one consequence is broken SpeedStep. At least, that's
-my understanding looking at Intel Errata. This revert is not a fix, because
-upstream is correct (upstream assumes microcode updates). We will simply
-maintain this revert patch in Libreboot, from now on.
----
- src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index 315e7c36fc..1423fd72bc 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
- wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
- }
-
--#define IA32_PECI_CTL 0x5a0
--
- static void configure_misc(const int eist, const int tm2, const int emttm)
- {
- msr_t msr;
-@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
- msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
- wrmsr(IA32_MISC_ENABLE, msr);
- }
--
-- /* Enable PECI
-- WARNING: due to Erratum AW67 described in Intel document #318733
-- the microcode must be updated before this MSR is written to. */
-- msr = rdmsr(IA32_PECI_CTL);
-- msr.lo |= 1;
-- wrmsr(IA32_PECI_CTL, msr);
- }
-
- #define PIC_SENS_CFG 0x1aa
---
-2.39.2
-
diff --git a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
similarity index 97%
rename from config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch
rename to config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
index 8de8060f..091a15c4 100644
--- a/config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch
+++ b/config/coreboot/default/patches/0016-nb-intel-gm45-Make-DDR2-raminit-work.patch
@@ -1,7 +1,7 @@
-From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
+From 9e0a6aa376db81f9409eda92b6783a8262c1fedb Mon Sep 17 00:00:00 2001
From: Angel Pons
Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 16/37] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@@ -20,10 +20,10 @@ Signed-off-by: Angel Pons
3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index d929533d92..997f8a0e5a 100644
+index 5d9ac56606..338260ea7a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
-@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
+@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
--
-2.39.2
+2.39.5
diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
deleted file mode 100644
index 4e5f5089..00000000
--- a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
+++ /dev/null
@@ -1,173 +0,0 @@
-From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
-
-This reverts the changes in coreboot revision:
-df7aecd92643d207feaf7fd840f8835097346644
-
-While this fix is *technically correct*, the one in
-coreboot, it breaks rebooting as tested on several
-GM45 ThinkPads e.g. X200, T400, when microcode
-updates are not applied.
-
-Since November 2022, Libreboot includes microcode
-updates by default, but it tells users how to remove
-it from the ROM (with cbfstool) if they wish.
-
-Well, with Libreboot 20221214, 20230319 and 20230413,
-mitigations present in Libreboot 20220710 (which did
-not have microcode updates) do not exist.
-
-This patch, along with the other patch to remove PECI
-support (which breaks speedstep when microcode updates
-are not applied) have now been re-added to Libreboot.
-
-It is still best to use microcode updates by default.
-These patches in coreboot are not critically urgent,
-and you can use the machines with or without them,
-regardless of ucode.
-
-I'll probably re-write this and the other patch at
-some point, applying the change conditionally upon
-whether or not microcode is applied.
-
-Pragmatism is a good thing. I recommend it.
----
- src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
- src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
- src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
- src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
- src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
- 5 files changed, 16 insertions(+), 26 deletions(-)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index 1423fd72bc..d1f98ca43a 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -8,6 +8,7 @@
- #include
- #include
- #include
-+#include
-
- #define MSR_BBL_CR_CTL3 0x11e
-
-@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
- fill_processor_name(processor_name);
- printk(BIOS_INFO, "CPU: %s.\n", processor_name);
-
-+ /* Set virtualization based on Kconfig option */
-+ set_vmx_and_lock();
-+
- /* Configure C States */
- configure_c_states(quad);
-
-diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
-index bc53214310..72f40f6762 100644
---- a/src/cpu/intel/model_1067x/mp_init.c
-+++ b/src/cpu/intel/model_1067x/mp_init.c
-@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
- smm_initialize();
- }
-
--#define SMRR_SUPPORTED (1 << 11)
--
- static void per_cpu_smm_trigger(void)
- {
-- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
-- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
-- set_feature_ctrl_vmx();
-- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
-- /* We don't care if the lock is already setting
-- as our smm relocation handler is able to handle
-- setups where SMRR is not enabled here. */
-- if (ia32_ft_ctrl.lo & (1 << 0)) {
-- /* IA32_FEATURE_CONTROL locked. If we set it again we
-- get an illegal instruction. */
-- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
-- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
-- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
-- } else {
-- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
-- printk(BIOS_INFO,
-- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
-- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
-- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
-- }
-- } else {
-- set_vmx_and_lock();
-- }
--
- /* Relocate the SMM handler. */
- smm_relocate();
- }
-diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
-index 05f5f327cc..0450c2ad83 100644
---- a/src/cpu/intel/model_106cx/model_106cx_init.c
-+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
-@@ -7,6 +7,7 @@
- #include
- #include
- #include
-+#include
-
- #define HIGHEST_CLEVEL 3
- static void configure_c_states(void)
-@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
- fill_processor_name(processor_name);
- printk(BIOS_INFO, "CPU: %s.\n", processor_name);
-
-+ /* Set virtualization based on Kconfig option */
-+ set_vmx_and_lock();
-+
- /* Configure C States */
- configure_c_states();
-
-diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
-index 5bd1c32815..f3bb08cde3 100644
---- a/src/cpu/intel/model_6ex/model_6ex_init.c
-+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
-@@ -7,6 +7,7 @@
- #include
- #include
- #include
-+#include
-
- #define HIGHEST_CLEVEL 3
- static void configure_c_states(void)
-@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
- /* Setup Page Attribute Tables (PAT) */
- // TODO set up PAT
-
-+ /* Set virtualization based on Kconfig option */
-+ set_vmx_and_lock();
-+
- /* Configure C States */
- configure_c_states();
-
-diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
-index 535fb8fae7..f7b05facd2 100644
---- a/src/cpu/intel/model_6fx/model_6fx_init.c
-+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
-@@ -7,6 +7,7 @@
- #include
- #include
- #include
-+#include
-
- #define HIGHEST_CLEVEL 3
- static void configure_c_states(void)
-@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
- /* Setup Page Attribute Tables (PAT) */
- // TODO set up PAT
-
-+ /* Set virtualization based on Kconfig option */
-+ set_vmx_and_lock();
-+
- /* Configure C States */
- configure_c_states();
-
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
new file mode 100644
index 00000000..4ba74757
--- /dev/null
+++ b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
@@ -0,0 +1,240 @@
+From 6acc310c1d695d47c148296da9da189de21d58be Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Tue, 6 Aug 2024 00:50:24 +0100
+Subject: [PATCH 17/37] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+
+We add this patch:
+
+commit commit_id_here
+Author: Angel Pons
+Date: Mon May 10 22:40:59 2021 +0200
+
+ nb/intel/gm45: Make DDR2 raminit work
+
+This patch was original applied, in lbmk, only on coreboot/dell,
+separately from coreboot/default, which was wasteful because it
+meant having an entire coreboot tree just for a single board. We
+did this, because the DDR2 RCOMP fix happened to break DDR3 init
+on other boards.
+
+What *this* new patch does on top of Angel's patch, is make sure
+that their changes only apply to DDR2, while DDR3 behaviour remains
+unchanged. This means that the Dell Latitude E6400 can be supported
+in the main coreboot tree, within lbmk.
+
+Essentially, this patch restores the old behaviour, prior to applying
+Angel's patch, only when DDR3 memory is used.
+
+Signed-off-by: Leah Rowe
+---
+ src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
+ .../intel/gm45/raminit_rcomp_calibration.c | 9 +-
+ 2 files changed, 88 insertions(+), 82 deletions(-)
+
+diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
+index df8f46fbbc..433db3a68c 100644
+--- a/src/northbridge/intel/gm45/raminit.c
++++ b/src/northbridge/intel/gm45/raminit.c
+@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
+ reg = (reg & ~(0xf << 10)) | (2 << 10);
+ else
+ reg = (reg & ~(0xf << 10)) | (3 << 10);
+- reg = (reg & ~(0x7 << 5)) | (2 << 5);
++ if (spd_type == DDR2)
++ reg = (reg & ~(0x7 << 5)) | (2 << 5);
++ else
++ reg = (reg & ~(0x7 << 5)) | (3 << 5);
+ } else if (timings->mem_clock != MEM_CLOCK_1067MT) {
+ reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
+ reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
+@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
+ raminit_write_training(timings->mem_clock, dimms, s3resume);
+ }
+
+- /*
+- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
+- * after receiver enable calibration, otherwise raminit sometimes
+- * completes with non-working memory.
+- */
+- mchbar_write32(0x0530, 0x06060005);
+- mchbar_write32(0x0680, 0x06060606);
+- mchbar_write32(0x0684, 0x08070606);
+- mchbar_write32(0x0688, 0x0e0e0c0a);
+- mchbar_write32(0x068c, 0x0e0e0e0e);
+- mchbar_write32(0x0698, 0x06060606);
+- mchbar_write32(0x069c, 0x08070606);
+- mchbar_write32(0x06a0, 0x0c0c0b0a);
+- mchbar_write32(0x06a4, 0x0c0c0c0c);
+-
+- mchbar_write32(0x06c0, 0x02020202);
+- mchbar_write32(0x06c4, 0x03020202);
+- mchbar_write32(0x06c8, 0x04040403);
+- mchbar_write32(0x06cc, 0x04040404);
+- mchbar_write32(0x06d8, 0x02020202);
+- mchbar_write32(0x06dc, 0x03020202);
+- mchbar_write32(0x06e0, 0x04040403);
+- mchbar_write32(0x06e4, 0x04040404);
+-
+- mchbar_write32(0x0700, 0x02020202);
+- mchbar_write32(0x0704, 0x03020202);
+- mchbar_write32(0x0708, 0x04040403);
+- mchbar_write32(0x070c, 0x04040404);
+- mchbar_write32(0x0718, 0x02020202);
+- mchbar_write32(0x071c, 0x03020202);
+- mchbar_write32(0x0720, 0x04040403);
+- mchbar_write32(0x0724, 0x04040404);
+-
+- mchbar_write32(0x0740, 0x02020202);
+- mchbar_write32(0x0744, 0x03020202);
+- mchbar_write32(0x0748, 0x04040403);
+- mchbar_write32(0x074c, 0x04040404);
+- mchbar_write32(0x0758, 0x02020202);
+- mchbar_write32(0x075c, 0x03020202);
+- mchbar_write32(0x0760, 0x04040403);
+- mchbar_write32(0x0764, 0x04040404);
+-
+- mchbar_write32(0x0780, 0x06060606);
+- mchbar_write32(0x0784, 0x09070606);
+- mchbar_write32(0x0788, 0x0e0e0c0b);
+- mchbar_write32(0x078c, 0x0e0e0e0e);
+- mchbar_write32(0x0798, 0x06060606);
+- mchbar_write32(0x079c, 0x09070606);
+- mchbar_write32(0x07a0, 0x0d0d0c0b);
+- mchbar_write32(0x07a4, 0x0d0d0d0d);
+-
+- mchbar_write32(0x07c0, 0x06060606);
+- mchbar_write32(0x07c4, 0x09070606);
+- mchbar_write32(0x07c8, 0x0e0e0c0b);
+- mchbar_write32(0x07cc, 0x0e0e0e0e);
+- mchbar_write32(0x07d8, 0x06060606);
+- mchbar_write32(0x07dc, 0x09070606);
+- mchbar_write32(0x07e0, 0x0d0d0c0b);
+- mchbar_write32(0x07e4, 0x0d0d0d0d);
+-
+- mchbar_write32(0x0840, 0x06060606);
+- mchbar_write32(0x0844, 0x08070606);
+- mchbar_write32(0x0848, 0x0e0e0c0a);
+- mchbar_write32(0x084c, 0x0e0e0e0e);
+- mchbar_write32(0x0858, 0x06060606);
+- mchbar_write32(0x085c, 0x08070606);
+- mchbar_write32(0x0860, 0x0c0c0b0a);
+- mchbar_write32(0x0864, 0x0c0c0c0c);
+-
+- mchbar_write32(0x0880, 0x02020202);
+- mchbar_write32(0x0884, 0x03020202);
+- mchbar_write32(0x0888, 0x04040403);
+- mchbar_write32(0x088c, 0x04040404);
+- mchbar_write32(0x0898, 0x02020202);
+- mchbar_write32(0x089c, 0x03020202);
+- mchbar_write32(0x08a0, 0x04040403);
+- mchbar_write32(0x08a4, 0x04040404);
++ if (sysinfo->spd_type == DDR2) {
++ /*
++ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
++ * after receiver enable calibration, otherwise raminit sometimes
++ * completes with non-working memory.
++ */
++ mchbar_write32(0x0530, 0x06060005);
++ mchbar_write32(0x0680, 0x06060606);
++ mchbar_write32(0x0684, 0x08070606);
++ mchbar_write32(0x0688, 0x0e0e0c0a);
++ mchbar_write32(0x068c, 0x0e0e0e0e);
++ mchbar_write32(0x0698, 0x06060606);
++ mchbar_write32(0x069c, 0x08070606);
++ mchbar_write32(0x06a0, 0x0c0c0b0a);
++ mchbar_write32(0x06a4, 0x0c0c0c0c);
++
++ mchbar_write32(0x06c0, 0x02020202);
++ mchbar_write32(0x06c4, 0x03020202);
++ mchbar_write32(0x06c8, 0x04040403);
++ mchbar_write32(0x06cc, 0x04040404);
++ mchbar_write32(0x06d8, 0x02020202);
++ mchbar_write32(0x06dc, 0x03020202);
++ mchbar_write32(0x06e0, 0x04040403);
++ mchbar_write32(0x06e4, 0x04040404);
++
++ mchbar_write32(0x0700, 0x02020202);
++ mchbar_write32(0x0704, 0x03020202);
++ mchbar_write32(0x0708, 0x04040403);
++ mchbar_write32(0x070c, 0x04040404);
++ mchbar_write32(0x0718, 0x02020202);
++ mchbar_write32(0x071c, 0x03020202);
++ mchbar_write32(0x0720, 0x04040403);
++ mchbar_write32(0x0724, 0x04040404);
++
++ mchbar_write32(0x0740, 0x02020202);
++ mchbar_write32(0x0744, 0x03020202);
++ mchbar_write32(0x0748, 0x04040403);
++ mchbar_write32(0x074c, 0x04040404);
++ mchbar_write32(0x0758, 0x02020202);
++ mchbar_write32(0x075c, 0x03020202);
++ mchbar_write32(0x0760, 0x04040403);
++ mchbar_write32(0x0764, 0x04040404);
++
++ mchbar_write32(0x0780, 0x06060606);
++ mchbar_write32(0x0784, 0x09070606);
++ mchbar_write32(0x0788, 0x0e0e0c0b);
++ mchbar_write32(0x078c, 0x0e0e0e0e);
++ mchbar_write32(0x0798, 0x06060606);
++ mchbar_write32(0x079c, 0x09070606);
++ mchbar_write32(0x07a0, 0x0d0d0c0b);
++ mchbar_write32(0x07a4, 0x0d0d0d0d);
++
++ mchbar_write32(0x07c0, 0x06060606);
++ mchbar_write32(0x07c4, 0x09070606);
++ mchbar_write32(0x07c8, 0x0e0e0c0b);
++ mchbar_write32(0x07cc, 0x0e0e0e0e);
++ mchbar_write32(0x07d8, 0x06060606);
++ mchbar_write32(0x07dc, 0x09070606);
++ mchbar_write32(0x07e0, 0x0d0d0c0b);
++ mchbar_write32(0x07e4, 0x0d0d0d0d);
++
++ mchbar_write32(0x0840, 0x06060606);
++ mchbar_write32(0x0844, 0x08070606);
++ mchbar_write32(0x0848, 0x0e0e0c0a);
++ mchbar_write32(0x084c, 0x0e0e0e0e);
++ mchbar_write32(0x0858, 0x06060606);
++ mchbar_write32(0x085c, 0x08070606);
++ mchbar_write32(0x0860, 0x0c0c0b0a);
++ mchbar_write32(0x0864, 0x0c0c0c0c);
++
++ mchbar_write32(0x0880, 0x02020202);
++ mchbar_write32(0x0884, 0x03020202);
++ mchbar_write32(0x0888, 0x04040403);
++ mchbar_write32(0x088c, 0x04040404);
++ mchbar_write32(0x0898, 0x02020202);
++ mchbar_write32(0x089c, 0x03020202);
++ mchbar_write32(0x08a0, 0x04040403);
++ mchbar_write32(0x08a4, 0x04040404);
++ }
+
+ igd_compute_ggc(sysinfo);
+
+diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+index b74765fd9c..5d4505e063 100644
+--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
++++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
+ reg = mchbar_read32(0x518);
+ lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
+ lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
+- if (i == 1) {
++ if ((i == 1) && (ddr_type == DDR2)) {
+ magic_comp[0] = (reg >> 8) & 0x3f;
+ magic_comp[1] = (reg >> 0) & 0x3f;
+ }
+@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
+ }
+ mchbar += 0x0040;
+ }
+-
+- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
++ if (ddr_type == DDR2) {
++ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
++ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
++ }
+ }
+--
+2.39.5
+
diff --git a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
similarity index 82%
rename from config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
rename to config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
index f64743a5..1cf7c0ac 100644
--- a/config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
+++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
@@ -1,7 +1,7 @@
-From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
+From 7461210ecc7c8e41f3f941bd5ce7943e5f66c711 Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 18/37] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin
2 files changed, 7 insertions(+)
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 034de4be2b..4cb16af697 100644
+index 417d95fd5d..6fe1b1c456 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
-@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
@@ -33,10 +33,10 @@ index 034de4be2b..4cb16af697 100644
default "dell/e6400"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index 2a266b9771..2432c9d78e 100644
+index fef0d735b3..fc5df8b11a 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
+@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
if NORTHBRIDGE_INTEL_GM45
@@ -48,5 +48,5 @@ index 2a266b9771..2432c9d78e 100644
select VBOOT_STARTS_IN_BOOTBLOCK
--
-2.45.1
+2.39.5
diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
new file mode 100644
index 00000000..2edfaae3
--- /dev/null
+++ b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
@@ -0,0 +1,52 @@
+From a683dffd774dbbe25cc77c0f7d3853232c17c2bf Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 12 Aug 2024 02:15:24 +0100
+Subject: [PATCH 19/37] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+
+set it to 96MHz. fixes the following build error when
+building for x4x boards e.g. gigabyte ga-g41m-es2l:
+
+hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
+make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
+
+this error was introduced when merging coreboot/dell
+into coreboot/default in lbmk. nicholas chin's fix in lbmk
+was as follows:
+
+commit 8629873a6043067affc137be275b7aa69cb1f10c
+Author: Nicholas Chin
+Date: Mon May 20 10:46:25 2024 -0600
+
+ Fix E6400 display issue with 1440 x 900 panel
+
+this currently corresponds to the patch in lbmk,
+as of 12 august 2024:
+
+0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
+
+The assumption prior to Nicholas's fix was 96MHz, so set
+it accordingly on x4x northbridge.
+
+Signed-off-by: Leah Rowe
+---
+ src/northbridge/intel/x4x/Kconfig | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
+index 097e11126c..6430319f6a 100644
+--- a/src/northbridge/intel/x4x/Kconfig
++++ b/src/northbridge/intel/x4x/Kconfig
+@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
+
+ if NORTHBRIDGE_INTEL_X4X
+
++config INTEL_GMA_DPLL_REF_FREQ
++ int
++ default 96000000
++
+ config CBFS_SIZE
+ default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
+
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
deleted file mode 100644
index fecaf88a..00000000
--- a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
+++ /dev/null
@@ -1,826 +0,0 @@
-From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
-
-Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
-is based on the autoport output with some manual tweaks. The flash is
-8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
-can also be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-Working:
-- Libgfxinit
-- USB EHCI debug (left side usb port is HCD index 2, middle port on the
- right side is HCD index 1)
-- Keyboard
-- Touchpad/trackpoint
-- ExpressCard
-- Audio
-- Ethernet
-- SD card reader
-- mPCIe WiFi
-- SeaBIOS 1.16.2
-- edk2 (MrChromebox' fork, uefipayload_202306)
-- Internal flashing using dell-flash-unlock
-
-Not working:
-- S3 suspend: Possibly EC related
-- Physical wireless switch - this triggers an SMI handler in the vendor
- firmware which sends commands to the EC to enable/disable wireless
- devices
-- Battery reporting - needs ACPI code for the EC
-- Brightness hotkeys - probably EC related
-
-Unknown/untested:
-- Dock
-- eSATA
-- TPM
-- dGPU on non-UMA model
-- Bluetooth module (not included on my system)
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e6430/Kconfig | 44 +++++
- src/mainboard/dell/e6430/Kconfig.name | 2 +
- src/mainboard/dell/e6430/Makefile.inc | 6 +
- src/mainboard/dell/e6430/acpi/ec.asl | 9 +
- src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
- src/mainboard/dell/e6430/acpi/superio.asl | 3 +
- src/mainboard/dell/e6430/acpi_tables.c | 16 ++
- src/mainboard/dell/e6430/board_info.txt | 6 +
- src/mainboard/dell/e6430/cmos.default | 9 +
- src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
- src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++
- src/mainboard/dell/e6430/dsdt.asl | 30 ++++
- src/mainboard/dell/e6430/early_init.c | 32 ++++
- src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
- src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
- src/mainboard/dell/e6430/hda_verb.c | 33 ++++
- src/mainboard/dell/e6430/mainboard.c | 21 +++
- 18 files changed, 593 insertions(+)
- create mode 100644 src/mainboard/dell/e6430/Kconfig
- create mode 100644 src/mainboard/dell/e6430/Kconfig.name
- create mode 100644 src/mainboard/dell/e6430/Makefile.inc
- create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6430/board_info.txt
- create mode 100644 src/mainboard/dell/e6430/cmos.default
- create mode 100644 src/mainboard/dell/e6430/cmos.layout
- create mode 100644 src/mainboard/dell/e6430/data.vbt
- create mode 100644 src/mainboard/dell/e6430/devicetree.cb
- create mode 100644 src/mainboard/dell/e6430/dsdt.asl
- create mode 100644 src/mainboard/dell/e6430/early_init.c
- create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6430/gpio.c
- create mode 100644 src/mainboard/dell/e6430/hda_verb.c
- create mode 100644 src/mainboard/dell/e6430/mainboard.c
-
-diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
-new file mode 100644
-index 0000000000..e4c799803e
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig
-@@ -0,0 +1,44 @@
-+if BOARD_DELL_LATITUDE_E6430
-+
-+config BOARD_SPECIFIC_OPTIONS
-+ def_bool y
-+ select BOARD_ROMSIZE_KB_12288
-+ select EC_ACPI
-+ select EC_DELL_MEC5035
-+ select GFX_GMA_PANEL_1_ON_LVDS
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select HAVE_CMOS_DEFAULT
-+ select HAVE_OPTION_TABLE
-+ select INTEL_GMA_HAVE_VBT
-+ select INTEL_INT15
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+ select SERIRQ_CONTINUOUS_MODE
-+ select SOUTHBRIDGE_INTEL_C216
-+ select SYSTEM_TYPE_LAPTOP
-+ select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+ default 60
-+
-+config MAINBOARD_DIR
-+ default "dell/e6430"
-+
-+config MAINBOARD_PART_NUMBER
-+ default "Latitude E6430"
-+
-+config PS2K_EISAID
-+ default "PNP0303"
-+
-+config PS2M_EISAID
-+ default "PNP0F13"
-+
-+config USBDEBUG_HCD_INDEX
-+ default 2
-+
-+config VGA_BIOS_ID
-+ default "8086,0166"
-+
-+endif
-diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
-new file mode 100644
-index 0000000000..f866b03585
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6430
-+ bool "Latitude E6430"
-diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+ Name (_HID, EISAID("PNP0C09"))
-+ Name (_UID, 0)
-+ Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+ /* FIXME: EC support */
-+ Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+ /* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+/* FIXME: check this function. */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+ /* The lid is open by default. */
-+ gnvs->lids = 1;
-+
-+ /* Temperature at which OS will shutdown */
-+ gnvs->tcrt = 100;
-+ /* Temperature at which OS will throttle CPU */
-+ gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
-new file mode 100644
-index 0000000000..4601a4aaba
---- /dev/null
-+++ b/src/mainboard/dell/e6430/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
-new file mode 100644
-index 0000000000..2a5b30f2b7
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Normal
-diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0 120 r 0 reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384 1 e 4 boot_option
-+388 4 h 0 reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395 4 e 6 debug_level
-+
-+#400 8 r 0 reserved for century byte
-+
-+# coreboot config options: southbridge
-+408 1 e 1 nmi
-+409 2 e 7 power_on_after_fail
-+411 1 e 9 sata_mode
-+
-+# coreboot config options: EC
-+412 1 e 1 bluetooth
-+413 1 e 1 wwan
-+414 1 e 1 wlan
-+
-+# coreboot config options: ME
-+424 1 e 14 me_state
-+425 2 h 0 me_state_prev
-+
-+# coreboot config options: northbridge
-+432 3 e 11 gfx_uma_size
-+435 2 e 12 hybrid_graphics_mode
-+440 8 h 0 volume
-+
-+# VBOOT
-+448 128 r 0 vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896 32 r 0 mrc_scrambler_seed
-+928 32 r 0 mrc_scrambler_seed_s3
-+960 16 r 0 mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984 16 h 0 check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value text
-+1 0 Disable
-+1 1 Enable
-+2 0 Enable
-+2 1 Disable
-+4 0 Fallback
-+4 1 Normal
-+6 0 Emergency
-+6 1 Alert
-+6 2 Critical
-+6 3 Error
-+6 4 Warning
-+6 5 Notice
-+6 6 Info
-+6 7 Debug
-+6 8 Spew
-+7 0 Disable
-+7 1 Enable
-+7 2 Keep
-+9 0 AHCI
-+9 1 Compatible
-+11 0 32M
-+11 1 64M
-+11 2 96M
-+11 3 128M
-+11 4 160M
-+11 5 192M
-+11 6 224M
-+14 0 Normal
-+14 1 Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
-GIT binary patch
-literal 6144
-zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp
-zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
-zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
-zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
-zIdrG4zSq6a*B6
-zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu
-zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T
-zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz
-z)}lBfx8o(*hgal&)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ
-zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBXmV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F
-zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P
-z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J
-zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r
-zYCPKK+S_PdhGTnR+18g0GR_nHOE`gieuP-A>69j*W0
-z>h~9>kwTD6>nL4
-zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sGp0XopwxoS
-z0g?6TPW!DCql9>N1GN_$T-UVr&HErC5juykd~Sxy
-zq!PK|<^jJ^DuQ9)7pt`
-z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
-ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
-z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
-zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{
-z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
-qS
-+
-+DefinitionBlock(
-+ "dsdt.aml",
-+ "DSDT",
-+ ACPI_DSDT_REV_2,
-+ OEM_ID,
-+ ACPI_TABLE_CREATOR,
-+ 0x20141018 /* OEM revision */
-+)
-+{
-+ #include
-+ #include "acpi/platform.asl"
-+ #include
-+ #include
-+ #include
-+ #include
-+
-+ Device (\_SB.PCI0)
-+ {
-+ #include
-+ #include
-+ #include
-+ }
-+}
-diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
-new file mode 100644
-index 0000000000..d882c3d78b
---- /dev/null
-+++ b/src/mainboard/dell/e6430/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include
-+#include
-+#include
-+#include
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+ { 1, 1, 0 },
-+ { 1, 1, 0 },
-+ { 1, 1, 1 },
-+ { 1, 1, 1 },
-+ { 1, 0, 2 },
-+ { 1, 1, 2 },
-+ { 1, 1, 3 },
-+ { 1, 1, 3 },
-+ { 1, 1, 4 },
-+ { 1, 1, 4 },
-+ { 1, 1, 5 },
-+ { 1, 1, 5 },
-+ { 1, 2, 6 },
-+ { 1, 2, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+ | COMB_LPC_EN | COMA_LPC_EN);
-+ mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
-new file mode 100644
-index 0000000000..1310830c8e
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+ ports : constant Port_List :=
-+ (
-+ HDMI1, -- mainboard HDMI
-+ DP2, -- dock DP
-+ DP3, -- dock DP
-+ Analog, --mainboard VGA
-+ LVDS,
-+ others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+ .gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
-new file mode 100644
-index 0000000000..56ada95c58
---- /dev/null
-+++ b/src/mainboard/dell/e6430/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
-+ 0x10280534, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x10280534),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
---- /dev/null
-+++ b/src/mainboard/dell/e6430/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+ /* FIXME: fix these values. */
-+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+ GMA_INT15_PANEL_FIT_DEFAULT,
-+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+ .enable_dev = mainboard_enable,
-+};
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
new file mode 100644
index 00000000..a0068142
--- /dev/null
+++ b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
@@ -0,0 +1,243 @@
+From a48ba23bb4a24730fa49b5a10b56c9de873dea8a Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Thu, 26 Sep 2024 19:48:26 -0600
+Subject: [PATCH 20/37] mb/dell: Convert E6400 into a variant
+
+All the GM45 Dell Latitudes should be nearly identical, so convert the
+E6400 port into a variant so that future ports for the other systems can
+share code with each other.
+
+Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/e6400/Makefile.mk | 10 --------
+ .../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++-----
+ .../{e6400 => gm45_latitude}/Kconfig.name | 0
+ src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++
+ .../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0
+ .../acpi/ich9_pci_irqs.asl | 0
+ .../{e6400 => gm45_latitude}/acpi/superio.asl | 0
+ .../dell/{e6400 => gm45_latitude}/blc.c | 0
+ .../{e6400 => gm45_latitude}/board_info.txt | 0
+ .../dell/{e6400 => gm45_latitude}/bootblock.c | 0
+ .../{e6400 => gm45_latitude}/cmos.default | 0
+ .../dell/{e6400 => gm45_latitude}/cmos.layout | 0
+ .../dell/{e6400 => gm45_latitude}/cstates.c | 0
+ .../{e6400 => gm45_latitude}/devicetree.cb | 1 -
+ .../dell/{e6400 => gm45_latitude}/dsdt.asl | 0
+ .../dell/{e6400 => gm45_latitude}/mainboard.c | 0
+ .../dell/{e6400 => gm45_latitude}/romstage.c | 0
+ .../variants}/e6400/data.vbt | Bin
+ .../variants}/e6400/gma-mainboard.ads | 0
+ .../{ => gm45_latitude/variants}/e6400/gpio.c | 0
+ .../variants}/e6400/hda_verb.c | 0
+ .../variants/e6400/overridetree.cb | 7 ++++++
+ 22 files changed, 34 insertions(+), 17 deletions(-)
+ delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
+ create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
+ rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
+ rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
+ rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
+ rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
+ rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
+
+diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
+deleted file mode 100644
+index ca3a82db48..0000000000
+--- a/src/mainboard/dell/e6400/Makefile.mk
++++ /dev/null
+@@ -1,10 +0,0 @@
+-## SPDX-License-Identifier: GPL-2.0-only
+-
+-bootblock-y += bootblock.c
+-
+-romstage-y += gpio.c
+-
+-ramstage-y += cstates.c
+-ramstage-y += blc.c
+-
+-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
+similarity index 64%
+rename from src/mainboard/dell/e6400/Kconfig
+rename to src/mainboard/dell/gm45_latitude/Kconfig
+index 6fe1b1c456..ba76fb6e8c 100644
+--- a/src/mainboard/dell/e6400/Kconfig
++++ b/src/mainboard/dell/gm45_latitude/Kconfig
+@@ -1,9 +1,7 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+
+-if BOARD_DELL_E6400
+-
+-config BOARD_SPECIFIC_OPTIONS
+- def_bool y
++config BOARD_DELL_GM45_LATITUDE_COMMON
++ def_bool n
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_P
+ select NORTHBRIDGE_INTEL_GM45
+@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
+ select INTEL_GMA_HAVE_VBT
+ select EC_DELL_MEC5035
+
++
++config BOARD_DELL_E6400
++ select BOARD_DELL_GM45_LATITUDE_COMMON
++
++if BOARD_DELL_GM45_LATITUDE_COMMON
++
+ config INTEL_GMA_DPLL_REF_FREQ
+ default 100000000
+
+ config MAINBOARD_DIR
+- default "dell/e6400"
++ default "dell/gm45_latitude"
+
+ config MAINBOARD_PART_NUMBER
+ default "Latitude E6400" if BOARD_DELL_E6400
+
++config OVERRIDE_DEVICETREE
++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
++
++config VARIANT_DIR
++ default "e6400" if BOARD_DELL_E6400
++
+ config USBDEBUG_HCD_INDEX
+ default 1
+
+ config CBFS_SIZE
+ default 0x1A0000
+
+-endif # BOARD_DELL_E6400
++endif # BOARD_DELL_GM45_LATITUDE_COMMON
+diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
+similarity index 100%
+rename from src/mainboard/dell/e6400/Kconfig.name
+rename to src/mainboard/dell/gm45_latitude/Kconfig.name
+diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
+new file mode 100644
+index 0000000000..5295d5be22
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
+@@ -0,0 +1,11 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++bootblock-y += bootblock.c
++
++romstage-y += variants/$(VARIANT_DIR)/gpio.c
++
++ramstage-y += cstates.c
++ramstage-y += blc.c
++ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
++
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
+similarity index 100%
+rename from src/mainboard/dell/e6400/acpi/ec.asl
+rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
+diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
+similarity index 100%
+rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
+rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
+diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
+similarity index 100%
+rename from src/mainboard/dell/e6400/acpi/superio.asl
+rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
+diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/blc.c
+rename to src/mainboard/dell/gm45_latitude/blc.c
+diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
+similarity index 100%
+rename from src/mainboard/dell/e6400/board_info.txt
+rename to src/mainboard/dell/gm45_latitude/board_info.txt
+diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/bootblock.c
+rename to src/mainboard/dell/gm45_latitude/bootblock.c
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
+similarity index 100%
+rename from src/mainboard/dell/e6400/cmos.default
+rename to src/mainboard/dell/gm45_latitude/cmos.default
+diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
+similarity index 100%
+rename from src/mainboard/dell/e6400/cmos.layout
+rename to src/mainboard/dell/gm45_latitude/cmos.layout
+diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/cstates.c
+rename to src/mainboard/dell/gm45_latitude/cstates.c
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
+similarity index 98%
+rename from src/mainboard/dell/e6400/devicetree.cb
+rename to src/mainboard/dell/gm45_latitude/devicetree.cb
+index e9f3915d17..76dae87153 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
++++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
+@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
+ register "pci_mmio_size" = "2048"
+
+ device domain 0 on
+- subsystemid 0x1028 0x0233 inherit
+ ops gm45_pci_domain_ops
+
+ device pci 00.0 on end # host bridge
+diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
+similarity index 100%
+rename from src/mainboard/dell/e6400/dsdt.asl
+rename to src/mainboard/dell/gm45_latitude/dsdt.asl
+diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/mainboard.c
+rename to src/mainboard/dell/gm45_latitude/mainboard.c
+diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/romstage.c
+rename to src/mainboard/dell/gm45_latitude/romstage.c
+diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
+similarity index 100%
+rename from src/mainboard/dell/e6400/data.vbt
+rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
+diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
+similarity index 100%
+rename from src/mainboard/dell/e6400/gma-mainboard.ads
+rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/gpio.c
+rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
+diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
+similarity index 100%
+rename from src/mainboard/dell/e6400/hda_verb.c
+rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
+new file mode 100644
+index 0000000000..acc34a2252
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
+@@ -0,0 +1,7 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++chip northbridge/intel/gm45
++ device domain 0 on
++ subsystemid 0x1028 0x0233 inherit
++ end
++end
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
new file mode 100644
index 00000000..af893982
--- /dev/null
+++ b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
@@ -0,0 +1,332 @@
+From b87e6774f0407ea48610c83ea54ab6a4b4a78a24 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Thu, 26 Sep 2024 19:51:25 -0600
+Subject: [PATCH 21/37] mb/dell/gm45_latitudes: Add E4300 variant
+
+Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/gm45_latitude/Kconfig | 5 +
+ src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
+ .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
+ .../variants/e4300/gma-mainboard.ads | 17 +++
+ .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
+ .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
+ .../variants/e4300/overridetree.cb | 10 ++
+ 7 files changed, 210 insertions(+)
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
+ create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
+
+diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
+index ba76fb6e8c..144f9bcdf0 100644
+--- a/src/mainboard/dell/gm45_latitude/Kconfig
++++ b/src/mainboard/dell/gm45_latitude/Kconfig
+@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
+ config BOARD_DELL_E6400
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
++config BOARD_DELL_E4300
++ select BOARD_DELL_GM45_LATITUDE_COMMON
++
+ if BOARD_DELL_GM45_LATITUDE_COMMON
+
+ config INTEL_GMA_DPLL_REF_FREQ
+@@ -31,12 +34,14 @@ config MAINBOARD_DIR
+
+ config MAINBOARD_PART_NUMBER
+ default "Latitude E6400" if BOARD_DELL_E6400
++ default "Latitude E4300" if BOARD_DELL_E4300
+
+ config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+ config VARIANT_DIR
+ default "e6400" if BOARD_DELL_E6400
++ default "e4300" if BOARD_DELL_E4300
+
+ config USBDEBUG_HCD_INDEX
+ default 1
+diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
+index aefe777109..4dc95f46be 100644
+--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
++++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
+@@ -1,4 +1,7 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+
++config BOARD_DELL_E4300
++ bool "Latitude E4300"
++
+ config BOARD_DELL_E6400
+ bool "Latitude E6400"
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
+GIT binary patch
+literal 3881
+zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
+zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
+zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!?
+zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
+z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
+z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^
+z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
+z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
+zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
+z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7
+zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
+zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
+zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf!
+zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
+new file mode 100644
+index 0000000000..b50f8da0b5
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
+@@ -0,0 +1,138 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++ .gpio0 = GPIO_MODE_NATIVE,
++ .gpio1 = GPIO_MODE_GPIO,
++ .gpio2 = GPIO_MODE_GPIO,
++ .gpio3 = GPIO_MODE_GPIO,
++ .gpio4 = GPIO_MODE_GPIO,
++ .gpio5 = GPIO_MODE_GPIO,
++ .gpio6 = GPIO_MODE_GPIO,
++ .gpio7 = GPIO_MODE_GPIO,
++ .gpio8 = GPIO_MODE_GPIO,
++ .gpio9 = GPIO_MODE_NATIVE,
++ .gpio10 = GPIO_MODE_NATIVE,
++ .gpio11 = GPIO_MODE_NATIVE,
++ .gpio12 = GPIO_MODE_NATIVE,
++ .gpio13 = GPIO_MODE_GPIO,
++ .gpio14 = GPIO_MODE_GPIO,
++ .gpio15 = GPIO_MODE_NATIVE,
++ .gpio16 = GPIO_MODE_NATIVE,
++ .gpio17 = GPIO_MODE_GPIO,
++ .gpio18 = GPIO_MODE_GPIO,
++ .gpio19 = GPIO_MODE_GPIO,
++ .gpio20 = GPIO_MODE_GPIO,
++ .gpio21 = GPIO_MODE_GPIO,
++ .gpio22 = GPIO_MODE_GPIO,
++ .gpio23 = GPIO_MODE_NATIVE,
++ .gpio24 = GPIO_MODE_GPIO,
++ .gpio25 = GPIO_MODE_NATIVE,
++ .gpio26 = GPIO_MODE_NATIVE,
++ .gpio27 = GPIO_MODE_GPIO,
++ .gpio28 = GPIO_MODE_GPIO,
++ .gpio29 = GPIO_MODE_NATIVE,
++ .gpio30 = GPIO_MODE_NATIVE,
++ .gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++ .gpio1 = GPIO_DIR_INPUT,
++ .gpio2 = GPIO_DIR_INPUT,
++ .gpio3 = GPIO_DIR_INPUT,
++ .gpio4 = GPIO_DIR_INPUT,
++ .gpio5 = GPIO_DIR_INPUT,
++ .gpio6 = GPIO_DIR_INPUT,
++ .gpio7 = GPIO_DIR_INPUT,
++ .gpio8 = GPIO_DIR_INPUT,
++ .gpio13 = GPIO_DIR_INPUT,
++ .gpio14 = GPIO_DIR_INPUT,
++ .gpio17 = GPIO_DIR_INPUT,
++ .gpio18 = GPIO_DIR_INPUT,
++ .gpio19 = GPIO_DIR_INPUT,
++ .gpio20 = GPIO_DIR_INPUT,
++ .gpio21 = GPIO_DIR_INPUT,
++ .gpio22 = GPIO_DIR_INPUT,
++ .gpio24 = GPIO_DIR_INPUT,
++ .gpio27 = GPIO_DIR_INPUT,
++ .gpio28 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++ .gpio1 = GPIO_INVERT,
++ .gpio7 = GPIO_INVERT,
++ .gpio8 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++ .gpio32 = GPIO_MODE_NATIVE,
++ .gpio33 = GPIO_MODE_GPIO,
++ .gpio34 = GPIO_MODE_GPIO,
++ .gpio35 = GPIO_MODE_NATIVE,
++ .gpio36 = GPIO_MODE_GPIO,
++ .gpio37 = GPIO_MODE_GPIO,
++ .gpio38 = GPIO_MODE_GPIO,
++ .gpio39 = GPIO_MODE_GPIO,
++ .gpio40 = GPIO_MODE_NATIVE,
++ .gpio41 = GPIO_MODE_NATIVE,
++ .gpio42 = GPIO_MODE_NATIVE,
++ .gpio43 = GPIO_MODE_NATIVE,
++ .gpio44 = GPIO_MODE_NATIVE,
++ .gpio45 = GPIO_MODE_NATIVE,
++ .gpio46 = GPIO_MODE_NATIVE,
++ .gpio47 = GPIO_MODE_NATIVE,
++ .gpio48 = GPIO_MODE_GPIO,
++ .gpio49 = GPIO_MODE_GPIO,
++ .gpio50 = GPIO_MODE_NATIVE,
++ .gpio51 = GPIO_MODE_NATIVE,
++ .gpio52 = GPIO_MODE_GPIO,
++ .gpio53 = GPIO_MODE_GPIO,
++ .gpio54 = GPIO_MODE_NATIVE,
++ .gpio55 = GPIO_MODE_NATIVE,
++ .gpio56 = GPIO_MODE_GPIO,
++ .gpio57 = GPIO_MODE_GPIO,
++ .gpio58 = GPIO_MODE_NATIVE,
++ .gpio59 = GPIO_MODE_NATIVE,
++ .gpio60 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++ .gpio33 = GPIO_DIR_INPUT,
++ .gpio34 = GPIO_DIR_INPUT,
++ .gpio36 = GPIO_DIR_INPUT,
++ .gpio37 = GPIO_DIR_INPUT,
++ .gpio38 = GPIO_DIR_INPUT,
++ .gpio39 = GPIO_DIR_INPUT,
++ .gpio48 = GPIO_DIR_INPUT,
++ .gpio49 = GPIO_DIR_INPUT,
++ .gpio52 = GPIO_DIR_INPUT,
++ .gpio53 = GPIO_DIR_INPUT,
++ .gpio56 = GPIO_DIR_INPUT,
++ .gpio57 = GPIO_DIR_INPUT,
++ .gpio60 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++ .set1 = {
++ .mode = &pch_gpio_set1_mode,
++ .direction = &pch_gpio_set1_direction,
++ .level = &pch_gpio_set1_level,
++ .blink = &pch_gpio_set1_blink,
++ .invert = &pch_gpio_set1_invert,
++ },
++ .set2 = {
++ .mode = &pch_gpio_set2_mode,
++ .direction = &pch_gpio_set2_direction,
++ .level = &pch_gpio_set2_level,
++ },
++};
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
+new file mode 100644
+index 0000000000..a9948a93dd
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ /* coreboot specific header */
++ 0x111d76b2, /* IDT 92HD71B7X */
++ 0x1028024d, /* Subsystem ID */
++ 13, /* Number of entries */
++
++ /* Pin Widget Verb Table */
++
++ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
++ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
++ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
++ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
++ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
++ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
++ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
++ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
++ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
++ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
++ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
++};
++
++const u32 pc_beep_verbs[] = {
++ 0x00170500, /* power up codec */
++ 0x00d70500, /* power up speakers */
++ 0x00d70102, /* select mixer (input 0x2) for speakers */
++ 0x00d70740, /* enable speakers output */
++ 0x02770720, /* enable beep input */
++ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
++ 0x00d37000, /* unmute speakers */
++};
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
+new file mode 100644
+index 0000000000..20dfa245fb
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
+@@ -0,0 +1,10 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++chip northbridge/intel/gm45
++ device domain 0 on
++ subsystemid 0x1028 0x024d inherit
++ chip southbridge/intel/i82801ix
++ device pci 1c.2 off end # PCIe Port #3
++ end
++ end
++end
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch
deleted file mode 100644
index f66909c6..00000000
--- a/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 22/30] don't use github for the acpica download
-
-i have the tarball from a previous download, and i placed
-it on libreboot rsync, which then got mirrored to princeton.
-
-today, github's ssl cert was b0rking the hell out and i really
-really wanted to finish a build, and didn't want to wait for
-github to fix their httpd.
-
-so i'm now hosting this specific acpica tarball on rsync.
-
-this patch makes that URL be used, instead of the github one.
-
-that's the 2nd time i've had to patch coreboot's acpica download!
-
-Signed-off-by: Leah Rowe
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 23a5caf2bb..36565a906c 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
- MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
- GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
- BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
--IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
-+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
- # CLANG toolchain archive locations
- LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
- CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
new file mode 100644
index 00000000..bbdce358
--- /dev/null
+++ b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
@@ -0,0 +1,70 @@
+From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Fri, 3 May 2024 16:31:12 -0600
+Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
+
+Integrate the previously added mec5035_smi_sleep() function into
+mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
+The E6400 does not require the EC command to sucessfully suspend and
+resume from S3, though sending it does enable the breathing effect on
+the power LED while in S3. Without it, all LEDs turn off during S3.
+
+Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/e7240/smihandler.c | 9 +++++++++
+ src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
+ src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
+ 3 files changed, 27 insertions(+)
+ create mode 100644 src/mainboard/dell/e7240/smihandler.c
+ create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
+
+diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/e7240/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/gm45_latitude/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+new file mode 100644
+index 0000000000..00e55b51db
+--- /dev/null
++++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++ mec5035_smi_sleep(slp_typ);
++}
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch
deleted file mode 100644
index 7701babf..00000000
--- a/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Tue, 31 Oct 2023 18:24:39 +0000
-Subject: [PATCH 23/30] crank up vram allocation on more intel boards
-
-these were added to libreboot, and it's a policy of
-libreboot to max out the vram settings. this was
-overlooked, in prior revisions and releases.
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/dell/e6400/cmos.default | 2 +-
- src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
- src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
- src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
- src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
- src/mainboard/lenovo/t420/cmos.default | 1 +
- src/mainboard/lenovo/t420s/cmos.default | 1 +
- src/mainboard/lenovo/t430/cmos.default | 1 +
- src/mainboard/lenovo/t520/cmos.default | 1 +
- src/mainboard/lenovo/t530/cmos.default | 1 +
- src/mainboard/lenovo/x201/cmos.default | 1 +
- src/mainboard/lenovo/x220/cmos.default | 1 +
- 12 files changed, 12 insertions(+), 4 deletions(-)
-
-diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
-index eeb6f47364..25dfa38cb5 100644
---- a/src/mainboard/dell/e6400/cmos.default
-+++ b/src/mainboard/dell/e6400/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- power_on_after_fail=Disable
- sata_mode=AHCI
--gfx_uma_size=32M
-+gfx_uma_size=256M
-diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
-index ccc7e64625..7c97b84baf 100644
---- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
-+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
-@@ -3,5 +3,5 @@ debug_level=Debug
- power_on_after_fail=Disable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=128M
-+gfx_uma_size=224M
- fan_full_speed=Disable
-diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
-index 6d27a79c66..4517ffc7c2 100644
---- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
-+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
-@@ -3,5 +3,5 @@ debug_level=Debug
- power_on_after_fail=Enable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-+gfx_uma_size=224M
- psu_fan_lvl=3
-diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
-index 6f3cec735e..9fc4db2990 100644
---- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
-+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
-@@ -3,4 +3,4 @@ debug_level=Debug
- power_on_after_fail=Enable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-+gfx_uma_size=224M
-diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
-index ad822d5043..89418a4cfc 100644
---- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
-+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
-@@ -3,3 +3,4 @@ debug_level=Debug
- power_on_after_fail=Disable
- nmi=Enable
- sata_mode=AHCI
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index c011867916..83f590d39d 100644
---- a/src/mainboard/lenovo/t420/cmos.default
-+++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -15,3 +15,4 @@ trackpoint=Enable
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
- me_state=Disabled
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index c011867916..83f590d39d 100644
---- a/src/mainboard/lenovo/t420s/cmos.default
-+++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -15,3 +15,4 @@ trackpoint=Enable
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
- me_state=Disabled
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index 55e1e6c04e..a72108f47e 100644
---- a/src/mainboard/lenovo/t430/cmos.default
-+++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -16,3 +16,4 @@ backlight=Both
- usb_always_on=Disable
- hybrid_graphics_mode=Integrated Only
- me_state=Disabled
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index b66f7034dc..a73ea6e9ee 100644
---- a/src/mainboard/lenovo/t520/cmos.default
-+++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -16,3 +16,4 @@ backlight=Both
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
- me_state=Disabled
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index b66f7034dc..a73ea6e9ee 100644
---- a/src/mainboard/lenovo/t530/cmos.default
-+++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -16,3 +16,4 @@ backlight=Both
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
- me_state=Disabled
-+gfx_uma_size=224M
-diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
-index 2cf484fd5a..46294d91ca 100644
---- a/src/mainboard/lenovo/x201/cmos.default
-+++ b/src/mainboard/lenovo/x201/cmos.default
-@@ -15,3 +15,4 @@ power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
- usb_always_on=Disable
-+gfx_uma_size=128M
-diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index 52f303dfdb..92a2026542 100644
---- a/src/mainboard/lenovo/x220/cmos.default
-+++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
- sticky_fn=Disable
- trackpoint=Enable
- me_state=Disabled
-+gfx_uma_size=224M
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
new file mode 100644
index 00000000..ab01c935
--- /dev/null
+++ b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
@@ -0,0 +1,92 @@
+From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Tue, 18 Jun 2024 21:31:08 -0600
+Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
+
+If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
+power button results in the EC powering off the system without letting
+the OS cleanly shutting itself down. This command and argument tells the
+EC to route power button events to the host so that it can determine
+what to do.
+
+The EC command was identified from the ec/google/wilco code, which is
+used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
+Kconfig help text, those ECs run a modified version of Dell's typical
+Latitude EC firmware, so it is likely that the two firmware
+implementations use similar commands. Examining LPC traffic between the
+host and the EC on the Latitude E6400 did reveal that the same command
+was being sent by the vendor firmware to the EC, but this does not
+confirm that it has the same meaning as the command from the Wilco code.
+Sending the command using inb/outb calls in a userspace C program while
+running coreboot without this patch did allow subsequent power button
+events to be handled by the host, confirming that the command was indeed
+the same.
+
+Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
+Signed-off-by: Nicholas Chin
+---
+ src/ec/dell/mec5035/mec5035.c | 8 ++++++++
+ src/ec/dell/mec5035/mec5035.h | 7 +++++++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 85c2ab0140..bdae929a27 100644
+--- a/src/ec/dell/mec5035/mec5035.c
++++ b/src/ec/dell/mec5035/mec5035.c
+@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
+ ec_command(CMD_RADIO_CTRL);
+ }
+
++void mec5035_power_button_route(enum ec_power_button_route target)
++{
++ u8 buf = (u8)target;
++ write_mailbox_regs(&buf, 2, 1);
++ ec_command(CMD_POWER_BUTTON_TO_HOST);
++}
++
+ void mec5035_change_wake(u8 source, enum ec_wake_change change)
+ {
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
+@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
+ /* Unconditionally use this argument for now as this setting
+ is probably the most sensible default out of the 3 choices. */
+ mec5035_mouse_touchpad(TP_PS2_MOUSE);
++ mec5035_power_button_route(HOST);
+
+ pc_keyboard_init(NO_AUX_DEVICE);
+
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index 8d4fded28b..51422598c4 100644
+--- a/src/ec/dell/mec5035/mec5035.h
++++ b/src/ec/dell/mec5035/mec5035.h
+@@ -11,6 +11,7 @@
+ enum mec5035_cmd {
+ CMD_MOUSE_TP = 0x1a,
+ CMD_RADIO_CTRL = 0x2b,
++ CMD_POWER_BUTTON_TO_HOST = 0x3e,
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
+ CMD_SLEEP_ENABLE = 0x64,
+ CMD_CPU_OK = 0xc2,
+@@ -36,6 +37,11 @@ enum ec_radio_state {
+ RADIO_ON
+ };
+
++enum ec_power_button_route {
++ EC = 0,
++ HOST
++};
++
+ #define ACPI_WAKEUP_NUM_ARGS 4
+ enum ec_wake_change {
+ WAKE_OFF = 0,
+@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
+ void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
++void mec5035_power_button_route(enum ec_power_button_route target);
+ void mec5035_change_wake(u8 source, enum ec_wake_change change);
+ void mec5035_sleep_enable(void);
+
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
new file mode 100644
index 00000000..c557e9d7
--- /dev/null
+++ b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
@@ -0,0 +1,31 @@
+From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Tue, 31 Dec 2024 14:42:24 +0000
+Subject: [PATCH 24/37] Disable compression on refcode insertion
+
+Compression is not reliably reproducible. In an lbmk release
+context, this means we cannot rely on vendorfile insertion.
+
+Therefore, use uncompressed refcode.
+
+Signed-off-by: Leah Rowe
+---
+ Makefile.mk | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.mk b/Makefile.mk
+index 3969bfbd05..15346569f8 100644
+--- a/Makefile.mk
++++ b/Makefile.mk
+@@ -1392,7 +1392,7 @@ endif
+ cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
+ $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
+ $(CONFIG_CBFS_PREFIX)/refcode-type := stage
+-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
++$(CONFIG_CBFS_PREFIX)/refcode-compression := none
+
+ cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
+ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
new file mode 100644
index 00000000..696be518
--- /dev/null
+++ b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
@@ -0,0 +1,187 @@
+From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 21 Apr 2025 02:58:47 +0100
+Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
+
+Signed-off-by: Leah Rowe
+---
+ src/northbridge/intel/e7505/Kconfig | 9 +++++++++
+ src/northbridge/intel/gm45/Kconfig | 9 +++++++++
+ src/northbridge/intel/haswell/Kconfig | 9 +++++++++
+ src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
+ src/northbridge/intel/i945/Kconfig | 9 +++++++++
+ src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
+ src/northbridge/intel/pineview/Kconfig | 9 +++++++++
+ src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
+ src/northbridge/intel/x4x/Kconfig | 9 +++++++++
+ 9 files changed, 85 insertions(+)
+
+diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
+index 039a7396f8..ddcb986f10 100644
+--- a/src/northbridge/intel/e7505/Kconfig
++++ b/src/northbridge/intel/e7505/Kconfig
+@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
+ select NO_CBFS_MCACHE
+ select SMM_TSEG
+ select NEED_SMALL_2MB_PAGE_TABLES
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
+diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
+index fc5df8b11a..95e3644b73 100644
+--- a/src/northbridge/intel/gm45/Kconfig
++++ b/src/northbridge/intel/gm45/Kconfig
+@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
+index 6191cb6ccf..0f5b5c7241 100644
+--- a/src/northbridge/intel/haswell/Kconfig
++++ b/src/northbridge/intel/haswell/Kconfig
+@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
+
+ if NORTHBRIDGE_INTEL_HASWELL
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ config USE_NATIVE_RAMINIT
+ bool "[NOT COMPLETE] Use native raminit"
+ default n
+diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
+index dbb2d7436b..5e9418b6a9 100644
+--- a/src/northbridge/intel/i440bx/Kconfig
++++ b/src/northbridge/intel/i440bx/Kconfig
+@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
+ If your board has 4 DIMM slots, you must use select this option, in
+ your Kconfig file of the board. On boards with 3 DIMM slots,
+ do _not_ select this option.
++
++if NORTHBRIDGE_INTEL_I440BX
++
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
++endif
+diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
+index 32eff1a611..9479d75c07 100644
+--- a/src/northbridge/intel/i945/Kconfig
++++ b/src/northbridge/intel/i945/Kconfig
+@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
+index 2bafebf92e..16b81705bb 100644
+--- a/src/northbridge/intel/ironlake/Kconfig
++++ b/src/northbridge/intel/ironlake/Kconfig
+@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
+index 59cfcd5e0a..a3ad8d3425 100644
+--- a/src/northbridge/intel/pineview/Kconfig
++++ b/src/northbridge/intel/pineview/Kconfig
+@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
+ config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
+index 973eed8bbd..6387cf926d 100644
+--- a/src/northbridge/intel/sandybridge/Kconfig
++++ b/src/northbridge/intel/sandybridge/Kconfig
+@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
+ default 2 if IGD_DEFAULT_UMA_SIZE_96MB
+ default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
+index 6430319f6a..1803ef5733 100644
+--- a/src/northbridge/intel/x4x/Kconfig
++++ b/src/northbridge/intel/x4x/Kconfig
+@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
+ config FIXED_EPBAR_MMIO_BASE
+ default 0xfed19000
+
++# Override DEBUG Kconfig to avoid false alarm about stack overflow.
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS
++ bool
++ default n
++
++config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
++ bool
++ default n
++
+ endif
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch
deleted file mode 100644
index 8275d6c5..00000000
--- a/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
-
-the gnu.org 302 redirect often fails
-
-Signed-off-by: Leah Rowe
----
- util/crossgcc/buildgcc | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 36565a906c..4d4ca06113 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
- # to the jenkins build as well, or the builder won't download it.
-
- # GCC toolchain archive locations
--GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
--MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
--MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
--GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
--BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
-+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
-+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
-+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
-+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
- IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
- # CLANG toolchain archive locations
- LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
deleted file mode 100644
index 33d743f1..00000000
--- a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
+++ /dev/null
@@ -1,792 +0,0 @@
-From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
-
-Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
-is based on the autoport output with some manual tweaks. The flash is
-8MiB + 4MiB. It can be internally flashed by sending a command to the
-EC, which causes the EC to pull the FDO pin low and the firmware to skip
-setting up any chipset based write protections. [1] The EC is the SMSC
-MEC5055, which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e6530/Kconfig | 37 ++++
- src/mainboard/dell/e6530/Kconfig.name | 2 +
- src/mainboard/dell/e6530/Makefile.inc | 6 +
- src/mainboard/dell/e6530/acpi/ec.asl | 9 +
- src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
- src/mainboard/dell/e6530/acpi/superio.asl | 3 +
- src/mainboard/dell/e6530/acpi_tables.c | 16 ++
- src/mainboard/dell/e6530/board_info.txt | 6 +
- src/mainboard/dell/e6530/cmos.default | 9 +
- src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
- src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
- src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
- src/mainboard/dell/e6530/dsdt.asl | 30 ++++
- src/mainboard/dell/e6530/early_init.c | 38 ++++
- src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
- src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
- src/mainboard/dell/e6530/hda_verb.c | 33 ++++
- src/mainboard/dell/e6530/mainboard.c | 21 +++
- 18 files changed, 590 insertions(+)
- create mode 100644 src/mainboard/dell/e6530/Kconfig
- create mode 100644 src/mainboard/dell/e6530/Kconfig.name
- create mode 100644 src/mainboard/dell/e6530/Makefile.inc
- create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6530/board_info.txt
- create mode 100644 src/mainboard/dell/e6530/cmos.default
- create mode 100644 src/mainboard/dell/e6530/cmos.layout
- create mode 100644 src/mainboard/dell/e6530/data.vbt
- create mode 100644 src/mainboard/dell/e6530/devicetree.cb
- create mode 100644 src/mainboard/dell/e6530/dsdt.asl
- create mode 100644 src/mainboard/dell/e6530/early_init.c
- create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6530/gpio.c
- create mode 100644 src/mainboard/dell/e6530/hda_verb.c
- create mode 100644 src/mainboard/dell/e6530/mainboard.c
-
-diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
-new file mode 100644
-index 0000000000..582adddbd4
---- /dev/null
-+++ b/src/mainboard/dell/e6530/Kconfig
-@@ -0,0 +1,37 @@
-+if BOARD_DELL_LATITUDE_E6530
-+
-+config BOARD_SPECIFIC_OPTIONS
-+ def_bool y
-+ select BOARD_ROMSIZE_KB_12288
-+ select EC_ACPI
-+ select EC_DELL_MEC5035
-+ select GFX_GMA_PANEL_1_ON_LVDS
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select HAVE_CMOS_DEFAULT
-+ select HAVE_OPTION_TABLE
-+ select INTEL_GMA_HAVE_VBT
-+ select INTEL_INT15
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+ select SERIRQ_CONTINUOUS_MODE
-+ select SOUTHBRIDGE_INTEL_C216
-+ select SYSTEM_TYPE_LAPTOP
-+ select USE_NATIVE_RAMINIT
-+
-+config MAINBOARD_DIR
-+ default "dell/e6530"
-+
-+config MAINBOARD_PART_NUMBER
-+ default "Latitude E6530"
-+
-+config VGA_BIOS_ID
-+ default "8086,0166"
-+
-+config DRAM_RESET_GATE_GPIO
-+ default 60
-+
-+config USBDEBUG_HCD_INDEX
-+ default 2
-+endif
-diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
-new file mode 100644
-index 0000000000..01ed76d107
---- /dev/null
-+++ b/src/mainboard/dell/e6530/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6530
-+ bool "Latitude E6530"
-diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
---- /dev/null
-+++ b/src/mainboard/dell/e6530/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
---- /dev/null
-+++ b/src/mainboard/dell/e6530/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+ Name (_HID, EISAID("PNP0C09"))
-+ Name (_UID, 0)
-+ Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
---- /dev/null
-+++ b/src/mainboard/dell/e6530/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+ /* FIXME: EC support */
-+ Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+ /* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
---- /dev/null
-+++ b/src/mainboard/dell/e6530/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
---- /dev/null
-+++ b/src/mainboard/dell/e6530/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+/* FIXME: check this function. */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+ /* The lid is open by default. */
-+ gnvs->lids = 1;
-+
-+ /* Temperature at which OS will shutdown */
-+ gnvs->tcrt = 100;
-+ /* Temperature at which OS will throttle CPU */
-+ gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
-new file mode 100644
-index 0000000000..4601a4aaba
---- /dev/null
-+++ b/src/mainboard/dell/e6530/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
---- /dev/null
-+++ b/src/mainboard/dell/e6530/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
-new file mode 100644
-index 0000000000..e85ea4c661
---- /dev/null
-+++ b/src/mainboard/dell/e6530/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0 120 r 0 reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384 1 e 4 boot_option
-+388 4 h 0 reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395 4 e 6 debug_level
-+
-+#400 8 r 0 reserved for century byte
-+
-+# coreboot config options: southbridge
-+408 1 e 1 nmi
-+409 2 e 7 power_on_after_fail
-+411 1 e 9 sata_mode
-+
-+# coreboot config options: EC
-+412 1 e 1 bluetooth
-+413 1 e 1 wwan
-+415 1 e 1 wlan
-+
-+# coreboot config options: ME
-+424 1 e 14 me_state
-+425 2 h 0 me_state_prev
-+
-+# coreboot config options: northbridge
-+432 3 e 11 gfx_uma_size
-+435 2 e 12 hybrid_graphics_mode
-+440 8 h 0 volume
-+
-+# VBOOT
-+448 128 r 0 vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896 32 r 0 mrc_scrambler_seed
-+928 32 r 0 mrc_scrambler_seed_s3
-+960 16 r 0 mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984 16 h 0 check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value text
-+1 0 Disable
-+1 1 Enable
-+2 0 Enable
-+2 1 Disable
-+4 0 Fallback
-+4 1 Normal
-+6 0 Emergency
-+6 1 Alert
-+6 2 Critical
-+6 3 Error
-+6 4 Warning
-+6 5 Notice
-+6 6 Info
-+6 7 Debug
-+6 8 Spew
-+7 0 Disable
-+7 1 Enable
-+7 2 Keep
-+9 0 AHCI
-+9 1 Compatible
-+11 0 32M
-+11 1 64M
-+11 2 96M
-+11 3 128M
-+11 4 160M
-+11 5 192M
-+11 6 224M
-+14 0 Normal
-+14 1 Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
-GIT binary patch
-literal 4280
-zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
-zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
-zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
-zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWpFv
-zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
-ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
-zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
-zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
-zfbB~~a>piTMAVDNyHR<{0{F7}8pool{7_h6u?7yg
-zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
-zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn
-z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
-zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
-z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
-zCmnxV&FgUDAWX}gZ+1AH&-C4Q=3sl5RX9=OWPfCtcRZi4tkX44YYfRH*@?H7T=Kz=
-zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH
-z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1(
-zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
-z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
-z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j
-z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=TGXaGC^5Cz)J
-z4?eb?Kub*nWYdmhV-4?jJW
-zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+yaZ_2@KjK>)nIBR-xB@+1PQ2*c$lV?Z13o
-zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d
-+
-+DefinitionBlock(
-+ "dsdt.aml",
-+ "DSDT",
-+ ACPI_DSDT_REV_2,
-+ OEM_ID,
-+ ACPI_TABLE_CREATOR,
-+ 0x20141018 /* OEM revision */
-+)
-+{
-+ #include
-+ #include "acpi/platform.asl"
-+ #include
-+ #include
-+ #include
-+ #include
-+
-+ Device (\_SB.PCI0)
-+ {
-+ #include
-+ #include
-+ #include
-+ }
-+}
-diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
-new file mode 100644
-index 0000000000..d57f48e7f1
---- /dev/null
-+++ b/src/mainboard/dell/e6530/early_init.c
-@@ -0,0 +1,38 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+ { 1, 1, 0 },
-+ { 1, 1, 0 },
-+ { 1, 1, 1 },
-+ { 1, 1, 1 },
-+ { 1, 1, 2 },
-+ { 1, 1, 2 },
-+ { 1, 0, 3 },
-+ { 1, 1, 3 },
-+ { 1, 1, 4 },
-+ { 1, 1, 4 },
-+ { 1, 1, 5 },
-+ { 1, 1, 5 },
-+ { 1, 2, 6 },
-+ { 1, 2, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
-+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-+ mec5035_early_init();
-+}
-+
-+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-+{
-+ read_spd(&spd[0], 0x50, id_only);
-+ read_spd(&spd[2], 0x52, id_only);
-+}
-diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
-new file mode 100644
-index 0000000000..1310830c8e
---- /dev/null
-+++ b/src/mainboard/dell/e6530/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+ ports : constant Port_List :=
-+ (
-+ HDMI1, -- mainboard HDMI
-+ DP2, -- dock DP
-+ DP3, -- dock DP
-+ Analog, --mainboard VGA
-+ LVDS,
-+ others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/e6530/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_GPIO,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_NATIVE,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_GPIO,
-+ .gpio16 = GPIO_MODE_GPIO,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_NATIVE,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_NATIVE,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_GPIO,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio0 = GPIO_DIR_INPUT,
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio15 = GPIO_DIR_INPUT,
-+ .gpio16 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_OUTPUT,
-+ .gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+ .gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+ .gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio0 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+ .gpio13 = GPIO_INVERT,
-+ .gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_GPIO,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_GPIO,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_GPIO,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_NATIVE,
-+ .gpio54 = GPIO_MODE_GPIO,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_NATIVE,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+ .gpio61 = GPIO_MODE_NATIVE,
-+ .gpio62 = GPIO_MODE_NATIVE,
-+ .gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_OUTPUT,
-+ .gpio35 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio45 = GPIO_DIR_OUTPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio51 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio54 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+ .gpio34 = GPIO_LEVEL_HIGH,
-+ .gpio45 = GPIO_LEVEL_LOW,
-+ .gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+ .gpio64 = GPIO_MODE_NATIVE,
-+ .gpio65 = GPIO_MODE_NATIVE,
-+ .gpio66 = GPIO_MODE_NATIVE,
-+ .gpio67 = GPIO_MODE_NATIVE,
-+ .gpio68 = GPIO_MODE_GPIO,
-+ .gpio69 = GPIO_MODE_GPIO,
-+ .gpio70 = GPIO_MODE_GPIO,
-+ .gpio71 = GPIO_MODE_GPIO,
-+ .gpio72 = GPIO_MODE_NATIVE,
-+ .gpio73 = GPIO_MODE_NATIVE,
-+ .gpio74 = GPIO_MODE_NATIVE,
-+ .gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+ .gpio68 = GPIO_DIR_INPUT,
-+ .gpio69 = GPIO_DIR_INPUT,
-+ .gpio70 = GPIO_DIR_INPUT,
-+ .gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ .reset = &pch_gpio_set1_reset,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ .reset = &pch_gpio_set2_reset,
-+ },
-+ .set3 = {
-+ .mode = &pch_gpio_set3_mode,
-+ .direction = &pch_gpio_set3_direction,
-+ .level = &pch_gpio_set3_level,
-+ .reset = &pch_gpio_set3_reset,
-+ },
-+};
-diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
-new file mode 100644
-index 0000000000..9de7e34311
---- /dev/null
-+++ b/src/mainboard/dell/e6530/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
-+ 0x10280535, /* Subsystem ID */
-+ 11, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(0, 0x10280535),
-+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+ 0x80862806, /* Codec Vendor / Device ID: Intel */
-+ 0x80860101, /* Subsystem ID */
-+ 4, /* Number of 4 dword sets */
-+ AZALIA_SUBVENDOR(3, 0x80860101),
-+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
---- /dev/null
-+++ b/src/mainboard/dell/e6530/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+ /* FIXME: fix these values. */
-+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+ GMA_INT15_PANEL_FIT_DEFAULT,
-+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+ .enable_dev = mainboard_enable,
-+};
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
new file mode 100644
index 00000000..c411c18b
--- /dev/null
+++ b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
@@ -0,0 +1,94 @@
+From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
+From: Felix Singer
+Date: Wed, 26 Jun 2024 04:24:31 +0200
+Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
+
+Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
+Signed-off-by: Felix Singer
+---
+ src/soc/intel/skylake/Kconfig | 1 +
+ src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
+ 2 files changed, 56 insertions(+), 1 deletion(-)
+
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index 4ad33496b2..9191ed0ff8 100644
+--- a/src/soc/intel/skylake/Kconfig
++++ b/src/soc/intel/skylake/Kconfig
+@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
+ select CPU_INTEL_COMMON
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select CPU_SUPPORTS_PM_TIMER_EMULATION
++ select DRIVERS_USB_ACPI
+ select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
+ select FSP_COMPRESS_FSP_S_LZ4
+ select FSP_M_XIP
+diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
+index 6538a1475b..dfb81d496e 100644
+--- a/src/soc/intel/skylake/chipset.cb
++++ b/src/soc/intel/skylake/chipset.cb
+@@ -13,7 +13,61 @@ chip soc/intel/skylake
+ device pci 07.0 alias chap off end
+ device pci 08.0 alias gmm off end # Gaussian Mixture Model
+ device pci 13.0 alias ish off end # SensorHub
+- device pci 14.0 alias south_xhci off ops usb_xhci_ops end
++ device pci 14.0 alias south_xhci off ops usb_xhci_ops
++ chip drivers/usb/acpi
++ register "type" = "UPC_TYPE_HUB"
++ device usb 0.0 alias xhci_root_hub off
++ chip drivers/usb/acpi
++ device usb 2.0 alias usb2_port1 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.1 alias usb2_port2 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.2 alias usb2_port3 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.3 alias usb2_port4 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.4 alias usb2_port5 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.5 alias usb2_port6 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.6 alias usb2_port7 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.7 alias usb2_port8 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.8 alias usb2_port9 off end
++ end
++ chip drivers/usb/acpi
++ device usb 2.9 alias usb2_port10 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.0 alias usb3_port1 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.1 alias usb3_port2 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.2 alias usb3_port3 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.3 alias usb3_port4 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.4 alias usb3_port5 off end
++ end
++ chip drivers/usb/acpi
++ device usb 3.5 alias usb3_port6 off end
++ end
++ end
++ end
++ end
+ device pci 14.1 alias south_xdci off ops usb_xdci_ops end
+ device pci 14.2 alias thermal off end
+ device pci 14.3 alias cio off end
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch
deleted file mode 100644
index 130984fb..00000000
--- a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Thu, 25 Jan 2024 14:30:03 +0000
-Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
-
-i diffed nicholas's current e6430 patch, versus the old one,
-prior to this revision update in lbmk, also cross referencing
-the original e6430 and e6530 patches, diffing them, and the
-result in this patch. most notably, spd data is now defined in
-the devicetree, instead of early_init.c as per:
-
-commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
-Author: Keith Hui
-Date: Sat Jul 22 12:49:05 2023 -0400
- mb/*: Update SPD mapping for sandybridge boards
-
-This should work fine. Will test after this builds.
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/dell/e6530/Kconfig | 15 +++++++++++----
- src/mainboard/dell/e6530/cmos.layout | 2 +-
- src/mainboard/dell/e6530/devicetree.cb | 8 +++++---
- src/mainboard/dell/e6530/early_init.c | 12 +++---------
- 4 files changed, 20 insertions(+), 17 deletions(-)
-
-diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
-index 582adddbd4..a104566890 100644
---- a/src/mainboard/dell/e6530/Kconfig
-+++ b/src/mainboard/dell/e6530/Kconfig
-@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
- select SYSTEM_TYPE_LAPTOP
- select USE_NATIVE_RAMINIT
-
-+config DRAM_RESET_GATE_GPIO
-+ default 60
-+
- config MAINBOARD_DIR
- default "dell/e6530"
-
- config MAINBOARD_PART_NUMBER
- default "Latitude E6530"
-
--config VGA_BIOS_ID
-- default "8086,0166"
-+config PS2K_EISAID
-+ default "PNP0303"
-
--config DRAM_RESET_GATE_GPIO
-- default 60
-+config PS2M_EISAID
-+ default "PNP0F13"
-
- config USBDEBUG_HCD_INDEX
- default 2
-+
-+config VGA_BIOS_ID
-+ default "8086,0166"
-+
- endif
-diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
-index e85ea4c661..1aa7e77bce 100644
---- a/src/mainboard/dell/e6530/cmos.layout
-+++ b/src/mainboard/dell/e6530/cmos.layout
-@@ -25,7 +25,7 @@ entries
- # coreboot config options: EC
- 412 1 e 1 bluetooth
- 413 1 e 1 wwan
--415 1 e 1 wlan
-+414 1 e 1 wlan
-
- # coreboot config options: ME
- 424 1 e 14 me_state
-diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
-index 96eed178c5..37135bcf0f 100644
---- a/src/mainboard/dell/e6530/devicetree.cb
-+++ b/src/mainboard/dell/e6530/devicetree.cb
-@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- register "gpu_panel_power_up_delay" = "400"
- register "gpu_pch_backlight" = "0x13121312"
-
-+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
- device domain 0x0 on
- subsystemid 0x1028 0x0535 inherit
-
-@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- register "gen1_dec" = "0x007c0681"
- register "gen2_dec" = "0x005c0921"
- register "gen3_dec" = "0x003c07e1"
-- register "gen4_dec" = "0x007c0901"
-+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
- register "gpi0_routing" = "2"
- register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
-@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- register "xhci_switchable_ports" = "0x0000000f"
-
- device ref xhci on end # USB 3.0 Controller
-- device ref mei1 off end # Management Engine Interface 1
-+ device ref mei1 on end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt on end # Management Engine KT
-@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- device ref pcie_rp2 on end # PCIe Port #2
- device ref pcie_rp3 on end # PCIe Port #3
- device ref pcie_rp4 on end # PCIe Port #4
-- device ref pcie_rp5 off end # PCIe Port #5
-+ device ref pcie_rp5 on end # PCIe Port #5
- device ref pcie_rp6 on end # PCIe Port #6
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
-diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
-index d57f48e7f1..2b40f6963f 100644
---- a/src/mainboard/dell/e6530/early_init.c
-+++ b/src/mainboard/dell/e6530/early_init.c
-@@ -4,7 +4,6 @@
- #include
- #include
- #include
--#include
- #include
-
- const struct southbridge_usb_port mainboard_usb_ports[] = {
-@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
-
- void bootblock_mainboard_early_init(void)
- {
-- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
-- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+ | COMB_LPC_EN | COMA_LPC_EN);
- mec5035_early_init();
- }
--
--void mainboard_get_spd(spd_raw_data *spd, bool id_only)
--{
-- read_spd(&spd[0], 0x50, id_only);
-- read_spd(&spd[2], 0x52, id_only);
--}
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
new file mode 100644
index 00000000..9d75cec6
--- /dev/null
+++ b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
@@ -0,0 +1,30 @@
+From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
+From: Mate Kukri
+Date: Fri, 22 Nov 2024 21:26:48 +0000
+Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
+ bootblock
+
+Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
+Signed-off-by: Mate Kukri
+---
+ src/soc/intel/skylake/bootblock/pch.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
+index df00bb85a9..beaece960b 100644
+--- a/src/soc/intel/skylake/bootblock/pch.c
++++ b/src/soc/intel/skylake/bootblock/pch.c
+@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
+
+ void pch_early_iorange_init(void)
+ {
+- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+- LPC_IOE_EC_62_66;
++ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
++ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
+
+ const config_t *config = config_of_soc();
+
+--
+2.39.5
+
diff --git a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
deleted file mode 100644
index fa7ab40d..00000000
--- a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Thu, 25 Jan 2024 14:37:30 +0000
-Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
-
-we neuter anyway. disabling it in devicetree will prevent linux
-from ever trying to use it or load a driver for it, and thus
-might prevent benign error messages from appearing in dmesg.
-
-this change was suggested by nicholas when asked on irc.
-
-Signed-off-by: Leah Rowe
----
- src/mainboard/dell/e6430/devicetree.cb | 4 ++--
- src/mainboard/dell/e6530/devicetree.cb | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
-index 054b01c5ac..2b8574c984 100644
---- a/src/mainboard/dell/e6430/devicetree.cb
-+++ b/src/mainboard/dell/e6430/devicetree.cb
-@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- register "xhci_switchable_ports" = "0x0000000f"
-
- device ref xhci on end
-- device ref mei1 on end
-+ device ref mei1 off end
- device ref mei2 off end
- device ref me_ide_r off end
-- device ref me_kt on end
-+ device ref me_kt off end
- device ref gbe on end
- device ref ehci2 on end
- device ref hda on end
-diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
-index 37135bcf0f..010200bb6d 100644
---- a/src/mainboard/dell/e6530/devicetree.cb
-+++ b/src/mainboard/dell/e6530/devicetree.cb
-@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- register "xhci_switchable_ports" = "0x0000000f"
-
- device ref xhci on end # USB 3.0 Controller
-- device ref mei1 on end # Management Engine Interface 1
-+ device ref mei1 off end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
-- device ref me_kt on end # Management Engine KT
-+ device ref me_kt off end # Management Engine KT
- device ref gbe on end # Intel Gigabit Ethernet
- device ref ehci2 on end # USB2 EHCI #2
- device ref hda on end # High Definition Audio
---
-2.39.2
-
diff --git a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
new file mode 100644
index 00000000..df71dc47
--- /dev/null
+++ b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
@@ -0,0 +1,2232 @@
+From b515ba5b0cd02dc1771f27eaa716582b0827a638 Mon Sep 17 00:00:00 2001
+From: Mate Kukri
+Date: Tue, 31 Dec 2024 22:49:15 +0000
+Subject: [PATCH 28/37] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
+
+These machine have BootGuard fused and requires deguard to
+boot coreboot.
+
+Known issues:
+- Alpine Ridge Thunderbolt 3 controller does not work
+- Some Fn+F{1-12} keys aren't handled correctly
+- Nvidia dGPU is finicky
+ - Needs option ROM
+ - Power enable code is buggy
+ - Nouveau only works on linux 6.8-6.9
+- Headphone jack isn't detected as plugged in despite correct verbs
+
+Thanks to Leah Rowe for helping with the T480s.
+
+Signed-off-by: Mate Kukri
+Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
+---
+ src/device/pci_rom.c | 4 +-
+ src/ec/lenovo/h8/acpi/ec.asl | 2 +-
+ src/ec/lenovo/h8/bluetooth.c | 6 +-
+ src/ec/lenovo/h8/wwan.c | 6 +-
+ src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++
+ .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 +
+ .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++
+ .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++
+ .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 +
+ .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++
+ .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++
+ src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++
+ src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 +
+ .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++
+ .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes
+ .../variants/t480/gma-mainboard.ads | 19 ++
+ .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++
+ .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++
+ .../variants/t480/memory_init_params.c | 20 ++
+ .../variants/t480/overridetree.cb | 103 +++++++++
+ .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
+ .../variants/t480s/gma-mainboard.ads | 19 ++
+ .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++
+ .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++
+ .../variants/t480s/memory_init_params.c | 44 ++++
+ .../variants/t480s/overridetree.cb | 103 +++++++++
+ .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes
+ .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes
+ 49 files changed, 1583 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
+ create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
+
+diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
+index dc41ef14ce..bba98d9dea 100644
+--- a/src/device/pci_rom.c
++++ b/src/device/pci_rom.c
+@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device)
+ rom = cbrom;
+ }
+
++#if 0
+ const char *scope = acpi_device_path(device);
+ if (!scope) {
+ printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
+ return;
+ }
++#endif
+
+ /* write _ROM method */
+- acpigen_write_scope(scope);
++ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
+ acpigen_write_rom((void *)rom, rom->size * 512);
+ acpigen_pop_len(); /* pop scope */
+ }
+diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
+index bc54d3b422..8f4a8e1986 100644
+--- a/src/ec/lenovo/h8/acpi/ec.asl
++++ b/src/ec/lenovo/h8/acpi/ec.asl
+@@ -331,7 +331,7 @@ Device(EC)
+ #include "sleepbutton.asl"
+ #include "lid.asl"
+ #include "beep.asl"
+-#include "thermal.asl"
++//#include "thermal.asl"
+ #include "systemstatus.asl"
+ #include "thinkpad.asl"
+ }
+diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
+index 16fc8dce39..be71a24ced 100644
+--- a/src/ec/lenovo/h8/bluetooth.c
++++ b/src/ec/lenovo/h8/bluetooth.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+
+-#include
++// #include
+ #include
+ #include
+ #include
+@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev)
+ {
+ struct ec_lenovo_h8_config *conf = dev->chip_info;
+
+- if (!conf->has_bdc_detection) {
++ if (1 || !conf->has_bdc_detection) {
+ printk(BIOS_INFO, "H8: BDC detection not implemented. "
+ "Assuming BDC installed\n");
+ return true;
+ }
+
++#if 0
+ if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
+ printk(BIOS_INFO, "H8: BDC installed\n");
+ return true;
+ }
++#endif
+
+ printk(BIOS_INFO, "H8: BDC not installed\n");
+ return false;
+diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
+index 685886fcce..5cdcf77406 100644
+--- a/src/ec/lenovo/h8/wwan.c
++++ b/src/ec/lenovo/h8/wwan.c
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+
+-#include
++// #include
+ #include
+ #include
+ #include
+@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev)
+ {
+ struct ec_lenovo_h8_config *conf = dev->chip_info;
+
+- if (!conf->has_wwan_detection) {
++ if (1 || !conf->has_wwan_detection) {
+ printk(BIOS_INFO, "H8: WWAN detection not implemented. "
+ "Assuming WWAN installed\n");
+ return true;
+ }
+
++#if 0
+ if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
+ printk(BIOS_INFO, "H8: WWAN installed\n");
+ return true;
+ }
++#endif
+
+ printk(BIOS_INFO, "H8: WWAN not installed\n");
+ return false;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+new file mode 100644
+index 0000000000..4998672943
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+@@ -0,0 +1,57 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++ bool
++ select BOARD_ROMSIZE_KB_16384
++ select EC_LENOVO_H8
++ select EC_LENOVO_PMH7
++ select H8_HAS_BAT_THRESHOLDS_IMPL
++ select H8_HAS_LEDLOGO
++ select H8_HAS_PRIMARY_FN_KEYS
++ select HAVE_ACPI_RESUME
++ select HAVE_ACPI_TABLES
++ select INTEL_GMA_HAVE_VBT
++ select INTEL_INT15
++ select MAINBOARD_HAS_LIBGFXINIT
++ select MAINBOARD_HAS_TPM2
++ select MAINBOARD_USES_IFD_GBE_REGION
++ select MEMORY_MAPPED_TPM
++ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
++ select SOC_INTEL_KABYLAKE
++ select SPD_READ_BY_WORD
++ select SYSTEM_TYPE_LAPTOP
++
++config BOARD_LENOVO_T480
++ bool
++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++config BOARD_LENOVO_T480S
++ bool
++ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
++
++config MAINBOARD_DIR
++ default "lenovo/sklkbl_thinkpad"
++
++config VARIANT_DIR
++ default "t480" if BOARD_LENOVO_T480
++ default "t480s" if BOARD_LENOVO_T480S
++
++config OVERRIDE_DEVICETREE
++ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
++
++config MAINBOARD_PART_NUMBER
++ default "T480" if BOARD_LENOVO_T480
++ default "T480s" if BOARD_LENOVO_T480S
++
++config CBFS_SIZE
++ default 0x900000
++
++config DIMM_MAX
++ default 2
++
++config DIMM_SPD_SIZE
++ default 512 # DDR4
++
++endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+new file mode 100644
+index 0000000000..abc273f387
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_LENOVO_T480
++ bool "ThinkPad T480"
++
++config BOARD_LENOVO_T480S
++ bool "ThinkPad T480s"
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+new file mode 100644
+index 0000000000..c308239177
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
+@@ -0,0 +1,73 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++bootblock-y += bootblock.c ec.c
++
++romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
++
++ramstage-y += ramstage.c ec.c
++ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
++
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin
++spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin
++spd_0.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin
++spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin
++spd_1.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin
++spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin
++spd_2.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin
++spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin
++spd_3.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin
++spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin
++spd_4.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin
++spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin
++spd_5.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin
++spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin
++spd_6.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin
++spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin
++spd_7.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin
++spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin
++spd_8.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin
++spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin
++spd_9.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin
++spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin
++spd_10.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin
++spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin
++spd_11.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin
++spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin
++spd_12.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin
++spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin
++spd_13.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin
++spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin
++spd_14.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin
++spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin
++spd_15.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin
++spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin
++spd_16.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin
++spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin
++spd_17.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin
++spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin
++spd_18.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin
++spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin
++spd_19.bin-type := raw
++cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin
++spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin
++spd_20.bin-type := raw
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+new file mode 100644
+index 0000000000..3a949a2fca
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++#define THINKPAD_EC_GPE 22
++
++Name(\TCRT, 100)
++Name(\TPSV, 90)
++Name(\FLVL, 0)
++
++#include
++#include
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+new file mode 100644
+index 0000000000..fb660dbdfa
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
+@@ -0,0 +1,60 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include "ec.h"
++
++static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno)
++{
++ microchip_pnp_enter_conf_state(port);
++
++ // Select LPC I/F LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
++ // Write UART BAR
++ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707);
++ // Set SIRQ4 to UART
++ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART);
++
++ // Configure UART LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_UART);
++ pnp_write(port, UART_ACTIVATE, 0x01);
++ pnp_write(port, UART_CONFIG_SELECT, 0x00);
++
++ microchip_pnp_exit_conf_state(port);
++
++#ifdef CONFIG_BOARD_LENOVO_T480
++ // Supply debug unlock key
++ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
++
++ // Use debug writes to set UART_TX and UART_RX GPIOs
++ debug_write_dword(0xf0c400 + 0x110, 0x00001000);
++ debug_write_dword(0xf0c400 + 0x114, 0x00001000);
++#endif
++}
++
++
++#define UART_PORT 0x3f8
++#define UART_IRQ 4
++
++void bootblock_mainboard_early_init(void)
++{
++ // Tell EC via BIOS Debug Port 1 that the world isn't on fire
++
++ // Let the EC know that BIOS code is running
++ outb(0x11, 0x86);
++ outb(0x6e, 0x86);
++
++ // Enable accesses to EC1 interface
++ ec0_write(0, ec0_read(0) | 0x20);
++
++ // Reset LEDs to power on state
++ // (Without this warm reboot leaves LEDs off)
++ ec0_write(0x0c, 0x80);
++ ec0_write(0x0c, 0x07);
++ ec0_write(0x0c, 0x8a);
++
++ // Setup debug UART
++ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+new file mode 100644
+index 0000000000..c07d4d53ca
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
+@@ -0,0 +1,71 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++chip soc/intel/skylake
++ # IGD Displays
++ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
++
++ register "panel_cfg" = "{
++ .up_delay_ms = 200,
++ .down_delay_ms = 50,
++ .cycle_delay_ms = 600,
++ .backlight_on_delay_ms = 1,
++ .backlight_off_delay_ms = 200,
++ .backlight_pwm_hz = 200,
++ }"
++
++ # Power
++ register "PmConfigSlpS3MinAssert" = "2" # 50ms
++ register "PmConfigSlpS4MinAssert" = "1" # 1s
++ register "PmConfigSlpSusMinAssert" = "3" # 500ms
++ register "PmConfigSlpAMinAssert" = "3" # 2s
++
++ device domain 0 on
++ device ref igpu on end
++ device ref sa_thermal on end
++ device ref thermal on end
++ device ref south_xhci on end
++ device ref lpc_espi on
++ register "serirq_mode" = "SERIRQ_CONTINUOUS"
++
++ register "gen1_dec" = "0x007c1601"
++ register "gen2_dec" = "0x000c15e1"
++
++ chip ec/lenovo/pmh7
++ register "backlight_enable" = "true"
++ register "dock_event_enable" = "true"
++ device pnp ff.1 on end # dummy
++ end
++
++ chip ec/lenovo/h8
++ register "beepmask0" = "0x00"
++ register "beepmask1" = "0x86"
++ register "config0" = "0xa6"
++ register "config1" = "0x0d"
++ register "config2" = "0xa8"
++ register "config3" = "0xc4"
++ register "has_keyboard_backlight" = "1"
++ register "event2_enable" = "0xff"
++ register "event3_enable" = "0xff"
++ register "event4_enable" = "0xd0"
++ register "event5_enable" = "0x3c"
++ register "event7_enable" = "0x01"
++ register "event8_enable" = "0x7b"
++ register "event9_enable" = "0xff"
++ register "eventc_enable" = "0xff"
++ register "eventd_enable" = "0xff"
++ register "evente_enable" = "0x9d"
++ device pnp ff.2 on # dummy
++ io 0x60 = 0x62
++ io 0x62 = 0x66
++ io 0x64 = 0x1600
++ io 0x66 = 0x1604
++ end
++ end
++
++ chip drivers/pc80/tpm
++ device pnp 0c31.0 on end
++ end
++ end
++ device ref hda on end
++ end
++end
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+new file mode 100644
+index 0000000000..aa4d4de2a6
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++DefinitionBlock(
++ "dsdt.aml",
++ "DSDT",
++ ACPI_DSDT_REV_2,
++ OEM_ID,
++ ACPI_TABLE_CREATOR,
++ 0x20110725
++)
++{
++ #include
++ #include
++ #include
++
++ Device (\_SB.PCI0)
++ {
++ #include
++ #include
++ #include
++ }
++
++ Scope (\_SB.PCI0.RP01)
++ {
++ Device (PEGP)
++ {
++ Name (_ADR, Zero)
++ }
++ }
++
++ #include
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+new file mode 100644
+index 0000000000..adb6a60324
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
+@@ -0,0 +1,153 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include "ec.h"
++
++#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55
++#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa
++
++void microchip_pnp_enter_conf_state(uint16_t port)
++{
++ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port);
++}
++
++void microchip_pnp_exit_conf_state(uint16_t port)
++{
++ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port);
++}
++
++uint8_t pnp_read(uint16_t port, uint8_t index)
++{
++ outb(index, port);
++ return inb(port + 1);
++}
++
++uint32_t pnp_read_le32(uint16_t port, uint8_t index)
++{
++ return (uint32_t) pnp_read(port, index) |
++ (uint32_t) pnp_read(port, index + 1) << 8 |
++ (uint32_t) pnp_read(port, index + 2) << 16 |
++ (uint32_t) pnp_read(port, index + 3) << 24;
++}
++
++void pnp_write(uint16_t port, uint8_t index, uint8_t value)
++{
++ outb(index, port);
++ outb(value, port + 1);
++}
++
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value)
++{
++ pnp_write(port, index, value & 0xff);
++ pnp_write(port, index + 1, value >> 8 & 0xff);
++ pnp_write(port, index + 2, value >> 16 & 0xff);
++ pnp_write(port, index + 3, value >> 24 & 0xff);
++}
++
++static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port)
++{
++ while (inb(cmd_port) & EC_OBF)
++ inb(data_port);
++}
++
++static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port)
++{
++ while (inb(cmd_port) & EC_IBF)
++ ;
++}
++
++static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port)
++{
++ while (!(inb(cmd_port) & EC_OBF))
++ ;
++}
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr)
++{
++ ecN_clear_out_queue(cmd_port, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(EC_READ, cmd_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(addr, data_port);
++ ecN_wait_to_recv(cmd_port, data_port);
++ return inb(data_port);
++}
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val)
++{
++ ecN_clear_out_queue(cmd_port, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(EC_WRITE, cmd_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(addr, data_port);
++ ecN_wait_to_send(cmd_port, data_port);
++ outb(val, data_port);
++}
++
++uint8_t eeprom_read(uint16_t addr)
++{
++ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(1, EC2_CMD);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(addr, EC2_DATA);
++ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++ return inl(EC2_DATA);
++}
++
++void eeprom_write(uint16_t addr, uint8_t val)
++{
++ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl(2, EC2_CMD);
++ ecN_wait_to_send(EC2_CMD, EC2_DATA);
++ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA);
++ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
++ inl(EC2_DATA);
++}
++
++uint16_t debug_loaded_keys(void)
++{
++ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86);
++}
++
++static void debug_cmd(uint8_t cmd)
++{
++ ec0_write(EC_DEBUG_CMD, cmd);
++ while (ec0_read(EC_DEBUG_CMD) & 0x80)
++ ;
++}
++
++void debug_read_key(uint8_t i, uint8_t *key)
++{
++ debug_cmd(0x80 | (i & 0xf));
++ for (int j = 0; j < 8; ++j)
++ key[j] = ec0_read(0x3e + j);
++}
++
++void debug_write_key(uint8_t i, const uint8_t *key)
++{
++ for (int j = 0; j < 8; ++j)
++ ec0_write(0x3e + j, key[j]);
++ debug_cmd(0xc0 | (i & 0xf));
++}
++
++uint32_t debug_read_dword(uint32_t addr)
++{
++ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(addr << 8 | 0xE2, EC3_DATA);
++ ecN_wait_to_recv(EC3_CMD, EC3_DATA);
++ return inl(EC3_DATA);
++}
++
++void debug_write_dword(uint32_t addr, uint32_t val)
++{
++ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(addr << 8 | 0xEA, EC3_DATA);
++ ecN_wait_to_send(EC3_CMD, EC3_DATA);
++ outl(val, EC3_DATA);
++}
++
++const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf };
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+new file mode 100644
+index 0000000000..d2963c8962
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
+@@ -0,0 +1,99 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef SKLKBL_THINKPAD_EC_H
++#define SKLKBL_THINKPAD_EC_H
++
++// EC configuration base address
++#define EC_CFG_PORT 0x4e
++
++// Chip global registers
++#define PNP_LDN_SELECT 0x07
++# define LDN_UART 0x07
++# define LDN_LPCIF 0x0c
++#define EC_DEVICE_ID 0x20
++#define EC_DEVICE_REV 0x21
++
++// LPC I/F registers
++#define LPCIF_SIRQ(i) (0x40 + (i))
++
++#define LPCIF_BAR_CFG 0x60
++#define LPCIF_BAR_MAILBOX 0x64
++#define LPCIF_BAR_8042 0x68
++#define LPCIF_BAR_ACPI_EC0 0x6c
++#define LPCIF_BAR_ACPI_EC1 0x70
++#define LPCIF_BAR_ACPI_EC2 0x74
++#define LPCIF_BAR_ACPI_EC3 0x78
++#define LPCIF_BAR_ACPI_PM0 0x7c
++#define LPCIF_BAR_UART 0x80
++#define LPCIF_BAR_FAST_KYBD 0x84
++#define LPCIF_BAR_EMBED_FLASH 0x88
++#define LPCIF_BAR_GP_SPI 0x8c
++#define LPCIF_BAR_EMI 0x90
++#define LPCIF_BAR_PMH7 0x94
++#define LPCIF_BAR_PORT80_DBG0 0x98
++#define LPCIF_BAR_PORT80_DBG1 0x9c
++#define LPCIF_BAR_RTC 0xa0
++
++// UART registers
++#define UART_ACTIVATE 0x30
++#define UART_CONFIG_SELECT 0xf0
++
++void microchip_pnp_enter_conf_state(uint16_t port);
++void microchip_pnp_exit_conf_state(uint16_t port);
++uint8_t pnp_read(uint16_t port, uint8_t index);
++uint32_t pnp_read_le32(uint16_t port, uint8_t index);
++void pnp_write(uint16_t port, uint8_t index, uint8_t value);
++void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value);
++
++#define EC0_CMD 0x0066
++#define EC0_DATA 0x0062
++#define EC1_CMD 0x1604
++#define EC1_DATA 0x1600
++#define EC2_CMD 0x1634
++#define EC2_DATA 0x1630
++#define EC3_CMD 0x161c
++#define EC3_DATA 0x1618
++
++#define EC_OBF (1 << 0)
++#define EC_IBF (1 << 1)
++
++#define EC_READ 0x80
++#define EC_WRITE 0x81
++
++uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr);
++
++void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val);
++
++// EC0 and EC1 mostly are useful with the READ/WRITE commands
++#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr)
++#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val)
++#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr)
++#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val)
++
++// Read from the emulated EEPROM
++uint8_t eeprom_read(uint16_t addr);
++
++// Write to the emulated EEPROM
++void eeprom_write(uint16_t addr, uint8_t val);
++
++// Read loaded debug key mask
++uint16_t debug_loaded_keys(void);
++
++// The following location (via either EC0 or EC1) can be used to interact with the debug interface
++#define EC_DEBUG_CMD 0x3d
++
++void debug_read_key(uint8_t i, uint8_t *key);
++
++void debug_write_key(uint8_t i, const uint8_t *key);
++
++uint32_t debug_read_dword(uint32_t addr);
++
++void debug_write_dword(uint32_t addr, uint32_t val);
++
++// RW unlock key index
++#define DEBUG_RW_KEY_IDX 1
++
++// RW unlock key for EC version N24HT37W
++extern const uint8_t debug_rw_key[8];
++
++#endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+new file mode 100644
+index 0000000000..d89ed712d4
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef GPIO_H
++#define GPIO_H
++
++void variant_config_gpios(void);
++
++#endif
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+new file mode 100644
+index 0000000000..44c8578852
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
+@@ -0,0 +1,105 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include
++#include "ec.h"
++#include "gpio.h"
++
++#define GPIO_GPU_RST GPP_E22 // active low
++#define GPIO_1R8VIDEO_AON_ON GPP_E23
++
++#define GPIO_DGFX_PWRGD GPP_F3
++
++#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low
++#define GPIO_DGFX_VRAM_ID0 GPP_D11
++#define GPIO_DGFX_VRAM_ID1 GPP_D12
++
++void mainboard_silicon_init_params(FSP_SIL_UPD *params)
++{
++ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
++
++ int dgfx_vram_id;
++
++ // Setup GPIOs
++ variant_config_gpios();
++
++ // Detect and enable dGPU
++ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low
++ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1;
++ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]);
++
++ // NOTE: i pulled this GPU enable sequence from thin air
++ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default.
++ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels
++ if (get_uint_option("dgpu_enable", 0)) {
++ printk(BIOS_DEBUG, "Enabling discrete GPU\n");
++ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail
++ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU
++ ;
++ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset
++ } else {
++ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n");
++ }
++
++ } else {
++ printk(BIOS_DEBUG, "Discrete GPU not present\n");
++ }
++}
++
++static void dump_ec_cfg(uint16_t port)
++{
++ microchip_pnp_enter_conf_state(port);
++
++ // Device info
++ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID));
++ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV));
++
++ // Switch to LPCIF LDN
++ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
++
++ // Dump SIRQs
++ for (int i = 0; i <= 15; i += 1)
++ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i)));
++
++ // Dump BARs
++ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG));
++ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX));
++ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042));
++ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0));
++ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1));
++ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2));
++ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3));
++ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0));
++ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART));
++ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD));
++ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH));
++ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI));
++ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI));
++ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7));
++ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0));
++ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1));
++ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC));
++
++ microchip_pnp_exit_conf_state(port);
++}
++
++static void mainboard_enable(struct device *dev)
++{
++ if (CONFIG(VGA_ROM_RUN))
++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
++ GMA_INT15_PANEL_FIT_DEFAULT,
++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++static void mainboard_init(void *chip_info)
++{
++ dump_ec_cfg(EC_CFG_PORT);
++}
++
++struct chip_operations mainboard_ops = {
++ .enable_dev = mainboard_enable,
++ .init = mainboard_init,
++};
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
+GIT binary patch
+literal 4106
+zcmeHJU2GIp6h5=FKeKmc=rAo()>4l^U|XP_ZDGYy!|YE>mu}hZ4|PdQy1bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+
+z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr
+zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^LXW8|
+z-Vsanq!Y==Kq9plQ+*gu^hf&pJ9?tY{h01cbtR&SfsVM!_*!D4W5>papLuo?gRur|
+zF$`lX;f2t48Dpd4V@(*z=dq95OkkfiVU53N<(gE+=U)KHEdU4}@R=aMjTTTOcb8-a
+zC9IXSxZB*|#u~SlHnpsY25L#Sxy6ljl16gI)H0f>for?qaszCX;ESpG=pqROFWR~Z
+zTqQzcH(berra`9K(R~0OJ_eeA=>
+z&R-)LYP^U3@%6h}+0)7m-mEOhOM92l32>zpvu-&@ZkPf<>~Bsv&Oy1O(`pbLUf3vt*0HIRk0U3EzI
+zIeSaIE9*jps%6qP7$EQo8=K#f^K_mFpy5prkNNSOU;oI@KK0}Ge*G6eyWz+6OyADf
+zE`}Db#-81u-uS=OJB*=`v}WPMs@ugdtLtbZo6OEUf}>!QL`
+z1zQ!pLt!Zek0|;p3VTDrj}`q(g?+8yuZk|KY?X>TRlP@LPpbH`s-ITbSygS+Jq6cQ
+zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~
+zJJ%lV6&>fxBjnbA8G(&P?a8o%P#c~Wo$7|%1UE-$r;6jwt1uejOfMLwF-BDgC-Q+N
+za!Hx;1S&$9!rlNCTsI*IMZ0#Y5aEO7sjIz#jb`S|q7OpRYx`h&=PK}_YnN#poNF=7
+z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA
+z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j
+z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+new file mode 100644
+index 0000000000..f7c29e1f39
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
+@@ -0,0 +1,203 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include "../../gpio.h"
++
++/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
++ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
++
++static const struct pad_config gpio_table[] = {
++
++ /* ------- GPIO Community 0 ------- */
++
++ /* ------- GPIO Group GPP_A ------- */
++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
++ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */
++ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */
++ PAD_NC(GPP_A11, NONE),
++ PAD_NC(GPP_A12, NONE),
++ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
++ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
++ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */
++ PAD_NC(GPP_A16, NONE),
++ PAD_NC(GPP_A17, NONE),
++ PAD_NC(GPP_A18, NONE),
++ PAD_NC(GPP_A19, NONE),
++ PAD_NC(GPP_A20, NONE),
++ PAD_NC(GPP_A21, NONE),
++ PAD_NC(GPP_A22, NONE),
++ PAD_NC(GPP_A23, NONE),
++
++ /* ------- GPIO Group GPP_B ------- */
++ PAD_NC(GPP_B0, NONE),
++ PAD_NC(GPP_B1, NONE),
++ PAD_NC(GPP_B2, NONE),
++ PAD_NC(GPP_B3, NONE),
++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */
++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */
++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */
++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */
++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */
++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */
++ PAD_NC(GPP_B11, NONE),
++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
++ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
++ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */
++ PAD_NC(GPP_B16, NONE),
++ PAD_NC(GPP_B17, NONE),
++ PAD_NC(GPP_B18, NONE),
++ PAD_NC(GPP_B19, NONE),
++ PAD_NC(GPP_B20, NONE),
++ PAD_NC(GPP_B21, NONE),
++ PAD_NC(GPP_B22, NONE),
++ PAD_NC(GPP_B23, NONE),
++
++ /* ------- GPIO Community 1 ------- */
++
++ /* ------- GPIO Group GPP_C ------- */
++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
++ PAD_NC(GPP_C2, NONE),
++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
++ PAD_NC(GPP_C5, NONE),
++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
++ PAD_NC(GPP_C8, NONE),
++ PAD_NC(GPP_C9, NONE),
++ PAD_NC(GPP_C10, NONE),
++ PAD_NC(GPP_C11, NONE),
++ PAD_NC(GPP_C12, NONE),
++ PAD_NC(GPP_C13, NONE),
++ PAD_NC(GPP_C14, NONE),
++ PAD_NC(GPP_C15, NONE),
++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
++ PAD_NC(GPP_C18, NONE),
++ PAD_NC(GPP_C19, NONE),
++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
++
++ /* ------- GPIO Group GPP_D ------- */
++ PAD_NC(GPP_D0, NONE),
++ PAD_NC(GPP_D1, NONE),
++ PAD_NC(GPP_D2, NONE),
++ PAD_NC(GPP_D3, NONE),
++ PAD_NC(GPP_D4, NONE),
++ PAD_NC(GPP_D5, NONE),
++ PAD_NC(GPP_D6, NONE),
++ PAD_NC(GPP_D7, NONE),
++ PAD_NC(GPP_D8, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
++ PAD_NC(GPP_D10, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
++ PAD_NC(GPP_D13, NONE),
++ PAD_NC(GPP_D14, NONE),
++ PAD_NC(GPP_D15, NONE),
++ PAD_NC(GPP_D16, NONE),
++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */
++ PAD_NC(GPP_D18, NONE),
++ PAD_NC(GPP_D19, NONE),
++ PAD_NC(GPP_D20, NONE),
++ PAD_NC(GPP_D21, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
++ PAD_NC(GPP_D23, NONE),
++
++ /* ------- GPIO Group GPP_E ------- */
++ PAD_NC(GPP_E0, NONE),
++ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */
++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
++ PAD_NC(GPP_E5, NONE),
++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
++ PAD_NC(GPP_E7, NONE),
++ PAD_NC(GPP_E8, NONE),
++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */
++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */
++ PAD_NC(GPP_E11, NONE),
++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
++ PAD_NC(GPP_E15, NONE),
++ PAD_NC(GPP_E16, NONE),
++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
++ PAD_NC(GPP_E18, NONE),
++ PAD_NC(GPP_E19, NONE),
++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
++
++ /* ------- GPIO Community 2 ------- */
++
++ /* -------- GPIO Group GPD -------- */
++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
++ PAD_NC(GPD7, NONE),
++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
++
++ /* ------- GPIO Community 3 ------- */
++
++ /* ------- GPIO Group GPP_F ------- */
++ PAD_NC(GPP_F0, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */
++ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */
++ PAD_NC(GPP_F5, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
++ PAD_NC(GPP_F16, NONE),
++ PAD_NC(GPP_F17, NONE),
++ PAD_NC(GPP_F18, NONE),
++ PAD_NC(GPP_F19, NONE),
++ PAD_NC(GPP_F20, NONE),
++ PAD_NC(GPP_F21, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
++
++ /* ------- GPIO Group GPP_G ------- */
++ PAD_NC(GPP_G0, NONE),
++ PAD_NC(GPP_G1, NONE),
++ PAD_NC(GPP_G2, NONE),
++ PAD_NC(GPP_G3, NONE),
++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
++};
++
++void variant_config_gpios(void)
++{
++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
+new file mode 100644
+index 0000000000..3a951ce0da
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
+@@ -0,0 +1,90 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
++ 0x17aa225d, // Subsystem ID
++ 11,
++ AZALIA_SUBVENDOR(0, 0x17aa225d),
++
++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
++ AZALIA_INTEGRATED,
++ AZALIA_INTERNAL,
++ AZALIA_MIC_IN,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_NO_JACK_PRESENCE_DETECT,
++ 2, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
++ AZALIA_INTEGRATED,
++ AZALIA_INTERNAL,
++ AZALIA_SPEAKER,
++ AZALIA_OTHER_ANALOG,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_NO_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
++ AZALIA_MIC_IN,
++ AZALIA_STEREO_MONO_1_8,
++ AZALIA_BLACK,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 3, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
++ AZALIA_HP_OUT,
++ AZALIA_STEREO_MONO_1_8,
++ AZALIA_BLACK,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 15
++ )),
++
++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
++ 0x80860101, // Subsystem ID
++ 4,
++ AZALIA_SUBVENDOR(2, 0x80860101),
++
++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 2, 0
++ )),
++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 3, 0
++ )),
++};
++
++const u32 pc_beep_verbs[] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
+new file mode 100644
+index 0000000000..5252a402f9
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
+@@ -0,0 +1,20 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++void mainboard_memory_init_params(FSPM_UPD *mupd)
++{
++ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
++ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */
++ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
++ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
++
++ /* Get SPD for memory slots */
++ struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
++ get_spd_smbus(&blk);
++ dump_spd_info(&blk);
++
++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+new file mode 100644
+index 0000000000..bf66bd3a69
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
+@@ -0,0 +1,103 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++chip soc/intel/skylake
++ device domain 0 on
++ device ref south_xhci on
++ register "usb2_ports" = "{
++ [0] = USB2_PORT_MID(OC1), // USB-A
++ [1] = USB2_PORT_MID(OC0), // USB-A (always on)
++ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot)
++ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port)
++ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera)
++ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB)
++ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB)
++ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam)
++ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader)
++ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel)
++ }"
++ register "usb3_ports" = "{
++ [0] = USB3_PORT_DEFAULT(OC1), // USB-A
++ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on)
++ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader)
++ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port)
++ }"
++ end
++
++ device ref sata on
++ # SATA_2 - JHDD1 SATA SSD
++ register "SataPortsEnable[2]" = "1"
++ register "SataPortsDevSlp[2]" = "1"
++ end
++
++ # PCIe controller 1 - 1x4
++ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0
++ #
++ # PCIe controller 2 - 2x1+1x2 (lane reversal)
++ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8)
++ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2
++ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3
++ #
++ # PCIe controller 3 - 2x2
++ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4
++ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5
++
++ # dGPU - x4
++ device ref pcie_rp1 on
++ register "PcieRpEnable[0]" = "1"
++ register "PcieRpClkReqSupport[0]" = "1"
++ register "PcieRpClkReqNumber[0]" = "0"
++ register "PcieRpClkSrcNumber[0]" = "0"
++ register "PcieRpAdvancedErrorReporting[0]" = "1"
++ register "PcieRpLtrEnable[0]" = "1"
++ end
++
++ # Ethernet (clobbers RP8)
++ device ref gbe on
++ register "LanClkReqSupported" = "1"
++ register "LanClkReqNumber" = "1"
++ register "EnableLanLtr" = "1"
++ register "EnableLanK1Off" = "1"
++ end
++
++ # M.2 WLAN - x1
++ device ref pcie_rp7 on
++ register "PcieRpEnable[6]" = "1"
++ register "PcieRpClkReqSupport[6]" = "1"
++ register "PcieRpClkReqNumber[6]" = "2"
++ register "PcieRpClkSrcNumber[6]" = "2"
++ register "PcieRpAdvancedErrorReporting[6]" = "1"
++ register "PcieRpLtrEnable[6]" = "1"
++ end
++
++ # M.2 WWAN - x2
++ device ref pcie_rp5 on
++ register "PcieRpEnable[4]" = "1"
++ register "PcieRpClkReqSupport[4]" = "1"
++ register "PcieRpClkReqNumber[4]" = "3"
++ register "PcieRpClkSrcNumber[4]" = "3"
++ register "PcieRpAdvancedErrorReporting[4]" = "1"
++ register "PcieRpLtrEnable[4]" = "1"
++ end
++
++ # TB3 (Alpine Ridge LP) - x2
++ device ref pcie_rp9 on
++ register "PcieRpEnable[8]" = "1"
++ register "PcieRpClkReqSupport[8]" = "1"
++ register "PcieRpClkReqNumber[8]" = "4"
++ register "PcieRpClkSrcNumber[8]" = "4"
++ register "PcieRpAdvancedErrorReporting[8]" = "1"
++ register "PcieRpLtrEnable[8]" = "1"
++ register "PcieRpHotPlug[8]" = "1"
++ end
++
++ # M.2 2280 caddy - x2
++ device ref pcie_rp11 on
++ register "PcieRpEnable[10]" = "1"
++ register "PcieRpClkReqSupport[10]" = "1"
++ register "PcieRpClkReqNumber[10]" = "5"
++ register "PcieRpClkSrcNumber[10]" = "5"
++ register "PcieRpAdvancedErrorReporting[10]" = "1"
++ register "PcieRpLtrEnable[10]" = "1"
++ end
++ end
++end
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840
+GIT binary patch
+literal 4106
+zcmeHJUu+a*5TCu>yW9JAmoD2P9tqx`iFWXCLD09RaS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU
+zTXkLEL3ly5L&oUX#CS7?b2%Kad?s-#@;mhg8>>>#S&)d2I
+zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP
+zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS
+z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp
+zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw
+z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b
+znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U
+z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6
+zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z
+XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
+new file mode 100644
+index 0000000000..fcfbd75a92
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
+@@ -0,0 +1,19 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++ ports : constant Port_List :=
++ (eDP,
++ DP1,
++ DP2,
++ HDMI1,
++ HDMI2,
++ others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+new file mode 100644
+index 0000000000..a98dd2bc4e
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
+@@ -0,0 +1,199 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include "../../gpio.h"
++
++static const struct pad_config gpio_table[] = {
++ /* ------- GPIO Community 0 ------- */
++
++ /* ------- GPIO Group GPP_A ------- */
++ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
++ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
++ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
++ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
++ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
++ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
++ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
++ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
++ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
++ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
++ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
++ PAD_NC(GPP_A11, NONE),
++ PAD_NC(GPP_A12, NONE),
++ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */
++ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */
++ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */
++ PAD_NC(GPP_A16, NONE),
++ PAD_NC(GPP_A17, NONE),
++ PAD_NC(GPP_A18, NONE),
++ PAD_NC(GPP_A19, NONE),
++ PAD_NC(GPP_A20, NONE),
++ PAD_NC(GPP_A21, NONE),
++ PAD_NC(GPP_A22, NONE),
++ PAD_NC(GPP_A23, NONE),
++
++ /* ------- GPIO Group GPP_B ------- */
++ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
++ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
++ PAD_NC(GPP_B2, NONE),
++ PAD_NC(GPP_B3, NONE),
++ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
++ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */
++ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */
++ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */
++ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */
++ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */
++ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */
++ PAD_NC(GPP_B11, NONE),
++ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
++ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
++ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */
++ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
++ PAD_NC(GPP_B16, NONE),
++ PAD_NC(GPP_B17, NONE),
++ PAD_NC(GPP_B18, NONE),
++ PAD_NC(GPP_B19, NONE),
++ PAD_NC(GPP_B20, NONE),
++ PAD_NC(GPP_B21, NONE),
++ PAD_NC(GPP_B22, NONE),
++ PAD_NC(GPP_B23, NONE),
++
++ /* ------- GPIO Community 1 ------- */
++
++ /* ------- GPIO Group GPP_C ------- */
++ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
++ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
++ PAD_CFG_GPO(GPP_C2, 1, DEEP),
++ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
++ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
++ PAD_NC(GPP_C5, NONE),
++ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
++ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
++ PAD_NC(GPP_C8, NONE),
++ PAD_NC(GPP_C9, NONE),
++ PAD_NC(GPP_C10, NONE),
++ PAD_NC(GPP_C11, NONE),
++ PAD_NC(GPP_C12, NONE),
++ PAD_NC(GPP_C13, NONE),
++ PAD_NC(GPP_C14, NONE),
++ PAD_NC(GPP_C15, NONE),
++ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
++ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
++ PAD_NC(GPP_C18, NONE),
++ PAD_NC(GPP_C19, NONE),
++ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
++ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
++ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
++ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
++
++ /* ------- GPIO Group GPP_D ------- */
++ PAD_NC(GPP_D0, NONE),
++ PAD_NC(GPP_D1, NONE),
++ PAD_NC(GPP_D2, NONE),
++ PAD_NC(GPP_D3, NONE),
++ PAD_NC(GPP_D4, NONE),
++ PAD_NC(GPP_D5, NONE),
++ PAD_NC(GPP_D6, NONE),
++ PAD_NC(GPP_D7, NONE),
++ PAD_NC(GPP_D8, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
++ PAD_NC(GPP_D10, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
++ PAD_NC(GPP_D13, NONE),
++ PAD_NC(GPP_D14, NONE),
++ PAD_NC(GPP_D15, NONE),
++ PAD_NC(GPP_D16, NONE),
++ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
++ PAD_NC(GPP_D18, NONE),
++ PAD_NC(GPP_D19, NONE),
++ PAD_NC(GPP_D20, NONE),
++ PAD_NC(GPP_D21, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
++ PAD_NC(GPP_D23, NONE),
++
++ /* ------- GPIO Group GPP_E ------- */
++ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
++ PAD_NC(GPP_E1, NONE),
++ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
++ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
++ PAD_NC(GPP_E5, NONE),
++ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
++ PAD_NC(GPP_E7, NONE),
++ PAD_NC(GPP_E8, NONE),
++ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
++ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
++ PAD_NC(GPP_E11, NONE),
++ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
++ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
++ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
++ PAD_NC(GPP_E15, NONE),
++ PAD_NC(GPP_E16, NONE),
++ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
++ PAD_NC(GPP_E18, NONE),
++ PAD_CFG_GPO(GPP_E19, 0, DEEP),
++ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
++ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
++ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
++ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
++
++ /* ------- GPIO Community 2 ------- */
++
++ /* -------- GPIO Group GPD -------- */
++ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
++ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
++ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
++ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
++ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
++ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
++ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
++ PAD_NC(GPD7, NONE),
++ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
++ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
++ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
++ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
++
++ /* ------- GPIO Community 3 ------- */
++
++ /* ------- GPIO Group GPP_F ------- */
++ PAD_CFG_GPO(GPP_F0, 0, DEEP),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
++ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */
++ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
++ PAD_NC(GPP_F5, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
++ PAD_NC(GPP_F21, NONE),
++ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */
++ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
++
++ /* ------- GPIO Group GPP_G ------- */
++ PAD_NC(GPP_G0, NONE),
++ PAD_NC(GPP_G1, NONE),
++ PAD_NC(GPP_G2, NONE),
++ PAD_NC(GPP_G3, NONE),
++ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
++ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
++ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
++ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
++};
++
++void variant_config_gpios(void)
++{
++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
++}
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
+new file mode 100644
+index 0000000000..b1d96c5a76
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
+@@ -0,0 +1,90 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
++ 0x17aa2258, // Subsystem ID
++ 11,
++ AZALIA_SUBVENDOR(0, 0x17aa2258),
++
++ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
++ AZALIA_INTEGRATED,
++ AZALIA_INTERNAL,
++ AZALIA_MIC_IN,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_NO_JACK_PRESENCE_DETECT,
++ 2, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
++ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
++ AZALIA_INTEGRATED,
++ AZALIA_INTERNAL,
++ AZALIA_SPEAKER,
++ AZALIA_OTHER_ANALOG,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_NO_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
++ AZALIA_MIC_IN,
++ AZALIA_STEREO_MONO_1_8,
++ AZALIA_BLACK,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 3, 0
++ )),
++ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
++ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
++ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
++ AZALIA_HP_OUT,
++ AZALIA_STEREO_MONO_1_8,
++ AZALIA_BLACK,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 15
++ )),
++
++ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
++ 0x80860101, // Subsystem ID
++ 4,
++ AZALIA_SUBVENDOR(2, 0x80860101),
++
++ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
++ AZALIA_JACK,
++ AZALIA_DIGITAL_DISPLAY,
++ AZALIA_DIGITAL_OTHER_OUT,
++ AZALIA_OTHER_DIGITAL,
++ AZALIA_COLOR_UNKNOWN,
++ AZALIA_JACK_PRESENCE_DETECT,
++ 1, 0
++ )),
++};
++
++const u32 pc_beep_verbs[] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+new file mode 100644
+index 0000000000..001e934b3a
+--- /dev/null
++++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
+@@ -0,0 +1,44 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include