diff --git a/.gitignore b/.gitignore
index 4979e1f9..36ac930c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,9 +1,8 @@
*~
*.o
-/cache/
/lbmk.err.log
-/repo/
/docs/
+/cbutils/
/pciroms/
/util/dell-flash-unlock/dell_flash_unlock
/TODO
@@ -24,23 +23,9 @@
/push
/version
/versiondate
-/.version
-/.versiondate
/vendorfiles/
*me.bin
*sch5545ec.bin
/mrc/
/util/nvmutil/nvm
/src/
-/CHANGELOG
-/todo.txt
-/lock
-/hash/
-/dump/
-/qrun*.sh
-*.tar.*
-/m
-/f
-/r
-/e
-/xbmkpath/
diff --git a/README.md b/README.md
index e6452dbd..7f73a3e2 100644
--- a/README.md
+++ b/README.md
@@ -1,57 +1,123 @@
Libreboot
=========
-Documentation: [libreboot.org](https://libreboot.org)\
-Support: [\#libreboot](https://web.libera.chat/#libreboot) on
- [Libera](https://libera.chat/) IRC
+Find libreboot documentation at .
-License for this README
------------------------
+LICENSE FOR THIS README
+=======================
-It's just a README file. It is released under
-[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
+It's just a README file. This README file is released under the terms of the
+Creative Commons Zero license, version 1.0 of the license, which you can
+read here:
+
diff --git a/build b/build
new file mode 100755
index 00000000..277390fd
--- /dev/null
+++ b/build
@@ -0,0 +1,134 @@
+#!/usr/bin/env sh
+# SPDX-License-Identifier: GPL-3.0-or-later
+# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe
+# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott
+# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni
+# SPDX-FileCopyrightText: 2022, Caleb La Grange
+
+set -u -e
+
+. "include/err.sh"
+. "include/option.sh"
+
+eval "$(setvars "" option aur_notice)"
+err="fail"
+
+linkpath="${0}"
+linkname="${linkpath##*/}"
+buildpath="./script/${linkname}"
+
+main()
+{
+ x_ id -u 1>/dev/null 2>/dev/null
+ [ $# -lt 1 ] && $err "Too few arguments. Try: ${0} help"
+
+ [ "$1" = "dependencies" ] && x_ install_packages $@ && lbmk_exit 0
+
+ for cmd in initcmd check_git check_project git_init excmd; do
+ eval "${cmd} \$@"
+ done
+ lbmk_exit 0
+}
+
+initcmd()
+{
+ [ "$(id -u)" != "0" ] || $err "this command as root is not permitted"
+
+ check_project
+
+ case "${1}" in
+ help) usage ${0} ;;
+ list) items "${buildpath}" ;;
+ version) mkversion ;;
+ *)
+ option="${1}"
+ return 0 ;;
+ esac
+ lbmk_exit 0
+}
+
+install_packages()
+{
+ if [ $# -lt 2 ]; then
+ printf "You must specify a distro, namely:\n" 1>&2
+ printf "Look at files under config/dependencies/\n" 1>&2
+ printf "Example: ./build dependencies debian\n" 1>&2
+ $err "install_packages: target not specified"
+ fi
+
+ [ -f "config/dependencies/${2}" ] || $err "Unsupported target"
+
+ . "config/dependencies/${2}"
+
+ x_ ${pkg_add} ${pkglist}
+ [ -z "${aur_notice}" ] && return 0
+ printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2
+}
+
+# release archives contain .gitignore, but not .git.
+# lbmk can be run from lbmk.git, or an archive.
+git_init()
+{
+ [ -L ".git" ] && $err "Reference .git is a symlink"
+ [ -e ".git" ] && return 0
+ eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
+
+ git init || $err "${PWD}: cannot initialise Git repository"
+ git add -A . || $err "${PWD}: cannot add files to Git repository"
+ git commit -m "${projectname} ${version}" --date "${cdate}" \
+ --author="lbmk " || \
+ $err "$PWD: can't commit ${projectname}/${version}, date $cdate"
+ git tag -a "${version}" -m "${projectname} ${version}" || \
+ $err "${PWD}: cannot git-tag ${projectname}/${version}"
+}
+
+excmd()
+{
+ lbmkcmd="${buildpath}/${option}"
+ [ -f "${lbmkcmd}" ] || $err "Invalid command. Run: ${linkpath} help"
+ shift 1; "$lbmkcmd" $@ || $err "excmd: ${lbmkcmd} ${@}"
+}
+
+usage()
+{
+ progname=${0}
+ cat <<- EOF
+ $(mkversion)
+
+ USAGE: ${progname}
+
+ possible values for 'OPTION':
+ $(items "${buildpath}")
+
+ To know what ${projectname} version you're on, type:
+ ${progname} version
+
+ Refer to ${projectname} documentation for more info.
+ EOF
+}
+
+mkversion()
+{
+ printf "revision: %s %s\n" "$projectname" "$version"
+ printf "revision date: %s\n" "$(date -Rud @${versiondate})"
+}
+
+lbmk_exit()
+{
+ tmp_cleanup || err_ "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir"
+ exit $1
+}
+
+fail()
+{
+ tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2
+ err_ "${1}"
+}
+
+tmp_cleanup()
+{
+ [ "${tmpdir_was_set}" = "n" ] || return 0
+ rm -Rf "${tmpdir}" || return 1
+}
+
+main $@
diff --git a/config/coreboot/build.list b/config/coreboot/build.list
new file mode 100644
index 00000000..f6535149
--- /dev/null
+++ b/config/coreboot/build.list
@@ -0,0 +1 @@
+build/coreboot.rom
diff --git a/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch b/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch
new file mode 100644
index 00000000..dfc684e1
--- /dev/null
+++ b/config/coreboot/coreboot413/patches/0001-cbfstool-Make-use-of-spurious-null-termination.patch
@@ -0,0 +1,56 @@
+From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
+From: Nico Huber
+Date: Tue, 22 Jun 2021 13:49:44 +0000
+Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
+
+The null-termination of `filetypes` was added after the code was
+written, obviously resulting in NULL dereferences. As some more
+code has grown around the termination, it's hard to revert the
+regression, so let's update the code that still used the array
+length.
+
+This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
+which actually did fix something, but only one path while it broke
+two others. We should be careful with fixes, they can always break
+something else. Especially when a dumb tool triggered the patching
+it seems likely that fewer people looked into related code.
+
+Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
+Signed-off-by: Nico Huber
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
+Tested-by: build bot (Jenkins)
+Reviewed-by: Julius Werner
+---
+ util/cbfstool/common.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
+index e2ed38ffc4..539d0baccf 100644
+--- a/util/cbfstool/common.c
++++ b/util/cbfstool/common.c
+@@ -168,10 +168,10 @@ void print_supported_architectures(void)
+
+ void print_supported_filetypes(void)
+ {
+- int i, number = ARRAY_SIZE(filetypes);
++ int i;
+
+- for (i=0; i
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
similarity index 90%
rename from config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
rename to config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
index 31c1bb30..8cd272ec 100644
--- a/config/coreboot/default/patches/0001-add-c3-and-clockgen-to-apple-macbook21.patch
+++ b/config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
@@ -1,7 +1,7 @@
-From bd959c38f6ee21db1ff8f4fbb0675e38bfbe1147 Mon Sep 17 00:00:00 2001
+From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -10,10 +10,10 @@ Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index 330d8efae2..cf10343554 100644
+index 5f5ffde588..27377b737c 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
end
end
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
new file mode 100644
index 00000000..34e12a6b
--- /dev/null
+++ b/config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
@@ -0,0 +1,23 @@
+From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
new file mode 100644
index 00000000..ee90dd63
--- /dev/null
+++ b/config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
@@ -0,0 +1,22 @@
+From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
new file mode 100644
index 00000000..35d74c75
--- /dev/null
+++ b/config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
@@ -0,0 +1,23 @@
+From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Fri, 14 May 2021 13:10:33 +0100
+Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/lenovo/t400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index a326e315b1..b907a3e2df 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
++++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -13,4 +13,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=32M
++gfx_uma_size=256M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
new file mode 100644
index 00000000..cc6abb00
--- /dev/null
+++ b/config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
@@ -0,0 +1,23 @@
+From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Fri, 14 May 2021 13:11:59 +0100
+Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/lenovo/x200/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index bb4323836e..458b3f19c5 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
++++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -12,4 +12,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
new file mode 100644
index 00000000..c4840ecc
--- /dev/null
+++ b/config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
@@ -0,0 +1,23 @@
+From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Fri, 14 May 2021 13:18:26 +0100
+Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index 8372032119..bedad54d2a 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=64M
++gfx_uma_size=256M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
new file mode 100644
index 00000000..19977870
--- /dev/null
+++ b/config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
@@ -0,0 +1,23 @@
+From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Fri, 14 May 2021 13:21:39 +0100
+Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/acer/g43t-am3/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 706f5dd551..e8b45ea22c 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
++++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=64M
++gfx_uma_size=256M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
similarity index 89%
rename from config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
rename to config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
index 0c2b080f..332b870e 100644
--- a/config/coreboot/default/patches/0002-lenovo-t400-Enable-all-SATA-ports.patch
+++ b/config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
@@ -1,7 +1,7 @@
-From e5eab4c8043b89a325b4a28bf7da456d68475144 Mon Sep 17 00:00:00 2001
+From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
From: persmule
Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/37] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
register "sata_traffic_monitor" = "0"
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
new file mode 100644
index 00000000..12917ed8
--- /dev/null
+++ b/config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
@@ -0,0 +1,22 @@
+From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 20 Dec 2021 01:29:31 +0000
+Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+ default
+
+---
+ src/mainboard/lenovo/x230/cmos.default | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 7314066c2b..2e315d4521 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
++++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+ me_state=Normal
++gfx_uma_size=224M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
similarity index 83%
rename from config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
rename to config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
index 4ccde9a6..dc3a33ca 100644
--- a/config/coreboot/default/patches/0003-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
+++ b/config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
@@ -1,7 +1,7 @@
-From fd398cc10600cccce3dd4931651a5294ffebde9a Mon Sep 17 00:00:00 2001
+From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/37] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@@ -23,15 +23,16 @@ Date: Thu Nov 21 21:47:31 2019 +0300
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 732e214b32..8454f0eac0 100644
+index 2e315d4521..3585cbd58b 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,5 +15,5 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
+ gfx_uma_size=224M
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
similarity index 81%
rename from config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
rename to config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
index 39319d58..49f4db9b 100644
--- a/config/coreboot/default/patches/0004-set-me_state-Disabled-on-all-cmos.default-files.patch
+++ b/config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
@@ -1,7 +1,7 @@
-From 74230d8123cb7c31afd084658720084b1a5ac5d9 Mon Sep 17 00:00:00 2001
+From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/37] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@@ -20,105 +20,103 @@ Signed-off-by: Leah Rowe
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
-index be08e0a342..b8970efa46 100644
+index 681c40e78b..57cdcf9162 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index c896eadec1..6d1e172056 100644
+index 26795fe5cf..55e1e6c04e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
-index 286fb0ae8c..5a05c73721 100644
+index 52dbf70377..b16800ca9e 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
-@@ -18,4 +18,4 @@ backlight=Both
+@@ -16,4 +16,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index ef706c1303..b318ab9772 100644
+index 6d1d57a795..52f303dfdb 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -15,4 +15,4 @@ usb_always_on=Disable
+@@ -13,4 +13,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
--- a/src/mainboard/protectli/vault_cml/cmos.default
+++ b/src/mainboard/protectli/vault_cml/cmos.default
-@@ -2,4 +2,4 @@
-
+@@ -1,3 +1,3 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
--- a/src/mainboard/system76/tgl-u/cmos.default
+++ b/src/mainboard/system76/tgl-u/cmos.default
-@@ -2,4 +2,4 @@
-
+@@ -1,3 +1,3 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
new file mode 100644
index 00000000..a71324db
--- /dev/null
+++ b/config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
@@ -0,0 +1,203 @@
+From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe
+---
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
+ 1 file changed, 81 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 191b3216de..38132b4a28 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
+ " tgl - Tiger Lake\n"
+ " wbg - Wellsburg\n"
+ " -S | --setpchstrap Write a PCH strap\n"
++ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n"
+ " -V | --newvalue The new value to write into PCH strap specified by -S\n"
+ " -v | --version: print the version\n"
+ " -h | --help: print this help\n\n"
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
+ "\n");
+ }
+
++static int
++get_region_type_string(const char *region_type_string)
++{
++ if (!strcasecmp("Descriptor", region_type_string))
++ return 0;
++ else if (!strcasecmp("BIOS", region_type_string))
++ return 1;
++ else if (!strcasecmp("ME", region_type_string))
++ return 2;
++ else if (!strcasecmp("GbE", region_type_string))
++ return 3;
++ else if (!strcasecmp("Platform Data", region_type_string))
++ return 4;
++ else if (!strcasecmp("Device Exp1", region_type_string))
++ return 5;
++ else if (!strcasecmp("Secondary BIOS", region_type_string))
++ return 6;
++ else if (!strcasecmp("Reserved", region_type_string))
++ return 7;
++ else if (!strcasecmp("EC", region_type_string))
++ return 8;
++ else if (!strcasecmp("Device Exp2", region_type_string))
++ return 9;
++ else if (!strcasecmp("IE", region_type_string))
++ return 10;
++ else if (!strcasecmp("10GbE_0", region_type_string))
++ return 11;
++ else if (!strcasecmp("10GbE_1", region_type_string))
++ return 12;
++ else if (!strcasecmp("PTT", region_type_string))
++ return 15;
++ return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++ int i;
++ struct region region;
++ const struct frba *frba = find_frba(image, size);
++ if (!frba)
++ exit(EXIT_FAILURE);
++
++ region = get_region(frba, region_type);
++ if (region.size > 0) {
++ for (i = region.base; i <= region.limit; i++) {
++ if ((i + 1) > (size))
++ break;
++ image[i] = 0xFF;
++ }
++ write_image(filename, image, size);
++ }
++}
++
+ int main(int argc, char *argv[])
+ {
+ int opt, option_index = 0;
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
+ int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++ int mode_nuke = 0;
+ int mode_gpr0_disable = 0;
+ char *region_type_string = NULL, *region_fname = NULL;
+ const char *layout_fname = NULL;
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
+ {"validate", 0, NULL, 't'},
+ {"setpchstrap", 1, NULL, 'S'},
+ {"newvalue", 1, NULL, 'V'},
++ {"nuke", 1, NULL, 'N'},
+ {0, 0, 0, 0}
+ };
+
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
+ region_fname++;
+ // Descriptor, BIOS, ME, GbE, Platform
+ // valid type?
+- if (!strcasecmp("Descriptor", region_type_string))
+- region_type = 0;
+- else if (!strcasecmp("BIOS", region_type_string))
+- region_type = 1;
+- else if (!strcasecmp("ME", region_type_string))
+- region_type = 2;
+- else if (!strcasecmp("GbE", region_type_string))
+- region_type = 3;
+- else if (!strcasecmp("Platform Data", region_type_string))
+- region_type = 4;
+- else if (!strcasecmp("Device Exp1", region_type_string))
+- region_type = 5;
+- else if (!strcasecmp("Secondary BIOS", region_type_string))
+- region_type = 6;
+- else if (!strcasecmp("Reserved", region_type_string))
+- region_type = 7;
+- else if (!strcasecmp("EC", region_type_string))
+- region_type = 8;
+- else if (!strcasecmp("Device Exp2", region_type_string))
+- region_type = 9;
+- else if (!strcasecmp("IE", region_type_string))
+- region_type = 10;
+- else if (!strcasecmp("10GbE_0", region_type_string))
+- region_type = 11;
+- else if (!strcasecmp("10GbE_1", region_type_string))
+- region_type = 12;
+- else if (!strcasecmp("PTT", region_type_string))
+- region_type = 15;
+- if (region_type == -1) {
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
+ case 't':
+ mode_validate = 1;
+ break;
++ case 'N':
++ region_type_string = strdup(optarg);
++ if (!region_type_string) {
++ fprintf(stderr, "No region specified\n");
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ if ((region_type =
++ get_region_type_string(region_type_string)) == -1) {
++ fprintf(stderr, "No such region type: '%s'\n\n",
++ region_type_string);
++ print_usage(argv[0]);
++ exit(EXIT_FAILURE);
++ }
++ mode_nuke = 1;
++ break;
+ case 'v':
+ print_version();
+ exit(EXIT_SUCCESS);
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+- mode_gpr0_disable) > 1) {
++ mode_gpr0_disable + mode_nuke) > 1) {
+ fprintf(stderr, "You may not specify more than one mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
+ if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+- mode_validate + mode_gpr0_disable) == 0) {
++ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
+ fprintf(stderr, "You need to specify a mode.\n\n");
+ fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ exit(EXIT_FAILURE);
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
+ write_image(new_filename, image, size);
+ }
+
++ if (mode_nuke) {
++ nuke(new_filename, image, size, region_type);
++ }
++
+ if (mode_altmedisable) {
+ struct fpsba *fpsba = find_fpsba(image, size);
+ struct fmsba *fmsba = find_fmsba(image, size);
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
new file mode 100644
index 00000000..279fdad1
--- /dev/null
+++ b/config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
@@ -0,0 +1,47 @@
+From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+
+-#define IA32_PECI_CTL 0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+ }
+-
+- /* Enable PECI
+- WARNING: due to Erratum AW67 described in Intel document #318733
+- the microcode must be updated before this MSR is written to. */
+- msr = rdmsr(IA32_PECI_CTL);
+- msr.lo |= 1;
+- wrmsr(IA32_PECI_CTL, msr);
+ }
+
+ #define PIC_SENS_CFG 0x1aa
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
new file mode 100644
index 00000000..4e5f5089
--- /dev/null
+++ b/config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
@@ -0,0 +1,173 @@
+From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
+ src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #define MSR_BBL_CR_CTL3 0x11e
+
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ fill_processor_name(processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states(quad);
+
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ smm_initialize();
+ }
+
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+- set_feature_ctrl_vmx();
+- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+- /* We don't care if the lock is already setting
+- as our smm relocation handler is able to handle
+- setups where SMRR is not enabled here. */
+- if (ia32_ft_ctrl.lo & (1 << 0)) {
+- /* IA32_FEATURE_CONTROL locked. If we set it again we
+- get an illegal instruction. */
+- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+- } else {
+- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+- printk(BIOS_INFO,
+- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+- }
+- } else {
+- set_vmx_and_lock();
+- }
+-
+ /* Relocate the SMM handler. */
+ smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ fill_processor_name(processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ /* Setup Page Attribute Tables (PAT) */
+ // TODO set up PAT
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #define HIGHEST_CLEVEL 3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ /* Setup Page Attribute Tables (PAT) */
+ // TODO set up PAT
+
++ /* Set virtualization based on Kconfig option */
++ set_vmx_and_lock();
++
+ /* Configure C States */
+ configure_c_states();
+
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch b/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
deleted file mode 100644
index 4ba74757..00000000
--- a/config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 6acc310c1d695d47c148296da9da189de21d58be Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 17/37] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
-
-We add this patch:
-
-commit commit_id_here
-Author: Angel Pons
-Date: Mon May 10 22:40:59 2021 +0200
-
- nb/intel/gm45: Make DDR2 raminit work
-
-This patch was original applied, in lbmk, only on coreboot/dell,
-separately from coreboot/default, which was wasteful because it
-meant having an entire coreboot tree just for a single board. We
-did this, because the DDR2 RCOMP fix happened to break DDR3 init
-on other boards.
-
-What *this* new patch does on top of Angel's patch, is make sure
-that their changes only apply to DDR2, while DDR3 behaviour remains
-unchanged. This means that the Dell Latitude E6400 can be supported
-in the main coreboot tree, within lbmk.
-
-Essentially, this patch restores the old behaviour, prior to applying
-Angel's patch, only when DDR3 memory is used.
-
-Signed-off-by: Leah Rowe
----
- src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
- .../intel/gm45/raminit_rcomp_calibration.c | 9 +-
- 2 files changed, 88 insertions(+), 82 deletions(-)
-
-diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index df8f46fbbc..433db3a68c 100644
---- a/src/northbridge/intel/gm45/raminit.c
-+++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
- reg = (reg & ~(0xf << 10)) | (2 << 10);
- else
- reg = (reg & ~(0xf << 10)) | (3 << 10);
-- reg = (reg & ~(0x7 << 5)) | (2 << 5);
-+ if (spd_type == DDR2)
-+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
-+ else
-+ reg = (reg & ~(0x7 << 5)) | (3 << 5);
- } else if (timings->mem_clock != MEM_CLOCK_1067MT) {
- reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
- reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
- raminit_write_training(timings->mem_clock, dimms, s3resume);
- }
-
-- /*
-- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
-- * after receiver enable calibration, otherwise raminit sometimes
-- * completes with non-working memory.
-- */
-- mchbar_write32(0x0530, 0x06060005);
-- mchbar_write32(0x0680, 0x06060606);
-- mchbar_write32(0x0684, 0x08070606);
-- mchbar_write32(0x0688, 0x0e0e0c0a);
-- mchbar_write32(0x068c, 0x0e0e0e0e);
-- mchbar_write32(0x0698, 0x06060606);
-- mchbar_write32(0x069c, 0x08070606);
-- mchbar_write32(0x06a0, 0x0c0c0b0a);
-- mchbar_write32(0x06a4, 0x0c0c0c0c);
--
-- mchbar_write32(0x06c0, 0x02020202);
-- mchbar_write32(0x06c4, 0x03020202);
-- mchbar_write32(0x06c8, 0x04040403);
-- mchbar_write32(0x06cc, 0x04040404);
-- mchbar_write32(0x06d8, 0x02020202);
-- mchbar_write32(0x06dc, 0x03020202);
-- mchbar_write32(0x06e0, 0x04040403);
-- mchbar_write32(0x06e4, 0x04040404);
--
-- mchbar_write32(0x0700, 0x02020202);
-- mchbar_write32(0x0704, 0x03020202);
-- mchbar_write32(0x0708, 0x04040403);
-- mchbar_write32(0x070c, 0x04040404);
-- mchbar_write32(0x0718, 0x02020202);
-- mchbar_write32(0x071c, 0x03020202);
-- mchbar_write32(0x0720, 0x04040403);
-- mchbar_write32(0x0724, 0x04040404);
--
-- mchbar_write32(0x0740, 0x02020202);
-- mchbar_write32(0x0744, 0x03020202);
-- mchbar_write32(0x0748, 0x04040403);
-- mchbar_write32(0x074c, 0x04040404);
-- mchbar_write32(0x0758, 0x02020202);
-- mchbar_write32(0x075c, 0x03020202);
-- mchbar_write32(0x0760, 0x04040403);
-- mchbar_write32(0x0764, 0x04040404);
--
-- mchbar_write32(0x0780, 0x06060606);
-- mchbar_write32(0x0784, 0x09070606);
-- mchbar_write32(0x0788, 0x0e0e0c0b);
-- mchbar_write32(0x078c, 0x0e0e0e0e);
-- mchbar_write32(0x0798, 0x06060606);
-- mchbar_write32(0x079c, 0x09070606);
-- mchbar_write32(0x07a0, 0x0d0d0c0b);
-- mchbar_write32(0x07a4, 0x0d0d0d0d);
--
-- mchbar_write32(0x07c0, 0x06060606);
-- mchbar_write32(0x07c4, 0x09070606);
-- mchbar_write32(0x07c8, 0x0e0e0c0b);
-- mchbar_write32(0x07cc, 0x0e0e0e0e);
-- mchbar_write32(0x07d8, 0x06060606);
-- mchbar_write32(0x07dc, 0x09070606);
-- mchbar_write32(0x07e0, 0x0d0d0c0b);
-- mchbar_write32(0x07e4, 0x0d0d0d0d);
--
-- mchbar_write32(0x0840, 0x06060606);
-- mchbar_write32(0x0844, 0x08070606);
-- mchbar_write32(0x0848, 0x0e0e0c0a);
-- mchbar_write32(0x084c, 0x0e0e0e0e);
-- mchbar_write32(0x0858, 0x06060606);
-- mchbar_write32(0x085c, 0x08070606);
-- mchbar_write32(0x0860, 0x0c0c0b0a);
-- mchbar_write32(0x0864, 0x0c0c0c0c);
--
-- mchbar_write32(0x0880, 0x02020202);
-- mchbar_write32(0x0884, 0x03020202);
-- mchbar_write32(0x0888, 0x04040403);
-- mchbar_write32(0x088c, 0x04040404);
-- mchbar_write32(0x0898, 0x02020202);
-- mchbar_write32(0x089c, 0x03020202);
-- mchbar_write32(0x08a0, 0x04040403);
-- mchbar_write32(0x08a4, 0x04040404);
-+ if (sysinfo->spd_type == DDR2) {
-+ /*
-+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
-+ * after receiver enable calibration, otherwise raminit sometimes
-+ * completes with non-working memory.
-+ */
-+ mchbar_write32(0x0530, 0x06060005);
-+ mchbar_write32(0x0680, 0x06060606);
-+ mchbar_write32(0x0684, 0x08070606);
-+ mchbar_write32(0x0688, 0x0e0e0c0a);
-+ mchbar_write32(0x068c, 0x0e0e0e0e);
-+ mchbar_write32(0x0698, 0x06060606);
-+ mchbar_write32(0x069c, 0x08070606);
-+ mchbar_write32(0x06a0, 0x0c0c0b0a);
-+ mchbar_write32(0x06a4, 0x0c0c0c0c);
-+
-+ mchbar_write32(0x06c0, 0x02020202);
-+ mchbar_write32(0x06c4, 0x03020202);
-+ mchbar_write32(0x06c8, 0x04040403);
-+ mchbar_write32(0x06cc, 0x04040404);
-+ mchbar_write32(0x06d8, 0x02020202);
-+ mchbar_write32(0x06dc, 0x03020202);
-+ mchbar_write32(0x06e0, 0x04040403);
-+ mchbar_write32(0x06e4, 0x04040404);
-+
-+ mchbar_write32(0x0700, 0x02020202);
-+ mchbar_write32(0x0704, 0x03020202);
-+ mchbar_write32(0x0708, 0x04040403);
-+ mchbar_write32(0x070c, 0x04040404);
-+ mchbar_write32(0x0718, 0x02020202);
-+ mchbar_write32(0x071c, 0x03020202);
-+ mchbar_write32(0x0720, 0x04040403);
-+ mchbar_write32(0x0724, 0x04040404);
-+
-+ mchbar_write32(0x0740, 0x02020202);
-+ mchbar_write32(0x0744, 0x03020202);
-+ mchbar_write32(0x0748, 0x04040403);
-+ mchbar_write32(0x074c, 0x04040404);
-+ mchbar_write32(0x0758, 0x02020202);
-+ mchbar_write32(0x075c, 0x03020202);
-+ mchbar_write32(0x0760, 0x04040403);
-+ mchbar_write32(0x0764, 0x04040404);
-+
-+ mchbar_write32(0x0780, 0x06060606);
-+ mchbar_write32(0x0784, 0x09070606);
-+ mchbar_write32(0x0788, 0x0e0e0c0b);
-+ mchbar_write32(0x078c, 0x0e0e0e0e);
-+ mchbar_write32(0x0798, 0x06060606);
-+ mchbar_write32(0x079c, 0x09070606);
-+ mchbar_write32(0x07a0, 0x0d0d0c0b);
-+ mchbar_write32(0x07a4, 0x0d0d0d0d);
-+
-+ mchbar_write32(0x07c0, 0x06060606);
-+ mchbar_write32(0x07c4, 0x09070606);
-+ mchbar_write32(0x07c8, 0x0e0e0c0b);
-+ mchbar_write32(0x07cc, 0x0e0e0e0e);
-+ mchbar_write32(0x07d8, 0x06060606);
-+ mchbar_write32(0x07dc, 0x09070606);
-+ mchbar_write32(0x07e0, 0x0d0d0c0b);
-+ mchbar_write32(0x07e4, 0x0d0d0d0d);
-+
-+ mchbar_write32(0x0840, 0x06060606);
-+ mchbar_write32(0x0844, 0x08070606);
-+ mchbar_write32(0x0848, 0x0e0e0c0a);
-+ mchbar_write32(0x084c, 0x0e0e0e0e);
-+ mchbar_write32(0x0858, 0x06060606);
-+ mchbar_write32(0x085c, 0x08070606);
-+ mchbar_write32(0x0860, 0x0c0c0b0a);
-+ mchbar_write32(0x0864, 0x0c0c0c0c);
-+
-+ mchbar_write32(0x0880, 0x02020202);
-+ mchbar_write32(0x0884, 0x03020202);
-+ mchbar_write32(0x0888, 0x04040403);
-+ mchbar_write32(0x088c, 0x04040404);
-+ mchbar_write32(0x0898, 0x02020202);
-+ mchbar_write32(0x089c, 0x03020202);
-+ mchbar_write32(0x08a0, 0x04040403);
-+ mchbar_write32(0x08a4, 0x04040404);
-+ }
-
- igd_compute_ggc(sysinfo);
-
-diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index b74765fd9c..5d4505e063 100644
---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- reg = mchbar_read32(0x518);
- lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
- lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
-- if (i == 1) {
-+ if ((i == 1) && (ddr_type == DDR2)) {
- magic_comp[0] = (reg >> 8) & 0x3f;
- magic_comp[1] = (reg >> 0) & 0x3f;
- }
-@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- }
- mchbar += 0x0040;
- }
--
-- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
-- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+ if (ddr_type == DDR2) {
-+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
-+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+ }
- }
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
similarity index 85%
rename from config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
rename to config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
index ee60c3c8..bfc9231a 100644
--- a/config/coreboot/default/patches/0006-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
+++ b/config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
@@ -1,7 +1,7 @@
-From 18069af7c0c6beedfadb615cca9127e82a0d8007 Mon Sep 17 00:00:00 2001
+From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/37] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch b/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
deleted file mode 100644
index 1cf7c0ac..00000000
--- a/config/coreboot/default/patches/0018-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 7461210ecc7c8e41f3f941bd5ce7943e5f66c711 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 18/37] mb/dell/e6400: Use 100 MHz reference clock for display
-
-The E6400 uses a 100 MHz reference clock for spread spectrum support on
-LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
-the more common 1280 x 800 display panels, the numerical error was not
-large enough to cause noticable issues, but the actual pixel clock
-frequency derived from a 100 MHz reference using PLL configs calculated
-assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
-which require a much higher pixel clock. This resulted in a garbled
-display in the pre-OS graphics environment provided by libgfxinit.
-
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e6400/Kconfig | 3 +++
- src/northbridge/intel/gm45/Kconfig | 4 ++++
- 2 files changed, 7 insertions(+)
-
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 417d95fd5d..6fe1b1c456 100644
---- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/e6400/Kconfig
-@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
- select INTEL_GMA_HAVE_VBT
- select EC_DELL_MEC5035
-
-+config INTEL_GMA_DPLL_REF_FREQ
-+ default 100000000
-+
- config MAINBOARD_DIR
- default "dell/e6400"
-
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index fef0d735b3..fc5df8b11a 100644
---- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
-
- if NORTHBRIDGE_INTEL_GM45
-
-+config INTEL_GMA_DPLL_REF_FREQ
-+ int
-+ default 96000000
-+
- config VBOOT
- select VBOOT_STARTS_IN_BOOTBLOCK
-
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
similarity index 85%
rename from config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
rename to config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
index 525bd366..090f2629 100644
--- a/config/coreboot/default/patches/0007-Remove-warning-for-coreboot-images-built-without-a-p.patch
+++ b/config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
@@ -1,7 +1,7 @@
-From 9563c107a4b40e66b610d7205a21590c7c181c78 Mon Sep 17 00:00:00 2001
+From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
From: Nicholas Chin
Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/37] Remove warning for coreboot images built without a
+Subject: [PATCH 19/30] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index 5f988dac1b..516133880f 100644
+index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
-@@ -50,16 +50,5 @@ distclean-payloads:
+@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch b/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
deleted file mode 100644
index 2edfaae3..00000000
--- a/config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From a683dffd774dbbe25cc77c0f7d3853232c17c2bf Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 19/37] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
-
-set it to 96MHz. fixes the following build error when
-building for x4x boards e.g. gigabyte ga-g41m-es2l:
-
-hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
-make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
-
-this error was introduced when merging coreboot/dell
-into coreboot/default in lbmk. nicholas chin's fix in lbmk
-was as follows:
-
-commit 8629873a6043067affc137be275b7aa69cb1f10c
-Author: Nicholas Chin
-Date: Mon May 20 10:46:25 2024 -0600
-
- Fix E6400 display issue with 1440 x 900 panel
-
-this currently corresponds to the patch in lbmk,
-as of 12 august 2024:
-
-0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
-
-The assumption prior to Nicholas's fix was 96MHz, so set
-it accordingly on x4x northbridge.
-
-Signed-off-by: Leah Rowe
----
- src/northbridge/intel/x4x/Kconfig | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 097e11126c..6430319f6a 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
-
- if NORTHBRIDGE_INTEL_X4X
-
-+config INTEL_GMA_DPLL_REF_FREQ
-+ int
-+ default 96000000
-+
- config CBFS_SIZE
- default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
-
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
new file mode 100644
index 00000000..fecaf88a
--- /dev/null
+++ b/config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
@@ -0,0 +1,826 @@
+From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
+
+Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
+can also be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+Working:
+- Libgfxinit
+- USB EHCI debug (left side usb port is HCD index 2, middle port on the
+ right side is HCD index 1)
+- Keyboard
+- Touchpad/trackpoint
+- ExpressCard
+- Audio
+- Ethernet
+- SD card reader
+- mPCIe WiFi
+- SeaBIOS 1.16.2
+- edk2 (MrChromebox' fork, uefipayload_202306)
+- Internal flashing using dell-flash-unlock
+
+Not working:
+- S3 suspend: Possibly EC related
+- Physical wireless switch - this triggers an SMI handler in the vendor
+ firmware which sends commands to the EC to enable/disable wireless
+ devices
+- Battery reporting - needs ACPI code for the EC
+- Brightness hotkeys - probably EC related
+
+Unknown/untested:
+- Dock
+- eSATA
+- TPM
+- dGPU on non-UMA model
+- Bluetooth module (not included on my system)
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/e6430/Kconfig | 44 +++++
+ src/mainboard/dell/e6430/Kconfig.name | 2 +
+ src/mainboard/dell/e6430/Makefile.inc | 6 +
+ src/mainboard/dell/e6430/acpi/ec.asl | 9 +
+ src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
+ src/mainboard/dell/e6430/acpi/superio.asl | 3 +
+ src/mainboard/dell/e6430/acpi_tables.c | 16 ++
+ src/mainboard/dell/e6430/board_info.txt | 6 +
+ src/mainboard/dell/e6430/cmos.default | 9 +
+ src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
+ src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++
+ src/mainboard/dell/e6430/dsdt.asl | 30 ++++
+ src/mainboard/dell/e6430/early_init.c | 32 ++++
+ src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
+ src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6430/hda_verb.c | 33 ++++
+ src/mainboard/dell/e6430/mainboard.c | 21 +++
+ 18 files changed, 593 insertions(+)
+ create mode 100644 src/mainboard/dell/e6430/Kconfig
+ create mode 100644 src/mainboard/dell/e6430/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6430/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6430/board_info.txt
+ create mode 100644 src/mainboard/dell/e6430/cmos.default
+ create mode 100644 src/mainboard/dell/e6430/cmos.layout
+ create mode 100644 src/mainboard/dell/e6430/data.vbt
+ create mode 100644 src/mainboard/dell/e6430/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6430/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6430/early_init.c
+ create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6430/gpio.c
+ create mode 100644 src/mainboard/dell/e6430/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6430/mainboard.c
+
+diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
+new file mode 100644
+index 0000000000..e4c799803e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig
+@@ -0,0 +1,44 @@
++if BOARD_DELL_LATITUDE_E6430
++
++config BOARD_SPECIFIC_OPTIONS
++ def_bool y
++ select BOARD_ROMSIZE_KB_12288
++ select EC_ACPI
++ select EC_DELL_MEC5035
++ select GFX_GMA_PANEL_1_ON_LVDS
++ select HAVE_ACPI_RESUME
++ select HAVE_ACPI_TABLES
++ select HAVE_CMOS_DEFAULT
++ select HAVE_OPTION_TABLE
++ select INTEL_GMA_HAVE_VBT
++ select INTEL_INT15
++ select MAINBOARD_HAS_LIBGFXINIT
++ select MAINBOARD_USES_IFD_GBE_REGION
++ select NORTHBRIDGE_INTEL_SANDYBRIDGE
++ select SERIRQ_CONTINUOUS_MODE
++ select SOUTHBRIDGE_INTEL_C216
++ select SYSTEM_TYPE_LAPTOP
++ select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++ default 60
++
++config MAINBOARD_DIR
++ default "dell/e6430"
++
++config MAINBOARD_PART_NUMBER
++ default "Latitude E6430"
++
++config PS2K_EISAID
++ default "PNP0303"
++
++config PS2M_EISAID
++ default "PNP0F13"
++
++config USBDEBUG_HCD_INDEX
++ default 2
++
++config VGA_BIOS_ID
++ default "8086,0166"
++
++endif
+diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
+new file mode 100644
+index 0000000000..f866b03585
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6430
++ bool "Latitude E6430"
+diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++ Name (_HID, EISAID("PNP0C09"))
++ Name (_UID, 0)
++ Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++ /* FIXME: EC support */
++ Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++ /* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
+diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++/* FIXME: check this function. */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++ /* The lid is open by default. */
++ gnvs->lids = 1;
++
++ /* Temperature at which OS will shutdown */
++ gnvs->tcrt = 100;
++ /* Temperature at which OS will throttle CPU */
++ gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6430/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
+new file mode 100644
+index 0000000000..2a5b30f2b7
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Normal
+diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0 120 r 0 reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384 1 e 4 boot_option
++388 4 h 0 reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395 4 e 6 debug_level
++
++#400 8 r 0 reserved for century byte
++
++# coreboot config options: southbridge
++408 1 e 1 nmi
++409 2 e 7 power_on_after_fail
++411 1 e 9 sata_mode
++
++# coreboot config options: EC
++412 1 e 1 bluetooth
++413 1 e 1 wwan
++414 1 e 1 wlan
++
++# coreboot config options: ME
++424 1 e 14 me_state
++425 2 h 0 me_state_prev
++
++# coreboot config options: northbridge
++432 3 e 11 gfx_uma_size
++435 2 e 12 hybrid_graphics_mode
++440 8 h 0 volume
++
++# VBOOT
++448 128 r 0 vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896 32 r 0 mrc_scrambler_seed
++928 32 r 0 mrc_scrambler_seed_s3
++960 16 r 0 mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984 16 h 0 check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID value text
++1 0 Disable
++1 1 Enable
++2 0 Enable
++2 1 Disable
++4 0 Fallback
++4 1 Normal
++6 0 Emergency
++6 1 Alert
++6 2 Critical
++6 3 Error
++6 4 Warning
++6 5 Notice
++6 6 Info
++6 7 Debug
++6 8 Spew
++7 0 Disable
++7 1 Enable
++7 2 Keep
++9 0 AHCI
++9 1 Compatible
++11 0 32M
++11 1 64M
++11 2 96M
++11 3 128M
++11 4 160M
++11 5 192M
++11 6 224M
++14 0 Normal
++14 1 Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
+GIT binary patch
+literal 6144
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+zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
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+zIdrG4zSq6a*B6
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+z)}lBfx8o(*hgal&)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ
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+zq!PK|<^jJ^DuQ9)7pt`
+z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
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+qS
++
++DefinitionBlock(
++ "dsdt.aml",
++ "DSDT",
++ ACPI_DSDT_REV_2,
++ OEM_ID,
++ ACPI_TABLE_CREATOR,
++ 0x20141018 /* OEM revision */
++)
++{
++ #include
++ #include "acpi/platform.asl"
++ #include
++ #include
++ #include
++ #include
++
++ Device (\_SB.PCI0)
++ {
++ #include
++ #include
++ #include
++ }
++}
+diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
+new file mode 100644
+index 0000000000..d882c3d78b
+--- /dev/null
++++ b/src/mainboard/dell/e6430/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include
++#include
++#include
++#include
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++ { 1, 1, 0 },
++ { 1, 1, 0 },
++ { 1, 1, 1 },
++ { 1, 1, 1 },
++ { 1, 0, 2 },
++ { 1, 1, 2 },
++ { 1, 1, 3 },
++ { 1, 1, 3 },
++ { 1, 1, 4 },
++ { 1, 1, 4 },
++ { 1, 1, 5 },
++ { 1, 1, 5 },
++ { 1, 2, 6 },
++ { 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++ | COMB_LPC_EN | COMA_LPC_EN);
++ mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++ ports : constant Port_List :=
++ (
++ HDMI1, -- mainboard HDMI
++ DP2, -- dock DP
++ DP3, -- dock DP
++ Analog, --mainboard VGA
++ LVDS,
++ others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++ .gpio0 = GPIO_MODE_GPIO,
++ .gpio1 = GPIO_MODE_GPIO,
++ .gpio2 = GPIO_MODE_GPIO,
++ .gpio3 = GPIO_MODE_GPIO,
++ .gpio4 = GPIO_MODE_GPIO,
++ .gpio5 = GPIO_MODE_NATIVE,
++ .gpio6 = GPIO_MODE_GPIO,
++ .gpio7 = GPIO_MODE_GPIO,
++ .gpio8 = GPIO_MODE_GPIO,
++ .gpio9 = GPIO_MODE_NATIVE,
++ .gpio10 = GPIO_MODE_NATIVE,
++ .gpio11 = GPIO_MODE_NATIVE,
++ .gpio12 = GPIO_MODE_NATIVE,
++ .gpio13 = GPIO_MODE_GPIO,
++ .gpio14 = GPIO_MODE_GPIO,
++ .gpio15 = GPIO_MODE_GPIO,
++ .gpio16 = GPIO_MODE_GPIO,
++ .gpio17 = GPIO_MODE_GPIO,
++ .gpio18 = GPIO_MODE_NATIVE,
++ .gpio19 = GPIO_MODE_GPIO,
++ .gpio20 = GPIO_MODE_NATIVE,
++ .gpio21 = GPIO_MODE_GPIO,
++ .gpio22 = GPIO_MODE_GPIO,
++ .gpio23 = GPIO_MODE_NATIVE,
++ .gpio24 = GPIO_MODE_GPIO,
++ .gpio25 = GPIO_MODE_NATIVE,
++ .gpio26 = GPIO_MODE_NATIVE,
++ .gpio27 = GPIO_MODE_GPIO,
++ .gpio28 = GPIO_MODE_GPIO,
++ .gpio29 = GPIO_MODE_GPIO,
++ .gpio30 = GPIO_MODE_NATIVE,
++ .gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++ .gpio0 = GPIO_DIR_INPUT,
++ .gpio1 = GPIO_DIR_INPUT,
++ .gpio2 = GPIO_DIR_INPUT,
++ .gpio3 = GPIO_DIR_INPUT,
++ .gpio4 = GPIO_DIR_INPUT,
++ .gpio6 = GPIO_DIR_INPUT,
++ .gpio7 = GPIO_DIR_INPUT,
++ .gpio8 = GPIO_DIR_INPUT,
++ .gpio13 = GPIO_DIR_INPUT,
++ .gpio14 = GPIO_DIR_INPUT,
++ .gpio15 = GPIO_DIR_INPUT,
++ .gpio16 = GPIO_DIR_INPUT,
++ .gpio17 = GPIO_DIR_INPUT,
++ .gpio19 = GPIO_DIR_INPUT,
++ .gpio21 = GPIO_DIR_INPUT,
++ .gpio22 = GPIO_DIR_INPUT,
++ .gpio24 = GPIO_DIR_INPUT,
++ .gpio27 = GPIO_DIR_INPUT,
++ .gpio28 = GPIO_DIR_OUTPUT,
++ .gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++ .gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++ .gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++ .gpio0 = GPIO_INVERT,
++ .gpio8 = GPIO_INVERT,
++ .gpio13 = GPIO_INVERT,
++ .gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++ .gpio32 = GPIO_MODE_NATIVE,
++ .gpio33 = GPIO_MODE_GPIO,
++ .gpio34 = GPIO_MODE_GPIO,
++ .gpio35 = GPIO_MODE_GPIO,
++ .gpio36 = GPIO_MODE_GPIO,
++ .gpio37 = GPIO_MODE_GPIO,
++ .gpio38 = GPIO_MODE_GPIO,
++ .gpio39 = GPIO_MODE_GPIO,
++ .gpio40 = GPIO_MODE_NATIVE,
++ .gpio41 = GPIO_MODE_NATIVE,
++ .gpio42 = GPIO_MODE_NATIVE,
++ .gpio43 = GPIO_MODE_NATIVE,
++ .gpio44 = GPIO_MODE_NATIVE,
++ .gpio45 = GPIO_MODE_GPIO,
++ .gpio46 = GPIO_MODE_NATIVE,
++ .gpio47 = GPIO_MODE_NATIVE,
++ .gpio48 = GPIO_MODE_GPIO,
++ .gpio49 = GPIO_MODE_GPIO,
++ .gpio50 = GPIO_MODE_NATIVE,
++ .gpio51 = GPIO_MODE_GPIO,
++ .gpio52 = GPIO_MODE_GPIO,
++ .gpio53 = GPIO_MODE_NATIVE,
++ .gpio54 = GPIO_MODE_GPIO,
++ .gpio55 = GPIO_MODE_NATIVE,
++ .gpio56 = GPIO_MODE_NATIVE,
++ .gpio57 = GPIO_MODE_GPIO,
++ .gpio58 = GPIO_MODE_NATIVE,
++ .gpio59 = GPIO_MODE_NATIVE,
++ .gpio60 = GPIO_MODE_GPIO,
++ .gpio61 = GPIO_MODE_NATIVE,
++ .gpio62 = GPIO_MODE_NATIVE,
++ .gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++ .gpio33 = GPIO_DIR_INPUT,
++ .gpio34 = GPIO_DIR_OUTPUT,
++ .gpio35 = GPIO_DIR_INPUT,
++ .gpio36 = GPIO_DIR_INPUT,
++ .gpio37 = GPIO_DIR_INPUT,
++ .gpio38 = GPIO_DIR_INPUT,
++ .gpio39 = GPIO_DIR_INPUT,
++ .gpio45 = GPIO_DIR_OUTPUT,
++ .gpio48 = GPIO_DIR_INPUT,
++ .gpio49 = GPIO_DIR_INPUT,
++ .gpio51 = GPIO_DIR_INPUT,
++ .gpio52 = GPIO_DIR_INPUT,
++ .gpio54 = GPIO_DIR_INPUT,
++ .gpio57 = GPIO_DIR_INPUT,
++ .gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++ .gpio34 = GPIO_LEVEL_HIGH,
++ .gpio45 = GPIO_LEVEL_LOW,
++ .gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++ .gpio64 = GPIO_MODE_NATIVE,
++ .gpio65 = GPIO_MODE_NATIVE,
++ .gpio66 = GPIO_MODE_NATIVE,
++ .gpio67 = GPIO_MODE_NATIVE,
++ .gpio68 = GPIO_MODE_GPIO,
++ .gpio69 = GPIO_MODE_GPIO,
++ .gpio70 = GPIO_MODE_GPIO,
++ .gpio71 = GPIO_MODE_GPIO,
++ .gpio72 = GPIO_MODE_NATIVE,
++ .gpio73 = GPIO_MODE_NATIVE,
++ .gpio74 = GPIO_MODE_NATIVE,
++ .gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++ .gpio68 = GPIO_DIR_INPUT,
++ .gpio69 = GPIO_DIR_INPUT,
++ .gpio70 = GPIO_DIR_INPUT,
++ .gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++ .set1 = {
++ .mode = &pch_gpio_set1_mode,
++ .direction = &pch_gpio_set1_direction,
++ .level = &pch_gpio_set1_level,
++ .blink = &pch_gpio_set1_blink,
++ .invert = &pch_gpio_set1_invert,
++ .reset = &pch_gpio_set1_reset,
++ },
++ .set2 = {
++ .mode = &pch_gpio_set2_mode,
++ .direction = &pch_gpio_set2_direction,
++ .level = &pch_gpio_set2_level,
++ .reset = &pch_gpio_set2_reset,
++ },
++ .set3 = {
++ .mode = &pch_gpio_set3_mode,
++ .direction = &pch_gpio_set3_direction,
++ .level = &pch_gpio_set3_level,
++ .reset = &pch_gpio_set3_reset,
++ },
++};
+diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
+new file mode 100644
+index 0000000000..56ada95c58
+--- /dev/null
++++ b/src/mainboard/dell/e6430/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ 0x111d76df, /* Codec Vendor / Device ID: IDT */
++ 0x10280534, /* Subsystem ID */
++ 11, /* Number of 4 dword sets */
++ AZALIA_SUBVENDOR(0, 0x10280534),
++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++ 0x80862806, /* Codec Vendor / Device ID: Intel */
++ 0x80860101, /* Subsystem ID */
++ 4, /* Number of 4 dword sets */
++ AZALIA_SUBVENDOR(3, 0x80860101),
++ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6430/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include
++#include
++
++static void mainboard_enable(struct device *dev)
++{
++
++ /* FIXME: fix these values. */
++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++ GMA_INT15_PANEL_FIT_DEFAULT,
++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++ .enable_dev = mainboard_enable,
++};
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch b/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
deleted file mode 100644
index a0068142..00000000
--- a/config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch
+++ /dev/null
@@ -1,243 +0,0 @@
-From a48ba23bb4a24730fa49b5a10b56c9de873dea8a Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 20/37] mb/dell: Convert E6400 into a variant
-
-All the GM45 Dell Latitudes should be nearly identical, so convert the
-E6400 port into a variant so that future ports for the other systems can
-share code with each other.
-
-Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e6400/Makefile.mk | 10 --------
- .../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++-----
- .../{e6400 => gm45_latitude}/Kconfig.name | 0
- src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++
- .../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0
- .../acpi/ich9_pci_irqs.asl | 0
- .../{e6400 => gm45_latitude}/acpi/superio.asl | 0
- .../dell/{e6400 => gm45_latitude}/blc.c | 0
- .../{e6400 => gm45_latitude}/board_info.txt | 0
- .../dell/{e6400 => gm45_latitude}/bootblock.c | 0
- .../{e6400 => gm45_latitude}/cmos.default | 0
- .../dell/{e6400 => gm45_latitude}/cmos.layout | 0
- .../dell/{e6400 => gm45_latitude}/cstates.c | 0
- .../{e6400 => gm45_latitude}/devicetree.cb | 1 -
- .../dell/{e6400 => gm45_latitude}/dsdt.asl | 0
- .../dell/{e6400 => gm45_latitude}/mainboard.c | 0
- .../dell/{e6400 => gm45_latitude}/romstage.c | 0
- .../variants}/e6400/data.vbt | Bin
- .../variants}/e6400/gma-mainboard.ads | 0
- .../{ => gm45_latitude/variants}/e6400/gpio.c | 0
- .../variants}/e6400/hda_verb.c | 0
- .../variants/e6400/overridetree.cb | 7 ++++++
- 22 files changed, 34 insertions(+), 17 deletions(-)
- delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-
-diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
-deleted file mode 100644
-index ca3a82db48..0000000000
---- a/src/mainboard/dell/e6400/Makefile.mk
-+++ /dev/null
-@@ -1,10 +0,0 @@
--## SPDX-License-Identifier: GPL-2.0-only
--
--bootblock-y += bootblock.c
--
--romstage-y += gpio.c
--
--ramstage-y += cstates.c
--ramstage-y += blc.c
--
--ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-similarity index 64%
-rename from src/mainboard/dell/e6400/Kconfig
-rename to src/mainboard/dell/gm45_latitude/Kconfig
-index 6fe1b1c456..ba76fb6e8c 100644
---- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -1,9 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
-
--if BOARD_DELL_E6400
--
--config BOARD_SPECIFIC_OPTIONS
-- def_bool y
-+config BOARD_DELL_GM45_LATITUDE_COMMON
-+ def_bool n
- select SYSTEM_TYPE_LAPTOP
- select CPU_INTEL_SOCKET_P
- select NORTHBRIDGE_INTEL_GM45
-@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
- select INTEL_GMA_HAVE_VBT
- select EC_DELL_MEC5035
-
-+
-+config BOARD_DELL_E6400
-+ select BOARD_DELL_GM45_LATITUDE_COMMON
-+
-+if BOARD_DELL_GM45_LATITUDE_COMMON
-+
- config INTEL_GMA_DPLL_REF_FREQ
- default 100000000
-
- config MAINBOARD_DIR
-- default "dell/e6400"
-+ default "dell/gm45_latitude"
-
- config MAINBOARD_PART_NUMBER
- default "Latitude E6400" if BOARD_DELL_E6400
-
-+config OVERRIDE_DEVICETREE
-+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+ default "e6400" if BOARD_DELL_E6400
-+
- config USBDEBUG_HCD_INDEX
- default 1
-
- config CBFS_SIZE
- default 0x1A0000
-
--endif # BOARD_DELL_E6400
-+endif # BOARD_DELL_GM45_LATITUDE_COMMON
-diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-similarity index 100%
-rename from src/mainboard/dell/e6400/Kconfig.name
-rename to src/mainboard/dell/gm45_latitude/Kconfig.name
-diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
-new file mode 100644
-index 0000000000..5295d5be22
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
-@@ -0,0 +1,11 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += bootblock.c
-+
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+ramstage-y += cstates.c
-+ramstage-y += blc.c
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ec.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
-diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/superio.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
-diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/blc.c
-rename to src/mainboard/dell/gm45_latitude/blc.c
-diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
-similarity index 100%
-rename from src/mainboard/dell/e6400/board_info.txt
-rename to src/mainboard/dell/gm45_latitude/board_info.txt
-diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/bootblock.c
-rename to src/mainboard/dell/gm45_latitude/bootblock.c
-diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.default
-rename to src/mainboard/dell/gm45_latitude/cmos.default
-diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.layout
-rename to src/mainboard/dell/gm45_latitude/cmos.layout
-diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/cstates.c
-rename to src/mainboard/dell/gm45_latitude/cstates.c
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
-similarity index 98%
-rename from src/mainboard/dell/e6400/devicetree.cb
-rename to src/mainboard/dell/gm45_latitude/devicetree.cb
-index e9f3915d17..76dae87153 100644
---- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
-@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
- register "pci_mmio_size" = "2048"
-
- device domain 0 on
-- subsystemid 0x1028 0x0233 inherit
- ops gm45_pci_domain_ops
-
- device pci 00.0 on end # host bridge
-diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/dsdt.asl
-rename to src/mainboard/dell/gm45_latitude/dsdt.asl
-diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/mainboard.c
-rename to src/mainboard/dell/gm45_latitude/mainboard.c
-diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/romstage.c
-rename to src/mainboard/dell/gm45_latitude/romstage.c
-diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-similarity index 100%
-rename from src/mainboard/dell/e6400/data.vbt
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-similarity index 100%
-rename from src/mainboard/dell/e6400/gma-mainboard.ads
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/gpio.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/hda_verb.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-new file mode 100644
-index 0000000000..acc34a2252
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-@@ -0,0 +1,7 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+ device domain 0 on
-+ subsystemid 0x1028 0x0233 inherit
-+ end
-+end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch b/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch
similarity index 77%
rename from config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
rename to config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch
index bd2c56bd..40e1ccee 100644
--- a/config/coreboot/default/patches/0008-HACK-Disable-coreboot-related-BL31-features.patch
+++ b/config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch
@@ -1,7 +1,7 @@
-From 7f650a19d30fe6157b150c5248d6086007323d72 Mon Sep 17 00:00:00 2001
+From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak
Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 08/37] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index f54c6d22fc..b075abfd42 100644
+index 538d254ace..18e451d63c 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
-@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
@@ -24,5 +24,5 @@ index f54c6d22fc..b075abfd42 100644
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch b/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
deleted file mode 100644
index af893982..00000000
--- a/config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From b87e6774f0407ea48610c83ea54ab6a4b4a78a24 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 21/37] mb/dell/gm45_latitudes: Add E4300 variant
-
-Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/gm45_latitude/Kconfig | 5 +
- src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
- .../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
- .../variants/e4300/gma-mainboard.ads | 17 +++
- .../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
- .../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
- .../variants/e4300/overridetree.cb | 10 ++
- 7 files changed, 210 insertions(+)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index ba76fb6e8c..144f9bcdf0 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
- config BOARD_DELL_E6400
- select BOARD_DELL_GM45_LATITUDE_COMMON
-
-+config BOARD_DELL_E4300
-+ select BOARD_DELL_GM45_LATITUDE_COMMON
-+
- if BOARD_DELL_GM45_LATITUDE_COMMON
-
- config INTEL_GMA_DPLL_REF_FREQ
-@@ -31,12 +34,14 @@ config MAINBOARD_DIR
-
- config MAINBOARD_PART_NUMBER
- default "Latitude E6400" if BOARD_DELL_E6400
-+ default "Latitude E4300" if BOARD_DELL_E4300
-
- config OVERRIDE_DEVICETREE
- default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
- config VARIANT_DIR
- default "e6400" if BOARD_DELL_E6400
-+ default "e4300" if BOARD_DELL_E4300
-
- config USBDEBUG_HCD_INDEX
- default 1
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-index aefe777109..4dc95f46be 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig.name
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
-@@ -1,4 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
-
-+config BOARD_DELL_E4300
-+ bool "Latitude E4300"
-+
- config BOARD_DELL_E6400
- bool "Latitude E6400"
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
-GIT binary patch
-literal 3881
-zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
-zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5aNhx3i7B*>RjEs#PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
-zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpDh$)OQqAIh6jOwCxuw)qvS0N+Nk!?
-zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
-z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
-z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L~qi^
-z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I8}OhGtOw#1e$Fn9wsUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
-z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
-zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
-z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7
-zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
-zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
-zI{c?gKNv~R$&eHj8!uus22Br_GkCD$Q)pf!
-zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692 Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-new file mode 100644
-index 0000000000..b50f8da0b5
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-@@ -0,0 +1,138 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+ .gpio0 = GPIO_MODE_NATIVE,
-+ .gpio1 = GPIO_MODE_GPIO,
-+ .gpio2 = GPIO_MODE_GPIO,
-+ .gpio3 = GPIO_MODE_GPIO,
-+ .gpio4 = GPIO_MODE_GPIO,
-+ .gpio5 = GPIO_MODE_GPIO,
-+ .gpio6 = GPIO_MODE_GPIO,
-+ .gpio7 = GPIO_MODE_GPIO,
-+ .gpio8 = GPIO_MODE_GPIO,
-+ .gpio9 = GPIO_MODE_NATIVE,
-+ .gpio10 = GPIO_MODE_NATIVE,
-+ .gpio11 = GPIO_MODE_NATIVE,
-+ .gpio12 = GPIO_MODE_NATIVE,
-+ .gpio13 = GPIO_MODE_GPIO,
-+ .gpio14 = GPIO_MODE_GPIO,
-+ .gpio15 = GPIO_MODE_NATIVE,
-+ .gpio16 = GPIO_MODE_NATIVE,
-+ .gpio17 = GPIO_MODE_GPIO,
-+ .gpio18 = GPIO_MODE_GPIO,
-+ .gpio19 = GPIO_MODE_GPIO,
-+ .gpio20 = GPIO_MODE_GPIO,
-+ .gpio21 = GPIO_MODE_GPIO,
-+ .gpio22 = GPIO_MODE_GPIO,
-+ .gpio23 = GPIO_MODE_NATIVE,
-+ .gpio24 = GPIO_MODE_GPIO,
-+ .gpio25 = GPIO_MODE_NATIVE,
-+ .gpio26 = GPIO_MODE_NATIVE,
-+ .gpio27 = GPIO_MODE_GPIO,
-+ .gpio28 = GPIO_MODE_GPIO,
-+ .gpio29 = GPIO_MODE_NATIVE,
-+ .gpio30 = GPIO_MODE_NATIVE,
-+ .gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+ .gpio1 = GPIO_DIR_INPUT,
-+ .gpio2 = GPIO_DIR_INPUT,
-+ .gpio3 = GPIO_DIR_INPUT,
-+ .gpio4 = GPIO_DIR_INPUT,
-+ .gpio5 = GPIO_DIR_INPUT,
-+ .gpio6 = GPIO_DIR_INPUT,
-+ .gpio7 = GPIO_DIR_INPUT,
-+ .gpio8 = GPIO_DIR_INPUT,
-+ .gpio13 = GPIO_DIR_INPUT,
-+ .gpio14 = GPIO_DIR_INPUT,
-+ .gpio17 = GPIO_DIR_INPUT,
-+ .gpio18 = GPIO_DIR_INPUT,
-+ .gpio19 = GPIO_DIR_INPUT,
-+ .gpio20 = GPIO_DIR_INPUT,
-+ .gpio21 = GPIO_DIR_INPUT,
-+ .gpio22 = GPIO_DIR_INPUT,
-+ .gpio24 = GPIO_DIR_INPUT,
-+ .gpio27 = GPIO_DIR_INPUT,
-+ .gpio28 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+ .gpio1 = GPIO_INVERT,
-+ .gpio7 = GPIO_INVERT,
-+ .gpio8 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+ .gpio32 = GPIO_MODE_NATIVE,
-+ .gpio33 = GPIO_MODE_GPIO,
-+ .gpio34 = GPIO_MODE_GPIO,
-+ .gpio35 = GPIO_MODE_NATIVE,
-+ .gpio36 = GPIO_MODE_GPIO,
-+ .gpio37 = GPIO_MODE_GPIO,
-+ .gpio38 = GPIO_MODE_GPIO,
-+ .gpio39 = GPIO_MODE_GPIO,
-+ .gpio40 = GPIO_MODE_NATIVE,
-+ .gpio41 = GPIO_MODE_NATIVE,
-+ .gpio42 = GPIO_MODE_NATIVE,
-+ .gpio43 = GPIO_MODE_NATIVE,
-+ .gpio44 = GPIO_MODE_NATIVE,
-+ .gpio45 = GPIO_MODE_NATIVE,
-+ .gpio46 = GPIO_MODE_NATIVE,
-+ .gpio47 = GPIO_MODE_NATIVE,
-+ .gpio48 = GPIO_MODE_GPIO,
-+ .gpio49 = GPIO_MODE_GPIO,
-+ .gpio50 = GPIO_MODE_NATIVE,
-+ .gpio51 = GPIO_MODE_NATIVE,
-+ .gpio52 = GPIO_MODE_GPIO,
-+ .gpio53 = GPIO_MODE_GPIO,
-+ .gpio54 = GPIO_MODE_NATIVE,
-+ .gpio55 = GPIO_MODE_NATIVE,
-+ .gpio56 = GPIO_MODE_GPIO,
-+ .gpio57 = GPIO_MODE_GPIO,
-+ .gpio58 = GPIO_MODE_NATIVE,
-+ .gpio59 = GPIO_MODE_NATIVE,
-+ .gpio60 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+ .gpio33 = GPIO_DIR_INPUT,
-+ .gpio34 = GPIO_DIR_INPUT,
-+ .gpio36 = GPIO_DIR_INPUT,
-+ .gpio37 = GPIO_DIR_INPUT,
-+ .gpio38 = GPIO_DIR_INPUT,
-+ .gpio39 = GPIO_DIR_INPUT,
-+ .gpio48 = GPIO_DIR_INPUT,
-+ .gpio49 = GPIO_DIR_INPUT,
-+ .gpio52 = GPIO_DIR_INPUT,
-+ .gpio53 = GPIO_DIR_INPUT,
-+ .gpio56 = GPIO_DIR_INPUT,
-+ .gpio57 = GPIO_DIR_INPUT,
-+ .gpio60 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+ .set1 = {
-+ .mode = &pch_gpio_set1_mode,
-+ .direction = &pch_gpio_set1_direction,
-+ .level = &pch_gpio_set1_level,
-+ .blink = &pch_gpio_set1_blink,
-+ .invert = &pch_gpio_set1_invert,
-+ },
-+ .set2 = {
-+ .mode = &pch_gpio_set2_mode,
-+ .direction = &pch_gpio_set2_direction,
-+ .level = &pch_gpio_set2_level,
-+ },
-+};
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-new file mode 100644
-index 0000000000..a9948a93dd
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-@@ -0,0 +1,37 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ /* coreboot specific header */
-+ 0x111d76b2, /* IDT 92HD71B7X */
-+ 0x1028024d, /* Subsystem ID */
-+ 13, /* Number of entries */
-+
-+ /* Pin Widget Verb Table */
-+
-+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
-+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
-+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
-+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
-+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
-+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
-+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
-+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
-+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
-+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
-+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
-+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
-+};
-+
-+const u32 pc_beep_verbs[] = {
-+ 0x00170500, /* power up codec */
-+ 0x00d70500, /* power up speakers */
-+ 0x00d70102, /* select mixer (input 0x2) for speakers */
-+ 0x00d70740, /* enable speakers output */
-+ 0x02770720, /* enable beep input */
-+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
-+ 0x00d37000, /* unmute speakers */
-+};
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-new file mode 100644
-index 0000000000..20dfa245fb
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+ device domain 0 on
-+ subsystemid 0x1028 0x024d inherit
-+ chip southbridge/intel/i82801ix
-+ device pci 1c.2 off end # PCIe Port #3
-+ end
-+ end
-+end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch
new file mode 100644
index 00000000..f66909c6
--- /dev/null
+++ b/config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch
@@ -0,0 +1,39 @@
+From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 22/30] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 23a5caf2bb..36565a906c 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch b/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
deleted file mode 100644
index bbdce358..00000000
--- a/config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
-
-Integrate the previously added mec5035_smi_sleep() function into
-mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
-The E6400 does not require the EC command to sucessfully suspend and
-resume from S3, though sending it does enable the breathing effect on
-the power LED while in S3. Without it, all LEDs turn off during S3.
-
-Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/e7240/smihandler.c | 9 +++++++++
- src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
- src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
- 3 files changed, 27 insertions(+)
- create mode 100644 src/mainboard/dell/e7240/smihandler.c
- create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
-
-diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/e7240/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+ mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+ mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+ mec5035_smi_sleep(slp_typ);
-+}
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch b/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch
new file mode 100644
index 00000000..7701babf
--- /dev/null
+++ b/config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch
@@ -0,0 +1,142 @@
+From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Tue, 31 Oct 2023 18:24:39 +0000
+Subject: [PATCH 23/30] crank up vram allocation on more intel boards
+
+these were added to libreboot, and it's a policy of
+libreboot to max out the vram settings. this was
+overlooked, in prior revisions and releases.
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/dell/e6400/cmos.default | 2 +-
+ src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
+ src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
+ src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
+ src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
+ src/mainboard/lenovo/t420/cmos.default | 1 +
+ src/mainboard/lenovo/t420s/cmos.default | 1 +
+ src/mainboard/lenovo/t430/cmos.default | 1 +
+ src/mainboard/lenovo/t520/cmos.default | 1 +
+ src/mainboard/lenovo/t530/cmos.default | 1 +
+ src/mainboard/lenovo/x201/cmos.default | 1 +
+ src/mainboard/lenovo/x220/cmos.default | 1 +
+ 12 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+index ccc7e64625..7c97b84baf 100644
+--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
++++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=128M
++gfx_uma_size=224M
+ fan_full_speed=Disable
+diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+index 6d27a79c66..4517ffc7c2 100644
+--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
++++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+ psu_fan_lvl=3
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+index 6f3cec735e..9fc4db2990 100644
+--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+index ad822d5043..89418a4cfc 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
++++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
++++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
++++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 55e1e6c04e..a72108f47e 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
++++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
++++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
++++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
+index 2cf484fd5a..46294d91ca 100644
+--- a/src/mainboard/lenovo/x201/cmos.default
++++ b/src/mainboard/lenovo/x201/cmos.default
+@@ -15,3 +15,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ usb_always_on=Disable
++gfx_uma_size=128M
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index 52f303dfdb..92a2026542 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
++++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+ me_state=Disabled
++gfx_uma_size=224M
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch b/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
deleted file mode 100644
index ab01c935..00000000
--- a/config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
-
-If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
-power button results in the EC powering off the system without letting
-the OS cleanly shutting itself down. This command and argument tells the
-EC to route power button events to the host so that it can determine
-what to do.
-
-The EC command was identified from the ec/google/wilco code, which is
-used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
-Kconfig help text, those ECs run a modified version of Dell's typical
-Latitude EC firmware, so it is likely that the two firmware
-implementations use similar commands. Examining LPC traffic between the
-host and the EC on the Latitude E6400 did reveal that the same command
-was being sent by the vendor firmware to the EC, but this does not
-confirm that it has the same meaning as the command from the Wilco code.
-Sending the command using inb/outb calls in a userspace C program while
-running coreboot without this patch did allow subsequent power button
-events to be handled by the host, confirming that the command was indeed
-the same.
-
-Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
-Signed-off-by: Nicholas Chin
----
- src/ec/dell/mec5035/mec5035.c | 8 ++++++++
- src/ec/dell/mec5035/mec5035.h | 7 +++++++
- 2 files changed, 15 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 85c2ab0140..bdae929a27 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
- ec_command(CMD_RADIO_CTRL);
- }
-
-+void mec5035_power_button_route(enum ec_power_button_route target)
-+{
-+ u8 buf = (u8)target;
-+ write_mailbox_regs(&buf, 2, 1);
-+ ec_command(CMD_POWER_BUTTON_TO_HOST);
-+}
-+
- void mec5035_change_wake(u8 source, enum ec_wake_change change)
- {
- u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
- /* Unconditionally use this argument for now as this setting
- is probably the most sensible default out of the 3 choices. */
- mec5035_mouse_touchpad(TP_PS2_MOUSE);
-+ mec5035_power_button_route(HOST);
-
- pc_keyboard_init(NO_AUX_DEVICE);
-
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 8d4fded28b..51422598c4 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -11,6 +11,7 @@
- enum mec5035_cmd {
- CMD_MOUSE_TP = 0x1a,
- CMD_RADIO_CTRL = 0x2b,
-+ CMD_POWER_BUTTON_TO_HOST = 0x3e,
- CMD_ACPI_WAKEUP_CHANGE = 0x4a,
- CMD_SLEEP_ENABLE = 0x64,
- CMD_CPU_OK = 0xc2,
-@@ -36,6 +37,11 @@ enum ec_radio_state {
- RADIO_ON
- };
-
-+enum ec_power_button_route {
-+ EC = 0,
-+ HOST
-+};
-+
- #define ACPI_WAKEUP_NUM_ARGS 4
- enum ec_wake_change {
- WAKE_OFF = 0,
-@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_power_button_route(enum ec_power_button_route target);
- void mec5035_change_wake(u8 source, enum ec_wake_change change);
- void mec5035_sleep_enable(void);
-
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch b/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
deleted file mode 100644
index c557e9d7..00000000
--- a/config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Tue, 31 Dec 2024 14:42:24 +0000
-Subject: [PATCH 24/37] Disable compression on refcode insertion
-
-Compression is not reliably reproducible. In an lbmk release
-context, this means we cannot rely on vendorfile insertion.
-
-Therefore, use uncompressed refcode.
-
-Signed-off-by: Leah Rowe
----
- Makefile.mk | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/Makefile.mk b/Makefile.mk
-index 3969bfbd05..15346569f8 100644
---- a/Makefile.mk
-+++ b/Makefile.mk
-@@ -1392,7 +1392,7 @@ endif
- cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
- $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
- $(CONFIG_CBFS_PREFIX)/refcode-type := stage
--$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
-+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
-
- cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
- vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch b/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch
similarity index 58%
rename from config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
rename to config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch
index ca3b6264..79ee4b6c 100644
--- a/config/coreboot/default/patches/0009-dell-e6430-use-ME-Soft-Temporary-Disable.patch
+++ b/config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch
@@ -1,7 +1,7 @@
-From 3f6f65ed6a435fe49534c8a0b5cb98c3eac71150 Mon Sep 17 00:00:00 2001
+From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
From: Leah Rowe
Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 09/37] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
@@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
Signed-off-by: Leah Rowe
---
- src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
+ src/mainboard/dell/e6430/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
index 2a5b30f2b7..279415dfd1 100644
---- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
-+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
+--- a/src/mainboard/dell/e6430/cmos.default
++++ b/src/mainboard/dell/e6430/cmos.default
@@ -6,4 +6,4 @@ bluetooth=Enable
wwan=Enable
wlan=Enable
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
-me_state=Normal
+me_state=Disabled
--
-2.39.5
+2.39.2
diff --git a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch b/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
deleted file mode 100644
index 696be518..00000000
--- a/config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
-From: Leah Rowe
-Date: Mon, 21 Apr 2025 02:58:47 +0100
-Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
-
-Signed-off-by: Leah Rowe
----
- src/northbridge/intel/e7505/Kconfig | 9 +++++++++
- src/northbridge/intel/gm45/Kconfig | 9 +++++++++
- src/northbridge/intel/haswell/Kconfig | 9 +++++++++
- src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
- src/northbridge/intel/i945/Kconfig | 9 +++++++++
- src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
- src/northbridge/intel/pineview/Kconfig | 9 +++++++++
- src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
- src/northbridge/intel/x4x/Kconfig | 9 +++++++++
- 9 files changed, 85 insertions(+)
-
-diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
-index 039a7396f8..ddcb986f10 100644
---- a/src/northbridge/intel/e7505/Kconfig
-+++ b/src/northbridge/intel/e7505/Kconfig
-@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
- select NO_CBFS_MCACHE
- select SMM_TSEG
- select NEED_SMALL_2MB_PAGE_TABLES
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index fc5df8b11a..95e3644b73 100644
---- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- default 0xfed19000
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index 6191cb6ccf..0f5b5c7241 100644
---- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
-
- if NORTHBRIDGE_INTEL_HASWELL
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- config USE_NATIVE_RAMINIT
- bool "[NOT COMPLETE] Use native raminit"
- default n
-diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
-index dbb2d7436b..5e9418b6a9 100644
---- a/src/northbridge/intel/i440bx/Kconfig
-+++ b/src/northbridge/intel/i440bx/Kconfig
-@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
- If your board has 4 DIMM slots, you must use select this option, in
- your Kconfig file of the board. On boards with 3 DIMM slots,
- do _not_ select this option.
-+
-+if NORTHBRIDGE_INTEL_I440BX
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
-+endif
-diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
-index 32eff1a611..9479d75c07 100644
---- a/src/northbridge/intel/i945/Kconfig
-+++ b/src/northbridge/intel/i945/Kconfig
-@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- default 0xfed19000
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
-diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
-index 2bafebf92e..16b81705bb 100644
---- a/src/northbridge/intel/ironlake/Kconfig
-+++ b/src/northbridge/intel/ironlake/Kconfig
-@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- default 0xfed19000
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
-diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
-index 59cfcd5e0a..a3ad8d3425 100644
---- a/src/northbridge/intel/pineview/Kconfig
-+++ b/src/northbridge/intel/pineview/Kconfig
-@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
- config DOMAIN_RESOURCE_32BIT_LIMIT
- default 0xfec00000
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
-diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
-index 973eed8bbd..6387cf926d 100644
---- a/src/northbridge/intel/sandybridge/Kconfig
-+++ b/src/northbridge/intel/sandybridge/Kconfig
-@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
- default 2 if IGD_DEFAULT_UMA_SIZE_96MB
- default 3 if IGD_DEFAULT_UMA_SIZE_128MB
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 6430319f6a..1803ef5733 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- default 0xfed19000
-
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+ bool
-+ default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+ bool
-+ default n
-+
- endif
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch
new file mode 100644
index 00000000..8275d6c5
--- /dev/null
+++ b/config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch
@@ -0,0 +1,36 @@
+From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 36565a906c..4d4ca06113 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
new file mode 100644
index 00000000..33d743f1
--- /dev/null
+++ b/config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
@@ -0,0 +1,792 @@
+From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
+
+Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB. It can be internally flashed by sending a command to the
+EC, which causes the EC to pull the FDO pin low and the firmware to skip
+setting up any chipset based write protections. [1] The EC is the SMSC
+MEC5055, which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin
+---
+ src/mainboard/dell/e6530/Kconfig | 37 ++++
+ src/mainboard/dell/e6530/Kconfig.name | 2 +
+ src/mainboard/dell/e6530/Makefile.inc | 6 +
+ src/mainboard/dell/e6530/acpi/ec.asl | 9 +
+ src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
+ src/mainboard/dell/e6530/acpi/superio.asl | 3 +
+ src/mainboard/dell/e6530/acpi_tables.c | 16 ++
+ src/mainboard/dell/e6530/board_info.txt | 6 +
+ src/mainboard/dell/e6530/cmos.default | 9 +
+ src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
+ src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
+ src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
+ src/mainboard/dell/e6530/dsdt.asl | 30 ++++
+ src/mainboard/dell/e6530/early_init.c | 38 ++++
+ src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
+ src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6530/hda_verb.c | 33 ++++
+ src/mainboard/dell/e6530/mainboard.c | 21 +++
+ 18 files changed, 590 insertions(+)
+ create mode 100644 src/mainboard/dell/e6530/Kconfig
+ create mode 100644 src/mainboard/dell/e6530/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6530/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6530/board_info.txt
+ create mode 100644 src/mainboard/dell/e6530/cmos.default
+ create mode 100644 src/mainboard/dell/e6530/cmos.layout
+ create mode 100644 src/mainboard/dell/e6530/data.vbt
+ create mode 100644 src/mainboard/dell/e6530/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6530/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6530/early_init.c
+ create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6530/gpio.c
+ create mode 100644 src/mainboard/dell/e6530/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6530/mainboard.c
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+new file mode 100644
+index 0000000000..582adddbd4
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E6530
++
++config BOARD_SPECIFIC_OPTIONS
++ def_bool y
++ select BOARD_ROMSIZE_KB_12288
++ select EC_ACPI
++ select EC_DELL_MEC5035
++ select GFX_GMA_PANEL_1_ON_LVDS
++ select HAVE_ACPI_RESUME
++ select HAVE_ACPI_TABLES
++ select HAVE_CMOS_DEFAULT
++ select HAVE_OPTION_TABLE
++ select INTEL_GMA_HAVE_VBT
++ select INTEL_INT15
++ select MAINBOARD_HAS_LIBGFXINIT
++ select MAINBOARD_USES_IFD_GBE_REGION
++ select NORTHBRIDGE_INTEL_SANDYBRIDGE
++ select SERIRQ_CONTINUOUS_MODE
++ select SOUTHBRIDGE_INTEL_C216
++ select SYSTEM_TYPE_LAPTOP
++ select USE_NATIVE_RAMINIT
++
++config MAINBOARD_DIR
++ default "dell/e6530"
++
++config MAINBOARD_PART_NUMBER
++ default "Latitude E6530"
++
++config VGA_BIOS_ID
++ default "8086,0166"
++
++config DRAM_RESET_GATE_GPIO
++ default 60
++
++config USBDEBUG_HCD_INDEX
++ default 2
++endif
+diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
+new file mode 100644
+index 0000000000..01ed76d107
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6530
++ bool "Latitude E6530"
+diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++ Name (_HID, EISAID("PNP0C09"))
++ Name (_UID, 0)
++ Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++ /* FIXME: EC support */
++ Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++ /* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
+diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++
++/* FIXME: check this function. */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++ /* The lid is open by default. */
++ gnvs->lids = 1;
++
++ /* Temperature at which OS will shutdown */
++ gnvs->tcrt = 100;
++ /* Temperature at which OS will throttle CPU */
++ gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6530/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+new file mode 100644
+index 0000000000..e85ea4c661
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0 120 r 0 reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384 1 e 4 boot_option
++388 4 h 0 reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395 4 e 6 debug_level
++
++#400 8 r 0 reserved for century byte
++
++# coreboot config options: southbridge
++408 1 e 1 nmi
++409 2 e 7 power_on_after_fail
++411 1 e 9 sata_mode
++
++# coreboot config options: EC
++412 1 e 1 bluetooth
++413 1 e 1 wwan
++415 1 e 1 wlan
++
++# coreboot config options: ME
++424 1 e 14 me_state
++425 2 h 0 me_state_prev
++
++# coreboot config options: northbridge
++432 3 e 11 gfx_uma_size
++435 2 e 12 hybrid_graphics_mode
++440 8 h 0 volume
++
++# VBOOT
++448 128 r 0 vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896 32 r 0 mrc_scrambler_seed
++928 32 r 0 mrc_scrambler_seed_s3
++960 16 r 0 mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984 16 h 0 check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID value text
++1 0 Disable
++1 1 Enable
++2 0 Enable
++2 1 Disable
++4 0 Fallback
++4 1 Normal
++6 0 Emergency
++6 1 Alert
++6 2 Critical
++6 3 Error
++6 4 Warning
++6 5 Notice
++6 6 Info
++6 7 Debug
++6 8 Spew
++7 0 Disable
++7 1 Enable
++7 2 Keep
++9 0 AHCI
++9 1 Compatible
++11 0 32M
++11 1 64M
++11 2 96M
++11 3 128M
++11 4 160M
++11 5 192M
++11 6 224M
++14 0 Normal
++14 1 Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
+GIT binary patch
+literal 4280
+zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
+zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
+zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
+zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWpFv
+zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
+ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
+zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
+zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
+zfbB~~a>piTMAVDNyHR<{0{F7}8pool{7_h6u?7yg
+zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
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+z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
+zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
+z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
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+zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH
+z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1(
+zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
+z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
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+zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+yaZ_2@KjK>)nIBR-xB@+1PQ2*c$lV?Z13o
+zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d
++
++DefinitionBlock(
++ "dsdt.aml",
++ "DSDT",
++ ACPI_DSDT_REV_2,
++ OEM_ID,
++ ACPI_TABLE_CREATOR,
++ 0x20141018 /* OEM revision */
++)
++{
++ #include
++ #include "acpi/platform.asl"
++ #include
++ #include
++ #include
++ #include
++
++ Device (\_SB.PCI0)
++ {
++ #include
++ #include
++ #include
++ }
++}
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+new file mode 100644
+index 0000000000..d57f48e7f1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -0,0 +1,38 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include
++#include
++#include
++#include
++#include
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++ { 1, 1, 0 },
++ { 1, 1, 0 },
++ { 1, 1, 1 },
++ { 1, 1, 1 },
++ { 1, 1, 2 },
++ { 1, 1, 2 },
++ { 1, 0, 3 },
++ { 1, 1, 3 },
++ { 1, 1, 4 },
++ { 1, 1, 4 },
++ { 1, 1, 5 },
++ { 1, 1, 5 },
++ { 1, 2, 6 },
++ { 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
++ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++ mec5035_early_init();
++}
++
++void mainboard_get_spd(spd_raw_data *spd, bool id_only)
++{
++ read_spd(&spd[0], 0x50, id_only);
++ read_spd(&spd[2], 0x52, id_only);
++}
+diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++ ports : constant Port_List :=
++ (
++ HDMI1, -- mainboard HDMI
++ DP2, -- dock DP
++ DP3, -- dock DP
++ Analog, --mainboard VGA
++ LVDS,
++ others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++ .gpio0 = GPIO_MODE_GPIO,
++ .gpio1 = GPIO_MODE_GPIO,
++ .gpio2 = GPIO_MODE_GPIO,
++ .gpio3 = GPIO_MODE_GPIO,
++ .gpio4 = GPIO_MODE_GPIO,
++ .gpio5 = GPIO_MODE_NATIVE,
++ .gpio6 = GPIO_MODE_GPIO,
++ .gpio7 = GPIO_MODE_GPIO,
++ .gpio8 = GPIO_MODE_GPIO,
++ .gpio9 = GPIO_MODE_NATIVE,
++ .gpio10 = GPIO_MODE_NATIVE,
++ .gpio11 = GPIO_MODE_NATIVE,
++ .gpio12 = GPIO_MODE_NATIVE,
++ .gpio13 = GPIO_MODE_GPIO,
++ .gpio14 = GPIO_MODE_GPIO,
++ .gpio15 = GPIO_MODE_GPIO,
++ .gpio16 = GPIO_MODE_GPIO,
++ .gpio17 = GPIO_MODE_GPIO,
++ .gpio18 = GPIO_MODE_NATIVE,
++ .gpio19 = GPIO_MODE_GPIO,
++ .gpio20 = GPIO_MODE_NATIVE,
++ .gpio21 = GPIO_MODE_GPIO,
++ .gpio22 = GPIO_MODE_GPIO,
++ .gpio23 = GPIO_MODE_NATIVE,
++ .gpio24 = GPIO_MODE_GPIO,
++ .gpio25 = GPIO_MODE_NATIVE,
++ .gpio26 = GPIO_MODE_NATIVE,
++ .gpio27 = GPIO_MODE_GPIO,
++ .gpio28 = GPIO_MODE_GPIO,
++ .gpio29 = GPIO_MODE_GPIO,
++ .gpio30 = GPIO_MODE_NATIVE,
++ .gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++ .gpio0 = GPIO_DIR_INPUT,
++ .gpio1 = GPIO_DIR_INPUT,
++ .gpio2 = GPIO_DIR_INPUT,
++ .gpio3 = GPIO_DIR_INPUT,
++ .gpio4 = GPIO_DIR_INPUT,
++ .gpio6 = GPIO_DIR_INPUT,
++ .gpio7 = GPIO_DIR_INPUT,
++ .gpio8 = GPIO_DIR_INPUT,
++ .gpio13 = GPIO_DIR_INPUT,
++ .gpio14 = GPIO_DIR_INPUT,
++ .gpio15 = GPIO_DIR_INPUT,
++ .gpio16 = GPIO_DIR_INPUT,
++ .gpio17 = GPIO_DIR_INPUT,
++ .gpio19 = GPIO_DIR_INPUT,
++ .gpio21 = GPIO_DIR_INPUT,
++ .gpio22 = GPIO_DIR_INPUT,
++ .gpio24 = GPIO_DIR_INPUT,
++ .gpio27 = GPIO_DIR_INPUT,
++ .gpio28 = GPIO_DIR_OUTPUT,
++ .gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++ .gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++ .gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++ .gpio0 = GPIO_INVERT,
++ .gpio8 = GPIO_INVERT,
++ .gpio13 = GPIO_INVERT,
++ .gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++ .gpio32 = GPIO_MODE_NATIVE,
++ .gpio33 = GPIO_MODE_GPIO,
++ .gpio34 = GPIO_MODE_GPIO,
++ .gpio35 = GPIO_MODE_GPIO,
++ .gpio36 = GPIO_MODE_GPIO,
++ .gpio37 = GPIO_MODE_GPIO,
++ .gpio38 = GPIO_MODE_GPIO,
++ .gpio39 = GPIO_MODE_GPIO,
++ .gpio40 = GPIO_MODE_NATIVE,
++ .gpio41 = GPIO_MODE_NATIVE,
++ .gpio42 = GPIO_MODE_NATIVE,
++ .gpio43 = GPIO_MODE_NATIVE,
++ .gpio44 = GPIO_MODE_NATIVE,
++ .gpio45 = GPIO_MODE_GPIO,
++ .gpio46 = GPIO_MODE_NATIVE,
++ .gpio47 = GPIO_MODE_NATIVE,
++ .gpio48 = GPIO_MODE_GPIO,
++ .gpio49 = GPIO_MODE_GPIO,
++ .gpio50 = GPIO_MODE_NATIVE,
++ .gpio51 = GPIO_MODE_GPIO,
++ .gpio52 = GPIO_MODE_GPIO,
++ .gpio53 = GPIO_MODE_NATIVE,
++ .gpio54 = GPIO_MODE_GPIO,
++ .gpio55 = GPIO_MODE_NATIVE,
++ .gpio56 = GPIO_MODE_NATIVE,
++ .gpio57 = GPIO_MODE_GPIO,
++ .gpio58 = GPIO_MODE_NATIVE,
++ .gpio59 = GPIO_MODE_NATIVE,
++ .gpio60 = GPIO_MODE_GPIO,
++ .gpio61 = GPIO_MODE_NATIVE,
++ .gpio62 = GPIO_MODE_NATIVE,
++ .gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++ .gpio33 = GPIO_DIR_INPUT,
++ .gpio34 = GPIO_DIR_OUTPUT,
++ .gpio35 = GPIO_DIR_INPUT,
++ .gpio36 = GPIO_DIR_INPUT,
++ .gpio37 = GPIO_DIR_INPUT,
++ .gpio38 = GPIO_DIR_INPUT,
++ .gpio39 = GPIO_DIR_INPUT,
++ .gpio45 = GPIO_DIR_OUTPUT,
++ .gpio48 = GPIO_DIR_INPUT,
++ .gpio49 = GPIO_DIR_INPUT,
++ .gpio51 = GPIO_DIR_INPUT,
++ .gpio52 = GPIO_DIR_INPUT,
++ .gpio54 = GPIO_DIR_INPUT,
++ .gpio57 = GPIO_DIR_INPUT,
++ .gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++ .gpio34 = GPIO_LEVEL_HIGH,
++ .gpio45 = GPIO_LEVEL_LOW,
++ .gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++ .gpio64 = GPIO_MODE_NATIVE,
++ .gpio65 = GPIO_MODE_NATIVE,
++ .gpio66 = GPIO_MODE_NATIVE,
++ .gpio67 = GPIO_MODE_NATIVE,
++ .gpio68 = GPIO_MODE_GPIO,
++ .gpio69 = GPIO_MODE_GPIO,
++ .gpio70 = GPIO_MODE_GPIO,
++ .gpio71 = GPIO_MODE_GPIO,
++ .gpio72 = GPIO_MODE_NATIVE,
++ .gpio73 = GPIO_MODE_NATIVE,
++ .gpio74 = GPIO_MODE_NATIVE,
++ .gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++ .gpio68 = GPIO_DIR_INPUT,
++ .gpio69 = GPIO_DIR_INPUT,
++ .gpio70 = GPIO_DIR_INPUT,
++ .gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++ .set1 = {
++ .mode = &pch_gpio_set1_mode,
++ .direction = &pch_gpio_set1_direction,
++ .level = &pch_gpio_set1_level,
++ .blink = &pch_gpio_set1_blink,
++ .invert = &pch_gpio_set1_invert,
++ .reset = &pch_gpio_set1_reset,
++ },
++ .set2 = {
++ .mode = &pch_gpio_set2_mode,
++ .direction = &pch_gpio_set2_direction,
++ .level = &pch_gpio_set2_level,
++ .reset = &pch_gpio_set2_reset,
++ },
++ .set3 = {
++ .mode = &pch_gpio_set3_mode,
++ .direction = &pch_gpio_set3_direction,
++ .level = &pch_gpio_set3_level,
++ .reset = &pch_gpio_set3_reset,
++ },
++};
+diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
+new file mode 100644
+index 0000000000..9de7e34311
+--- /dev/null
++++ b/src/mainboard/dell/e6530/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++
++const u32 cim_verb_data[] = {
++ 0x111d76df, /* Codec Vendor / Device ID: IDT */
++ 0x10280535, /* Subsystem ID */
++ 11, /* Number of 4 dword sets */
++ AZALIA_SUBVENDOR(0, 0x10280535),
++ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++ 0x80862806, /* Codec Vendor / Device ID: Intel */
++ 0x80860101, /* Subsystem ID */
++ 4, /* Number of 4 dword sets */
++ AZALIA_SUBVENDOR(3, 0x80860101),
++ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6530/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include
++#include
++#include
++#include
++#include
++#include
++
++static void mainboard_enable(struct device *dev)
++{
++
++ /* FIXME: fix these values. */
++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++ GMA_INT15_PANEL_FIT_DEFAULT,
++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++ .enable_dev = mainboard_enable,
++};
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch b/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
deleted file mode 100644
index c411c18b..00000000
--- a/config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
-From: Felix Singer
-Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
-
-Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
-Signed-off-by: Felix Singer
----
- src/soc/intel/skylake/Kconfig | 1 +
- src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
- 2 files changed, 56 insertions(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 4ad33496b2..9191ed0ff8 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
- select CPU_INTEL_COMMON
- select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
- select CPU_SUPPORTS_PM_TIMER_EMULATION
-+ select DRIVERS_USB_ACPI
- select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
- select FSP_M_XIP
-diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
-index 6538a1475b..dfb81d496e 100644
---- a/src/soc/intel/skylake/chipset.cb
-+++ b/src/soc/intel/skylake/chipset.cb
-@@ -13,7 +13,61 @@ chip soc/intel/skylake
- device pci 07.0 alias chap off end
- device pci 08.0 alias gmm off end # Gaussian Mixture Model
- device pci 13.0 alias ish off end # SensorHub
-- device pci 14.0 alias south_xhci off ops usb_xhci_ops end
-+ device pci 14.0 alias south_xhci off ops usb_xhci_ops
-+ chip drivers/usb/acpi
-+ register "type" = "UPC_TYPE_HUB"
-+ device usb 0.0 alias xhci_root_hub off
-+ chip drivers/usb/acpi
-+ device usb 2.0 alias usb2_port1 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.1 alias usb2_port2 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.2 alias usb2_port3 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.3 alias usb2_port4 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.4 alias usb2_port5 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.5 alias usb2_port6 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.6 alias usb2_port7 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.7 alias usb2_port8 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.8 alias usb2_port9 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 2.9 alias usb2_port10 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.0 alias usb3_port1 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.1 alias usb3_port2 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.2 alias usb3_port3 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.3 alias usb3_port4 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.4 alias usb3_port5 off end
-+ end
-+ chip drivers/usb/acpi
-+ device usb 3.5 alias usb3_port6 off end
-+ end
-+ end
-+ end
-+ end
- device pci 14.1 alias south_xdci off ops usb_xdci_ops end
- device pci 14.2 alias thermal off end
- device pci 14.3 alias cio off end
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch
new file mode 100644
index 00000000..130984fb
--- /dev/null
+++ b/config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch
@@ -0,0 +1,145 @@
+From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Thu, 25 Jan 2024 14:30:03 +0000
+Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
+
+i diffed nicholas's current e6430 patch, versus the old one,
+prior to this revision update in lbmk, also cross referencing
+the original e6430 and e6530 patches, diffing them, and the
+result in this patch. most notably, spd data is now defined in
+the devicetree, instead of early_init.c as per:
+
+commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
+Author: Keith Hui
+Date: Sat Jul 22 12:49:05 2023 -0400
+ mb/*: Update SPD mapping for sandybridge boards
+
+This should work fine. Will test after this builds.
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/dell/e6530/Kconfig | 15 +++++++++++----
+ src/mainboard/dell/e6530/cmos.layout | 2 +-
+ src/mainboard/dell/e6530/devicetree.cb | 8 +++++---
+ src/mainboard/dell/e6530/early_init.c | 12 +++---------
+ 4 files changed, 20 insertions(+), 17 deletions(-)
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+index 582adddbd4..a104566890 100644
+--- a/src/mainboard/dell/e6530/Kconfig
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
++config DRAM_RESET_GATE_GPIO
++ default 60
++
+ config MAINBOARD_DIR
+ default "dell/e6530"
+
+ config MAINBOARD_PART_NUMBER
+ default "Latitude E6530"
+
+-config VGA_BIOS_ID
+- default "8086,0166"
++config PS2K_EISAID
++ default "PNP0303"
+
+-config DRAM_RESET_GATE_GPIO
+- default 60
++config PS2M_EISAID
++ default "PNP0F13"
+
+ config USBDEBUG_HCD_INDEX
+ default 2
++
++config VGA_BIOS_ID
++ default "8086,0166"
++
+ endif
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+index e85ea4c661..1aa7e77bce 100644
+--- a/src/mainboard/dell/e6530/cmos.layout
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -25,7 +25,7 @@ entries
+ # coreboot config options: EC
+ 412 1 e 1 bluetooth
+ 413 1 e 1 wwan
+-415 1 e 1 wlan
++414 1 e 1 wlan
+
+ # coreboot config options: ME
+ 424 1 e 14 me_state
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 96eed178c5..37135bcf0f 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
++ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
+ device domain 0x0 on
+ subsystemid 0x1028 0x0535 inherit
+
+@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+- register "gen4_dec" = "0x007c0901"
++ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+- device ref mei1 off end # Management Engine Interface 1
++ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt on end # Management Engine KT
+@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+- device ref pcie_rp5 off end # PCIe Port #5
++ device ref pcie_rp5 on end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+index d57f48e7f1..2b40f6963f 100644
+--- a/src/mainboard/dell/e6530/early_init.c
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -4,7 +4,6 @@
+ #include
+ #include
+ #include
+-#include
+ #include
+
+ const struct southbridge_usb_port mainboard_usb_ports[] = {
+@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
+
+ void bootblock_mainboard_early_init(void)
+ {
+- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+ }
+-
+-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+-{
+- read_spd(&spd[0], 0x50, id_only);
+- read_spd(&spd[2], 0x52, id_only);
+-}
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch b/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
deleted file mode 100644
index 9d75cec6..00000000
--- a/config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
-From: Mate Kukri
-Date: Fri, 22 Nov 2024 21:26:48 +0000
-Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
- bootblock
-
-Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
-Signed-off-by: Mate Kukri
----
- src/soc/intel/skylake/bootblock/pch.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
-index df00bb85a9..beaece960b 100644
---- a/src/soc/intel/skylake/bootblock/pch.c
-+++ b/src/soc/intel/skylake/bootblock/pch.c
-@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
-
- void pch_early_iorange_init(void)
- {
-- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-- LPC_IOE_EC_62_66;
-+ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
-+ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
-
- const config_t *config = config_of_soc();
-
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
new file mode 100644
index 00000000..fa7ab40d
--- /dev/null
+++ b/config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch
@@ -0,0 +1,54 @@
+From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
+From: Leah Rowe
+Date: Thu, 25 Jan 2024 14:37:30 +0000
+Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
+
+we neuter anyway. disabling it in devicetree will prevent linux
+from ever trying to use it or load a driver for it, and thus
+might prevent benign error messages from appearing in dmesg.
+
+this change was suggested by nicholas when asked on irc.
+
+Signed-off-by: Leah Rowe
+---
+ src/mainboard/dell/e6430/devicetree.cb | 4 ++--
+ src/mainboard/dell/e6530/devicetree.cb | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+index 054b01c5ac..2b8574c984 100644
+--- a/src/mainboard/dell/e6430/devicetree.cb
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+- device ref mei1 on end
++ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+- device ref me_kt on end
++ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 37135bcf0f..010200bb6d 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+- device ref mei1 on end # Management Engine Interface 1
++ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+- device ref me_kt on end # Management Engine KT
++ device ref me_kt off end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+--
+2.39.2
+
diff --git a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch b/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
deleted file mode 100644
index df71dc47..00000000
--- a/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
+++ /dev/null
@@ -1,2232 +0,0 @@
-From b515ba5b0cd02dc1771f27eaa716582b0827a638 Mon Sep 17 00:00:00 2001
-From: Mate Kukri
-Date: Tue, 31 Dec 2024 22:49:15 +0000
-Subject: [PATCH 28/37] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
-
-These machine have BootGuard fused and requires deguard to
-boot coreboot.
-
-Known issues:
-- Alpine Ridge Thunderbolt 3 controller does not work
-- Some Fn+F{1-12} keys aren't handled correctly
-- Nvidia dGPU is finicky
- - Needs option ROM
- - Power enable code is buggy
- - Nouveau only works on linux 6.8-6.9
-- Headphone jack isn't detected as plugged in despite correct verbs
-
-Thanks to Leah Rowe for helping with the T480s.
-
-Signed-off-by: Mate Kukri
-Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
----
- src/device/pci_rom.c | 4 +-
- src/ec/lenovo/h8/acpi/ec.asl | 2 +-
- src/ec/lenovo/h8/bluetooth.c | 6 +-
- src/ec/lenovo/h8/wwan.c | 6 +-
- src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++
- .../lenovo/sklkbl_thinkpad/Kconfig.name | 7 +
- .../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++
- .../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++
- .../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 +
- .../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++
- .../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++
- src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++
- src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++
- src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++
- src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 +
- .../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++
- .../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes
- .../variants/t480/gma-mainboard.ads | 19 ++
- .../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++
- .../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++
- .../variants/t480/memory_init_params.c | 20 ++
- .../variants/t480/overridetree.cb | 103 +++++++++
- .../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
- .../variants/t480s/gma-mainboard.ads | 19 ++
- .../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++
- .../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++
- .../variants/t480s/memory_init_params.c | 44 ++++
- .../variants/t480s/overridetree.cb | 103 +++++++++
- .../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes
- .../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes
- 49 files changed, 1583 insertions(+), 6 deletions(-)
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
- create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
-
-diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
-index dc41ef14ce..bba98d9dea 100644
---- a/src/device/pci_rom.c
-+++ b/src/device/pci_rom.c
-@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device)
- rom = cbrom;
- }
-
-+#if 0
- const char *scope = acpi_device_path(device);
- if (!scope) {
- printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
- return;
- }
-+#endif
-
- /* write _ROM method */
-- acpigen_write_scope(scope);
-+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
- acpigen_write_rom((void *)rom, rom->size * 512);
- acpigen_pop_len(); /* pop scope */
- }
-diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
-index bc54d3b422..8f4a8e1986 100644
---- a/src/ec/lenovo/h8/acpi/ec.asl
-+++ b/src/ec/lenovo/h8/acpi/ec.asl
-@@ -331,7 +331,7 @@ Device(EC)
- #include "sleepbutton.asl"
- #include "lid.asl"
- #include "beep.asl"
--#include "thermal.asl"
-+//#include "thermal.asl"
- #include "systemstatus.asl"
- #include "thinkpad.asl"
- }
-diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
-index 16fc8dce39..be71a24ced 100644
---- a/src/ec/lenovo/h8/bluetooth.c
-+++ b/src/ec/lenovo/h8/bluetooth.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
-
--#include
-+// #include
- #include
- #include
- #include
-@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev)
- {
- struct ec_lenovo_h8_config *conf = dev->chip_info;
-
-- if (!conf->has_bdc_detection) {
-+ if (1 || !conf->has_bdc_detection) {
- printk(BIOS_INFO, "H8: BDC detection not implemented. "
- "Assuming BDC installed\n");
- return true;
- }
-
-+#if 0
- if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
- printk(BIOS_INFO, "H8: BDC installed\n");
- return true;
- }
-+#endif
-
- printk(BIOS_INFO, "H8: BDC not installed\n");
- return false;
-diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
-index 685886fcce..5cdcf77406 100644
---- a/src/ec/lenovo/h8/wwan.c
-+++ b/src/ec/lenovo/h8/wwan.c
-@@ -1,6 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
-
--#include
-+// #include
- #include
- #include
- #include
-@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev)
- {
- struct ec_lenovo_h8_config *conf = dev->chip_info;
-
-- if (!conf->has_wwan_detection) {
-+ if (1 || !conf->has_wwan_detection) {
- printk(BIOS_INFO, "H8: WWAN detection not implemented. "
- "Assuming WWAN installed\n");
- return true;
- }
-
-+#if 0
- if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
- printk(BIOS_INFO, "H8: WWAN installed\n");
- return true;
- }
-+#endif
-
- printk(BIOS_INFO, "H8: WWAN not installed\n");
- return false;
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-new file mode 100644
-index 0000000000..4998672943
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-@@ -0,0 +1,57 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+ bool
-+ select BOARD_ROMSIZE_KB_16384
-+ select EC_LENOVO_H8
-+ select EC_LENOVO_PMH7
-+ select H8_HAS_BAT_THRESHOLDS_IMPL
-+ select H8_HAS_LEDLOGO
-+ select H8_HAS_PRIMARY_FN_KEYS
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select INTEL_GMA_HAVE_VBT
-+ select INTEL_INT15
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select MAINBOARD_HAS_TPM2
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select MEMORY_MAPPED_TPM
-+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-+ select SOC_INTEL_KABYLAKE
-+ select SPD_READ_BY_WORD
-+ select SYSTEM_TYPE_LAPTOP
-+
-+config BOARD_LENOVO_T480
-+ bool
-+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+
-+config BOARD_LENOVO_T480S
-+ bool
-+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+
-+if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
-+
-+config MAINBOARD_DIR
-+ default "lenovo/sklkbl_thinkpad"
-+
-+config VARIANT_DIR
-+ default "t480" if BOARD_LENOVO_T480
-+ default "t480s" if BOARD_LENOVO_T480S
-+
-+config OVERRIDE_DEVICETREE
-+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config MAINBOARD_PART_NUMBER
-+ default "T480" if BOARD_LENOVO_T480
-+ default "T480s" if BOARD_LENOVO_T480S
-+
-+config CBFS_SIZE
-+ default 0x900000
-+
-+config DIMM_MAX
-+ default 2
-+
-+config DIMM_SPD_SIZE
-+ default 512 # DDR4
-+
-+endif
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
-new file mode 100644
-index 0000000000..abc273f387
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
-@@ -0,0 +1,7 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_LENOVO_T480
-+ bool "ThinkPad T480"
-+
-+config BOARD_LENOVO_T480S
-+ bool "ThinkPad T480s"
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
-new file mode 100644
-index 0000000000..c308239177
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
-@@ -0,0 +1,73 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += bootblock.c ec.c
-+
-+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
-+
-+ramstage-y += ramstage.c ec.c
-+ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-+
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin
-+spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin
-+spd_0.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin
-+spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin
-+spd_1.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin
-+spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin
-+spd_2.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin
-+spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin
-+spd_3.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin
-+spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin
-+spd_4.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin
-+spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin
-+spd_5.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin
-+spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin
-+spd_6.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin
-+spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin
-+spd_7.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin
-+spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin
-+spd_8.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin
-+spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin
-+spd_9.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin
-+spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin
-+spd_10.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin
-+spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin
-+spd_11.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin
-+spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin
-+spd_12.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin
-+spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin
-+spd_13.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin
-+spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin
-+spd_14.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin
-+spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin
-+spd_15.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin
-+spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin
-+spd_16.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin
-+spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin
-+spd_17.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin
-+spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin
-+spd_18.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin
-+spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin
-+spd_19.bin-type := raw
-+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin
-+spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin
-+spd_20.bin-type := raw
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
-new file mode 100644
-index 0000000000..3a949a2fca
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+#define THINKPAD_EC_GPE 22
-+
-+Name(\TCRT, 100)
-+Name(\TPSV, 90)
-+Name(\FLVL, 0)
-+
-+#include
-+#include
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
-new file mode 100644
-index 0000000000..fb660dbdfa
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
-@@ -0,0 +1,60 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include "ec.h"
-+
-+static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno)
-+{
-+ microchip_pnp_enter_conf_state(port);
-+
-+ // Select LPC I/F LDN
-+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
-+ // Write UART BAR
-+ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707);
-+ // Set SIRQ4 to UART
-+ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART);
-+
-+ // Configure UART LDN
-+ pnp_write(port, PNP_LDN_SELECT, LDN_UART);
-+ pnp_write(port, UART_ACTIVATE, 0x01);
-+ pnp_write(port, UART_CONFIG_SELECT, 0x00);
-+
-+ microchip_pnp_exit_conf_state(port);
-+
-+#ifdef CONFIG_BOARD_LENOVO_T480
-+ // Supply debug unlock key
-+ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
-+
-+ // Use debug writes to set UART_TX and UART_RX GPIOs
-+ debug_write_dword(0xf0c400 + 0x110, 0x00001000);
-+ debug_write_dword(0xf0c400 + 0x114, 0x00001000);
-+#endif
-+}
-+
-+
-+#define UART_PORT 0x3f8
-+#define UART_IRQ 4
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+ // Tell EC via BIOS Debug Port 1 that the world isn't on fire
-+
-+ // Let the EC know that BIOS code is running
-+ outb(0x11, 0x86);
-+ outb(0x6e, 0x86);
-+
-+ // Enable accesses to EC1 interface
-+ ec0_write(0, ec0_read(0) | 0x20);
-+
-+ // Reset LEDs to power on state
-+ // (Without this warm reboot leaves LEDs off)
-+ ec0_write(0x0c, 0x80);
-+ ec0_write(0x0c, 0x07);
-+ ec0_write(0x0c, 0x8a);
-+
-+ // Setup debug UART
-+ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
-new file mode 100644
-index 0000000000..c07d4d53ca
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
-@@ -0,0 +1,71 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+chip soc/intel/skylake
-+ # IGD Displays
-+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
-+
-+ register "panel_cfg" = "{
-+ .up_delay_ms = 200,
-+ .down_delay_ms = 50,
-+ .cycle_delay_ms = 600,
-+ .backlight_on_delay_ms = 1,
-+ .backlight_off_delay_ms = 200,
-+ .backlight_pwm_hz = 200,
-+ }"
-+
-+ # Power
-+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
-+ register "PmConfigSlpS4MinAssert" = "1" # 1s
-+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
-+ register "PmConfigSlpAMinAssert" = "3" # 2s
-+
-+ device domain 0 on
-+ device ref igpu on end
-+ device ref sa_thermal on end
-+ device ref thermal on end
-+ device ref south_xhci on end
-+ device ref lpc_espi on
-+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
-+
-+ register "gen1_dec" = "0x007c1601"
-+ register "gen2_dec" = "0x000c15e1"
-+
-+ chip ec/lenovo/pmh7
-+ register "backlight_enable" = "true"
-+ register "dock_event_enable" = "true"
-+ device pnp ff.1 on end # dummy
-+ end
-+
-+ chip ec/lenovo/h8
-+ register "beepmask0" = "0x00"
-+ register "beepmask1" = "0x86"
-+ register "config0" = "0xa6"
-+ register "config1" = "0x0d"
-+ register "config2" = "0xa8"
-+ register "config3" = "0xc4"
-+ register "has_keyboard_backlight" = "1"
-+ register "event2_enable" = "0xff"
-+ register "event3_enable" = "0xff"
-+ register "event4_enable" = "0xd0"
-+ register "event5_enable" = "0x3c"
-+ register "event7_enable" = "0x01"
-+ register "event8_enable" = "0x7b"
-+ register "event9_enable" = "0xff"
-+ register "eventc_enable" = "0xff"
-+ register "eventd_enable" = "0xff"
-+ register "evente_enable" = "0x9d"
-+ device pnp ff.2 on # dummy
-+ io 0x60 = 0x62
-+ io 0x62 = 0x66
-+ io 0x64 = 0x1600
-+ io 0x66 = 0x1604
-+ end
-+ end
-+
-+ chip drivers/pc80/tpm
-+ device pnp 0c31.0 on end
-+ end
-+ end
-+ device ref hda on end
-+ end
-+end
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-new file mode 100644
-index 0000000000..aa4d4de2a6
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+DefinitionBlock(
-+ "dsdt.aml",
-+ "DSDT",
-+ ACPI_DSDT_REV_2,
-+ OEM_ID,
-+ ACPI_TABLE_CREATOR,
-+ 0x20110725
-+)
-+{
-+ #include
-+ #include
-+ #include
-+
-+ Device (\_SB.PCI0)
-+ {
-+ #include
-+ #include
-+ #include
-+ }
-+
-+ Scope (\_SB.PCI0.RP01)
-+ {
-+ Device (PEGP)
-+ {
-+ Name (_ADR, Zero)
-+ }
-+ }
-+
-+ #include
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
-new file mode 100644
-index 0000000000..adb6a60324
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
-@@ -0,0 +1,153 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include "ec.h"
-+
-+#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55
-+#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa
-+
-+void microchip_pnp_enter_conf_state(uint16_t port)
-+{
-+ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port);
-+}
-+
-+void microchip_pnp_exit_conf_state(uint16_t port)
-+{
-+ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port);
-+}
-+
-+uint8_t pnp_read(uint16_t port, uint8_t index)
-+{
-+ outb(index, port);
-+ return inb(port + 1);
-+}
-+
-+uint32_t pnp_read_le32(uint16_t port, uint8_t index)
-+{
-+ return (uint32_t) pnp_read(port, index) |
-+ (uint32_t) pnp_read(port, index + 1) << 8 |
-+ (uint32_t) pnp_read(port, index + 2) << 16 |
-+ (uint32_t) pnp_read(port, index + 3) << 24;
-+}
-+
-+void pnp_write(uint16_t port, uint8_t index, uint8_t value)
-+{
-+ outb(index, port);
-+ outb(value, port + 1);
-+}
-+
-+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value)
-+{
-+ pnp_write(port, index, value & 0xff);
-+ pnp_write(port, index + 1, value >> 8 & 0xff);
-+ pnp_write(port, index + 2, value >> 16 & 0xff);
-+ pnp_write(port, index + 3, value >> 24 & 0xff);
-+}
-+
-+static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port)
-+{
-+ while (inb(cmd_port) & EC_OBF)
-+ inb(data_port);
-+}
-+
-+static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port)
-+{
-+ while (inb(cmd_port) & EC_IBF)
-+ ;
-+}
-+
-+static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port)
-+{
-+ while (!(inb(cmd_port) & EC_OBF))
-+ ;
-+}
-+
-+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr)
-+{
-+ ecN_clear_out_queue(cmd_port, data_port);
-+ ecN_wait_to_send(cmd_port, data_port);
-+ outb(EC_READ, cmd_port);
-+ ecN_wait_to_send(cmd_port, data_port);
-+ outb(addr, data_port);
-+ ecN_wait_to_recv(cmd_port, data_port);
-+ return inb(data_port);
-+}
-+
-+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val)
-+{
-+ ecN_clear_out_queue(cmd_port, data_port);
-+ ecN_wait_to_send(cmd_port, data_port);
-+ outb(EC_WRITE, cmd_port);
-+ ecN_wait_to_send(cmd_port, data_port);
-+ outb(addr, data_port);
-+ ecN_wait_to_send(cmd_port, data_port);
-+ outb(val, data_port);
-+}
-+
-+uint8_t eeprom_read(uint16_t addr)
-+{
-+ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
-+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
-+ outl(1, EC2_CMD);
-+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
-+ outl(addr, EC2_DATA);
-+ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
-+ return inl(EC2_DATA);
-+}
-+
-+void eeprom_write(uint16_t addr, uint8_t val)
-+{
-+ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
-+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
-+ outl(2, EC2_CMD);
-+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
-+ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA);
-+ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
-+ inl(EC2_DATA);
-+}
-+
-+uint16_t debug_loaded_keys(void)
-+{
-+ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86);
-+}
-+
-+static void debug_cmd(uint8_t cmd)
-+{
-+ ec0_write(EC_DEBUG_CMD, cmd);
-+ while (ec0_read(EC_DEBUG_CMD) & 0x80)
-+ ;
-+}
-+
-+void debug_read_key(uint8_t i, uint8_t *key)
-+{
-+ debug_cmd(0x80 | (i & 0xf));
-+ for (int j = 0; j < 8; ++j)
-+ key[j] = ec0_read(0x3e + j);
-+}
-+
-+void debug_write_key(uint8_t i, const uint8_t *key)
-+{
-+ for (int j = 0; j < 8; ++j)
-+ ec0_write(0x3e + j, key[j]);
-+ debug_cmd(0xc0 | (i & 0xf));
-+}
-+
-+uint32_t debug_read_dword(uint32_t addr)
-+{
-+ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
-+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
-+ outl(addr << 8 | 0xE2, EC3_DATA);
-+ ecN_wait_to_recv(EC3_CMD, EC3_DATA);
-+ return inl(EC3_DATA);
-+}
-+
-+void debug_write_dword(uint32_t addr, uint32_t val)
-+{
-+ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
-+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
-+ outl(addr << 8 | 0xEA, EC3_DATA);
-+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
-+ outl(val, EC3_DATA);
-+}
-+
-+const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf };
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
-new file mode 100644
-index 0000000000..d2963c8962
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
-@@ -0,0 +1,99 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef SKLKBL_THINKPAD_EC_H
-+#define SKLKBL_THINKPAD_EC_H
-+
-+// EC configuration base address
-+#define EC_CFG_PORT 0x4e
-+
-+// Chip global registers
-+#define PNP_LDN_SELECT 0x07
-+# define LDN_UART 0x07
-+# define LDN_LPCIF 0x0c
-+#define EC_DEVICE_ID 0x20
-+#define EC_DEVICE_REV 0x21
-+
-+// LPC I/F registers
-+#define LPCIF_SIRQ(i) (0x40 + (i))
-+
-+#define LPCIF_BAR_CFG 0x60
-+#define LPCIF_BAR_MAILBOX 0x64
-+#define LPCIF_BAR_8042 0x68
-+#define LPCIF_BAR_ACPI_EC0 0x6c
-+#define LPCIF_BAR_ACPI_EC1 0x70
-+#define LPCIF_BAR_ACPI_EC2 0x74
-+#define LPCIF_BAR_ACPI_EC3 0x78
-+#define LPCIF_BAR_ACPI_PM0 0x7c
-+#define LPCIF_BAR_UART 0x80
-+#define LPCIF_BAR_FAST_KYBD 0x84
-+#define LPCIF_BAR_EMBED_FLASH 0x88
-+#define LPCIF_BAR_GP_SPI 0x8c
-+#define LPCIF_BAR_EMI 0x90
-+#define LPCIF_BAR_PMH7 0x94
-+#define LPCIF_BAR_PORT80_DBG0 0x98
-+#define LPCIF_BAR_PORT80_DBG1 0x9c
-+#define LPCIF_BAR_RTC 0xa0
-+
-+// UART registers
-+#define UART_ACTIVATE 0x30
-+#define UART_CONFIG_SELECT 0xf0
-+
-+void microchip_pnp_enter_conf_state(uint16_t port);
-+void microchip_pnp_exit_conf_state(uint16_t port);
-+uint8_t pnp_read(uint16_t port, uint8_t index);
-+uint32_t pnp_read_le32(uint16_t port, uint8_t index);
-+void pnp_write(uint16_t port, uint8_t index, uint8_t value);
-+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value);
-+
-+#define EC0_CMD 0x0066
-+#define EC0_DATA 0x0062
-+#define EC1_CMD 0x1604
-+#define EC1_DATA 0x1600
-+#define EC2_CMD 0x1634
-+#define EC2_DATA 0x1630
-+#define EC3_CMD 0x161c
-+#define EC3_DATA 0x1618
-+
-+#define EC_OBF (1 << 0)
-+#define EC_IBF (1 << 1)
-+
-+#define EC_READ 0x80
-+#define EC_WRITE 0x81
-+
-+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr);
-+
-+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val);
-+
-+// EC0 and EC1 mostly are useful with the READ/WRITE commands
-+#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr)
-+#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val)
-+#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr)
-+#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val)
-+
-+// Read from the emulated EEPROM
-+uint8_t eeprom_read(uint16_t addr);
-+
-+// Write to the emulated EEPROM
-+void eeprom_write(uint16_t addr, uint8_t val);
-+
-+// Read loaded debug key mask
-+uint16_t debug_loaded_keys(void);
-+
-+// The following location (via either EC0 or EC1) can be used to interact with the debug interface
-+#define EC_DEBUG_CMD 0x3d
-+
-+void debug_read_key(uint8_t i, uint8_t *key);
-+
-+void debug_write_key(uint8_t i, const uint8_t *key);
-+
-+uint32_t debug_read_dword(uint32_t addr);
-+
-+void debug_write_dword(uint32_t addr, uint32_t val);
-+
-+// RW unlock key index
-+#define DEBUG_RW_KEY_IDX 1
-+
-+// RW unlock key for EC version N24HT37W
-+extern const uint8_t debug_rw_key[8];
-+
-+#endif
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
-new file mode 100644
-index 0000000000..d89ed712d4
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef GPIO_H
-+#define GPIO_H
-+
-+void variant_config_gpios(void);
-+
-+#endif
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
-new file mode 100644
-index 0000000000..44c8578852
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
-@@ -0,0 +1,105 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include "ec.h"
-+#include "gpio.h"
-+
-+#define GPIO_GPU_RST GPP_E22 // active low
-+#define GPIO_1R8VIDEO_AON_ON GPP_E23
-+
-+#define GPIO_DGFX_PWRGD GPP_F3
-+
-+#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low
-+#define GPIO_DGFX_VRAM_ID0 GPP_D11
-+#define GPIO_DGFX_VRAM_ID1 GPP_D12
-+
-+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
-+{
-+ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
-+
-+ int dgfx_vram_id;
-+
-+ // Setup GPIOs
-+ variant_config_gpios();
-+
-+ // Detect and enable dGPU
-+ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low
-+ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1;
-+ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]);
-+
-+ // NOTE: i pulled this GPU enable sequence from thin air
-+ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default.
-+ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels
-+ if (get_uint_option("dgpu_enable", 0)) {
-+ printk(BIOS_DEBUG, "Enabling discrete GPU\n");
-+ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail
-+ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU
-+ ;
-+ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset
-+ } else {
-+ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n");
-+ }
-+
-+ } else {
-+ printk(BIOS_DEBUG, "Discrete GPU not present\n");
-+ }
-+}
-+
-+static void dump_ec_cfg(uint16_t port)
-+{
-+ microchip_pnp_enter_conf_state(port);
-+
-+ // Device info
-+ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID));
-+ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV));
-+
-+ // Switch to LPCIF LDN
-+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
-+
-+ // Dump SIRQs
-+ for (int i = 0; i <= 15; i += 1)
-+ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i)));
-+
-+ // Dump BARs
-+ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG));
-+ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX));
-+ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042));
-+ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0));
-+ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1));
-+ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2));
-+ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3));
-+ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0));
-+ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART));
-+ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD));
-+ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH));
-+ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI));
-+ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI));
-+ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7));
-+ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0));
-+ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1));
-+ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC));
-+
-+ microchip_pnp_exit_conf_state(port);
-+}
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+ if (CONFIG(VGA_ROM_RUN))
-+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
-+ GMA_INT15_PANEL_FIT_DEFAULT,
-+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+static void mainboard_init(void *chip_info)
-+{
-+ dump_ec_cfg(EC_CFG_PORT);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+ .enable_dev = mainboard_enable,
-+ .init = mainboard_init,
-+};
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
-GIT binary patch
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-z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr
-zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^LXW8|
-z-Vsanq!Y==Kq9plQ+*gu^hf&pJ9?tY{h01cbtR&SfsVM!_*!D4W5>papLuo?gRur|
-zF$`lX;f2t48Dpd4V@(*z=dq95OkkfiVU53N<(gE+=U)KHEdU4}@R=aMjTTTOcb8-a
-zC9IXSxZB*|#u~SlHnpsY25L#Sxy6ljl16gI)H0f>for?qaszCX;ESpG=pqROFWR~Z
-zTqQzcH(berra`9K(R~0OJ_eeA=>
-z&R-)LYP^U3@%6h}+0)7m-mEOhOM92l32>zpvu-&@ZkPf<>~Bsv&Oy1O(`pbLUf3vt*0HIRk0U3EzI
-zIeSaIE9*jps%6qP7$EQo8=K#f^K_mFpy5prkNNSOU;oI@KK0}Ge*G6eyWz+6OyADf
-zE`}Db#-81u-uS=OJB*=`v}WPMs@ugdtLtbZo6OEUf}>!QL`
-z1zQ!pLt!Zek0|;p3VTDrj}`q(g?+8yuZk|KY?X>TRlP@LPpbH`s-ITbSygS+Jq6cQ
-zp|Em=T_#B53Y|R}mtw!K3mUyWRhytxx_wi^(}HurDkx@L%OlKIA%rq@7%bE{p{Wl~
-zJJ%lV6&>fxBjnbA8G(&P?a8o%P#c~Wo$7|%1UE-$r;6jwt1uejOfMLwF-BDgC-Q+N
-za!Hx;1S&$9!rlNCTsI*IMZ0#Y5aEO7sjIz#jb`S|q7OpRYx`h&=PK}_YnN#poNF=7
-z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA
-z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j
-z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
-new file mode 100644
-index 0000000000..f7c29e1f39
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
-@@ -0,0 +1,203 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include "../../gpio.h"
-+
-+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
-+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
-+
-+static const struct pad_config gpio_table[] = {
-+
-+ /* ------- GPIO Community 0 ------- */
-+
-+ /* ------- GPIO Group GPP_A ------- */
-+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
-+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
-+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
-+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
-+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
-+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
-+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
-+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
-+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
-+ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */
-+ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */
-+ PAD_NC(GPP_A11, NONE),
-+ PAD_NC(GPP_A12, NONE),
-+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
-+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
-+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */
-+ PAD_NC(GPP_A16, NONE),
-+ PAD_NC(GPP_A17, NONE),
-+ PAD_NC(GPP_A18, NONE),
-+ PAD_NC(GPP_A19, NONE),
-+ PAD_NC(GPP_A20, NONE),
-+ PAD_NC(GPP_A21, NONE),
-+ PAD_NC(GPP_A22, NONE),
-+ PAD_NC(GPP_A23, NONE),
-+
-+ /* ------- GPIO Group GPP_B ------- */
-+ PAD_NC(GPP_B0, NONE),
-+ PAD_NC(GPP_B1, NONE),
-+ PAD_NC(GPP_B2, NONE),
-+ PAD_NC(GPP_B3, NONE),
-+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
-+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */
-+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */
-+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */
-+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */
-+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */
-+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */
-+ PAD_NC(GPP_B11, NONE),
-+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
-+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
-+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
-+ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */
-+ PAD_NC(GPP_B16, NONE),
-+ PAD_NC(GPP_B17, NONE),
-+ PAD_NC(GPP_B18, NONE),
-+ PAD_NC(GPP_B19, NONE),
-+ PAD_NC(GPP_B20, NONE),
-+ PAD_NC(GPP_B21, NONE),
-+ PAD_NC(GPP_B22, NONE),
-+ PAD_NC(GPP_B23, NONE),
-+
-+ /* ------- GPIO Community 1 ------- */
-+
-+ /* ------- GPIO Group GPP_C ------- */
-+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
-+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
-+ PAD_NC(GPP_C2, NONE),
-+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
-+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
-+ PAD_NC(GPP_C5, NONE),
-+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
-+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
-+ PAD_NC(GPP_C8, NONE),
-+ PAD_NC(GPP_C9, NONE),
-+ PAD_NC(GPP_C10, NONE),
-+ PAD_NC(GPP_C11, NONE),
-+ PAD_NC(GPP_C12, NONE),
-+ PAD_NC(GPP_C13, NONE),
-+ PAD_NC(GPP_C14, NONE),
-+ PAD_NC(GPP_C15, NONE),
-+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
-+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
-+ PAD_NC(GPP_C18, NONE),
-+ PAD_NC(GPP_C19, NONE),
-+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
-+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
-+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
-+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
-+
-+ /* ------- GPIO Group GPP_D ------- */
-+ PAD_NC(GPP_D0, NONE),
-+ PAD_NC(GPP_D1, NONE),
-+ PAD_NC(GPP_D2, NONE),
-+ PAD_NC(GPP_D3, NONE),
-+ PAD_NC(GPP_D4, NONE),
-+ PAD_NC(GPP_D5, NONE),
-+ PAD_NC(GPP_D6, NONE),
-+ PAD_NC(GPP_D7, NONE),
-+ PAD_NC(GPP_D8, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
-+ PAD_NC(GPP_D10, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
-+ PAD_NC(GPP_D13, NONE),
-+ PAD_NC(GPP_D14, NONE),
-+ PAD_NC(GPP_D15, NONE),
-+ PAD_NC(GPP_D16, NONE),
-+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */
-+ PAD_NC(GPP_D18, NONE),
-+ PAD_NC(GPP_D19, NONE),
-+ PAD_NC(GPP_D20, NONE),
-+ PAD_NC(GPP_D21, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
-+ PAD_NC(GPP_D23, NONE),
-+
-+ /* ------- GPIO Group GPP_E ------- */
-+ PAD_NC(GPP_E0, NONE),
-+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */
-+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
-+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
-+ PAD_NC(GPP_E5, NONE),
-+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
-+ PAD_NC(GPP_E7, NONE),
-+ PAD_NC(GPP_E8, NONE),
-+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */
-+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */
-+ PAD_NC(GPP_E11, NONE),
-+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
-+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
-+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
-+ PAD_NC(GPP_E15, NONE),
-+ PAD_NC(GPP_E16, NONE),
-+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
-+ PAD_NC(GPP_E18, NONE),
-+ PAD_NC(GPP_E19, NONE),
-+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
-+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
-+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
-+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
-+
-+ /* ------- GPIO Community 2 ------- */
-+
-+ /* -------- GPIO Group GPD -------- */
-+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
-+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
-+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
-+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
-+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
-+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
-+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
-+ PAD_NC(GPD7, NONE),
-+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
-+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
-+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
-+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
-+
-+ /* ------- GPIO Community 3 ------- */
-+
-+ /* ------- GPIO Group GPP_F ------- */
-+ PAD_NC(GPP_F0, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
-+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */
-+ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */
-+ PAD_NC(GPP_F5, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
-+ PAD_NC(GPP_F16, NONE),
-+ PAD_NC(GPP_F17, NONE),
-+ PAD_NC(GPP_F18, NONE),
-+ PAD_NC(GPP_F19, NONE),
-+ PAD_NC(GPP_F20, NONE),
-+ PAD_NC(GPP_F21, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
-+
-+ /* ------- GPIO Group GPP_G ------- */
-+ PAD_NC(GPP_G0, NONE),
-+ PAD_NC(GPP_G1, NONE),
-+ PAD_NC(GPP_G2, NONE),
-+ PAD_NC(GPP_G3, NONE),
-+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
-+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
-+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
-+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
-+};
-+
-+void variant_config_gpios(void)
-+{
-+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
-new file mode 100644
-index 0000000000..3a951ce0da
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
-@@ -0,0 +1,90 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
-+ 0x17aa225d, // Subsystem ID
-+ 11,
-+ AZALIA_SUBVENDOR(0, 0x17aa225d),
-+
-+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
-+ AZALIA_INTEGRATED,
-+ AZALIA_INTERNAL,
-+ AZALIA_MIC_IN,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_NO_JACK_PRESENCE_DETECT,
-+ 2, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
-+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
-+ AZALIA_INTEGRATED,
-+ AZALIA_INTERNAL,
-+ AZALIA_SPEAKER,
-+ AZALIA_OTHER_ANALOG,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_NO_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-+ AZALIA_MIC_IN,
-+ AZALIA_STEREO_MONO_1_8,
-+ AZALIA_BLACK,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 3, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
-+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-+ AZALIA_HP_OUT,
-+ AZALIA_STEREO_MONO_1_8,
-+ AZALIA_BLACK,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 15
-+ )),
-+
-+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
-+ 0x80860101, // Subsystem ID
-+ 4,
-+ AZALIA_SUBVENDOR(2, 0x80860101),
-+
-+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 2, 0
-+ )),
-+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 3, 0
-+ )),
-+};
-+
-+const u32 pc_beep_verbs[] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
-new file mode 100644
-index 0000000000..5252a402f9
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
-@@ -0,0 +1,20 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+
-+void mainboard_memory_init_params(FSPM_UPD *mupd)
-+{
-+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
-+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */
-+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
-+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
-+
-+ /* Get SPD for memory slots */
-+ struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
-+ get_spd_smbus(&blk);
-+ dump_spd_info(&blk);
-+
-+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
-+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-new file mode 100644
-index 0000000000..bf66bd3a69
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-@@ -0,0 +1,103 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+chip soc/intel/skylake
-+ device domain 0 on
-+ device ref south_xhci on
-+ register "usb2_ports" = "{
-+ [0] = USB2_PORT_MID(OC1), // USB-A
-+ [1] = USB2_PORT_MID(OC0), // USB-A (always on)
-+ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot)
-+ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port)
-+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera)
-+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB)
-+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB)
-+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam)
-+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader)
-+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel)
-+ }"
-+ register "usb3_ports" = "{
-+ [0] = USB3_PORT_DEFAULT(OC1), // USB-A
-+ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on)
-+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader)
-+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port)
-+ }"
-+ end
-+
-+ device ref sata on
-+ # SATA_2 - JHDD1 SATA SSD
-+ register "SataPortsEnable[2]" = "1"
-+ register "SataPortsDevSlp[2]" = "1"
-+ end
-+
-+ # PCIe controller 1 - 1x4
-+ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0
-+ #
-+ # PCIe controller 2 - 2x1+1x2 (lane reversal)
-+ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8)
-+ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2
-+ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3
-+ #
-+ # PCIe controller 3 - 2x2
-+ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4
-+ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5
-+
-+ # dGPU - x4
-+ device ref pcie_rp1 on
-+ register "PcieRpEnable[0]" = "1"
-+ register "PcieRpClkReqSupport[0]" = "1"
-+ register "PcieRpClkReqNumber[0]" = "0"
-+ register "PcieRpClkSrcNumber[0]" = "0"
-+ register "PcieRpAdvancedErrorReporting[0]" = "1"
-+ register "PcieRpLtrEnable[0]" = "1"
-+ end
-+
-+ # Ethernet (clobbers RP8)
-+ device ref gbe on
-+ register "LanClkReqSupported" = "1"
-+ register "LanClkReqNumber" = "1"
-+ register "EnableLanLtr" = "1"
-+ register "EnableLanK1Off" = "1"
-+ end
-+
-+ # M.2 WLAN - x1
-+ device ref pcie_rp7 on
-+ register "PcieRpEnable[6]" = "1"
-+ register "PcieRpClkReqSupport[6]" = "1"
-+ register "PcieRpClkReqNumber[6]" = "2"
-+ register "PcieRpClkSrcNumber[6]" = "2"
-+ register "PcieRpAdvancedErrorReporting[6]" = "1"
-+ register "PcieRpLtrEnable[6]" = "1"
-+ end
-+
-+ # M.2 WWAN - x2
-+ device ref pcie_rp5 on
-+ register "PcieRpEnable[4]" = "1"
-+ register "PcieRpClkReqSupport[4]" = "1"
-+ register "PcieRpClkReqNumber[4]" = "3"
-+ register "PcieRpClkSrcNumber[4]" = "3"
-+ register "PcieRpAdvancedErrorReporting[4]" = "1"
-+ register "PcieRpLtrEnable[4]" = "1"
-+ end
-+
-+ # TB3 (Alpine Ridge LP) - x2
-+ device ref pcie_rp9 on
-+ register "PcieRpEnable[8]" = "1"
-+ register "PcieRpClkReqSupport[8]" = "1"
-+ register "PcieRpClkReqNumber[8]" = "4"
-+ register "PcieRpClkSrcNumber[8]" = "4"
-+ register "PcieRpAdvancedErrorReporting[8]" = "1"
-+ register "PcieRpLtrEnable[8]" = "1"
-+ register "PcieRpHotPlug[8]" = "1"
-+ end
-+
-+ # M.2 2280 caddy - x2
-+ device ref pcie_rp11 on
-+ register "PcieRpEnable[10]" = "1"
-+ register "PcieRpClkReqSupport[10]" = "1"
-+ register "PcieRpClkReqNumber[10]" = "5"
-+ register "PcieRpClkSrcNumber[10]" = "5"
-+ register "PcieRpAdvancedErrorReporting[10]" = "1"
-+ register "PcieRpLtrEnable[10]" = "1"
-+ end
-+ end
-+end
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840
-GIT binary patch
-literal 4106
-zcmeHJUu+a*5TCu>yW9JAmoD2P9tqx`iFWXCLD09RaS&4j$?kY0KGYdgn6;MZ*!anbk!PNr!a%eU
-zTXkLEL3ly5L&oUX#CS7?b2%Kad?s-#@;mhg8>>>#S&)d2I
-zmP&-g0$k02szSQj(Y*j}YYtQnDH0;2ui{mPhI!flfFgv9nqI4Wr~5_?s`k0kALiCvcP
-zCrRUFrpVYPYn?Jn%6MGXUXj_GGJYa!U&-tn8Gn&ANnz_0+@olH3VTw)mlf@-!p8{!e#p0ct5}M(h16D>p?OGjSz6v3juERjS
-z#z{?mXvVqrXs_rvUmYR40gNzg(QD6y9E94?4DWO|6eb83LI-smcVC6x1n2reH}rAp
-zLM);f=tWDCr``UF5T>!;PYu^H1g>EBP8A}2*fM>s-@nC3pDV|}6+CtfhG(II7`pcw
-z`jLfJ!?;*R@Bp=Nw2EPOC7FEs(cugIP_K6tN_$~tvS8nx6iOv|IMrO3&-m*N9ZP#b
-znG^~>I|l1cUVSeD9r^k3h0TP}WWD9=MZxY<Z3B2yU!k71#YRpThOJtVheMDA50rV#s@U
-z+nKbA{O(olYR}icuzQD*-cjBQ9;%!eMDVP>7mWsF@=%>o)wSgq=n%DHNOYwRr4Ao6
-zbNdgEn*RdDS>Rud+fIY0N8JkP3q6;>8o%R(CE2n3?Xg%qP+U%~6|{XFyxv7Y#;J2Z
-XK$lk*wsY^m4}9|iz?mg_AjCfat$CyH
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
-new file mode 100644
-index 0000000000..fcfbd75a92
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
-@@ -0,0 +1,19 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+ ports : constant Port_List :=
-+ (eDP,
-+ DP1,
-+ DP2,
-+ HDMI1,
-+ HDMI2,
-+ others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
-new file mode 100644
-index 0000000000..a98dd2bc4e
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
-@@ -0,0 +1,199 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include "../../gpio.h"
-+
-+static const struct pad_config gpio_table[] = {
-+ /* ------- GPIO Community 0 ------- */
-+
-+ /* ------- GPIO Group GPP_A ------- */
-+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
-+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
-+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
-+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
-+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
-+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
-+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
-+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
-+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
-+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
-+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
-+ PAD_NC(GPP_A11, NONE),
-+ PAD_NC(GPP_A12, NONE),
-+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */
-+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */
-+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */
-+ PAD_NC(GPP_A16, NONE),
-+ PAD_NC(GPP_A17, NONE),
-+ PAD_NC(GPP_A18, NONE),
-+ PAD_NC(GPP_A19, NONE),
-+ PAD_NC(GPP_A20, NONE),
-+ PAD_NC(GPP_A21, NONE),
-+ PAD_NC(GPP_A22, NONE),
-+ PAD_NC(GPP_A23, NONE),
-+
-+ /* ------- GPIO Group GPP_B ------- */
-+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
-+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-+ PAD_NC(GPP_B2, NONE),
-+ PAD_NC(GPP_B3, NONE),
-+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
-+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */
-+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */
-+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */
-+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */
-+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */
-+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */
-+ PAD_NC(GPP_B11, NONE),
-+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
-+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
-+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */
-+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
-+ PAD_NC(GPP_B16, NONE),
-+ PAD_NC(GPP_B17, NONE),
-+ PAD_NC(GPP_B18, NONE),
-+ PAD_NC(GPP_B19, NONE),
-+ PAD_NC(GPP_B20, NONE),
-+ PAD_NC(GPP_B21, NONE),
-+ PAD_NC(GPP_B22, NONE),
-+ PAD_NC(GPP_B23, NONE),
-+
-+ /* ------- GPIO Community 1 ------- */
-+
-+ /* ------- GPIO Group GPP_C ------- */
-+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
-+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
-+ PAD_CFG_GPO(GPP_C2, 1, DEEP),
-+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
-+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
-+ PAD_NC(GPP_C5, NONE),
-+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
-+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
-+ PAD_NC(GPP_C8, NONE),
-+ PAD_NC(GPP_C9, NONE),
-+ PAD_NC(GPP_C10, NONE),
-+ PAD_NC(GPP_C11, NONE),
-+ PAD_NC(GPP_C12, NONE),
-+ PAD_NC(GPP_C13, NONE),
-+ PAD_NC(GPP_C14, NONE),
-+ PAD_NC(GPP_C15, NONE),
-+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
-+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
-+ PAD_NC(GPP_C18, NONE),
-+ PAD_NC(GPP_C19, NONE),
-+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
-+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
-+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
-+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
-+
-+ /* ------- GPIO Group GPP_D ------- */
-+ PAD_NC(GPP_D0, NONE),
-+ PAD_NC(GPP_D1, NONE),
-+ PAD_NC(GPP_D2, NONE),
-+ PAD_NC(GPP_D3, NONE),
-+ PAD_NC(GPP_D4, NONE),
-+ PAD_NC(GPP_D5, NONE),
-+ PAD_NC(GPP_D6, NONE),
-+ PAD_NC(GPP_D7, NONE),
-+ PAD_NC(GPP_D8, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
-+ PAD_NC(GPP_D10, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
-+ PAD_NC(GPP_D13, NONE),
-+ PAD_NC(GPP_D14, NONE),
-+ PAD_NC(GPP_D15, NONE),
-+ PAD_NC(GPP_D16, NONE),
-+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
-+ PAD_NC(GPP_D18, NONE),
-+ PAD_NC(GPP_D19, NONE),
-+ PAD_NC(GPP_D20, NONE),
-+ PAD_NC(GPP_D21, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
-+ PAD_NC(GPP_D23, NONE),
-+
-+ /* ------- GPIO Group GPP_E ------- */
-+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
-+ PAD_NC(GPP_E1, NONE),
-+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
-+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
-+ PAD_NC(GPP_E5, NONE),
-+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
-+ PAD_NC(GPP_E7, NONE),
-+ PAD_NC(GPP_E8, NONE),
-+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
-+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
-+ PAD_NC(GPP_E11, NONE),
-+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
-+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
-+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
-+ PAD_NC(GPP_E15, NONE),
-+ PAD_NC(GPP_E16, NONE),
-+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
-+ PAD_NC(GPP_E18, NONE),
-+ PAD_CFG_GPO(GPP_E19, 0, DEEP),
-+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
-+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
-+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
-+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
-+
-+ /* ------- GPIO Community 2 ------- */
-+
-+ /* -------- GPIO Group GPD -------- */
-+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
-+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
-+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
-+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
-+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
-+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
-+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
-+ PAD_NC(GPD7, NONE),
-+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
-+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
-+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
-+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
-+
-+ /* ------- GPIO Community 3 ------- */
-+
-+ /* ------- GPIO Group GPP_F ------- */
-+ PAD_CFG_GPO(GPP_F0, 0, DEEP),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
-+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */
-+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
-+ PAD_NC(GPP_F5, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
-+ PAD_NC(GPP_F21, NONE),
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
-+
-+ /* ------- GPIO Group GPP_G ------- */
-+ PAD_NC(GPP_G0, NONE),
-+ PAD_NC(GPP_G1, NONE),
-+ PAD_NC(GPP_G2, NONE),
-+ PAD_NC(GPP_G3, NONE),
-+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
-+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
-+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
-+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
-+};
-+
-+void variant_config_gpios(void)
-+{
-+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
-new file mode 100644
-index 0000000000..b1d96c5a76
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
-@@ -0,0 +1,90 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+const u32 cim_verb_data[] = {
-+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
-+ 0x17aa2258, // Subsystem ID
-+ 11,
-+ AZALIA_SUBVENDOR(0, 0x17aa2258),
-+
-+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
-+ AZALIA_INTEGRATED,
-+ AZALIA_INTERNAL,
-+ AZALIA_MIC_IN,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_NO_JACK_PRESENCE_DETECT,
-+ 2, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
-+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
-+ AZALIA_INTEGRATED,
-+ AZALIA_INTERNAL,
-+ AZALIA_SPEAKER,
-+ AZALIA_OTHER_ANALOG,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_NO_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-+ AZALIA_MIC_IN,
-+ AZALIA_STEREO_MONO_1_8,
-+ AZALIA_BLACK,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 3, 0
-+ )),
-+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
-+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
-+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
-+ AZALIA_HP_OUT,
-+ AZALIA_STEREO_MONO_1_8,
-+ AZALIA_BLACK,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 15
-+ )),
-+
-+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
-+ 0x80860101, // Subsystem ID
-+ 4,
-+ AZALIA_SUBVENDOR(2, 0x80860101),
-+
-+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
-+ AZALIA_JACK,
-+ AZALIA_DIGITAL_DISPLAY,
-+ AZALIA_DIGITAL_OTHER_OUT,
-+ AZALIA_OTHER_DIGITAL,
-+ AZALIA_COLOR_UNKNOWN,
-+ AZALIA_JACK_PRESENCE_DETECT,
-+ 1, 0
-+ )),
-+};
-+
-+const u32 pc_beep_verbs[] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
-new file mode 100644
-index 0000000000..001e934b3a
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
-@@ -0,0 +1,44 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+static const struct pad_config memory_id_gpio_table[] = {
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
-+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
-+};
-+
-+void mainboard_memory_init_params(FSPM_UPD *mupd)
-+{
-+ int spd_idx;
-+ char spd_name[20];
-+ size_t spd_size;
-+
-+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
-+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */
-+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
-+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
-+
-+ /* Get SPD for soldered RAM SPD (CH A) */
-+ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
-+
-+ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
-+ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
-+ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
-+ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
-+ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size);
-+
-+ /* Get SPD for memory slot (CH B) */
-+ struct spd_block blk = { .addr_map = { [1] = 0x51, } };
-+ get_spd_smbus(&blk);
-+ dump_spd_info(&blk);
-+
-+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
-+}
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-new file mode 100644
-index 0000000000..d4afca20c4
---- /dev/null
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-@@ -0,0 +1,103 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+chip soc/intel/skylake
-+ device domain 0 on
-+ device ref south_xhci on
-+ register "usb2_ports" = "{
-+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on)
-+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A)
-+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot)
-+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C)
-+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera)
-+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB)
-+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB)
-+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam)
-+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader)
-+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel)
-+ }"
-+ register "usb3_ports" = "{
-+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on)
-+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A)
-+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader)
-+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C)
-+ }"
-+ end
-+
-+ device ref sata on
-+ # SATA_2 - Main M.2 SATA SSD
-+ register "SataPortsEnable[2]" = "1"
-+ register "SataPortsDevSlp[2]" = "1"
-+ end
-+
-+ # PCIe controller 1 - 1x2+2x1
-+ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0
-+ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1
-+ #
-+ # PCIe controller 2 - 2x1+1x2 (lane reversal)
-+ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8)
-+ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3
-+ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4
-+ #
-+ # PCIe controller 3 - 1x4 (lane reversal)
-+ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5
-+
-+ # dGPU - x2
-+ device ref pcie_rp1 on
-+ register "PcieRpEnable[0]" = "1"
-+ register "PcieRpClkReqSupport[0]" = "1"
-+ register "PcieRpClkReqNumber[0]" = "0"
-+ register "PcieRpClkSrcNumber[0]" = "0"
-+ register "PcieRpAdvancedErrorReporting[0]" = "1"
-+ register "PcieRpLtrEnable[0]" = "1"
-+ end
-+
-+ # M.2 WWAN - x1
-+ device ref pcie_rp4 on
-+ register "PcieRpEnable[3]" = "1"
-+ register "PcieRpClkReqSupport[3]" = "1"
-+ register "PcieRpClkReqNumber[3]" = "1"
-+ register "PcieRpClkSrcNumber[3]" = "1"
-+ register "PcieRpAdvancedErrorReporting[3]" = "1"
-+ register "PcieRpLtrEnable[3]" = "1"
-+ end
-+
-+ # Ethernet (clobbers RP8)
-+ device ref gbe on
-+ register "LanClkReqSupported" = "1"
-+ register "LanClkReqNumber" = "2"
-+ register "EnableLanLtr" = "1"
-+ register "EnableLanK1Off" = "1"
-+ end
-+
-+ # M.2 WLAN - x1
-+ device ref pcie_rp7 on
-+ register "PcieRpEnable[6]" = "1"
-+ register "PcieRpClkReqSupport[6]" = "1"
-+ register "PcieRpClkReqNumber[6]" = "3"
-+ register "PcieRpClkSrcNumber[6]" = "3"
-+ register "PcieRpAdvancedErrorReporting[6]" = "1"
-+ register "PcieRpLtrEnable[6]" = "1"
-+ end
-+
-+ # TB3 (Alpine Ridge LP) - x2
-+ device ref pcie_rp5 on
-+ register "PcieRpEnable[4]" = "1"
-+ register "PcieRpClkReqSupport[4]" = "1"
-+ register "PcieRpClkReqNumber[4]" = "4"
-+ register "PcieRpClkSrcNumber[4]" = "4"
-+ register "PcieRpAdvancedErrorReporting[4]" = "1"
-+ register "PcieRpLtrEnable[4]" = "1"
-+ register "PcieRpHotPlug[4]" = "1"
-+ end
-+
-+ # M.2 2280 SSD - x2
-+ device ref pcie_rp9 on
-+ register "PcieRpEnable[8]" = "1"
-+ register "PcieRpClkReqSupport[8]" = "1"
-+ register "PcieRpClkReqNumber[8]" = "5"
-+ register "PcieRpClkSrcNumber[8]" = "5"
-+ register "PcieRpAdvancedErrorReporting[8]" = "1"
-+ register "PcieRpLtrEnable[8]" = "1"
-+ end
-+ end
-+end
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e
-GIT binary patch
-literal 512
-zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD
-YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..df0f6e58b79286a4aeb690c5027adf7a1f5f668b
-GIT binary patch
-literal 512
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-Yx&j>hH(SqvWezd%<4`dwOs5b40B_I==>Px#
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..24f0d8992bc5244c62488da9633e4885f52f3e22
-GIT binary patch
-literal 512
-zcmY!ucy&~OfFg0G3Wp`)phiHWn5fv$6q
-PvjPw>z-1}5hGzN!nb#F$
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..59b6b9e78263c42aae367ab7d4a784d888f30efe
-GIT binary patch
-literal 512
-zcmY!ucy(6E*fVuXjUqlKwqu$iMg7pDLK
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..a2a64a5e1adada3fc00b2e4edc60c77e610881a9
-GIT binary patch
-literal 512
-zcmY!u<-XH%N8S?V-1R3%^a4B#wurhqmHql_HU=XnZ$x{Q&
-z*$Oh{IYWaWKO+-03?$Qx1CPkm2-nu217(^xhPas;8kw1RMCls2o4FbS#SI&DT;VDQ
-GCj$V){1T)9
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..a2a64a5e1adada3fc00b2e4edc60c77e610881a9
-GIT binary patch
-literal 512
-zcmY!u<-XH%N8S?V-1R3%^a4B#wurhqmHql_HU=XnZ$x{Q&
-z*$Oh{IYWaWKO+-03?$Qx1CPkm2-nu217(^xhPas;8kw1RMCls2o4FbS#SI&DT;VDQ
-GCj$V){1T)9
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
-GIT binary patch
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-NcmZQz7zHCa1ONg600961
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..5f23e86606094d3e5d2011db902ebd4a500bbffa
-GIT binary patch
-literal 512
-zcmY!u<-XHc140(BZf(&^dxD+@TSQ$QOn`kgpFo@WIT6
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-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..857da9c9828cdac842329f6cef4539283777268b
-GIT binary patch
-literal 512
-zcmY!uenuv07)YiW2Og2B5w5L42g)>Y3~@6xG%_>sh|)E7H}WzBiW@fQc)?W;
-GP6hy+m=i1j
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..b5b14cf2dfa06ae183b0379da4dc825129e1589f
-GIT binary patch
-literal 512
-zcmY!u;9+)EWZ+<6U|?oq29gXMJU@VRUS6IcN7)B11r7#Qh7a1tdLSuupuhlu3{YAD
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-HcmV?d00001
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-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..829f149547bc24859646c33d5926938d7a1b90cb
-GIT binary patch
-literal 512
-zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1tdLSuupuhlu3{YAD
-XT>%b$o8(ro%%OI594bbI=@bG0z{d&v
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
-GIT binary patch
-literal 512
-NcmZQz7zHCa1ONg600961
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..a64a5a93fb4aef4d5f63d79cb2582731b9ac5063
-GIT binary patch
-literal 512
-NcmZQz7zHCa1ONg600961
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..940f1e3cd8e5bd9ea32a82a14edcdcbc8132d8c7
-GIT binary patch
-literal 512
-zcmY!u<-XH%N8S?V-1R3%^a4B#wurjQW(9mG0U=XnZ$x{Q&
-z0UPq1A)%L_QJxwGl4(Y*BAFWD+8T7AOcTeDU_*B^6OSleBX=`bLy)jxgN`d)<=|uh
-E020*^DF6Tf
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..30c84410d417ef7afa8705c93cdb64a9f4e915a0
-GIT binary patch
-literal 512
-zcmY!uW!enxp}7)YiWinU~FgllWifig`TLxK(6%}hL^bdB7N9Ss$Lz^FmT39fQ*
-FG5`?&65ap+
-
-literal 0
-HcmV?d00001
-
---
-2.39.5
-
diff --git a/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch b/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
deleted file mode 100644
index eb9263b9..00000000
--- a/config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch
+++ /dev/null
@@ -1,708 +0,0 @@
-From 75cc0ea09234064318046624845b0afc5afb0ce5 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin
-Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 29/37] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
-
-Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
-Signed-off-by: Nicholas Chin
----
- src/mainboard/dell/optiplex_780/Kconfig | 40 ++++
- src/mainboard/dell/optiplex_780/Kconfig.name | 4 +
- src/mainboard/dell/optiplex_780/Makefile.mk | 10 +
- src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 +
- .../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++
- .../dell/optiplex_780/acpi/superio.asl | 18 ++
- .../dell/optiplex_780/board_info.txt | 6 +
- src/mainboard/dell/optiplex_780/cmos.default | 8 +
- src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++
- src/mainboard/dell/optiplex_780/cstates.c | 8 +
- src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++
- src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++
- .../dell/optiplex_780/gma-mainboard.ads | 16 ++
- .../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes
- .../optiplex_780/variants/780_mt/early_init.c | 12 ++
- .../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++
- .../optiplex_780/variants/780_mt/hda_verb.c | 26 +++
- .../variants/780_mt/overridetree.cb | 10 +
- 18 files changed, 530 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
- create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
- create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
- create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
- create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
- create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
- create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-new file mode 100644
-index 0000000000..2d06c75c9a
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -0,0 +1,40 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_COMMON
-+ def_bool n
-+ select BOARD_ROMSIZE_KB_8192
-+ select CPU_INTEL_SOCKET_LGA775
-+ select DRIVERS_I2C_CK505
-+ select HAVE_ACPI_RESUME
-+ select HAVE_ACPI_TABLES
-+ select HAVE_CMOS_DEFAULT
-+ select HAVE_OPTION_TABLE
-+ select INTEL_GMA_HAVE_VBT
-+ select MAINBOARD_HAS_LIBGFXINIT
-+ select MAINBOARD_USES_IFD_GBE_REGION
-+ select NORTHBRIDGE_INTEL_X4X
-+ select PCIEXP_ASPM
-+ select PCIEXP_CLK_PM
-+ select SOUTHBRIDGE_INTEL_I82801JX
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+ select BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+if BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+config VGA_BIOS_ID
-+ default "8086,2e22"
-+
-+config MAINBOARD_DIR
-+ default "dell/optiplex_780"
-+
-+config MAINBOARD_PART_NUMBER
-+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+config OVERRIDE_DEVICETREE
-+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+endif # BOARD_DELL_OPTIPLEX_780_COMMON
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
-new file mode 100644
-index 0000000000..db7f2e8fe3
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
-@@ -0,0 +1,4 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+ bool "OptiPlex 780 MT"
-diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
-new file mode 100644
-index 0000000000..d462995d75
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
-@@ -0,0 +1,10 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+ramstage-y += cstates.c
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
-+romstage-y += variants/$(VARIANT_DIR)/early_init.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-new file mode 100644
-index 0000000000..479296cb76
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-@@ -0,0 +1,5 @@
-+/* SPDX-License-Identifier: CC-PDDC */
-+
-+/* Please update the license if adding licensable material. */
-+
-+/* dummy */
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-new file mode 100644
-index 0000000000..b7588dcc41
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+/* This is board specific information:
-+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
-+ */
-+
-+If (PICM) {
-+ Return (Package() {
-+ /* PCI slot */
-+ Package() { 0x0001ffff, 0, 0, 0x14},
-+ Package() { 0x0001ffff, 1, 0, 0x15},
-+ Package() { 0x0001ffff, 2, 0, 0x16},
-+ Package() { 0x0001ffff, 3, 0, 0x17},
-+
-+ Package() { 0x0002ffff, 0, 0, 0x15},
-+ Package() { 0x0002ffff, 1, 0, 0x16},
-+ Package() { 0x0002ffff, 2, 0, 0x17},
-+ Package() { 0x0002ffff, 3, 0, 0x14},
-+ })
-+} Else {
-+ Return (Package() {
-+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
-+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
-+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
-+
-+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
-+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
-+ })
-+}
-diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-new file mode 100644
-index 0000000000..9f3900b86c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-@@ -0,0 +1,18 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#undef SUPERIO_DEV
-+#undef SUPERIO_PNP_BASE
-+#undef IT8720F_SHOW_SP1
-+#undef IT8720F_SHOW_SP2
-+#undef IT8720F_SHOW_EC
-+#undef IT8720F_SHOW_KBCK
-+#undef IT8720F_SHOW_KBCM
-+#undef IT8720F_SHOW_GPIO
-+#undef IT8720F_SHOW_CIR
-+#define SUPERIO_DEV SIO0
-+#define SUPERIO_PNP_BASE 0x2e
-+#define IT8720F_SHOW_EC 1
-+#define IT8720F_SHOW_KBCK 1
-+#define IT8720F_SHOW_KBCM 1
-+#define IT8720F_SHOW_GPIO 1
-+#include
-diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
-new file mode 100644
-index 0000000000..aaf657b583
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: desktop
-+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
-new file mode 100644
-index 0000000000..23f0e55f3e
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.default
-@@ -0,0 +1,8 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+sata_mode=AHCI
-+gfx_uma_size=64M
-diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
-new file mode 100644
-index 0000000000..9f5012adb4
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.layout
-@@ -0,0 +1,72 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0 120 r 0 reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384 1 e 4 boot_option
-+388 4 h 0 reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395 4 e 6 debug_level
-+
-+# coreboot config options: southbridge
-+408 1 e 10 sata_mode
-+409 2 e 7 power_on_after_fail
-+411 1 e 1 nmi
-+
-+# coreboot config options: cpu
-+
-+# coreboot config options: northbridge
-+432 4 e 11 gfx_uma_size
-+
-+# coreboot config options: check sums
-+984 16 h 0 check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value text
-+1 0 Disable
-+1 1 Enable
-+2 0 Enable
-+2 1 Disable
-+4 0 Fallback
-+4 1 Normal
-+6 0 Emergency
-+6 1 Alert
-+6 2 Critical
-+6 3 Error
-+6 4 Warning
-+6 5 Notice
-+6 6 Info
-+6 7 Debug
-+6 8 Spew
-+7 0 Disable
-+7 1 Enable
-+7 2 Keep
-+10 0 AHCI
-+10 1 Compatible
-+11 1 4M
-+11 2 8M
-+11 3 16M
-+11 4 32M
-+11 5 48M
-+11 6 64M
-+11 7 128M
-+11 8 256M
-+11 9 96M
-+11 10 160M
-+11 11 224M
-+11 12 352M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 983 984
-diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
-new file mode 100644
-index 0000000000..4adf0edc63
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cstates.c
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include
-+
-+int get_cst_entries(const acpi_cstate_t **entries)
-+{
-+ return 0;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
-new file mode 100644
-index 0000000000..95e3bd517c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
-@@ -0,0 +1,63 @@
-+# SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
-+ device domain 0 on
-+ ops x4x_pci_domain_ops # PCI domain
-+ subsystemid 0x8086 0x0028 inherit
-+ device pci 0.0 on end # Host Bridge
-+ device pci 1.0 on end # PCIe x16 2.0 slot
-+ device pci 2.0 on end # Integrated graphics controller
-+ device pci 2.1 on end # Integrated graphics controller 2
-+ device pci 3.0 off end # ME
-+ device pci 3.1 off end # ME
-+ chip southbridge/intel/i82801jx # ICH10
-+ register "gpe0_en" = "0x40"
-+
-+ # Set AHCI mode.
-+ register "sata_port_map" = "0x3f"
-+ register "sata_clock_request" = "1"
-+
-+ # Enable PCIe ports 0,1 as slots.
-+ register "pcie_slot_implemented" = "0x3"
-+
-+ device pci 19.0 on end # GBE
-+ device pci 1a.0 on end # USB
-+ device pci 1a.1 on end # USB
-+ device pci 1a.2 on end # USB
-+ device pci 1a.7 on end # USB
-+ device pci 1b.0 on end # Audio
-+ device pci 1c.0 off end # PCIe 1
-+ device pci 1c.1 off end # PCIe 2
-+ device pci 1c.2 off end # PCIe 3
-+ device pci 1c.3 off end # PCIe 4
-+ device pci 1c.4 off end # PCIe 5
-+ device pci 1c.5 off end # PCIe 6
-+ device pci 1d.0 on end # USB
-+ device pci 1d.1 on end # USB
-+ device pci 1d.2 on end # USB
-+ device pci 1d.7 on end # USB
-+ device pci 1e.0 on end # PCI bridge
-+ device pci 1f.0 on end # LPC bridge
-+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
-+ device pci 1f.3 on # SMBus
-+ chip drivers/i2c/ck505 # IDT CV194
-+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
-+ 0xff, 0xff, 0xff, 0xff,
-+ 0xff, 0xff, 0xff, 0xff,
-+ 0xff, 0xff, 0xff, 0xff,
-+ 0xff, 0xff, 0xff }"
-+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
-+ 0xff, 0x00, 0x00, 0x95,
-+ 0x00, 0x65, 0x7d, 0x56,
-+ 0x13, 0xc0, 0x00, 0x07,
-+ 0x01, 0x0a, 0x64 }"
-+ device i2c 69 on end
-+ end
-+ end
-+ device pci 1f.4 off end
-+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
-+ device pci 1f.6 off end # Thermal Subsystem
-+ end
-+ end
-+end
-diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
-new file mode 100644
-index 0000000000..9ad70469de
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include