From db074b785ccbca67bf3de54ac4414fb72f1cdf8f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 27 Feb 2024 18:52:31 +0000 Subject: [PATCH 0001/1319] enable serial console on fam15h boards Signed-off-by: Leah Rowe --- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../kfsn4-dre_1mb/config/libgfxinit_txtmode | 36 +++++++++++++++---- .../kfsn4-dre_2mb/config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- .../config/libgfxinit_txtmode | 36 +++++++++++++++---- 10 files changed, 290 insertions(+), 70 deletions(-) diff --git a/config/coreboot/kcma-d8-rdimm_16mb/config/libgfxinit_txtmode b/config/coreboot/kcma-d8-rdimm_16mb/config/libgfxinit_txtmode index e5c58008..39cfe811 100644 --- a/config/coreboot/kcma-d8-rdimm_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/kcma-d8-rdimm_16mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kcma-d8" CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x1000000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,10 +153,11 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -220,6 +222,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -468,6 +471,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -559,29 +564,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -651,6 +672,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kcma-d8-rdimm_2mb/config/libgfxinit_txtmode b/config/coreboot/kcma-d8-rdimm_2mb/config/libgfxinit_txtmode index 19da9a2c..7949bcfd 100644 --- a/config/coreboot/kcma-d8-rdimm_2mb/config/libgfxinit_txtmode +++ b/config/coreboot/kcma-d8-rdimm_2mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kcma-d8" CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,10 +153,11 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -220,6 +222,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -468,6 +471,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -559,29 +564,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -651,6 +672,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kcma-d8-udimm_16mb/config/libgfxinit_txtmode b/config/coreboot/kcma-d8-udimm_16mb/config/libgfxinit_txtmode index e5c58008..39cfe811 100644 --- a/config/coreboot/kcma-d8-udimm_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/kcma-d8-udimm_16mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kcma-d8" CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x1000000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,10 +153,11 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -220,6 +222,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -468,6 +471,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -559,29 +564,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -651,6 +672,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kcma-d8-udimm_2mb/config/libgfxinit_txtmode b/config/coreboot/kcma-d8-udimm_2mb/config/libgfxinit_txtmode index 19da9a2c..7949bcfd 100644 --- a/config/coreboot/kcma-d8-udimm_2mb/config/libgfxinit_txtmode +++ b/config/coreboot/kcma-d8-udimm_2mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kcma-d8" CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,10 +153,11 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -220,6 +222,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -468,6 +471,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -559,29 +564,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -651,6 +672,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kfsn4-dre_1mb/config/libgfxinit_txtmode b/config/coreboot/kfsn4-dre_1mb/config/libgfxinit_txtmode index 32d61412..b538c0f9 100644 --- a/config/coreboot/kfsn4-dre_1mb/config/libgfxinit_txtmode +++ b/config/coreboot/kfsn4-dre_1mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kfsn4-dre" CONFIG_MAINBOARD_PART_NUMBER="KFSN4-DRE" CONFIG_MAX_CPUS=12 CONFIG_CBFS_SIZE=0x100000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -150,10 +151,11 @@ CONFIG_FMDFILE="" CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_POST_DEVICE=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -216,6 +218,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0xfa CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -450,6 +453,8 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_SPI_FLASH is not set # CONFIG_SPI_SDCARD is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -541,29 +546,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set @@ -633,6 +654,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kfsn4-dre_2mb/config/libgfxinit_txtmode b/config/coreboot/kfsn4-dre_2mb/config/libgfxinit_txtmode index 6c7cc560..a5329039 100644 --- a/config/coreboot/kfsn4-dre_2mb/config/libgfxinit_txtmode +++ b/config/coreboot/kfsn4-dre_2mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kfsn4-dre" CONFIG_MAINBOARD_PART_NUMBER="KFSN4-DRE" CONFIG_MAX_CPUS=12 CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -150,10 +151,11 @@ CONFIG_FMDFILE="" CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_POST_DEVICE=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set @@ -216,6 +218,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0xfa CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -450,6 +453,8 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_SPI_FLASH is not set # CONFIG_SPI_SDCARD is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -541,29 +546,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set @@ -633,6 +654,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kgpe-d16-rdimm_16mb/config/libgfxinit_txtmode b/config/coreboot/kgpe-d16-rdimm_16mb/config/libgfxinit_txtmode index 765025d2..c29a71f8 100644 --- a/config/coreboot/kgpe-d16-rdimm_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/kgpe-d16-rdimm_16mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_MAX_CPUS=32 CONFIG_CBFS_SIZE=0x1000000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,11 +153,12 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_IPMI_KCS_REGISTER_SPACING=1 CONFIG_IPMI_FRU_SINGLE_RW_SZ=16 @@ -223,6 +225,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -472,6 +475,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -567,29 +572,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -659,6 +680,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kgpe-d16-rdimm_2mb/config/libgfxinit_txtmode b/config/coreboot/kgpe-d16-rdimm_2mb/config/libgfxinit_txtmode index c203474a..060966a5 100644 --- a/config/coreboot/kgpe-d16-rdimm_2mb/config/libgfxinit_txtmode +++ b/config/coreboot/kgpe-d16-rdimm_2mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_MAX_CPUS=32 CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,11 +153,12 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_IPMI_KCS_REGISTER_SPACING=1 CONFIG_IPMI_FRU_SINGLE_RW_SZ=16 @@ -223,6 +225,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -472,6 +475,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -567,29 +572,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -659,6 +680,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kgpe-d16-udimm_16mb/config/libgfxinit_txtmode b/config/coreboot/kgpe-d16-udimm_16mb/config/libgfxinit_txtmode index 765025d2..c29a71f8 100644 --- a/config/coreboot/kgpe-d16-udimm_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/kgpe-d16-udimm_16mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_MAX_CPUS=32 CONFIG_CBFS_SIZE=0x1000000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,11 +153,12 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_IPMI_KCS_REGISTER_SPACING=1 CONFIG_IPMI_FRU_SINGLE_RW_SZ=16 @@ -223,6 +225,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -472,6 +475,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -567,29 +572,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -659,6 +680,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y diff --git a/config/coreboot/kgpe-d16-udimm_2mb/config/libgfxinit_txtmode b/config/coreboot/kgpe-d16-udimm_2mb/config/libgfxinit_txtmode index c203474a..060966a5 100644 --- a/config/coreboot/kgpe-d16-udimm_2mb/config/libgfxinit_txtmode +++ b/config/coreboot/kgpe-d16-udimm_2mb/config/libgfxinit_txtmode @@ -91,6 +91,7 @@ CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_MAX_CPUS=32 CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 CONFIG_MAINBOARD_VENDOR="ASUS" CONFIG_APIC_ID_OFFSET=0x0 CONFIG_HW_MEM_HOLE_SIZEK=0x100000 @@ -152,11 +153,12 @@ CONFIG_POST_DEVICE=y CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_DRIVERS_INTEL_WIFI is not set -# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_DIMM_MAX=4 CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_USBDEBUG is not set CONFIG_IPMI_KCS_REGISTER_SPACING=1 CONFIG_IPMI_FRU_SINGLE_RW_SZ=16 @@ -223,6 +225,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 CONFIG_HPET_MIN_TICKS=0x14 CONFIG_UART_PCI_ADDR=0x0 # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -472,6 +475,8 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -567,29 +572,45 @@ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # Console # CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HWBASE_DEBUG_CB is not set -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y @@ -659,6 +680,7 @@ CONFIG_HAVE_DEBUG_CAR=y # # General Debug Settings # +# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y From 944cafa2306c1cd519c1599d249ae81b237fdfda Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 22:55:29 +0000 Subject: [PATCH 0002/1319] coreboot/haswell: make IOMMU a runtime option It is now possible to disable the IOMMU on Haswell boards, by doing this on your ROM image: ./nvramtool -C libreboot.rom -w iommu=Disable To enable it again, do this: ./nvramtool -C libreboot.rom -w iommu=Enable If not specified, the default behaviour is *on*. A follow-up patch will turn IOMMU *off* by default, on Dell OptiPlex 9020 SFF/MT, by setting it as such in cmos.default. This is to make graphics cards work properly to work around a bug when it's turned on. Leaving the IOMMU enabled is recommended, if it works. It works in most cases, including on 9020 SFF/MT when using the Intel GPU without a graphics card inserted. Signed-off-by: Leah Rowe --- ...-haswell-make-IOMMU-a-runtime-option.patch | 292 ++++++++++++++++++ 1 file changed, 292 insertions(+) create mode 100644 config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch diff --git a/config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch new file mode 100644 index 00000000..8401e8b8 --- /dev/null +++ b/config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -0,0 +1,292 @@ +From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 22:51:09 +0000 +Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option + +When I tested graphics cards on a coreboot port for Dell +OptiPlex 9020 SFF, I could not use a graphics card unless +I set iommu=off on the Linux cmdline. + +Coreboot's current behaviour is to check whether the CPU +has vt-d support and, if it does, initialise the IOMMU. + +This patch maintains the current behaviour by default, but +allows the user to turn *off* the IOMMU, even if vt-d is +supported by the host CPU. + +If iommu=Disable is specified, the check will not be +performed, and the IOMMU will be left disabled. This option +has been added to all current Haswell boards, though it is +recommended to leave the IOMMU turned on in most setups. + +Signed-off-by: Leah Rowe +--- + src/mainboard/asrock/b85m_pro4/cmos.default | 1 + + src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ + src/mainboard/asrock/h81m-hds/cmos.default | 1 + + src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ + src/mainboard/google/beltino/cmos.layout | 5 +++++ + src/mainboard/google/slippy/cmos.layout | 5 +++++ + src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ + src/mainboard/lenovo/haswell/cmos.default | 1 + + src/mainboard/lenovo/haswell/cmos.layout | 3 +++ + src/mainboard/supermicro/x10slm-f/cmos.default | 1 + + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ + src/northbridge/intel/haswell/early_init.c | 5 +++++ + 14 files changed, 48 insertions(+) + +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default +index c51001c03c..1c5c17f841 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.default ++++ b/src/mainboard/asrock/b85m_pro4/cmos.default +@@ -2,3 +2,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout +index efdc333fc2..c9883ea71d 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.layout ++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout +@@ -11,6 +11,7 @@ + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail ++ 412 1 e 6 iommu + 984 16 h 0 check_sum + # ----------------------------------------------------------------- + +@@ -38,6 +39,8 @@ + 5 0 Disable + 5 1 Enable + 5 2 Keep ++ 6 0 Disable ++ 6 1 Enable + # ----------------------------------------------------------------- + + # ----------------------------------------------------------------- +diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default +index c51001c03c..1c5c17f841 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.default ++++ b/src/mainboard/asrock/h81m-hds/cmos.default +@@ -2,3 +2,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout +index c9ba76c78f..95ee3d36fb 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.layout ++++ b/src/mainboard/asrock/h81m-hds/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index b159660aa8..8253570f19 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -2,3 +2,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index c9ba76c78f..72ff9c4bee 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# turn iommu on or off ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/beltino/cmos.layout ++++ b/src/mainboard/google/beltino/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/slippy/cmos.layout ++++ b/src/mainboard/google/slippy/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout +index 78d44c1415..f2c602f541 100644 +--- a/src/mainboard/intel/baskingridge/cmos.layout ++++ b/src/mainboard/intel/baskingridge/cmos.layout +@@ -19,6 +19,8 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +49,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default +index bb8626d48b..051658d757 100644 +--- a/src/mainboard/lenovo/haswell/cmos.default ++++ b/src/mainboard/lenovo/haswell/cmos.default +@@ -12,3 +12,4 @@ trackpoint=Enable + backlight=Keyboard + enable_dual_graphics=Disable + usb_always_on=Disable ++iommu=Enable +diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout +index 27915d3ab7..59df76b64c 100644 +--- a/src/mainboard/lenovo/haswell/cmos.layout ++++ b/src/mainboard/lenovo/haswell/cmos.layout +@@ -23,6 +23,7 @@ entries + + # coreboot config options: EC + 411 1 e 8 first_battery ++413 1 e 14 iommu + 415 1 e 1 wlan + 416 1 e 1 trackpoint + 417 1 e 1 fn_ctrl_swap +@@ -72,6 +73,8 @@ enumerations + 13 0 Disable + 13 1 AC and battery + 13 2 AC only ++14 0 Disable ++14 1 Enable + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default +index f4047147f7..eea2c36b88 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.default ++++ b/src/mainboard/supermicro/x10slm-f/cmos.default +@@ -3,3 +3,4 @@ debug_level=Debug + nmi=Enable + power_on_after_fail=Keep + hide_ast2400=Disable ++iommu=Enable +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout +index 38ba87aa45..24d39e97ee 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.layout ++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: mainboard + 416 1 e 1 hide_ast2400 + +@@ -55,6 +58,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index e47deb5da6..1a7e0b1076 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + + #include "haswell.h" + +@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) + static void haswell_setup_iommu(void) + { + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ u8 enable_iommu = get_uint_option("iommu", 1); ++ ++ if (!enable_iommu) ++ return; + + if (capid0_a & VTD_DISABLE) + return; +-- +2.39.2 + From 665840b2b9b296fe50fe4fa78b4ffda072c1033b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 2 Mar 2024 23:02:52 +0000 Subject: [PATCH 0003/1319] coreboot/dell9020*_12mb: Disable IOMMU by default Needed to make graphics cards work. Turn it on if you're using only the Intel GPU. With IOMMU *enabled*, graphics cards do not work reliably at all. The cause still needs to be investigated, but the symptoms are graphical corruption on the screen, and Xorg usually crashes. In some cases (on some cards), TTYs can still be used; the payload can still be used reliably, on a graphics card, but Xorg fails to work properly. This could be a bug in Linux drivers, instead of anything that coreboot does (not yet tested in factory BIOS). Leaving it off by default will ensure reliable operation on all setups, whether an iGPU or dGPU is used. Signed-off-by: Leah Rowe --- ...tiplex_9020-Disable-IOMMU-by-default.patch | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch diff --git a/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch new file mode 100644 index 00000000..c8cde72e --- /dev/null +++ b/config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -0,0 +1,29 @@ +From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 23:00:09 +0000 +Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default + +Needed to make graphics cards work. Turning it on is +recommended if only using iGPU, otherwise leave it off +by default. The IOMMU is extremely buggy when a graphics +card is used. Leaving it off by default will ensure that +the default ROM images in Libreboot will work on any setup. + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_9020/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index 8253570f19..7bccc80e51 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -2,4 +2,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable +-iommu=Enable ++iommu=Disable +-- +2.39.2 + From 036bf2c69a64c7a3bfdcfde3139ae2285e790a5b Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Mon, 4 Mar 2024 18:17:21 -0700 Subject: [PATCH 0004/1319] config: Add Dell Latitude E5420 Signed-off-by: Nicholas Chin --- ...dell-Add-Latitude-E5420-Sandy-Bridge.patch | 774 ++++++++++++++++++ .../config/libgfxinit_corebootfb | 1 + .../dell9020mt_12mb/config/libgfxinit_txtmode | 1 + .../config/libgfxinit_corebootfb | 1 + .../config/libgfxinit_txtmode | 1 + .../e5420_6mb/config/libgfxinit_corebootfb | 620 ++++++++++++++ .../e5420_6mb/config/libgfxinit_txtmode | 617 ++++++++++++++ config/coreboot/e5420_6mb/target.cfg | 11 + .../e5520_6mb/config/libgfxinit_corebootfb | 1 + .../e5520_6mb/config/libgfxinit_txtmode | 1 + .../e5530_12mb/config/libgfxinit_corebootfb | 1 + .../e5530_12mb/config/libgfxinit_txtmode | 1 + .../e6420_10mb/config/libgfxinit_corebootfb | 1 + .../e6420_10mb/config/libgfxinit_txtmode | 1 + .../e6430_12mb/config/libgfxinit_corebootfb | 1 + .../e6430_12mb/config/libgfxinit_txtmode | 1 + .../e6520_10mb/config/libgfxinit_corebootfb | 1 + .../e6520_10mb/config/libgfxinit_txtmode | 1 + .../e6530_12mb/config/libgfxinit_corebootfb | 1 + .../e6530_12mb/config/libgfxinit_txtmode | 1 + .../t1650_12mb/config/libgfxinit_txtmode | 1 + config/vendor/sources | 2 +- 22 files changed, 2040 insertions(+), 1 deletion(-) create mode 100644 config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch create mode 100644 config/coreboot/e5420_6mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/e5420_6mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/e5420_6mb/target.cfg diff --git a/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch b/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch new file mode 100644 index 00000000..11f95a63 --- /dev/null +++ b/config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch @@ -0,0 +1,774 @@ +From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Mon, 4 Mar 2024 18:05:43 -0700 +Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge) + +--- + src/mainboard/dell/e5420/Kconfig | 37 ++++ + src/mainboard/dell/e5420/Kconfig.name | 2 + + src/mainboard/dell/e5420/Makefile.mk | 5 + + src/mainboard/dell/e5420/acpi/ec.asl | 9 + + src/mainboard/dell/e5420/acpi/platform.asl | 12 ++ + src/mainboard/dell/e5420/acpi/superio.asl | 3 + + src/mainboard/dell/e5420/acpi_tables.c | 16 ++ + src/mainboard/dell/e5420/board_info.txt | 6 + + src/mainboard/dell/e5420/cmos.default | 9 + + src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++ + src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes + src/mainboard/dell/e5420/devicetree.cb | 66 +++++++ + src/mainboard/dell/e5420/dsdt.asl | 30 ++++ + src/mainboard/dell/e5420/early_init.c | 32 ++++ + src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++ + src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++ + src/mainboard/dell/e5420/hda_verb.c | 33 ++++ + src/mainboard/dell/e5420/mainboard.c | 21 +++ + 18 files changed, 584 insertions(+) + create mode 100644 src/mainboard/dell/e5420/Kconfig + create mode 100644 src/mainboard/dell/e5420/Kconfig.name + create mode 100644 src/mainboard/dell/e5420/Makefile.mk + create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl + create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl + create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl + create mode 100644 src/mainboard/dell/e5420/acpi_tables.c + create mode 100644 src/mainboard/dell/e5420/board_info.txt + create mode 100644 src/mainboard/dell/e5420/cmos.default + create mode 100644 src/mainboard/dell/e5420/cmos.layout + create mode 100755 src/mainboard/dell/e5420/data.vbt + create mode 100644 src/mainboard/dell/e5420/devicetree.cb + create mode 100644 src/mainboard/dell/e5420/dsdt.asl + create mode 100644 src/mainboard/dell/e5420/early_init.c + create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads + create mode 100644 src/mainboard/dell/e5420/gpio.c + create mode 100644 src/mainboard/dell/e5420/hda_verb.c + create mode 100644 src/mainboard/dell/e5420/mainboard.c + +diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig +new file mode 100644 +index 0000000000..f4385045ae +--- /dev/null ++++ b/src/mainboard/dell/e5420/Kconfig +@@ -0,0 +1,37 @@ ++if BOARD_DELL_LATITUDE_E5420 ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ select BOARD_ROMSIZE_KB_6144 ++ select EC_ACPI ++ select EC_DELL_MEC5035 ++ select GFX_GMA_PANEL_1_ON_LVDS ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_CMOS_DEFAULT ++ select HAVE_OPTION_TABLE ++ select INTEL_GMA_HAVE_VBT ++ select INTEL_INT15 ++ select MAINBOARD_HAS_LIBGFXINIT ++ select NORTHBRIDGE_INTEL_SANDYBRIDGE ++ select SERIRQ_CONTINUOUS_MODE ++ select SOUTHBRIDGE_INTEL_BD82X6X ++ select SYSTEM_TYPE_LAPTOP ++ select USE_NATIVE_RAMINIT ++ ++config DRAM_RESET_GATE_GPIO ++ default 60 ++ ++config MAINBOARD_DIR ++ default "dell/e5420" ++ ++config MAINBOARD_PART_NUMBER ++ default "Latitude E5420" ++ ++config USBDEBUG_HCD_INDEX ++ default 2 ++ ++config VGA_BIOS_ID ++ default "8086,0116" ++ ++endif # BOARD_DELL_LATITUDE_E5420 +diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name +new file mode 100644 +index 0000000000..eb495fb705 +--- /dev/null ++++ b/src/mainboard/dell/e5420/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_DELL_LATITUDE_E5420 ++ bool "Latitude E5420" +diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk +new file mode 100644 +index 0000000000..18391d8b18 +--- /dev/null ++++ b/src/mainboard/dell/e5420/Makefile.mk +@@ -0,0 +1,5 @@ ++bootblock-y += early_init.c ++bootblock-y += gpio.c ++romstage-y += early_init.c ++romstage-y += gpio.c ++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl +new file mode 100644 +index 0000000000..0d429410a9 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/ec.asl +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Device(EC) ++{ ++ Name (_HID, EISAID("PNP0C09")) ++ Name (_UID, 0) ++ Name (_GPE, 16) ++/* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl +new file mode 100644 +index 0000000000..2d24bbd9b9 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/platform.asl +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++Method(_WAK, 1) ++{ ++ /* FIXME: EC support */ ++ Return(Package() {0, 0}) ++} ++ ++Method(_PTS,1) ++{ ++ /* FIXME: EC support */ ++} +diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl +new file mode 100644 +index 0000000000..55b1db5b11 +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi/superio.asl +@@ -0,0 +1,3 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include +diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c +new file mode 100644 +index 0000000000..e2759659bf +--- /dev/null ++++ b/src/mainboard/dell/e5420/acpi_tables.c +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++/* FIXME: check this function. */ ++void mainboard_fill_gnvs(struct global_nvs *gnvs) ++{ ++ /* The lid is open by default. */ ++ gnvs->lids = 1; ++ ++ /* Temperature at which OS will shutdown */ ++ gnvs->tcrt = 100; ++ /* Temperature at which OS will throttle CPU */ ++ gnvs->tpsv = 90; ++} +diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt +new file mode 100644 +index 0000000000..34d5ad9e0b +--- /dev/null ++++ b/src/mainboard/dell/e5420/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y ++Release year: 2011 +diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default +new file mode 100644 +index 0000000000..279415dfd1 +--- /dev/null ++++ b/src/mainboard/dell/e5420/cmos.default +@@ -0,0 +1,9 @@ ++boot_option=Fallback ++debug_level=Debug ++power_on_after_fail=Disable ++nmi=Enable ++bluetooth=Enable ++wwan=Enable ++wlan=Enable ++sata_mode=AHCI ++me_state=Disabled +diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout +new file mode 100644 +index 0000000000..1aa7e77bce +--- /dev/null ++++ b/src/mainboard/dell/e5420/cmos.layout +@@ -0,0 +1,88 @@ ++## SPDX-License-Identifier: GPL-2.0-only ++ ++# ----------------------------------------------------------------- ++entries ++ ++# ----------------------------------------------------------------- ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++ ++#400 8 r 0 reserved for century byte ++ ++# coreboot config options: southbridge ++408 1 e 1 nmi ++409 2 e 7 power_on_after_fail ++411 1 e 9 sata_mode ++ ++# coreboot config options: EC ++412 1 e 1 bluetooth ++413 1 e 1 wwan ++414 1 e 1 wlan ++ ++# coreboot config options: ME ++424 1 e 14 me_state ++425 2 h 0 me_state_prev ++ ++# coreboot config options: northbridge ++432 3 e 11 gfx_uma_size ++435 2 e 12 hybrid_graphics_mode ++440 8 h 0 volume ++ ++# VBOOT ++448 128 r 0 vbnv ++ ++# SandyBridge MRC Scrambler Seed values ++896 32 r 0 mrc_scrambler_seed ++928 32 r 0 mrc_scrambler_seed_s3 ++960 16 r 0 mrc_scrambler_seed_chk ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++9 0 AHCI ++9 1 Compatible ++11 0 32M ++11 1 64M ++11 2 96M ++11 3 128M ++11 4 160M ++11 5 192M ++11 6 224M ++14 0 Normal ++14 1 Disabled ++ ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 447 984 +diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt +new file mode 100755 +index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57 +GIT binary patch +literal 6144 +zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H +zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q +z^SfW?+;h)4_uO+|XEfEV$91)}c;!*XQ5O +z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt +zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(Ke?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY +z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_DV +zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf +zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ +zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K*}ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu +zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F +z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75 +z4f0oz(xQ3MWqz5>qW5M4tZWExHs8X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l +znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV +zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b +zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO +zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP +zG5R*k=);S}ZnA}on(uzNF +zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et +z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#( +z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T +zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p? +z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1 +ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O +zAJ@bxp2>n}u*mUIYFd>}O_wuwBD^r9<#=!0 +X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb +new file mode 100644 +index 0000000000..f26413557d +--- /dev/null ++++ b/src/mainboard/dell/e5420/devicetree.cb +@@ -0,0 +1,66 @@ ++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. ++ register "gfx" = "GMA_STATIC_DISPLAYS(1)" ++ register "gpu_cpu_backlight" = "0x00000c31" ++ register "gpu_dp_b_hotplug" = "4" ++ register "gpu_dp_c_hotplug" = "4" ++ register "gpu_dp_d_hotplug" = "4" ++ register "gpu_panel_port_select" = "0" ++ register "gpu_panel_power_backlight_off_delay" = "2300" ++ register "gpu_panel_power_backlight_on_delay" = "2300" ++ register "gpu_panel_power_cycle_delay" = "6" ++ register "gpu_panel_power_down_delay" = "400" ++ register "gpu_panel_power_up_delay" = "400" ++ register "gpu_pch_backlight" = "0x13121312" ++ ++ register "spd_addresses" = "{0x50, 0, 0x52, 0}" ++ ++ device domain 0x0 on ++ subsystemid 0x1028 0x049b inherit ++ ++ device ref host_bridge on end # Host bridge ++ device ref peg10 on end # PEG ++ device ref igd on end # iGPU ++ ++ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH ++ register "docking_supported" = "1" ++ register "gen1_dec" = "0x007c0681" ++ register "gen2_dec" = "0x007c0901" ++ register "gen3_dec" = "0x003c07e1" ++ register "gen4_dec" = "0x001c0901" ++ register "gpi0_routing" = "2" ++ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" ++ register "pcie_port_coalesce" = "1" ++ register "sata_interface_speed_support" = "0x3" ++ register "sata_port_map" = "0x3b" ++ register "spi_lvscc" = "0x2005" ++ register "spi_uvscc" = "0x2005" ++ ++ device ref mei1 off end ++ device ref mei2 off end ++ device ref me_ide_r off end ++ device ref me_kt off end ++ device ref gbe off end ++ device ref ehci2 on end ++ device ref hda on end ++ device ref pcie_rp1 on end ++ device ref pcie_rp2 on end ++ device ref pcie_rp3 on end ++ device ref pcie_rp4 off end ++ device ref pcie_rp5 on end ++ device ref pcie_rp6 on end ++ device ref pcie_rp7 on end ++ device ref pcie_rp8 off end ++ device ref ehci1 on end ++ device ref pci_bridge off end ++ device ref lpc on ++ chip ec/dell/mec5035 ++ device pnp ff.0 on end ++ end ++ end ++ device ref sata1 on end ++ device ref smbus on end ++ device ref sata2 off end ++ device ref thermal off end ++ end ++ end ++end +diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl +new file mode 100644 +index 0000000000..7d13c55b08 +--- /dev/null ++++ b/src/mainboard/dell/e5420/dsdt.asl +@@ -0,0 +1,30 @@ ++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB ++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include ++ ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ ACPI_DSDT_REV_2, ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20141018 /* OEM revision */ ++) ++{ ++ #include ++ #include "acpi/platform.asl" ++ #include ++ #include ++ #include ++ #include ++ ++ Device (\_SB.PCI0) ++ { ++ #include ++ #include ++ #include ++ } ++} +diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c +new file mode 100644 +index 0000000000..7297921546 +--- /dev/null ++++ b/src/mainboard/dell/e5420/early_init.c +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++ ++#include ++#include ++#include ++#include ++ ++const struct southbridge_usb_port mainboard_usb_ports[] = { ++ { 1, 1, 0 }, ++ { 1, 1, 0 }, ++ { 1, 1, 1 }, ++ { 1, 1, 1 }, ++ { 1, 1, 2 }, ++ { 1, 1, 2 }, ++ { 1, 1, 3 }, ++ { 1, 1, 3 }, ++ { 1, 1, 5 }, ++ { 1, 1, 5 }, ++ { 1, 1, 7 }, ++ { 1, 1, 6 }, ++ { 1, 1, 6 }, ++ { 1, 1, 7 }, ++}; ++ ++void bootblock_mainboard_early_init(void) ++{ ++ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN ++ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN ++ | COMB_LPC_EN | COMA_LPC_EN); ++ mec5035_early_init(); ++} +diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads +new file mode 100644 +index 0000000000..2a16f44360 +--- /dev/null ++++ b/src/mainboard/dell/e5420/gma-mainboard.ads +@@ -0,0 +1,20 @@ ++-- SPDX-License-Identifier: GPL-2.0-or-later ++ ++with HW.GFX.GMA; ++with HW.GFX.GMA.Display_Probing; ++ ++use HW.GFX.GMA; ++use HW.GFX.GMA.Display_Probing; ++ ++private package GMA.Mainboard is ++ ++ ports : constant Port_List := ++ ( ++ HDMI1, -- mainboard HDMI ++ DP2, -- dock DP ++ DP3, -- dock DP ++ Analog, -- mainboard VGA ++ LVDS, ++ others => Disabled); ++ ++end GMA.Mainboard; +diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c +new file mode 100644 +index 0000000000..f76b93d9f0 +--- /dev/null ++++ b/src/mainboard/dell/e5420/gpio.c +@@ -0,0 +1,195 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++static const struct pch_gpio_set1 pch_gpio_set1_mode = { ++ .gpio0 = GPIO_MODE_GPIO, ++ .gpio1 = GPIO_MODE_NATIVE, ++ .gpio2 = GPIO_MODE_GPIO, ++ .gpio3 = GPIO_MODE_GPIO, ++ .gpio4 = GPIO_MODE_GPIO, ++ .gpio5 = GPIO_MODE_NATIVE, ++ .gpio6 = GPIO_MODE_GPIO, ++ .gpio7 = GPIO_MODE_GPIO, ++ .gpio8 = GPIO_MODE_GPIO, ++ .gpio9 = GPIO_MODE_NATIVE, ++ .gpio10 = GPIO_MODE_NATIVE, ++ .gpio11 = GPIO_MODE_NATIVE, ++ .gpio12 = GPIO_MODE_GPIO, ++ .gpio13 = GPIO_MODE_GPIO, ++ .gpio14 = GPIO_MODE_GPIO, ++ .gpio15 = GPIO_MODE_GPIO, ++ .gpio16 = GPIO_MODE_NATIVE, ++ .gpio17 = GPIO_MODE_GPIO, ++ .gpio18 = GPIO_MODE_NATIVE, ++ .gpio19 = GPIO_MODE_GPIO, ++ .gpio20 = GPIO_MODE_NATIVE, ++ .gpio21 = GPIO_MODE_GPIO, ++ .gpio22 = GPIO_MODE_GPIO, ++ .gpio23 = GPIO_MODE_NATIVE, ++ .gpio24 = GPIO_MODE_GPIO, ++ .gpio25 = GPIO_MODE_NATIVE, ++ .gpio26 = GPIO_MODE_NATIVE, ++ .gpio27 = GPIO_MODE_GPIO, ++ .gpio28 = GPIO_MODE_GPIO, ++ .gpio29 = GPIO_MODE_GPIO, ++ .gpio30 = GPIO_MODE_GPIO, ++ .gpio31 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_direction = { ++ .gpio0 = GPIO_DIR_INPUT, ++ .gpio2 = GPIO_DIR_INPUT, ++ .gpio3 = GPIO_DIR_INPUT, ++ .gpio4 = GPIO_DIR_INPUT, ++ .gpio6 = GPIO_DIR_INPUT, ++ .gpio7 = GPIO_DIR_INPUT, ++ .gpio8 = GPIO_DIR_INPUT, ++ .gpio12 = GPIO_DIR_OUTPUT, ++ .gpio13 = GPIO_DIR_INPUT, ++ .gpio14 = GPIO_DIR_INPUT, ++ .gpio15 = GPIO_DIR_INPUT, ++ .gpio17 = GPIO_DIR_INPUT, ++ .gpio19 = GPIO_DIR_INPUT, ++ .gpio21 = GPIO_DIR_INPUT, ++ .gpio22 = GPIO_DIR_INPUT, ++ .gpio24 = GPIO_DIR_INPUT, ++ .gpio27 = GPIO_DIR_INPUT, ++ .gpio28 = GPIO_DIR_INPUT, ++ .gpio29 = GPIO_DIR_INPUT, ++ .gpio30 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_level = { ++ .gpio12 = GPIO_LEVEL_HIGH, ++ .gpio30 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_reset = { ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_invert = { ++ .gpio0 = GPIO_INVERT, ++ .gpio8 = GPIO_INVERT, ++ .gpio14 = GPIO_INVERT, ++}; ++ ++static const struct pch_gpio_set1 pch_gpio_set1_blink = { ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_mode = { ++ .gpio32 = GPIO_MODE_NATIVE, ++ .gpio33 = GPIO_MODE_GPIO, ++ .gpio34 = GPIO_MODE_GPIO, ++ .gpio35 = GPIO_MODE_GPIO, ++ .gpio36 = GPIO_MODE_GPIO, ++ .gpio37 = GPIO_MODE_GPIO, ++ .gpio38 = GPIO_MODE_GPIO, ++ .gpio39 = GPIO_MODE_GPIO, ++ .gpio40 = GPIO_MODE_NATIVE, ++ .gpio41 = GPIO_MODE_NATIVE, ++ .gpio42 = GPIO_MODE_NATIVE, ++ .gpio43 = GPIO_MODE_NATIVE, ++ .gpio44 = GPIO_MODE_NATIVE, ++ .gpio45 = GPIO_MODE_NATIVE, ++ .gpio46 = GPIO_MODE_GPIO, ++ .gpio47 = GPIO_MODE_NATIVE, ++ .gpio48 = GPIO_MODE_GPIO, ++ .gpio49 = GPIO_MODE_NATIVE, ++ .gpio50 = GPIO_MODE_GPIO, ++ .gpio51 = GPIO_MODE_GPIO, ++ .gpio52 = GPIO_MODE_GPIO, ++ .gpio53 = GPIO_MODE_GPIO, ++ .gpio54 = GPIO_MODE_GPIO, ++ .gpio55 = GPIO_MODE_GPIO, ++ .gpio56 = GPIO_MODE_GPIO, ++ .gpio57 = GPIO_MODE_GPIO, ++ .gpio58 = GPIO_MODE_NATIVE, ++ .gpio59 = GPIO_MODE_NATIVE, ++ .gpio60 = GPIO_MODE_GPIO, ++ .gpio61 = GPIO_MODE_NATIVE, ++ .gpio62 = GPIO_MODE_NATIVE, ++ .gpio63 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_direction = { ++ .gpio33 = GPIO_DIR_INPUT, ++ .gpio34 = GPIO_DIR_OUTPUT, ++ .gpio35 = GPIO_DIR_INPUT, ++ .gpio36 = GPIO_DIR_INPUT, ++ .gpio37 = GPIO_DIR_OUTPUT, ++ .gpio38 = GPIO_DIR_INPUT, ++ .gpio39 = GPIO_DIR_INPUT, ++ .gpio46 = GPIO_DIR_OUTPUT, ++ .gpio48 = GPIO_DIR_INPUT, ++ .gpio50 = GPIO_DIR_OUTPUT, ++ .gpio51 = GPIO_DIR_OUTPUT, ++ .gpio52 = GPIO_DIR_INPUT, ++ .gpio53 = GPIO_DIR_INPUT, ++ .gpio54 = GPIO_DIR_INPUT, ++ .gpio55 = GPIO_DIR_OUTPUT, ++ .gpio56 = GPIO_DIR_INPUT, ++ .gpio57 = GPIO_DIR_INPUT, ++ .gpio60 = GPIO_DIR_OUTPUT, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_level = { ++ .gpio34 = GPIO_LEVEL_LOW, ++ .gpio37 = GPIO_LEVEL_LOW, ++ .gpio46 = GPIO_LEVEL_HIGH, ++ .gpio50 = GPIO_LEVEL_HIGH, ++ .gpio51 = GPIO_LEVEL_LOW, ++ .gpio55 = GPIO_LEVEL_LOW, ++ .gpio60 = GPIO_LEVEL_HIGH, ++}; ++ ++static const struct pch_gpio_set2 pch_gpio_set2_reset = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_mode = { ++ .gpio64 = GPIO_MODE_NATIVE, ++ .gpio65 = GPIO_MODE_NATIVE, ++ .gpio66 = GPIO_MODE_NATIVE, ++ .gpio67 = GPIO_MODE_NATIVE, ++ .gpio68 = GPIO_MODE_NATIVE, ++ .gpio69 = GPIO_MODE_NATIVE, ++ .gpio70 = GPIO_MODE_NATIVE, ++ .gpio71 = GPIO_MODE_NATIVE, ++ .gpio72 = GPIO_MODE_NATIVE, ++ .gpio73 = GPIO_MODE_NATIVE, ++ .gpio74 = GPIO_MODE_GPIO, ++ .gpio75 = GPIO_MODE_NATIVE, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_direction = { ++ .gpio74 = GPIO_DIR_INPUT, ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_level = { ++}; ++ ++static const struct pch_gpio_set3 pch_gpio_set3_reset = { ++}; ++ ++const struct pch_gpio_map mainboard_gpio_map = { ++ .set1 = { ++ .mode = &pch_gpio_set1_mode, ++ .direction = &pch_gpio_set1_direction, ++ .level = &pch_gpio_set1_level, ++ .blink = &pch_gpio_set1_blink, ++ .invert = &pch_gpio_set1_invert, ++ .reset = &pch_gpio_set1_reset, ++ }, ++ .set2 = { ++ .mode = &pch_gpio_set2_mode, ++ .direction = &pch_gpio_set2_direction, ++ .level = &pch_gpio_set2_level, ++ .reset = &pch_gpio_set2_reset, ++ }, ++ .set3 = { ++ .mode = &pch_gpio_set3_mode, ++ .direction = &pch_gpio_set3_direction, ++ .level = &pch_gpio_set3_level, ++ .reset = &pch_gpio_set3_reset, ++ }, ++}; +diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c +new file mode 100644 +index 0000000000..70e7c2e79a +--- /dev/null ++++ b/src/mainboard/dell/e5420/hda_verb.c +@@ -0,0 +1,33 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++ ++const u32 cim_verb_data[] = { ++ 0x111d76e7, /* Codec Vendor / Device ID: IDT */ ++ 0x1028049b, /* Subsystem ID */ ++ 11, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(0, 0x1028049b), ++ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), ++ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), ++ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x0d, 0x90170110), ++ AZALIA_PIN_CFG(0, 0x0e, 0x23011050), ++ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), ++ AZALIA_PIN_CFG(0, 0x10, 0x400000f3), ++ AZALIA_PIN_CFG(0, 0x11, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), ++ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), ++ ++ 0x80862805, /* Codec Vendor / Device ID: Intel */ ++ 0x80860101, /* Subsystem ID */ ++ 4, /* Number of 4 dword sets */ ++ AZALIA_SUBVENDOR(3, 0x80860101), ++ AZALIA_PIN_CFG(3, 0x05, 0x18560010), ++ AZALIA_PIN_CFG(3, 0x06, 0x18560020), ++ AZALIA_PIN_CFG(3, 0x07, 0x18560030), ++ ++}; ++ ++const u32 pc_beep_verbs[0] = {}; ++ ++AZALIA_ARRAY_SIZES; +diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c +new file mode 100644 +index 0000000000..31e49802fc +--- /dev/null ++++ b/src/mainboard/dell/e5420/mainboard.c +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void mainboard_enable(struct device *dev) ++{ ++ ++ /* FIXME: fix these values. */ ++ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, ++ GMA_INT15_PANEL_FIT_DEFAULT, ++ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +-- +2.44.0 + diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb index 1925ed68..ea4cfb53 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode index ffca5b39..c52eae4c 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb index ada13b04..26202d3a 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode index d6279c26..0cceca51 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..9abe57a3 --- /dev/null +++ b/config/coreboot/e5420_6mb/config/libgfxinit_corebootfb @@ -0,0 +1,620 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/e5420" +CONFIG_VGA_BIOS_ID="8086,0116" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x5ea000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_DRAM_RESET_GATE_GPIO=60 +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_BOARD_DELL_LATITUDE_E5420=y +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe" +CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +CONFIG_COREBOOT_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=6144 +CONFIG_ROM_SIZE=0x00600000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +# CONFIG_USE_EXP_X86_64_SUPPORT is not set +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set +# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set +CONFIG_RAMINIT_ENABLE_ECC=y + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +# CONFIG_HIDE_MEI_ON_ERROR is not set +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_DELL_MEC5035=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Ironlake" +CONFIG_GFX_GMA_PCH="Cougar_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/e5420_6mb/config/libgfxinit_txtmode b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..5606a017 --- /dev/null +++ b/config/coreboot/e5420_6mb/config/libgfxinit_txtmode @@ -0,0 +1,617 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/e5420" +CONFIG_VGA_BIOS_ID="8086,0116" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x5ea000 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_DRAM_RESET_GATE_GPIO=60 +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_BOARD_DELL_LATITUDE_E5420=y +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xfefe0000 +CONFIG_DCACHE_RAM_SIZE=0x20000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe" +CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +CONFIG_COREBOOT_ROMSIZE_KB_6144=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=6144 +CONFIG_ROM_SIZE=0x00600000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +# CONFIG_USE_EXP_X86_64_SUPPORT is not set +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_MODEL_206AX=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_USE_NATIVE_RAMINIT=y +CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y +# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set +# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set +# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set +CONFIG_RAMINIT_ENABLE_ECC=y + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y +# CONFIG_HIDE_MEI_ON_ERROR is not set +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_DELL_MEC5035=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_HAVE_EXP_X86_64_SUPPORT=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x800 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Ironlake" +CONFIG_GFX_GMA_PCH="Cougar_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg new file mode 100644 index 00000000..1cf0792e --- /dev/null +++ b/config/coreboot/e5420_6mb/target.cfg @@ -0,0 +1,11 @@ +tree="default" +romtype="normal" +arch="x86_64" +payload_grub="n" +payload_grub_withseabios="n" +payload_seabios="y" +payload_memtest="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +grub_scan_disk="ahci" +microcode_required="n" diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb index 5276c108..e57da732 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5520_6mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set CONFIG_BOARD_DELL_LATITUDE_E5520=y # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode index 29148416..b9c2cd0a 100644 --- a/config/coreboot/e5520_6mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5520_6mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set CONFIG_BOARD_DELL_LATITUDE_E5520=y # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb index a93401db..7f4cdc8b 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e5530_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set CONFIG_BOARD_DELL_LATITUDE_E5530=y # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode index e42a9972..4e1303a4 100644 --- a/config/coreboot/e5530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e5530_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set CONFIG_BOARD_DELL_LATITUDE_E5530=y # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb index d3cc4360..5bdd1843 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6420_10mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode index 5766398d..b7aafbaa 100644 --- a/config/coreboot/e6420_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6420_10mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb index b7a11ae9..7d1fd1ed 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6430_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode index 694f1eab..fe8d8105 100644 --- a/config/coreboot/e6430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6430_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb index 28214b76..7b3385ff 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6520_10mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode index 31c9df68..c5195de0 100644 --- a/config/coreboot/e6520_10mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6520_10mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb index 6344db92..3824cd7e 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/e6530_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode index 59f22da1..7bcc0d08 100644 --- a/config/coreboot/e6530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/e6530_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode index b88ef084..3128736d 100644 --- a/config/coreboot/t1650_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t1650_12mb/config/libgfxinit_txtmode @@ -135,6 +135,7 @@ CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set # CONFIG_BOARD_DELL_E6400 is not set diff --git a/config/vendor/sources b/config/vendor/sources index f60ad862..b87953e8 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -156,7 +156,7 @@ E6400_VGA_romname mod_21.bin } -{e5520 e6420 e6520}{ +{e5420 e5520 e6420 e6520}{ DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3 DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe From 98caceb1ce7893e725a3d5d9ef9b9d6b45f91250 Mon Sep 17 00:00:00 2001 From: Leo Heitmann Ruiz Date: Tue, 5 Mar 2024 20:33:17 +0000 Subject: [PATCH 0005/1319] Use proper autolink --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index df1945ca..7f73a3e2 100644 --- a/README.md +++ b/README.md @@ -111,7 +111,7 @@ written in Markdown and hosted in a [separate repository](https://codeberg.org/libreboot/lbwww) where you can send patches. Any and all development discussion and user support are all done on the IRC -channel. More information is on https://libreboot.org/contact.html. +channel. More information is on . LICENSE FOR THIS README ======================= From e119ffa54d32bba49ab16db565680a0e386cdeb6 Mon Sep 17 00:00:00 2001 From: linear cannon Date: Sat, 16 Mar 2024 01:33:10 -0400 Subject: [PATCH 0006/1319] dell-flash-unlock: add NetBSD support --- util/dell-flash-unlock/Makefile | 3 +++ util/dell-flash-unlock/README.md | 4 ++-- util/dell-flash-unlock/accessors.c | 32 +++++++++++++++++++++++++++--- 3 files changed, 34 insertions(+), 5 deletions(-) diff --git a/util/dell-flash-unlock/Makefile b/util/dell-flash-unlock/Makefile index fae52dea..aee07167 100644 --- a/util/dell-flash-unlock/Makefile +++ b/util/dell-flash-unlock/Makefile @@ -6,6 +6,9 @@ CFLAGS=-Wall -Wextra -Werror -O2 -pedantic ifeq ($(shell uname), OpenBSD) CFLAGS += -l$(shell uname -p) endif +ifeq ($(shell uname), NetBSD) + CFLAGS += -l$(shell uname -p) +endif SRCS=dell_flash_unlock.c accessors.c all: $(SRCS) accessors.h diff --git a/util/dell-flash-unlock/README.md b/util/dell-flash-unlock/README.md index 9c7d292c..aca01743 100644 --- a/util/dell-flash-unlock/README.md +++ b/util/dell-flash-unlock/README.md @@ -20,8 +20,8 @@ around 2008 (E6400 era). If it says it is not set, then you will need to install or compile a kernel with that option set. -### OpenBSD -- On OpenBSD, ensure you are booting with securelevel set to -1. +### OpenBSD/NetBSD +- On OpenBSD/NetBSD, ensure you are booting with securelevel set to -1. ### General Make sure an AC adapter is plugged into your system diff --git a/util/dell-flash-unlock/accessors.c b/util/dell-flash-unlock/accessors.c index 6fca2817..a35f8139 100644 --- a/util/dell-flash-unlock/accessors.c +++ b/util/dell-flash-unlock/accessors.c @@ -5,15 +5,15 @@ #include #endif -#if defined(__OpenBSD__) -#include +#if defined(__OpenBSD__) || defined(__NetBSD__) #include +#include #if defined(__amd64__) #include #elif defined(__i386__) #include #endif /* __i386__ */ -#endif /* __OpenBSD__ */ +#endif /* __OpenBSD__ || __NetBSD__ */ #include @@ -42,6 +42,9 @@ sys_outb(unsigned int port, uint8_t data) #if defined(__OpenBSD__) outb(port, data); #endif + #if defined(__NetBSD__) + __asm__ volatile ( "outb %b0, %w1" : : "a"(data), "d"(port) : "memory"); + #endif } void @@ -53,6 +56,9 @@ sys_outl(unsigned int port, uint32_t data) #if defined(__OpenBSD__) outl(port, data); #endif + #if defined(__NetBSD__) + __asm__ volatile ( "outl %0, %w1" : : "a"(data), "d"(port) : "memory"); + #endif } uint8_t @@ -61,6 +67,12 @@ sys_inb(unsigned int port) #if defined(__linux__) || defined (__OpenBSD__) return inb(port); #endif + + #if defined(__NetBSD__) + uint8_t retval; + __asm__ volatile("inb %w1, %b0" : "=a" (retval) : "d" (port) : "memory"); + return retval; + #endif return 0; } @@ -70,6 +82,11 @@ sys_inl(unsigned int port) #if defined(__linux__) || defined (__OpenBSD__) return inl(port); #endif + #if defined(__NetBSD__) + int retval; + __asm__ volatile("inl %w1, %0" : "=a" (retval) : "d" (port) : "memory"); + return retval; + #endif return 0; } @@ -86,6 +103,15 @@ sys_iopl(int level) return amd64_iopl(level); #endif /* __amd64__ */ #endif /* __OpenBSD__ */ + +#if defined(__NetBSD__) +#if defined(__i386__) + return i386_iopl(level); +#elif defined(__amd64__) + return x86_64_iopl(level); +#endif /* __amd64__ */ +#endif /* __NetBSD__ */ + errno = ENOSYS; return -1; } From 8cba237086dfbb312a5913bb75eef4f6046aeae5 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Mon, 18 Mar 2024 10:45:05 -0600 Subject: [PATCH 0007/1319] util: Import autoport with Haswell patches This is a copy of coreboot's autoport utility, with a patch applied to support Haswell/Lynx Point platforms. That patch is currently in review on coreboot's Gerrit. https://review.coreboot.org/c/coreboot/+/30890 Signed-off-by: Nicholas Chin --- util/autoport/azalia.go | 67 +++ util/autoport/bd82x6x.go | 337 +++++++++++ util/autoport/description.md | 1 + util/autoport/ec_fixme.go | 91 +++ util/autoport/ec_lenovo.go | 245 ++++++++ util/autoport/ec_none.go | 24 + util/autoport/go.mod | 1 + util/autoport/gpio_common.go | 113 ++++ util/autoport/haswell.go | 139 +++++ util/autoport/log_maker.go | 190 ++++++ util/autoport/log_reader.go | 417 +++++++++++++ util/autoport/lynxpoint.go | 490 +++++++++++++++ util/autoport/lynxpoint_lp_gpio.go | 252 ++++++++ util/autoport/main.go | 915 +++++++++++++++++++++++++++++ util/autoport/rce823.go | 39 ++ util/autoport/readme.md | 457 ++++++++++++++ util/autoport/root.go | 47 ++ util/autoport/sandybridge.go | 93 +++ 18 files changed, 3918 insertions(+) create mode 100644 util/autoport/azalia.go create mode 100644 util/autoport/bd82x6x.go create mode 100644 util/autoport/description.md create mode 100644 util/autoport/ec_fixme.go create mode 100644 util/autoport/ec_lenovo.go create mode 100644 util/autoport/ec_none.go create mode 100644 util/autoport/go.mod create mode 100644 util/autoport/gpio_common.go create mode 100644 util/autoport/haswell.go create mode 100644 util/autoport/log_maker.go create mode 100644 util/autoport/log_reader.go create mode 100644 util/autoport/lynxpoint.go create mode 100644 util/autoport/lynxpoint_lp_gpio.go create mode 100644 util/autoport/main.go create mode 100644 util/autoport/rce823.go create mode 100644 util/autoport/readme.md create mode 100644 util/autoport/root.go create mode 100644 util/autoport/sandybridge.go diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 00000000..6dd78b1e --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,67 @@ +package main + +import ( + "fmt" + "sort" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + Add_gpl(az) + az.WriteString( + `#include + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x,\t/* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x,\t/* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(%d, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + keys := []int{} + for nid, _ := range codec.PinConfig { + keys = append(keys, nid) + } + + sort.Ints(keys) + + for _, nid := range keys { + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(%d, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, codec.PinConfig[nid]) + } + az.WriteString("\n"); + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* BD82X6X/sandybridge */ + RegisterPCI(0x8086, 0x1c20, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) + /* Lynx Point */ + RegisterPCI(0x8086, 0x8c20, azalia{}) + RegisterPCI(0x8086, 0x9c20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 00000000..8c418e30 --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,337 @@ +package main + +import "fmt" + +type bd82x6x struct { + variant string + node *DevTreeNode +} + +func IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func ich9GetFlashSize(ctx Context) { + inteltool := ctx.InfoSource.GetInteltool() + switch (inteltool.RCBA[0x3410] >> 10) & 3 { + /* SPI. All boards I've seen with sandy/ivy use SPI. */ + case 3: + ROMProtocol = "SPI" + highflkb := uint32(0) + for reg := uint16(0); reg < 5; reg++ { + fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff + flkb := (fl + 1) << 2 + if flkb > highflkb { + highflkb = flkb + } + } + ROMSizeKB = int(highflkb) + /* Shared with ME. Flashrom is unable to handle it. */ + FlashROMSupport = "n" + } +} + +func (b bd82x6x) GetGPIOHeader() string { + return "southbridge/intel/bd82x6x/pch.h" +} + +func (b bd82x6x) EnableGPE(in int) { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" +} + +func (b bd82x6x) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b bd82x6x) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b bd82x6x) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + dmi := ctx.InfoSource.GetDMI() + if dmi.Vendor == "LENOVO" { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + } else { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 + } + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + ich9GetFlashSize(ctx) + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "BRIGHTNESS_UP", + Value: "\\_SB.PCI0.GFX0.INCB", + }, + DSDTDefine{ + Key: "BRIGHTNESS_DOWN", + Value: "\\_SB.PCI0.GFX0.DECB", + }) + + /* SPI init */ + MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h") + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + pcieHotplugMap := "{ " + + for port := 0; port < 7; port++ { + if IsPCIeHotplug(ctx, port) { + pcieHotplugMap += "1, " + } else { + pcieHotplugMap += "0, " + } + } + + if IsPCIeHotplug(ctx, 7) { + pcieHotplugMap += "1 }" + } else { + pcieHotplugMap += "0 }" + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + + Registers: map[string]string{ + "sata_interface_speed_support": "0x3", + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "pcie_port_coalesce": "1", + "pcie_hotplug_map": pcieHotplugMap, + + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), + "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "ehci2", additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"}, + }, + } + + b.node = &cur + + xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}] + + if ok { + cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8]) + cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0]) + cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + AddBootBlockFile("early_init.c", "") + AddROMStageFile("early_init.c", "") + + sb := Create(ctx, "early_init.c") + defer sb.Close() + Add_gpl(sb) + + sb.WriteString(` +#include +#include +#include +#include + +`) + sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + + currentMap := map[uint32]int{ + 0x20000153: 0, + 0x20000f57: 1, + 0x2000055b: 2, + 0x20000f51: 3, + 0x2000094a: 4, + 0x2000035f: 5, + 0x20000f53: 6, + 0x20000357: 7, + 0x20000353: 8, + } + + for port := uint(0); port < 14; port++ { + var pinmask uint32 + OCPin := -1 + if port < 8 { + pinmask = inteltool.RCBA[0x35a0] + } else { + pinmask = inteltool.RCBA[0x35a4] + } + for pin := uint(0); pin < 4; pin++ { + if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { + OCPin = int(pin) + if port >= 8 { + OCPin += 4 + } + } + } + current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] + comment := "" + if !ok { + comment = fmt.Sprintf("// FIXME: Unknown current: RCBA(0x%x)=0x%x", 0x3500+4*port, uint16(0x3500+4*port)) + } + fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + current, + OCPin, + comment) + } + sb.WriteString("};\n") + + guessedMap := GuessSPDMap(ctx) + + sb.WriteString(` +void bootblock_mainboard_early_init(void) +{ +`) + RestorePCI16Simple(sb, addr, 0x82) + + RestorePCI16Simple(sb, addr, 0x80) + + sb.WriteString(`} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ +`) + for i, spd := range guessedMap { + fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) + } + sb.WriteString("}\n") + + gnvs := Create(ctx, "acpi_tables.c") + defer gnvs.Close() + + Add_gpl(gnvs) + gnvs.WriteString(`#include +#include + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} +`) +} + +func init() { + /* BD82X6X LPC */ + for id := 0x1c40; id <= 0x1c5f; id++ { + RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"}) + } + + /* C216 LPC */ + for id := 0x1e41; id <= 0x1e5f; id++ { + RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x1c10, 0x1c12, 0x1c14, 0x1c16, + 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, + 0x1e10, 0x1e12, 0x1e14, 0x1e16, + 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, + 0x1e25, 0x244e, 0x2448, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x1c00, 0x1c01, 0x1c02, 0x1c03, + 0x1e00, 0x1e01, 0x1e02, 0x1e03, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d, + 0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1503, GenericPCI{}) + +} diff --git a/util/autoport/description.md b/util/autoport/description.md new file mode 100644 index 00000000..9a0e8d43 --- /dev/null +++ b/util/autoport/description.md @@ -0,0 +1 @@ +Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go new file mode 100644 index 00000000..54f78ab4 --- /dev/null +++ b/util/autoport/ec_fixme.go @@ -0,0 +1,91 @@ +package main + +import "fmt" + +func FIXMEEC(ctx Context) { + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + hasKeyboard := ctx.InfoSource.HasPS2() + + sbGPE := GuessECGPE(ctx) + var GPEUnsure bool + if sbGPE < 0 { + sbGPE = SouthBridge.EncodeGPE(1) + GPEUnsure = true + SouthBridge.NeedRouteGPIOManually() + } else { + GPEUnsure = false + SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE)) + } + + Add_gpl(ap) + ap.WriteString( + `Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} +`) + + ecs := ctx.InfoSource.GetEC() + MainboardIncludes = append(MainboardIncludes, "ec/acpi/ec.h") + MainboardIncludes = append(MainboardIncludes, "console/console.h") + + MainboardInit += + ` /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = {` + for i := 0; i < 0x100; i++ { + if (i & 0xf) == 0 { + MainboardInit += fmt.Sprintf("\n\t\t\t/* %02x */ ", i) + } + MainboardInit += fmt.Sprintf("0x%02x,", ecs[i]) + if (i & 0xf) != 0xf { + MainboardInit += " " + } + } + MainboardInit += "\n\t\t};\n" + MainboardInit += ` + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } +` + + KconfigBool["EC_ACPI"] = true + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + + if hasKeyboard { + Add_gpl(si) + si.WriteString("#include \n") + MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n") + MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h") + } + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + + Add_gpl(ec) + ec.WriteString(`Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) +`) + if GPEUnsure { + ec.WriteString("\t/* FIXME: Set GPE */\n") + ec.WriteString("\t/* Name (_GPE, ?) */\n") + } else { + fmt.Fprintf(ec, "\tName (_GPE, %d)\n", sbGPE) + } + ec.WriteString("/* FIXME: EC support */\n") + ec.WriteString("}\n") +} diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go new file mode 100644 index 00000000..a34960ff --- /dev/null +++ b/util/autoport/ec_lenovo.go @@ -0,0 +1,245 @@ +package main + +import "fmt" + +func LenovoEC(ctx Context) { + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + wakeGPE := 13 + + sbGPE := GuessECGPE(ctx) + var GPE int + var GPEUnsure bool + if sbGPE < 0 { + sbGPE = SouthBridge.EncodeGPE(1) + GPE = 1 + GPEUnsure = true + SouthBridge.NeedRouteGPIOManually() + } else { + GPE = SouthBridge.DecodeGPE(sbGPE) + GPEUnsure = false + } + + SouthBridge.EnableGPE(wakeGPE) + SouthBridge.EnableGPE(GPE) + + GPEDefine := DSDTDefine{ + Key: "THINKPAD_EC_GPE", + } + + GPEDefine.Value = fmt.Sprintf("%d", sbGPE) + if GPEUnsure { + GPEDefine.Comment = "FIXME: Check this" + } + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "EC_LENOVO_H8_ME_WORKAROUND", + Value: "1", + }, GPEDefine) + + Add_gpl(ap) + ap.WriteString( + `Method(_WAK, 1) +{ + /* ME may not be up yet. */ + Store(0, \_TZ.MEB1) + Store(0, \_TZ.MEB2) + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} +`) + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + + Add_gpl(si) + si.WriteString("#include \n") + + /* FIXME:XX Move this to ec/lenovo. */ + smi := Create(ctx, "smihandler.c") + defer smi.Close() + + AddSMMFile("smihandler.c", "") + + Add_gpl(smi) + smi.WriteString( + `#include +#include +#include +#include +#include +#include +#include <` + SouthBridge.GetGPIOHeader() + ">\n\n") + + if GPEUnsure { + smi.WriteString("/* FIXME: check this */\n") + } + fmt.Fprintf(smi, "#define GPE_EC_SCI %d\n", GPE) + + smi.WriteString("/* FIXME: check this */\n") + fmt.Fprintf(smi, "#define GPE_EC_WAKE %d\n", wakeGPE) + + smi.WriteString(` +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %#02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} +`) + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + + Add_gpl(ec) + ec.WriteString("#include \n") + + KconfigBool["EC_LENOVO_PMH7"] = true + KconfigBool["EC_LENOVO_H8"] = true + + pmh := DevTreeNode{ + Chip: "ec/lenovo/pmh7", + Registers: map[string]string{ + "backlight_enable": "true", + "dock_event_enable": "true", + }, + Children: []DevTreeNode{ + DevTreeNode{ + Chip: "pnp", + Comment: "dummy", + Dev: 0xff, + Func: 1, + }, + }, + } + PutChip("lpc", pmh) + + ecs := ctx.InfoSource.GetEC() + h8 := DevTreeNode{ + Chip: "ec/lenovo/h8", + Children: []DevTreeNode{ + DevTreeNode{ + Chip: "pnp", + Comment: "dummy", + Dev: 0xff, + Func: 2, + IOs: map[uint16]uint16{ + 0x60: 0x62, + 0x62: 0x66, + 0x64: 0x1600, + 0x66: 0x1604, + }, + }, + }, + Comment: "FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb", + Registers: map[string]string{ + "config0": FormatHex8(ecs[0]), + "config1": FormatHex8(ecs[1]), + "config2": FormatHex8(ecs[2]), + "config3": FormatHex8(ecs[3]), + "beepmask0": FormatHex8(ecs[4]), + "beepmask1": FormatHex8(ecs[5]), + }, + } + for i := 0; i < 0x10; i++ { + if ecs[0x10+i] != 0 { + h8.Registers[fmt.Sprintf("event%x_enable", i)] = FormatHex8(ecs[0x10+i]) + } + } + PutChip("lpc", h8) + + eeprom := DevTreeNode{ + Chip: "drivers/i2c/at24rf08c", + Comment: "eeprom, 8 virtual devices, same chip", + Children: []DevTreeNode{ + DevTreeNode{ + Chip: "i2c", + Dev: 0x54, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x55, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x56, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x57, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x5c, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x5d, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x5e, + }, + DevTreeNode{ + Chip: "i2c", + Dev: 0x5f, + }, + }, + } + PutChip("smbus", eeprom) +} diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go new file mode 100644 index 00000000..bcb61bf0 --- /dev/null +++ b/util/autoport/ec_none.go @@ -0,0 +1,24 @@ +package main + +func NoEC(ctx Context) { + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + Add_gpl(ap) + ap.WriteString( + `Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} +`) + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() +} diff --git a/util/autoport/go.mod b/util/autoport/go.mod new file mode 100644 index 00000000..55a89cc9 --- /dev/null +++ b/util/autoport/go.mod @@ -0,0 +1 @@ +module autoport diff --git a/util/autoport/gpio_common.go b/util/autoport/gpio_common.go new file mode 100644 index 00000000..a869dce4 --- /dev/null +++ b/util/autoport/gpio_common.go @@ -0,0 +1,113 @@ +/* code to generate common GPIO code for Intel 6/7/8 Series Chipset */ + +package main + +import ( + "fmt" + "os" +) + +func writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if (constraint>>i)&1 == 1 { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddBootBlockFile("gpio.c", "") + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include \n\n") + + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go new file mode 100644 index 00000000..645b197a --- /dev/null +++ b/util/autoport/haswell.go @@ -0,0 +1,139 @@ +package main + +import "fmt" + +type haswellmc struct { + variant string +} + +func divceil(a uint32, b uint32) uint32 { + return (a + b - 1) / b +} + +func getPanelCfg(inteltool InteltoolData, isULT bool) string { + var refclk uint32 + var pwm_hz uint32 + + if isULT { + refclk = 24000000 + } else { + refclk = 135000000 + } + if (inteltool.IGD[0xc8254] >> 16) != 0 { + pwm_hz = refclk / 128 / (inteltool.IGD[0xc8254] >> 16) + } else { + pwm_hz = 0 + } + + gpu_panel_power_up_delay := (inteltool.IGD[0xc7208] >> 16) & 0x1fff + gpu_panel_power_backlight_on_delay := inteltool.IGD[0xc7208] & 0x1fff + gpu_panel_power_down_delay := (inteltool.IGD[0xc720c] >> 16) & 0x1fff + gpu_panel_power_backlight_off_delay := inteltool.IGD[0xc720c] & 0x1fff + gpu_panel_power_cycle_delay := inteltool.IGD[0xc7210] & 0x1f + + return fmt.Sprintf(`{ + .up_delay_ms = %3d, + .down_delay_ms = %3d, + .cycle_delay_ms = %3d, + .backlight_on_delay_ms = %3d, + .backlight_off_delay_ms = %3d, + .backlight_pwm_hz = %3d, + }`, + divceil(gpu_panel_power_up_delay, 10), + divceil(gpu_panel_power_down_delay, 10), + (gpu_panel_power_cycle_delay-1)*100, + divceil(gpu_panel_power_backlight_on_delay, 10), + divceil(gpu_panel_power_backlight_off_delay, 10), + pwm_hz) +} + +func (i haswellmc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + isULT := (i.variant == "ULT") + DevTree = DevTreeNode{ + Chip: "northbridge/intel/haswell", + MissingParent: "northbridge", + Comment: "FIXME: check ec_present, usb_xhci_on_resume, gfx", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "panel_cfg": getPanelCfg(inteltool, isULT), + "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0), + "ec_present": "false", + "usb_xhci_on_resume": "false", + /* FIXME:XX hardcoded. */ + "gfx": "GMA_STATIC_DISPLAYS(0)", + }, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/haswell", + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Ops: "haswell_cpu_bus_ops", + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + Ops: "haswell_pci_domain_ops", + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: i.variant}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: !isULT, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + }, + }, + }, + } + + if isULT { + DevTree.Registers["dq_pins_interleaved"] = FormatBool(((inteltool.MCHBAR[0x2008] >> 10) & 1) == 0) + } + + PutPCIDev(addr, "Host bridge") + + KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/haswell/acpi/hostbridge.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + Comment: "FIXME: remove this if the board doesn't have backlight", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"}) + RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"}) + RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"}) + RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"}) + RegisterPCI(0x8086, 0x0d00, haswellmc{variant: "Crystal Well Desktop"}) + RegisterPCI(0x8086, 0x0d04, haswellmc{variant: "Crystal Well Mobile"}) + RegisterPCI(0x8086, 0x0d08, haswellmc{variant: "Crystal Well Server"}) + for _, id := range []uint16{ + 0x0402, 0x0412, 0x0422, /* Desktop */ + 0x0406, 0x0416, 0x0426, /* Mobile */ + 0x040a, 0x041a, 0x042a, /* Server */ + 0x0a06, 0x0a16, 0x0a26, /* ULT */ + 0x0d16, 0x0d22, 0x0d26, 0x0d36, /* Mobile 4+3, GT3e */ + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } + /* CPU HD Audio */ + RegisterPCI(0x8086, 0x0a0c, GenericPCI{}) + RegisterPCI(0x8086, 0x0c0c, GenericPCI{}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 00000000..2a524d38 --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,190 @@ +package main + +import ( + "errors" + "fmt" + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" + "bytes" +) + +func TryRunAndSave(output string, name string, arg []string) error { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + return err + } + cmd.Wait() + return nil +} + +func RunAndSave(output string, name string, arg ...string) { + err := TryRunAndSave(output, name, arg) + if err == nil { + return + } + idx := strings.LastIndex(name, "/") + relname := name + if idx >= 0 { + relname = name[idx+1:] + } + relname = "./" + relname + err = TryRunAndSave(output, relname, arg) + if err != nil { + log.Fatal(err) + } +} + +const MAXPROMPTRETRY = 3 + +func PromptUser(prompt string, opts []string) (match string, err error) { + for i := 1; i < MAXPROMPTRETRY; i++ { + fmt.Printf("%s. (%s) Default:%s\n", prompt, + strings.Join(opts, "/"), opts[0]) + var usrInput string + fmt.Scanln(&usrInput) + + // Check for default entry + if usrInput == "" { + match = opts[0] + return + } + + for _, opt := range opts { + if opt == usrInput { + match = opt + return + } + } + } + err = errors.New("max retries exceeded") + fmt.Fprintln(os.Stderr, "ERROR: max retries exceeded") + return +} + +func MakeHDALogs(outDir string, cardName string) { + SysDir := "/sys/class/sound/" + cardName + "/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/" + cardName + "/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + + inteltoolArgs := "-a" + opt, err := PromptUser("WARNING: The following tool MAY cause your system to hang when it attempts "+ + "to probe for graphics registers. Having the graphics registers will help create a better port. "+ + "Should autoport probe these registers?", + []string{"y", "yes", "n", "no"}) + + // Continue even if there is an error + + switch opt { + case "y", "yes": + inteltoolArgs += "f" + } + + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", inteltoolArgs) + RunAndSave(outDir+"/ectool.log", "../ectool/ectool", "-pd") + RunAndSave(outDir+"/superiotool.log", "../superiotool/superiotool", "-ade") + + SysSound := "/sys/class/sound/" + card := "" + cards, _ := ioutil.ReadDir(SysSound) + for _, f := range cards { + if strings.HasPrefix(f.Name(), "card") { + cid, err := ioutil.ReadFile(SysSound + f.Name() + "/id") + if err == nil && bytes.Equal(cid, []byte("PCH\n")) { + fmt.Fprintln(os.Stderr, "PCH sound card is", f.Name()) + card = f.Name() + } + } + } + + if card != "" { + MakeHDALogs(outDir, card) + } else { + fmt.Fprintln(os.Stderr, "HDAudio not found on PCH.") + } + + for _, fname := range []string{"cpuinfo", "ioports"} { + in, err := os.Open("/proc/" + fname) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + fname + ".log") + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + + out, err := os.Create(outDir + "/input_bustypes.log") + if err != nil { + log.Fatal(err) + } + defer out.Close() + + ClassInputDir := "/sys/class/input/" + files, _ := ioutil.ReadDir(ClassInputDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "input") && !f.Mode().IsRegular() { /* Allow both dirs and symlinks. */ + in, err := os.Open(ClassInputDir + f.Name() + "/id/bustype") + defer in.Close() + if err != nil { + log.Fatal(err) + } + io.Copy(out, in) + } + } +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 00000000..b0518d25 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,417 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "regexp" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte + EC []byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetEC() []byte { + if l.EC != nil { + return l.EC + } + l.EC = make([]byte, 0x100, 0x100) + + file, err := os.Open(l.InputDirectory + "/ectool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + for scanner.Scan() { + line := scanner.Text() + if len(line) > 7 && isXDigit(line[0]) && isXDigit(line[1]) && line[2] == ':' { + l.EC = l.AssignHexLine(line, l.EC) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return l.EC +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + /* Only supports ACPI tables up to 0x100000 in size, FIXME if needed */ + is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4,5}: ", line) + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 0x100000) + case is_hexline: + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + ret.IOBP = map[uint32]uint32{} + ret.IGD = map[uint32]uint32{} + ret.MCHBAR = map[uint16]uint32{} + ret.PMBASE = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case len(line) > 11 && line[0] == '0' && line[1] == 'x' && line[10] == ':' && paragraph == "IOBP": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.IOBP[uint32(addr)] = uint32(value) + case len(line) > 9 && line[0] == '0' && line[1] == 'x' && line[8] == ':' && paragraph == "IGD": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.IGD[uint32(addr)] = uint32(value) + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "MCHBAR": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.MCHBAR[uint16(addr)] = uint32(value) + case strings.Contains(line, "DEFAULT"): + continue + case strings.Contains(line, "DIFF"): + continue + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "pmbase"): + addr, value := 0, 0 + fmt.Sscanf(line, "pmbase+0x%x: 0x%x", &addr, &value) + ret.PMBASE[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + cardno := -1 + for i := 0; i < 10; i++ { + pin, err := os.Open(l.InputDirectory + "/pin_hwC" + strconv.Itoa(i) + "D0") + if err == nil { + pin.Close() + cardno = i + break + } + } + if cardno == -1 { + return + } + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC" + strconv.Itoa(cardno) + + "D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +func (l *LogDevReader) GetIOPorts() []IOPorts { + file, err := os.Open(l.InputDirectory + "/ioports.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + scanner := bufio.NewScanner(file) + ret := make([]IOPorts, 0, 100) + for scanner.Scan() { + line := scanner.Text() + el := IOPorts{} + fmt.Sscanf(line, " %x-%x : %s", &el.Start, &el.End, &el.Usage) + ret = append(ret, el) + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return ret + +} + +func (l *LogDevReader) GetCPUModel() (ret []uint32) { + file, err := os.Open(l.InputDirectory + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + ret = make([]uint32, 0, 100) + proc := 0 + for scanner.Scan() { + line := scanner.Text() + sep := strings.Index(line, ":") + if sep < 0 { + continue + } + key := strings.TrimSpace(line[0:sep]) + val := strings.TrimSpace(line[sep+1:]) + + if key == "processor" { + proc, _ := strconv.Atoi(val) + if len(ret) <= proc { + ret = ret[0 : proc+1] + } + continue + } + if key == "cpu family" { + family, _ := strconv.Atoi(val) + ret[proc] |= uint32(((family & 0xf) << 8) | ((family & 0xff0) << 16)) + } + if key == "model" { + model, _ := strconv.Atoi(val) + ret[proc] |= uint32(((model & 0xf) << 4) | ((model & 0xf0) << 12)) + } + if key == "stepping" { + stepping, _ := strconv.Atoi(val) + ret[proc] |= uint32(stepping & 0xf) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) HasPS2() bool { + file, err := os.Open(l.InputDirectory + "/input_bustypes.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + scanner := bufio.NewScanner(file) + for scanner.Scan() { + line := scanner.Text() + if strings.Index(line, "0011") >= 0 { + return true + } + } + return false +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go new file mode 100644 index 00000000..98a1ca82 --- /dev/null +++ b/util/autoport/lynxpoint.go @@ -0,0 +1,490 @@ +package main + +import "fmt" + +type LPVariant int + +const ( + LYNX_POINT_MOBILE LPVariant = iota + LYNX_POINT_DESKTOP + LYNX_POINT_SERVER + LYNX_POINT_ULT +) + +type lynxpoint struct { + variant LPVariant + node *DevTreeNode +} + +func lpPchGetFlashSize(ctx Context) { + inteltool := ctx.InfoSource.GetInteltool() + /* In LP PCH, Boot BIOS Straps field in GCS has only one bit. */ + switch (inteltool.RCBA[0x3410] >> 10) & 1 { + case 0: + ROMProtocol = "SPI" + highflkb := uint32(0) + for reg := uint16(0); reg < 5; reg++ { + fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff + flkb := (fl + 1) << 2 + if flkb > highflkb { + highflkb = flkb + } + } + ROMSizeKB = int(highflkb) + FlashROMSupport = "y" + } +} + +func (b lynxpoint) GetGPIOHeader() string { + return "southbridge/intel/lynxpoint/pch.h" +} + +func (b lynxpoint) EnableGPE(in int) { + if b.variant != LYNX_POINT_ULT { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" + } +} + +func (b lynxpoint) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b lynxpoint) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b lynxpoint) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func GetLptDesktopEHCISetting(loc_param uint32, txamp uint32) (string, int) { + var port_pos string + var port_length int + + if loc_param == 4 { + port_pos = "USB_PORT_BACK_PANEL" + if txamp <= 2 { + port_length = 0x40 + } else if txamp >= 4 { + port_length = 0x140 + } else { + port_length = 0x110 + } + } else { + port_pos = "USB_PORT_FLEX" + port_length = 0x40 + } + return port_pos, port_length +} + +func GetLptMobileEHCISetting(loc_param uint32, txamp uint32) (string, int) { + var port_pos string + var port_length int + + if loc_param == 4 { + port_pos = "USB_PORT_DOCK" + if txamp <= 1 { + port_length = 0x40 + } else { + port_length = 0x80 + } + } else if loc_param == 6 { + /* not internal, not dock, port_length >= 0x70 */ + port_pos = "USB_PORT_BACK_PANEL" + if txamp <= 2 { + port_length = 0x80 + } else { + port_length = 0x110 + } + } else { + port_pos = "USB_PORT_BACK_PANEL" + port_length = 0x40 + } + return port_pos, port_length +} + +func GetLptLPEHCISetting(loc_param uint32, txamp uint32) (string, int) { + var port_pos string + var port_length int + + if loc_param == 6 { + /* back panel or mini pcie, length >= 0x70 */ + port_pos = "USB_PORT_MINI_PCIE" + if txamp <= 2 { + port_length = 0x80 + } else { + port_length = 0x110 + } + } else if loc_param == 4 { + port_pos = "USB_PORT_DOCK" + if txamp <= 1 { + port_length = 0x40 + } else { + port_length = 0x80 + } + } else { + port_pos = "USB_PORT_BACK_PANEL" + port_length = 0x40 + } + return port_pos, port_length +} + +func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + + isULT := (b.variant == LYNX_POINT_ULT) + + if isULT { + Lynxpoint_LP_GPIO(ctx, inteltool) + } else { + GPIO(ctx, inteltool) + } + + KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true + if isULT { + KconfigBool["INTEL_LYNXPOINT_LP"] = true + } + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + if isULT { + KconfigInt["USBDEBUG_HCD_INDEX"] = 1 + } else { + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + } + + if isULT { + lpPchGetFlashSize(ctx) + } else { + ich9GetFlashSize(ctx) + } + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + sp0dtle_data := (inteltool.IOBP[0xea002750] >> 24) & 0xf + sp0dtle_edge := (inteltool.IOBP[0xea002754] >> 16) & 0xf + sp1dtle_data := (inteltool.IOBP[0xea002550] >> 24) & 0xf + sp1dtle_edge := (inteltool.IOBP[0xea002554] >> 16) & 0xf + + if sp0dtle_data != sp0dtle_edge { + fmt.Printf("Different SATA Gen3 port0 DTLE data and edge values are used.\n") + } + + if sp1dtle_data != sp1dtle_edge { + fmt.Printf("Different SATA Gen3 port1 DTLE data and edge values are used.\n") + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/lynxpoint", + Comment: "Intel Series 8 Lynx Point PCH", + + /* alt_gp_smi_en is not generated because coreboot doesn't use SMI like OEM firmware */ + Registers: map[string]string{ + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + "sata_port0_gen3_dtle": fmt.Sprintf("0x%x", sp0dtle_data), + "sata_port1_gen3_dtle": fmt.Sprintf("0x%x", sp1dtle_data), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x13, Func: 0}, writeEmpty: isULT, additionalComment: "Smart Sound Audio DSP"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: true, additionalComment: "xHCI Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 0}, writeEmpty: isULT, additionalComment: "Serial I/O DMA"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 1}, writeEmpty: isULT, additionalComment: "I2C0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 2}, writeEmpty: isULT, additionalComment: "I2C1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 3}, writeEmpty: isULT, additionalComment: "GSPI0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 4}, writeEmpty: isULT, additionalComment: "GSPI1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 5}, writeEmpty: isULT, additionalComment: "UART0"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x15, Func: 6}, writeEmpty: isULT, additionalComment: "UART1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x17, Func: 0}, writeEmpty: isULT, additionalComment: "SDIO"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: !isULT, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: !isULT, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: !isULT, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller (AHCI)"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: !isULT, additionalComment: "SATA Controller (Legacy)"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + if isULT { + cur.Registers["gpe0_en_1"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x90]) + cur.Registers["gpe0_en_2"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x94]) + cur.Registers["gpe0_en_3"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x98]) + cur.Registers["gpe0_en_4"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x9c]) + } else { + cur.Registers["gpe0_en_1"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x28]) + cur.Registers["gpe0_en_2"] = fmt.Sprintf("0x%x", inteltool.PMBASE[0x2c]) + } + + b.node = &cur + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/pch.asl", + }) + + AddBootBlockFile("bootblock.c", "") + bb := Create(ctx, "bootblock.c") + defer bb.Close() + Add_gpl(bb) + bb.WriteString(`#include + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} +`) + + sb := Create(ctx, "romstage.c") + defer sb.Close() + Add_gpl(sb) + sb.WriteString(`#include +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + /* FIXME: check this */ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ +`) + + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + + var pdo2 uint8 + var ocmap2 []uint8 + var nPorts uint + if isULT { + nPorts = 8 + } else { + pdo2 = PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64] + ocmap2 = PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78] + nPorts = 14 + } + + xusb2pr := GetLE16(PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xd0:0xd4]) + + for port := uint(0); port < nPorts; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + if port < 8 { + port_disable = ((pdo1 >> port) & (uint8(xusb2pr>>port) ^ 1)) & 1 + for oc := 0; oc < 4; oc++ { + if (ocmap1[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + } else { + port_disable = ((pdo2 >> (port - 8)) & (uint8(xusb2pr>>port) ^ 1)) & 1 + for oc := 0; oc < 4; oc++ { + if (ocmap2[oc] & (1 << (port - 8))) != 0 { + port_oc = oc + 4 + break + } + } + } + + /* get USB2 port length and location from IOBP */ + port_iobp := inteltool.IOBP[0xe5004100+uint32(port)*0x100] + loc_param := (port_iobp >> 8) & 7 + txamp := (port_iobp >> 11) & 7 + var port_length int + + if isULT { + port_pos, port_length = GetLptLPEHCISetting(loc_param, txamp) + } else if b.variant == LYNX_POINT_MOBILE { + port_pos, port_length = GetLptMobileEHCISetting(loc_param, txamp) + } else { /* desktop or server */ + port_pos, port_length = GetLptDesktopEHCISetting(loc_param, txamp) + } + + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } + + if port_oc == -1 { + fmt.Fprintf(sb, "\t{ 0x%04x, %d, USB_OC_PIN_SKIP, %s },\n", + port_length, (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(sb, "\t{ 0x%04x, %d, %d, %s },\n", + port_length, (port_disable ^ 1), port_oc, port_pos) + } + } + + sb.WriteString(`}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { +`) + + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + if !isULT { + nPorts = 6 + } else { + nPorts = 4 + } + + for port := uint(0); port < nPorts; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + if port_oc == -1 { + fmt.Fprintf(sb, "\t{ %d, USB_OC_PIN_SKIP },\n", + (port_disable ^ 1)) + } else { + fmt.Fprintf(sb, "\t{ %d, %d },\n", + (port_disable ^ 1), port_oc) + } + } + + sb.WriteString(`}; +`) + +} + +func init() { + for _, id := range []uint16{ + 0x8c41, 0x8c49, 0x8c4b, 0x8c4f, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_MOBILE}) + } + + for _, id := range []uint16{ + 0x8c42, 0x8c44, 0x8c46, 0x8c4a, + 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_DESKTOP}) + } + + for _, id := range []uint16{ + 0x8c52, 0x8c54, 0x8c56, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_SERVER}) + } + + for _, id := range []uint16{ + 0x9c41, 0x9c43, 0x9c45, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: LYNX_POINT_ULT}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x9c26, 0x8c26, 0x8c2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x8c31, GenericPCI{}) + RegisterPCI(0x8086, 0x9c31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x8c3a, 0x8c3b, 0x8c3c, 0x8c3d, + 0x9c3a, 0x9c3b, 0x9c3c, 0x9c3d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x8c33, GenericPCI{}) + + /* Thermal */ + RegisterPCI(0x8086, 0x8c24, GenericPCI{}) + RegisterPCI(0x8086, 0x9c24, GenericPCI{}) + + /* LAN Controller on LP PCH (if EEPROM has 0x0000/0xffff in DID) */ + RegisterPCI(0x8086, 0x155a, GenericPCI{}) + + /* SDIO */ + RegisterPCI(0x8086, 0x9c35, GenericPCI{}) + + /* Smart Sound Technology Controller */ + RegisterPCI(0x8086, 0x9c36, GenericPCI{}) + + /* Serial I/O */ + for id := uint16(0x9c60); id <= 0x9c66; id++ { + RegisterPCI(0x8086, id, GenericPCI{}) + } +} diff --git a/util/autoport/lynxpoint_lp_gpio.go b/util/autoport/lynxpoint_lp_gpio.go new file mode 100644 index 00000000..fbc1686a --- /dev/null +++ b/util/autoport/lynxpoint_lp_gpio.go @@ -0,0 +1,252 @@ +package main + +import ( + "fmt" + "os" + "strings" +) + +const ( + PIRQI = 0 + PIRQJ = 1 + PIRQK = 2 + PIRQL = 3 + PIRQM = 4 + PIRQN = 5 + PIRQO = 6 + PIRQP = 7 + PIRQQ = 8 + PIRQR = 9 + PIRQS = 10 + PIRQT = 11 + PIRQU = 12 + PIRQV = 13 + PIRQW = 14 + PIRQX = 15 +) + +/* from sb/intel/lynxpoint/lp_gpio.c */ +func lp_gpio_to_pirq(gpioNum uint16) int { + switch gpioNum { + case 8: + return PIRQI + case 9: + return PIRQJ + case 10: + return PIRQK + case 13: + return PIRQL + case 14: + return PIRQM + case 45: + return PIRQN + case 46: + return PIRQO + case 47: + return PIRQP + case 48: + return PIRQQ + case 49: + return PIRQR + case 50: + return PIRQS + case 51: + return PIRQT + case 52: + return PIRQU + case 53: + return PIRQV + case 54: + return PIRQW + case 55: + return PIRQX + default: + return -1 + } +} + +func conf0str(conf0 uint32) string { + if (conf0 & 1) == 0 { + return "GPIO_MODE_NATIVE" + } else { + s := []string{"GPIO_MODE_GPIO"} + var gpio_output bool + if ((conf0 >> 2) & 1) == 1 { + s = append(s, "GPIO_DIR_INPUT") + gpio_output = false + } else { + s = append(s, "GPIO_DIR_OUTPUT") + gpio_output = true + } + if ((conf0 >> 3) & 1) == 1 { + s = append(s, "GPIO_INVERT") + } + if ((conf0 >> 4) & 1) == 1 { + s = append(s, "GPIO_IRQ_LEVEL") + } + if gpio_output { + if ((conf0 >> 31) & 1) == 1 { + s = append(s, "GPO_LEVEL_HIGH") + } else { + s = append(s, "GPO_LEVEL_LOW") + } + } + return strings.Join(s, " | ") + } +} + +func lpgpio_preset(conf0 uint32, owner uint32, route uint32, irqen uint32, pirq uint32) string { + if conf0 == 0xd { /* 0b1101: MODE_GPIO | INPUT | INVERT */ + if owner == 0 { /* OWNER_ACPI */ + if irqen == 0 && pirq == 0 { + if route == 0 { /* SCI */ + return "GPIO_ACPI_SCI" + } else { + return "GPIO_ACPI_SMI" + } + } + return "" + } else { /* OWNER_GPIO */ + if route == 0 && irqen == 0 && pirq != 0 { + return "GPIO_INPUT_INVERT" + } + return "" + } + } + + if conf0 == 0x5 && owner == 1 { /* 0b101: MODE_GPIO | INPUT, OWNER_GPIO */ + if route == 0 && irqen == 0 { + if pirq == 1 { + return "GPIO_PIRQ" + } else { + return "GPIO_INPUT" + } + } + return "" + } + + if owner == 1 && irqen == 1 { + if route == 0 && pirq == 0 { + if conf0 == 0x5 { /* 0b00101 */ + return "GPIO_IRQ_EDGE" + } + if conf0 == 0x15 { /* 0b10101 */ + return "GPIO_IRQ_LEVEL" + } + } + return "" + } + return "" +} + +func gpio_str(conf0 uint32, conf1 uint32, owner uint32, route uint32, irqen uint32, reset uint32, blink uint32, pirq uint32) string { + s := []string{} + s = append(s, fmt.Sprintf(".conf0 = %s", conf0str(conf0))) + if conf1 != 0 { + s = append(s, fmt.Sprintf(".conf1 = 0x%x", conf1)) + } + if owner != 0 { + s = append(s, ".owner = GPIO_OWNER_GPIO") + } + if route != 0 { + s = append(s, ".route = GPIO_ROUTE_SMI") + } + if irqen != 0 { + s = append(s, ".irqen = GPIO_IRQ_ENABLE") + } + if reset != 0 { + s = append(s, ".reset = GPIO_RESET_RSMRST") + } + if blink != 0 { + s = append(s, ".blink = GPO_BLINK") + } + if pirq != 0 { + s = append(s, ".pirq = GPIO_PIRQ_APIC_ROUTE") + } + return strings.Join(s, ", ") +} + +/* start addresses of GPIO registers */ +const ( + GPIO_OWN = 0x0 + GPIPIRQ2IOXAPIC = 0x10 + GPO_BLINK = 0x18 + GPI_ROUT = 0x30 + GP_RST_SEL = 0x60 + GPI_IE = 0x90 + GPnCONFIGA = 0x100 + GPnCONFIGB = 0x104 +) + +func PrintLPGPIO(gpio *os.File, inteltool InteltoolData) { + for gpioNum := uint16(0); gpioNum <= 94; gpioNum++ { + if gpioNum < 10 { + fmt.Fprintf(gpio, "\t[%d] = ", gpioNum) + } else { + fmt.Fprintf(gpio, "\t[%d] = ", gpioNum) + } + conf0 := inteltool.GPIO[GPnCONFIGA+gpioNum*8] + conf1 := inteltool.GPIO[GPnCONFIGB+gpioNum*8] + set := gpioNum / 32 + bit := gpioNum % 32 + /* owner only effective in GPIO mode */ + owner := (inteltool.GPIO[GPIO_OWN+set*4] >> bit) & 1 + route := (inteltool.GPIO[GPI_ROUT+set*4] >> bit) & 1 + irqen := (inteltool.GPIO[GPI_IE+set*4] >> bit) & 1 + reset := (inteltool.GPIO[GP_RST_SEL+set*4] >> bit) & 1 + var blink, pirq uint32 + /* blink only effective in GPIO output mode */ + if set == 0 { + blink = (inteltool.GPIO[GPO_BLINK] >> bit) & 1 + } else { + blink = 0 + } + irqset := lp_gpio_to_pirq(gpioNum) + if irqset >= 0 { + pirq = (inteltool.GPIO[GPIPIRQ2IOXAPIC] >> uint(irqset)) & 1 + } else { + pirq = 0 + } + + if (conf0 & 1) == 0 { + fmt.Fprintf(gpio, "LP_GPIO_NATIVE,\n") + } else if (conf0 & 4) == 0 { + /* configured as output */ + if ((conf0 >> 31) & 1) == 0 { + fmt.Fprintf(gpio, "LP_GPIO_OUT_LOW,\n") + } else { + fmt.Fprintf(gpio, "LP_GPIO_OUT_HIGH,\n") + } + } else if (conf1 & 4) != 0 { + /* configured as input and sensing disabled */ + fmt.Fprintf(gpio, "LP_GPIO_UNUSED,\n") + } else { + is_preset := false + if conf1 == 0 && reset == 0 && blink == 0 { + preset := lpgpio_preset(conf0, owner, route, irqen, pirq) + if preset != "" { + fmt.Fprintf(gpio, "LP_%s,\n", preset) + is_preset = true + } + } + if !is_preset { + fmt.Fprintf(gpio, "{ %s },\n", gpio_str(conf0, conf1, owner, route, irqen, reset, blink, pirq)) + } + } + } +} + +func Lynxpoint_LP_GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString(`#include + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { +`) + PrintLPGPIO(gpio, inteltool) + gpio.WriteString("\tLP_GPIO_END\n};\n") +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 00000000..3a2f0617 --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,915 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "bytes" + "flag" + "fmt" + "log" + "os" + "sort" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 + IOBP map[uint32]uint32 + IGD map[uint32]uint32 + MCHBAR map[uint16]uint32 + PMBASE map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte + GetCPUModel() []uint32 + GetEC() []byte + GetIOPorts() []IOPorts + HasPS2() bool +} + +type IOPorts struct { + Start uint16 + End uint16 + Usage string +} + +type SouthBridger interface { + GetGPIOHeader() string + EncodeGPE(int) int + DecodeGPE(int) int + EnableGPE(int) + NeedRouteGPIOManually() +} + +var SouthBridge SouthBridger +var BootBlockFiles map[string]string = map[string]string{} +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} +var SMMFiles map[string]string = map[string]string{} +var MainboardInit string +var MainboardEnable string +var MainboardIncludes []string + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader + SaneVendor string +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigComment map[string]string = map[string]string{} +var KconfigString map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} +var ROMSizeKB = 0 +var ROMProtocol = "" +var FlashROMSupport = "" + +func GetLE16(inp []byte) uint16 { + return uint16(inp[0]) | (uint16(inp[1]) << 8) +} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf("0x%04x", GetLE16(inp)) +} + +func FormatHex32(u uint32) string { + return fmt.Sprintf("0x%08x", u) +} + +func FormatHex8(u uint8) string { + return fmt.Sprintf("0x%02x", u) +} + +func FormatInt32(u uint32) string { + return fmt.Sprintf("%d", u) +} + +func FormatHexLE32(d []uint8) string { + u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24) + return FormatHex32(u) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + result = strings.Replace(result, "-", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddBootBlockFile(Name string, Condition string) { + BootBlockFiles[Name] = Condition +} + +func AddROMStageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMStageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +func AddSMMFile(Name string, Condition string) { + SMMFiles[Name] = Condition +} + +func IsIOPortUsedBy(ctx Context, port uint16, name string) bool { + for _, io := range ctx.InfoSource.GetIOPorts() { + if io.Start <= port && port <= io.End && io.Usage == name { + return true + } + } + return false +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + keys := []string{} + for file, _ := range files { + keys = append(keys, file) + } + + sort.Strings(keys) + + for _, file := range keys { + condition := files[file] + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func Add_gpl(f *os.File) { + fmt.Fprintln(f, "/* SPDX-License-Identifier: GPL-2.0-only */") + fmt.Fprintln(f) +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+3], + pcidev.ConfigDump[addr+2], + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + alias string + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + IOs map[uint16]uint16 + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Ops string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot.PCIAddr) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete(MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, alias string, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci", "pnp": + if alias != "" { + fmt.Fprintf(dt, "device ref %s ", alias) + } else { + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + } + writeOn(dt, dev) + case "i2c": + fmt.Fprintf(dt, "device %s %02x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Ops != "" { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ops %s\n", dev.Ops) + } + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + keys := []string{} + for reg, _ := range dev.Registers { + keys = append(keys, reg) + } + + sort.Strings(keys) + + for _, reg := range keys { + val := dev.Registers[reg] + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + ios := []int{} + for reg, _ := range dev.IOs { + ios = append(ios, int(reg)) + } + + sort.Ints(ios) + + for _, reg := range ios { + val := dev.IOs[uint16(reg)] + Offset(dt, offset+1) + fmt.Fprintf(dt, "io 0x%x = 0x%x\n", reg, val) + } + + for _, child := range dev.Children { + alias = "" + for _, slot := range dev.PCISlots { + if slot.PCIAddr.Bus == child.Bus && + slot.PCIAddr.Dev == child.Dev && slot.PCIAddr.Func == child.Func { + alias = slot.alias + } + } + WriteDev(dt, offset+1, alias, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIChip(addr PCIDevData, cur DevTreeNode) { + unmatchedPCIChips[addr.PCIAddr] = cur +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 { + cur.PCIController = true + cur.ChildPCIBus = int(addr.ConfigDump[0x19]) + + loopCtr := 0 + for capPtr := addr.ConfigDump[0x34]; capPtr != 0; capPtr = addr.ConfigDump[capPtr+1] { + /* Avoid hangs. There are only 0x100 different possible values for capPtr. + If we iterate longer than that, we're in endless loop. */ + loopCtr++ + if loopCtr > 0x100 { + break + } + if addr.ConfigDump[capPtr] == 0x0d { + cur.SubVendor = GetLE16(addr.ConfigDump[capPtr+4 : capPtr+6]) + cur.SubSystem = GetLE16(addr.ConfigDump[capPtr+6 : capPtr+8]) + } + } + } else { + cur.SubVendor = GetLE16(addr.ConfigDump[0x2c:0x2e]) + cur.SubSystem = GetLE16(addr.ConfigDump[0x2e:0x30]) + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + +type DSDTInclude struct { + Comment string + File string +} + +type DSDTDefine struct { + Key string + Comment string + Value string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude +var DSDTDefines []DSDTDefine + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +var IGDEnabled bool = false + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) + IGDEnabled = true +} + +func makeKconfigName(ctx Context) { + kn := Create(ctx, "Kconfig.name") + defer kn.Close() + + fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model) +} + +func makeComment(name string) string { + cmt, ok := KconfigComment[name] + if !ok { + return "" + } + return " # " + cmt +} + +func makeKconfig(ctx Context) { + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n") + keys := []string{} + for name, val := range KconfigBool { + if val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, "\tselect %s%s\n", name, makeComment(name)) + } + + keys = nil + for name, val := range KconfigBool { + if !val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + bool + default n +`, name, makeComment(name)) + } + + keys = nil + for name, _ := range KconfigString { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + string + default "%s" +`, name, makeComment(name), KconfigString[name]) + } + + keys = nil + for name, _ := range KconfigHex { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + hex + default 0x%x +`, name, makeComment(name), KconfigHex[name]) + } + + keys = nil + for name, _ := range KconfigInt { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + int + default %d +`, name, makeComment(name), KconfigInt[name]) + } + + fmt.Fprintf(kc, "endif\n") +} + +const MoboDir = "/src/mainboard/" + +func makeVendor(ctx Context) { + vendor := ctx.Vendor + vendorSane := ctx.SaneVendor + vendorDir := *FlagOutDir + MoboDir + vendorSane + vendorUpper := strings.ToUpper(vendorSane) + kconfig := vendorDir + "/Kconfig" + if _, err := os.Stat(kconfig); os.IsNotExist(err) { + f, err := os.Create(kconfig) + if err != nil { + log.Fatal(err) + } + defer f.Close() + f.WriteString(`if VENDOR_` + vendorUpper + ` + +choice + prompt "Mainboard model" + +source "src/mainboard/` + vendorSane + `/*/Kconfig.name" + +endchoice + +source "src/mainboard/` + vendorSane + `/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "` + vendor + `" + +endif # VENDOR_` + vendorUpper + "\n") + } + kconfigName := vendorDir + "/Kconfig.name" + if _, err := os.Stat(kconfigName); os.IsNotExist(err) { + f, err := os.Create(kconfigName) + if err != nil { + log.Fatal(err) + } + defer f.Close() + f.WriteString(`config VENDOR_` + vendorUpper + ` + bool "` + vendor + `" +`) + } + +} + +func GuessECGPE(ctx Context) int { + /* FIXME:XX Use iasl -d and/or better parsing */ + dsdt := ctx.InfoSource.GetACPI()["DSDT"] + idx := bytes.Index(dsdt, []byte{0x08, '_', 'G', 'P', 'E', 0x0a}) /* Name (_GPE, byte). */ + if idx > 0 { + return int(dsdt[idx+6]) + } + return -1 +} + +func GuessSPDMap(ctx Context) []uint8 { + dmi := ctx.InfoSource.GetDMI() + + if dmi.Vendor == "LENOVO" { + return []uint8{0x50, 0x52, 0x51, 0x53} + } + return []uint8{0x50, 0x51, 0x52, 0x53} +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.SaneVendor = sanitize(ctx.Vendor) + for { + last := ctx.SaneVendor + for _, suf := range []string{"_inc", "_co", "_corp"} { + ctx.SaneVendor = strings.TrimSuffix(ctx.SaneVendor, suf) + } + if last == ctx.SaneVendor { + break + } + } + ctx.MoboID = ctx.SaneVendor + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(ctx.SaneVendor+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + MoboDir + ctx.MoboID + KconfigString["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + os.MkdirAll(ctx.BaseDirectory, 0700) + + makeVendor(ctx) + + ScanRoot(ctx) + + if IGDEnabled { + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + } + + if len(BootBlockFiles) > 0 || len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { + mf := Create(ctx, "Makefile.mk") + defer mf.Close() + writeMF(mf, BootBlockFiles, "bootblock") + writeMF(mf, ROMStageFiles, "romstage") + writeMF(mf, RAMStageFiles, "ramstage") + writeMF(mf, SMMFiles, "smm") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, "", DevTree) + + if MainboardInit != "" || MainboardEnable != "" || MainboardIncludes != nil { + mainboard := Create(ctx, "mainboard.c") + defer mainboard.Close() + Add_gpl(mainboard) + mainboard.WriteString("#include \n") + for _, include := range MainboardIncludes { + mainboard.WriteString("#include <" + include + ">\n") + } + mainboard.WriteString("\n") + if MainboardInit != "" { + mainboard.WriteString(`static void mainboard_init(struct device *dev) +{ +` + MainboardInit + "}\n\n") + } + if MainboardInit != "" || MainboardEnable != "" { + mainboard.WriteString("static void mainboard_enable(struct device *dev)\n{\n") + if MainboardInit != "" { + mainboard.WriteString("\tdev->ops->init = mainboard_init;\n\n") + } + mainboard.WriteString(MainboardEnable) + mainboard.WriteString("}\n\n") + mainboard.WriteString(`struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + } + } + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + fixme := "" + + if dmi.IsLaptop { + bi.WriteString("Category: laptop\n") + } else { + bi.WriteString("Category: desktop\n") + fixme += "check category, " + } + + missing := "ROM package, ROM socketed" + + if ROMProtocol != "" { + fmt.Fprintf(bi, "ROM protocol: %s\n", ROMProtocol) + } else { + missing += ", ROM protocol" + } + + if FlashROMSupport != "" { + fmt.Fprintf(bi, "Flashrom support: %s\n", FlashROMSupport) + } else { + missing += ", Flashrom support" + } + + missing += ", Release year" + + if fixme != "" { + fmt.Fprintf(bi, "FIXME: %s, put %s\n", fixme, missing) + } else { + fmt.Fprintf(bi, "FIXME: put %s\n", missing) + } + + if ROMSizeKB == 0 { + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this" + } else { + KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true + } + + makeKconfig(ctx) + makeKconfigName(ctx) + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + for _, define := range DSDTDefines { + if define.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + } + dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") + } + + Add_gpl(dsdt) + dsdt.WriteString( + ` +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Device (\_SB.PCI0) + { +`) + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } +} +`) + + if IGDEnabled { + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; +`) + } +} diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go new file mode 100644 index 00000000..7c921093 --- /dev/null +++ b/util/autoport/rce823.go @@ -0,0 +1,39 @@ +package main + +import "fmt" + +type rce823 struct { + variant string +} + +func (r rce823) Scan(ctx Context, addr PCIDevData) { + if addr.Dev == 0 && addr.Func == 0 { + cur := DevTreeNode{ + Chip: "drivers/ricoh/rce822", + Comment: "Ricoh cardreader", + Registers: map[string]string{ + + "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1), + "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false}, + }, + } + PutPCIChip(addr, cur) + } + PutPCIDev(addr, "Ricoh SD card reader") + KconfigBool["DRIVERS_RICOH_RCE822"] = true +} + +func init() { + RegisterPCI(0x1180, 0xe822, rce823{}) + RegisterPCI(0x1180, 0xe823, rce823{}) +} diff --git a/util/autoport/readme.md b/util/autoport/readme.md new file mode 100644 index 00000000..b546120f --- /dev/null +++ b/util/autoport/readme.md @@ -0,0 +1,457 @@ +# Porting coreboot using autoport + +## Supported platforms + +### Chipset +For any Sandy Bridge or Ivy Bridge platform the generated result should +be bootable, possibly with minor fixes. + +### EC / SuperIO +EC support is likely to work on Intel-based thinkpads. Other laptops are +likely to miss EC support. SuperIO support on desktops is more likely to +work out of the box than any EC. + +## How to use autoport + +Enable as many devices as possible in the firmware setup of your system. +This is useful to detect as many devices as possible and make the port +more complete, as disabled devices cannot be detected. + +Boot into target machine under any Linux-based distribution and install +the following tools on it: +* `gcc` +* `golang` +* `lspci` +* `dmidecode` +* `acpidump` (part of `acpica` on some distros) + +Clone the coreboot tree and `cd` into it. For more detailed steps, refer +to Rookie Guide, Lesson 1. Afterwards, run these commands: + + cd util/ectool + make + cd ../inteltool + make + cd ../superiotool + make + cd ../autoport + go build + sudo ./autoport --input_log=logs --make_logs --coreboot_dir=../.. + + Note: in case you have problems getting gcc and golang on the target + machine, you can compile the utilities on another computer and copy + the binaries to the target machine. You will still need the other + listed programs on the target machine, but you may place them in the + same directory as autoport. + +Check for unknown detected PCI devices, e.g.: + + Unknown PCI device 8086:0085, assuming removable + +If autoport says `assuming removable`, you are fine. If it doesn't, +you may want to add the relevant PCI IDs to autoport. Run `lspci -nn` +and check which device this is using the PCI ID. Devices which are not +part of the chipset, such as GPUs or network cards, can be considered +removable, whereas devices inside the CPU or the PCH such as integrated +GPUs and bus controllers (SATA, USB, LPC, SMBus...) are non-removable. + +Your board has now been added to the tree. However, do not flash it +in its current state. It can brick your machine. Instead, keep this +new port and the logs from `util/autoport/logs` somewhere safe. The +following steps will back up your current firmware, which is always +recommended, since coreboot may not boot on the first try. + +Disassemble your computer and find the flash chip(s). Since there could be +more than one, this guide will refer to "flash chips" as one or more chips. +Refer to as a reference. The flash chip is +usually in a `SOIC-8` (2x4 pins, 200mil) or `SOIC-16` (2x8 pins) package. As +it can be seen on flashrom's wiki, the former package is like any other 8-pin +chip on the mainboard, but it is slightly larger. The latter package is much +easier to locate. Always make sure it is a flash chip by looking up what its +model, printed on it, refers to. + +There may be a smaller flash chip for the EC on some laptops, and other chips +such as network cards may use similar flash chips. These should be left as-is. +If in doubt, ask! + +Once located, use an external flasher to read the flash chips with `flashrom -r`. +Verify with `flashrom -v` several times that reading is consistent. If it is not, +troubleshoot your flashing setup. Save the results somewhere safe, preferably on +media that cannot be easily overwritten and on several devices. You may need this +later. The write process erases the flash chips first, and erased data on a flash +chip is lost for a very long time, usually forever! + +Compile coreboot for your ported mainboard with some console enabled. The most +common ones are EHCI debug, serial port and SPI flash console as a last resort. +If your system is a laptop and has a dedicated video card, you may need to add +a video BIOS (VBIOS) to coreboot to be able to see any video output. Desktop +video cards, as well as some MXM video cards, have this VBIOS on a flash chip +on the card's PCB, so this step is not necessary for them. + +Flash coreboot on the machine. On recent Intel chipsets, the flash space is split +in several regions. Only the one known as "BIOS region" should be flashed. If +there is only one flash chip present, this is best done by adding the `--ifd` +and `-i bios` parameters flashrom has (from v1.0 onwards) to specify what flash +descriptor region it should operate on. If the ME (Management Engine) region is +not readable, which is the case on most systems, use the `--noverify-all` +parameter as well. + +For systems with two flash chips, this is not so easy. It is probably better to +ask in coreboot or flashrom communication channels, such as via IRC or on the +mailing lists. + +Once flashed, try to boot. Anything is possible. If a log is generated, save it +and use it to address any issues. See the next section for useful information. +Find all the sections marked with `FIXME` and correct them. + +Send your work to review.coreboot.org. I mean it, your effort is very appreciated. +Refer to Rookie Guide, Lesson 2 for instructions on how to submit a patch. + +## Manual fixes +### SPD +In order to initialize the RAM memory, coreboot needs to know its timings, which vary between +modules. Socketed RAM has a small EEPROM chip, which is accessible via SMBus and contains the +timing data. This data is usually known as SPD. Unfortunately, the SMBus addresses may not +correlate with the RAM slots and cannot always be detected automatically. The address map is +encoded in function `mainboard_get_spd` in `romstage.c`. By default, autoport uses the most +common map `0x50, 0x51, 0x52, 0x53` on everything except for Lenovo systems, which are known +to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map, the easiest way is to boot +on the vendor firmware with just one module in channel 0, slot 0, and check the SMBus address +the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: + + $ sudo modprobe i2c-dev + $ sudo modprobe i2c-i801 + $ sudo i2cdetect -l + i2c-0 i2c i915 gmbus ssc I2C adapter + i2c-1 i2c i915 gmbus vga I2C adapter + i2c-2 i2c i915 gmbus panel I2C adapter + i2c-3 i2c i915 gmbus dpc I2C adapter + i2c-4 i2c i915 gmbus dpb I2C adapter + i2c-5 i2c i915 gmbus dpd I2C adapter + i2c-6 i2c DPDDC-B I2C adapter + i2c-7 i2c DPDDC-C I2C adapter + i2c-8 i2c DPDDC-D I2C adapter + i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter + + $ sudo i2cdetect 9 + WARNING! This program can confuse your I2C bus, cause data loss and worse! + I will probe file /dev/i2c-9. + I will probe address range 0x03-0x77. + Continue? [Y/n] y + 0 1 2 3 4 5 6 7 8 9 a b c d e f + 00: -- -- -- -- -- 08 -- -- -- -- -- -- -- + 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 20: -- -- -- -- 24 -- -- -- -- -- -- -- -- -- -- -- + 30: 30 31 -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 50: 50 -- -- -- 54 55 56 57 -- -- -- -- 5c 5d 5e 5f + 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 70: -- -- -- -- -- -- -- -- + +Make sure to replace the `9` on the last command with the bus number for SMBus on +your system. Here, there is a module at address `0x50`. Since only one module was +installed on the first slot of the first channel, we know the first position of +the SPD array must be `0x50`. After testing all the slots, your `mainboard_get_spd` +should look similar to this: + + void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); + } + +Note that there should be one line per memory slot on the mainboard. + +Note: slot labelling may be missing or unreliable. Use `inteltool` to see +which slots have modules in them. + +This procedure is ideal, if your RAM is socketed. If you have soldered RAM, +remove any socketed memory modules and check if any EEPROM appears on SMBus. +If this is the case, you can proceed as if the RAM was socketed. However, +you may have to guess some entries if there multiple EEPROMs appear. + +Most of the time, soldered RAM does not have an EEPROM. Instead, the SPD data is +inside the main flash chip where the firmware is. If this is the case, you need +to generate the SPD data to use with coreboot. Look at `inteltool.log`. There +should be something like this: + + /* SPD matching current mode: */ + /* CH0S0 */ + 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 + 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 + 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 + 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 + 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + /* CH1S0 */ + 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 + 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 + 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 + 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d 17 + 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +This is not a full-fledged SPD dump, as it only lists +the currently-used speed configuration, and lacks info +such as a serial number, vendor and model. Use `xxd` +to create a binary file with this SPD data: + + $ cat | xxd -r > spd.bin <= 128) + memcpy(&spd[0], spd_file, 128); + + /* C1S0 is a physical slot. */ + read_spd(&spd[2], 0x52); + } + +If several slots are soldered there are two ways to handle them: + +* If all use the same SPD data, use the same file for all the slots. Do + not forget to copy the data on all the array elements that need it. +* If they use different data, use several files. + +If memory initialization is not working, in particular write training (timB) +on DIMM's second rank fails, try enabling rank 1 mirroring, which can't be +detected by inteltool. It is described by SPD field "Address Mapping from Edge +Connector to DRAM", byte `63` (`0x3f`). Bit 0 describes Rank 1 Mapping, +0 = standard, 1 = mirrored; set it to 1. Bits 1-7 are reserved. + +### `board_info.txt` + +`board_info.txt` is a text file used in the board status page to list all +the supported boards and their specifications. Most of the information +cannot be detected by autoport. Common entries are: + +* `ROM package`, `ROM protocol` and `ROM socketed`: + These refer to the flash chips you found earlier. You can visit + for more information. + +* `Release year`: Use the power of Internet to find that information. +* `Category`: This describes the type of mainboard you have. + Valid categories are: + * `desktop`. Desktops and workstations. + * `server`. Servers. + * `laptop`. Laptops, notebooks and netbooks. + * `half`. Embedded / PC/104 / Half-size boards. + * `mini`. Mini-ITX / Micro-ITX / Nano-ITX + * `settop`. Set-top-boxes / Thin clients. + * `eval`. Development / Evaluation Boards. + * `sbc`. Single-Board computer. + * `emulation`: Virtual machines and emulators. May require especial care + as they often behave differently from real counterparts. + * `misc`. Anything not fitting the categories above. Not recommended. + +* `Flashrom support`: This means whether the internal programmer is usable. + If flashing coreboot internally works, this should be set to `y`. Else, + feel free to investigate why it is not working. + +### `USBDEBUG_HCD_INDEX` + +Which controller the most easily accessible USB debug port is. On Intel, +1 is for `00:1d.0` and 2 is for `00:1a.0` (yes, it's reversed). Refer to + for more info. + +If you are able to use EHCI debug without setting the HCD index manually, +this is correct. + +### `BOARD_ROMSIZE_KB_2048` + +This parameter refers to the total size of the flash chips coreboot will be in. +This value must be correct for S3 resume to work properly. This parameter also +defines the size of the generated coreboot image, but that is not a major issue +since tools like `dd` can be used to cut fragments of a coreboot image to flash +on smaller chips. + +This should be detected automatically, but it may not be detected properly in +some cases. If it was not detected, put the correct total size here to serve +as a sane default when configuring coreboot. + +### `DRAM_RESET_GATE_GPIO` + +When the computer is suspended to RAM (ACPI S3), the RAM reset signal must not +reach the RAM modules. Otherwise, the computer will not resume and any opened +programs will be lost. This is done by powering down a MOSFET, which disconnects +the reset signal from the RAM modules. Most manufacturers put this gate on GPIO +60 but Lenovo is known to put it on GPIO 10. If suspending and resuming works, +this value is correct. This can also be determined from the board's schematics. + +## GNVS + +`mainboard_fill_gnvs` sets values in GNVS, which then ACPI makes use of for +various power-related functions. Normally, there is no need to modify it +on laptops (desktops have no "lid"!) but it makes sense to proofread it. + +## `gfx.ndid` and `gfx.did` + +Those describe which video outputs are declared in ACPI tables. +Normally, there is no need to have these values, but if you miss some +non-standard video output, you can declare it there. Bit 31 is set to +indicate the presence of the output. Byte 1 is the type and byte 0 is +used for disambigution so that ID composed of byte 1 and 0 is unique. + +Types are: +* 1 = VGA +* 2 = TV +* 3 = DVI +* 4 = LCD + +## `c*_acpower` and `c*_battery` + +Which mwait states to match to which ACPI levels. Normally, there is no +need to modify anything unless your device has very special power saving +requirements. + +## `install_intel_vga_int15_handler` + +This is used with the Intel VGA BIOS, which is not the default option. +It is more error-prone than open-source graphics initialization, so do +not bother with this until your mainboard boots. This is a function +which takes four parameters: +1. Which type of LCD panel is connected. +2. Panel fit. +3. Boot display. +4. Display type. + +Refer to `src/drivers/intel/gma/int15.h` to see which values can be used. +For desktops, there is no LCD panel directly connected to the Intel GPU, +so the first parameter should be `GMA_INT15_ACTIVE_LFP_NONE`. On other +mainboards, it depends. + +## CMOS options + +Due to the poor state of CMOS support in coreboot, autoport does not +support it and this probably won't change until the format in the tree +improves. If you really care about CMOS options: + +* Create files `cmos.layout` and `cmos.default` +* Enable `HAVE_OPTION_TABLE` and `HAVE_CMOS_DEFAULT` in `Kconfig` + +## EC (lenovo) + +You need to set `has_keyboard_backlight` (backlit keyboard like X230), +`has_power_management_beeps` (optional beeps when e.g. plugging the cord +in) and `has_uwb` (third MiniPCIe slot) in accordance to functions available +on your machine + +In rare cases autoport is unable to detect GPE. You can detect it from +dmesg or ACPI tables. Look for line in dmesg like + + ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 + +This means that GPE is `0x11` in ACPI notation. This is the correct +value for `THINKPAD_EC_GPE`. To get the correct value for `GPE_EC_SCI` +you need to substract `0x10`, so value for it is `1`. + +The pin used to wake the machine from EC is guessed. If your machine doesn't +wake on lid open and pressing of Fn, change `GPE_EC_WAKE`. + +Keep `GPE_EC_WAKE` and `GPE_EC_SCI` in sync with `gpi*_routing`. +`gpi*_routing` matching `GPE_EC_WAKE` or `GPE_EC_SCI` is set to `2` +and all others are absent. + +If your dock has LPC wires or needs some special treatement you may +need to add codes to initialize the dock and support code to +DSDT. See the `init_dock()` for `x60`, `x200` or `x201`. + +## EC (generic laptop) + +Almost any laptop has an embedded controller. In a nutshell, it's a +small, low-powered computer designed to be used on laptops. Exact +functionality differs between machines. Its main functions include: + +* Control of power and rfkill to different component +* Keyboard (PS/2) interface implementation +* Battery, AC, LID and thermal information exporting +* Hotkey support + +autoport automatically attempts to restore the dumped config but it +may or may not work and may even lead to a hang or powerdown. If your +machine stops at `Replaying EC dump ...` try commenting EC replay out + +autoport tries to detect if machine has PS/2 interface and if so calls +`pc_keyboard_init` and exports relevant ACPI objects. If detection fails +you may have to add them yourself + +ACPI methods `_PTS` (prepare to sleep) and `_WAK` (wake) are executed +when transitioning to sleep or wake state respectively. You may need to +add power-related calls there to either shutdown some components or to +add a workaround to stop giving OS thermal info until next refresh. + +For exporting the battery/AC/LID/hotkey/thermal info you need to write +`acpi/ec.asl`. For an easy example look into `apple/macbook21` or +`packardbell/ms2290`. For information about needed methods consult +relevant ACPI specs. Tracing which EC events can be done using +[dynamic debug](https://wiki.ubuntu.com/Kernel/Reference/ACPITricksAndTips) + +EC GPE needs to be routed to SCI in order for OS in order to receive +EC events like "hotkey X pressed" or "AC plugged". autoport attempts +to detect GPE but in rare cases may fail. You can detect it from +dmesg or ACPI tables. Look for line in dmesg like + + ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 + +This means that GPE is `0x11` in ACPI notation. This is the correct +value for `_GPE`. + +Keep GPE in sync with `gpi*_routing`. +`gpi*_routing` matching `GPE - 0x10` is set to `2` +and all others are absent. If EC has separate wake pin +then this GPE needs to be routed as well diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 00000000..7e9e8145 --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,47 @@ +package main + +import "fmt" +import "os" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + if pciDev.PCIAddr.Bus != 0 { + fmt.Printf("Unknown PCI device %04x:%04x, assuming removable\n", + pciDev.PCIVenID, pciDev.PCIDevID) + continue + } + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x", + pciDev.PCIVenID, pciDev.PCIDevID)} + } + dev.Scan(ctx, pciDev) + } + if SouthBridge == nil { + fmt.Println("Could not detect southbridge. Aborting!") + os.Exit(1) + } + dmi := ctx.InfoSource.GetDMI() + if !dmi.IsLaptop { + NoEC(ctx) + } else if dmi.Vendor == "LENOVO" { + LenovoEC(ctx) + } else { + FIXMEEC(ctx) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 00000000..bd7f0f0c --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,93 @@ +package main + +import "fmt" + +type sandybridgemc struct { +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Comment: "FIXME: GPU registers may not always apply.", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), + "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), + "gfx": fmt.Sprintf("GMA_STATIC_DISPLAYS(%d)", (inteltool.IGD[0xc6200] >> 12) & 1), + }, + Children: []DevTreeNode{ + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX some configs are unsupported. */ + KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true + KconfigBool["USE_NATIVE_RAMINIT"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0100, sandybridgemc{}) + RegisterPCI(0x8086, 0x0104, sandybridgemc{}) + RegisterPCI(0x8086, 0x0150, sandybridgemc{}) + RegisterPCI(0x8086, 0x0154, sandybridgemc{}) + RegisterPCI(0x8086, 0x0158, sandybridgemc{}) + for _, id := range []uint16{ + 0x0102, 0x0106, 0x010a, + 0x0112, 0x0116, 0x0122, 0x0126, + 0x0152, 0x0156, 0x0162, 0x0166, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } +} From 6ebab10caa5be6fc1cfd244e745851687d4bd70d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 27 Mar 2024 01:19:39 +0000 Subject: [PATCH 0008/1319] safer, simpler error handling in lbmk in shell scripts, a function named the same as a program included in the $PATH will override that program. for example, you could make a function called ls() and this would override the standand "ls". in lbmk, a part of it was first trying to run the "fail" command, deferring to "err", because some scripts call fail() which does some minor cleanup before calling err. in most cases, fail() is not defined, and it's possible that the user could have a program called "fail" in their $PATH, the behaviour of which we could not determine, and it could have disastrous effects. lbmk error handling has been re-engineered in such a way that the err function is defined in a variable, which defaults to err_ which calls err_, so defined under include/err.sh. in functions that require cleanup prior to error handling, a fail() function is still defined, and err is overridden, thus: err="fail" this change has made xx_() obsolete, so now only x_ is used. the x_ function is a wrapper that can be used to run a command and exit with non-zero status (from lbmk) if the command fails. the xx_ command did the same thing, but called fail() which would have called err(); now everything is $err example: rm -f "$filename" || err "could not delete file" this would now be: rm -f "$filename" || $err "could not delete file" overriding of err= must be done *after* including err.sh. for example: err="fail" . "include/err.sh" ^ this is wrong. instead, one must do: . "include/err.sh" err="fail" this is because err is set as a global variable under err.sh the new error handling is much cleaner, and safer. it also reduces the chance of mistakes such as: calling err when you meant to call fail. this is because the standard way is now to call $err, so you set err="fail" at the top of the script and all is well. Signed-off-by: Leah Rowe --- build | 33 +++++++-------- include/err.sh | 25 ++++-------- include/git.sh | 42 +++++++++---------- include/mrc.sh | 22 +++++----- include/option.sh | 9 ++--- script/build/roms | 36 ++++++++--------- script/build/serprog | 6 +-- script/update/release | 92 +++++++++++++++++++++--------------------- script/update/trees | 30 +++++++------- script/vendor/download | 54 ++++++++++++------------- script/vendor/inject | 44 ++++++++++---------- 11 files changed, 191 insertions(+), 202 deletions(-) diff --git a/build b/build index 214cec30..38d1694c 100755 --- a/build +++ b/build @@ -14,6 +14,7 @@ export LC_ALL=C . "include/option.sh" eval "$(setvars "" option aur_notice tmpdir)" +err="fail" tmpdir_was_set="y" set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" @@ -35,10 +36,10 @@ buildpath="./script/${linkname}" main() { - xx_ id -u 1>/dev/null 2>/dev/null - [ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help" + x_ id -u 1>/dev/null 2>/dev/null + [ $# -lt 1 ] && $err "Too few arguments. Try: ${0} help" - [ "$1" = "dependencies" ] && xx_ install_packages $@ && lbmk_exit 0 + [ "$1" = "dependencies" ] && x_ install_packages $@ && lbmk_exit 0 for cmd in initcmd check_git check_project git_init excmd; do eval "${cmd} \$@" @@ -48,7 +49,7 @@ main() initcmd() { - [ "$(id -u)" != "0" ] || fail "this command as root is not permitted" + [ "$(id -u)" != "0" ] || $err "this command as root is not permitted" check_project @@ -69,14 +70,14 @@ install_packages() printf "You must specify a distro, namely:\n" 1>&2 printf "Look at files under config/dependencies/\n" 1>&2 printf "Example: ./build dependencies debian\n" 1>&2 - fail "install_packages: target not specified" + $err "install_packages: target not specified" fi - [ -f "config/dependencies/${2}" ] || fail "Unsupported target" + [ -f "config/dependencies/${2}" ] || $err "Unsupported target" . "config/dependencies/${2}" - xx_ ${pkg_add} ${pkglist} + x_ ${pkg_add} ${pkglist} [ -z "${aur_notice}" ] && return 0 printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2 } @@ -85,24 +86,24 @@ install_packages() # lbmk can be run from lbmk.git, or an archive. git_init() { - [ -L ".git" ] && fail "Reference .git is a symlink" + [ -L ".git" ] && $err "Reference .git is a symlink" [ -e ".git" ] && return 0 eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)" - git init || fail "${PWD}: cannot initialise Git repository" - git add -A . || fail "${PWD}: cannot add files to Git repository" + git init || $err "${PWD}: cannot initialise Git repository" + git add -A . || $err "${PWD}: cannot add files to Git repository" git commit -m "${projectname} ${version}" --date "${cdate}" \ --author="lbmk " || \ - fail "$PWD: can't commit ${projectname}/${version}, date $cdate" + $err "$PWD: can't commit ${projectname}/${version}, date $cdate" git tag -a "${version}" -m "${projectname} ${version}" || \ - fail "${PWD}: cannot git-tag ${projectname}/${version}" + $err "${PWD}: cannot git-tag ${projectname}/${version}" } excmd() { lbmkcmd="${buildpath}/${option}" - [ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help" - shift 1; "$lbmkcmd" $@ || fail "excmd: ${lbmkcmd} ${@}" + [ -f "${lbmkcmd}" ] || $err "Invalid command. Run: ${linkpath} help" + shift 1; "$lbmkcmd" $@ || $err "excmd: ${lbmkcmd} ${@}" } usage() @@ -131,14 +132,14 @@ mkversion() lbmk_exit() { - tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir" + tmp_cleanup || err_ "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir" exit $1 } fail() { tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2 - err "${1}" + err_ "${1}" } tmp_cleanup() diff --git a/include/err.sh b/include/err.sh index cab81d02..5b66c999 100755 --- a/include/err.sh +++ b/include/err.sh @@ -2,19 +2,10 @@ # SPDX-FileCopyrightText: 2022, 2023 Leah Rowe version=""; versiondate=""; projectname=""; _nogit="" +err="err_" x_() { - [ $# -lt 1 ] || ${@} || err_exit err ${@} -} -xx_() { - [ $# -lt 1 ] || ${@} || err_exit fail ${@} -} - -err_exit() -{ - _fail="${1}" && shift 1 - echo "Non-zero exit: $@" - $_fail "Unhandled error" + [ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0 } check_git() @@ -30,8 +21,7 @@ check_git() git_err() { printf "You need to set git name/email, like so:\n%s\n\n" "$1" 1>&2 - fail "Git name/email not configured" || \ - err "Git name/email not configured" + $err "Git name/email not configured" } check_project() @@ -49,9 +39,8 @@ check_project() --pretty='%ct' HEAD)" || versiondate="${versiondate_}" for p in projectname version versiondate; do - eval "[ -n \"\$$p\" ] || fail \"$p unset\" || err \"$p unset\"" - p_="x_ printf \"%s\\n\" \"\$$p\" > $p" - eval "x$p_ || $p_" + eval "[ -n \"\$$p\" ] || $err \"$p unset\"" + eval "x_ printf \"%s\\n\" \"\$$p\" > $p" done export LOCALVERSION="-${projectname}-${version%%-*}" } @@ -59,7 +48,7 @@ check_project() setvars() { _setvars="" - [ $# -lt 2 ] && err "setvars: too few arguments" + [ $# -lt 2 ] && $err "setvars: too few arguments" val="${1}" && shift 1 for var in $@; do _setvars="${var}=\"${val}\"; ${_setvars}" @@ -67,7 +56,7 @@ setvars() printf "%s\n" "${_setvars% }" } -err() +err_() { printf "ERROR %s: %s\n" "${0}" "${1}" 1>&2 exit 1 diff --git a/include/git.sh b/include/git.sh index 1fb8046d..5c456706 100755 --- a/include/git.sh +++ b/include/git.sh @@ -29,7 +29,7 @@ fetch_from_upstream() fetch_config() { - rm -f "${cfgsdir}/"*/seen || err "fetch_config ${cfgsdir}: !rm seen" + rm -f "${cfgsdir}/"*/seen || $err "fetch_config ${cfgsdir}: !rm seen" eval "$(setvars "" xtree tree_depend)" while true; do eval "$(setvars "" rev tree)" @@ -44,12 +44,12 @@ fetch_config() load_target_config() { - [ -f "$cfgsdir/$1/target.cfg" ] || err "$1: target.cfg missing" + [ -f "$cfgsdir/$1/target.cfg" ] || $err "$1: target.cfg missing" [ -f "${cfgsdir}/${1}/seen" ] && \ - err "${_xm} check: infinite loop in tree definitions" + $err "${_xm} check: infinite loop in tree definitions" - . "$cfgsdir/$1/target.cfg" || err "load_target_config !$cfgsdir/$1" - touch "$cfgsdir/$1/seen" || err "load_config $cfgsdir/$1: !mk seen" + . "$cfgsdir/$1/target.cfg" || $err "load_target_config !$cfgsdir/$1" + touch "$cfgsdir/$1/seen" || $err "load_config $cfgsdir/$1: !mk seen" } prepare_new_tree() @@ -57,7 +57,7 @@ prepare_new_tree() printf "Creating %s tree %s (%s)\n" "$project" "$tree" "$_target" cp -R "src/${project}/${project}" "${tmpgit}" || \ - err "prepare_new_tree ${project}/${tree}: can't make tmpclone" + $err "prepare_new_tree ${project}/${tree}: can't make tmpclone" git_prep "$PWD/$cfgsdir/$tree/patches" "src/$project/$tree" "update" } @@ -65,15 +65,15 @@ fetch_project_repo() { eval "$(setvars "" xtree tree_depend)" - scan_config "${project}" "config/git" "err" - [ -z "${loc+x}" ] && err "fetch_project_repo $project: loc not set" - [ -z "${url+x}" ] && err "fetch_project_repo $project: url not set" + scan_config "${project}" "config/git" + [ -z "${loc+x}" ] && $err "fetch_project_repo $project: loc not set" + [ -z "${url+x}" ] && $err "fetch_project_repo $project: url not set" clone_project [ -z "${depend}" ] || for d in ${depend} ; do x_ ./update trees -f ${d} done - rm -Rf "${tmpgit}" || err "fetch_repo: !rm -Rf ${tmpgit}" + rm -Rf "${tmpgit}" || $err "fetch_repo: !rm -Rf ${tmpgit}" } clone_project() @@ -86,7 +86,7 @@ clone_project() fi git clone $url "$tmpgit" || git clone $bkup_url "$tmpgit" \ - || err "clone_project: could not download ${project}" + || $err "clone_project: could not download ${project}" git_prep "$PWD/config/$project/patches" "$loc" } @@ -95,26 +95,26 @@ git_prep() _patchdir="$1" _loc="$2" - [ -z "${rev+x}" ] && err "git_prep $_loc: rev not set" - git -C "$tmpgit" reset --hard $rev || err "git -C $_loc: !reset $rev" - git_am_patches "$tmpgit" "$_patchdir" || err "!am $_loc $_patchdir" + [ -z "${rev+x}" ] && $err "git_prep $_loc: rev not set" + git -C "$tmpgit" reset --hard $rev || $err "git -C $_loc: !reset $rev" + git_am_patches "$tmpgit" "$_patchdir" || $err "!am $_loc $_patchdir" if [ "$project" != "coreboot" ] || [ $# -gt 2 ]; then [ ! -f "$tmpgit/.gitmodules" ] || git -C "$tmpgit" submodule \ - update --init --checkout || err "git_prep $_loc: !submod" + update --init --checkout || $err "git_prep $_loc: !submod" if [ "$project" = "coreboot" ] && [ -n "$xtree" ] && \ [ "$xtree" != "$tree" ]; then ( - cd "$tmpgit/util" || err "prep $_loc: !cd $tmpgit/util" - rm -Rf crossgcc || err "prep $_loc: !rm xgcc" + cd "$tmpgit/util" || $err "prep $_loc: !cd $tmpgit/util" + rm -Rf crossgcc || $err "prep $_loc: !rm xgcc" ln -s "../../$xtree/util/crossgcc" crossgcc || \ - err "prep $_loc: can't create xgcc symlink" - ) || err "prep $_loc: can't create xgcc symlink" + $err "prep $_loc: can't create xgcc symlink" + ) || $err "prep $_loc: can't create xgcc symlink" fi fi [ "$_loc" = "${_loc%/*}" ] || x_ mkdir -p "${_loc%/*}" - mv "$tmpgit" "$_loc" || err "git_prep: !mv $tmpgit $_loc" + mv "$tmpgit" "$_loc" || $err "git_prep: !mv $tmpgit $_loc" [ -n "$xtree" ] && [ ! -d "src/coreboot/$xtree" ] && \ x_ ./update project trees -f coreboot "$xtree"; return 0 } @@ -123,7 +123,7 @@ git_am_patches() { for _patch in "$2/"*; do [ -L "$_patch" ] || [ ! -f "$_patch" ] || git -C "$1" am \ - "$_patch" || err "git_am $1 $2: !git am $_patch"; continue + "$_patch" || $err "git_am $1 $2: !git am $_patch"; continue done for _patches in "$2/"*; do [ ! -L "$_patches" ] && [ -d "$_patches" ] && \ diff --git a/include/mrc.sh b/include/mrc.sh index 32c68a83..901a3c3b 100755 --- a/include/mrc.sh +++ b/include/mrc.sh @@ -14,7 +14,7 @@ extract_ref() # but refcode is downloaded alongside mrc. in cases where lbmk # erred, downloading only mrc, we must ensure downloading refcode [ -n "$CONFIG_MRC_FILE" ] || \ - err "extract_ref $board: CONFIG_MRC_FILE not defined" + $err "extract_ref $board: CONFIG_MRC_FILE not defined" # the extract_mrc function actually downloads the refcode fetch "mrc" "$MRC_url" "$MRC_url_bkup" "$MRC_hash" "$CONFIG_MRC_FILE" @@ -22,9 +22,9 @@ extract_ref() extract_mrc() { - [ -z "$MRC_board" ] && err "extract_mrc $MRC_hash: MRC_board not set" + [ -z "$MRC_board" ] && $err "extract_mrc $MRC_hash: MRC_board not set" [ -z "${CONFIG_MRC_FILE}" ] && \ - err "extract_mrc $MRC_hash: CONFIG_MRC_FILE not set" + $err "extract_mrc $MRC_hash: CONFIG_MRC_FILE not set" SHELLBALL="chromeos-firmwareupdate-${MRC_board}" @@ -32,10 +32,10 @@ extract_mrc() x_ cd "${appdir}" extract_partition "${MRC_url##*/}" extract_archive "${SHELLBALL}" . - ) || err "mrc download/extract failure" + ) || $err "mrc download/extract failure" "${cbfstool}" "${appdir}/"bios.bin extract -n mrc.bin \ - -f "$_dest" -r RO_SECTION || err "extract_mrc: cbfstool $_dest" + -f "$_dest" -r RO_SECTION || $err "extract_mrc: cbfstool $_dest" [ -n "$CONFIG_REFCODE_BLOB_FILE" ] && extract_refcode; return 0 } @@ -51,10 +51,10 @@ extract_partition() dd if="${1%.zip}" of="root-a.ext2" bs=1024 \ skip=$(( ${START} / 1024 )) count=$(( ${SIZE} / 1024 )) || \ - err "extract_partition, dd ${1%.zip}, root-a.ext2" + $err "extract_partition, dd ${1%.zip}, root-a.ext2" printf "cd /usr/sbin\ndump chromeos-firmwareupdate ${SHELLBALL}\nquit" \ - | debugfs "root-a.ext2" || err "can't extract shellball" + | debugfs "root-a.ext2" || $err "can't extract shellball" } extract_refcode() @@ -66,16 +66,16 @@ extract_refcode() # incompatible with older versions before coreboot 4.14, # so we need coreboot 4.13 cbfstool for certain refcode files [ -n "$cbfstoolref" ] || \ - err "extract_refcode $board: MRC_refcode_cbtree not set" + $err "extract_refcode $board: MRC_refcode_cbtree not set" mkdir -p "${_refdest%/*}" || \ - err "extract_refcode $board: !mkdir -p ${_refdest%/*}" + $err "extract_refcode $board: !mkdir -p ${_refdest%/*}" "$cbfstoolref" "$appdir/bios.bin" extract \ -m x86 -n fallback/refcode -f "$_refdest" -r RO_SECTION \ - || err "extract_refcode $board: !cbfstoolref $_refdest" + || $err "extract_refcode $board: !cbfstoolref $_refdest" # enable the Intel GbE device, if told by offset MRC_refcode_gbe [ -z "$MRC_refcode_gbe" ] || dd if="config/ifd/hp820g2/1.bin" \ of="$_refdest" bs=1 seek=$MRC_refcode_gbe count=1 conv=notrunc || \ - err "extract_refcode $_refdest: byte $MRC_refcode_gbe"; return 0 + $err "extract_refcode $_refdest: byte $MRC_refcode_gbe"; return 0 } diff --git a/include/option.sh b/include/option.sh index 2284fb0b..64442d15 100755 --- a/include/option.sh +++ b/include/option.sh @@ -43,10 +43,9 @@ scan_config() { awkstr=" /\{.*${1}.*}{/ {flag=1;next} /\}/{flag=0} flag { print }" confdir="${2}" - _fail="${3}" revfile="$(mktemp -t sources.XXXXXXXXXX)" cat "${confdir}/"* > "${revfile}" || \ - "${_fail}" "scan_config ${confdir}: Cannot concatenate files" + $err "scan_config ${confdir}: Cannot concatenate files" while read -r line ; do set ${line} 1>/dev/null 2>/dev/null || : if [ "${1%:}" = "depend" ]; then @@ -57,7 +56,7 @@ scan_config() done << EOF $(eval "awk '${awkstr}' \"${revfile}\"") EOF - rm -f "$revfile" || "$_fail" "scan_config: Cannot remove tmpfile" + rm -f "$revfile" || $err "scan_config: Cannot remove tmpfile" } check_defconfig() @@ -81,6 +80,6 @@ handle_coreboot_utils() remkdir() { - rm -Rf "${1}" || err "remkdir: !rm -Rf \"${1}\"" - mkdir -p "${1}" || err "remkdir: !mkdir -p \"${1}\"" + rm -Rf "${1}" || $err "remkdir: !rm -Rf \"${1}\"" + mkdir -p "${1}" || $err "remkdir: !mkdir -p \"${1}\"" } diff --git a/script/build/roms b/script/build/roms index 9e7c69ee..a90e1daa 100755 --- a/script/build/roms +++ b/script/build/roms @@ -49,7 +49,7 @@ main() done [ "${all}" != "y" ] || boards=$(items config/coreboot) || \ - err "Cannot generate list of boards for building" + $err "Cannot generate list of boards for building" for x in ${boards}; do eval "$(setvars "n" ${pv}) $(setvars "" ${v})" @@ -62,7 +62,7 @@ main() targets="* bin/${board}\n${targets}" done - [ -z "${targets}" ] && err "No ROM images were compiled" + [ -z "${targets}" ] && $err "No ROM images were compiled" printf "\nROM images available in these directories:\n" eval "printf \"${targets}\"" printf "^^ ROM images available in these directories.\n\n" @@ -74,7 +74,7 @@ configure_target() { targetdir="${cfgsdir}/${board}" [ -f "${targetdir}/target.cfg" ] || \ - err "Missing target.cfg for target: ${board}" + $err "Missing target.cfg for target: ${board}" # Override the above defaults using target.cfg . "${targetdir}/target.cfg" @@ -84,7 +84,7 @@ configure_target() && [ "${grub_scan_disk}" != "ahci" ] && \ grub_scan_disk="both" - [ -z "$tree" ] && err "$board: tree not defined" + [ -z "$tree" ] && $err "$board: tree not defined" [ "${payload_memtest}" != "y" ] && payload_memtest="n" [ "${payload_grub_withseabios}" = "y" ] && payload_grub="y" @@ -101,7 +101,7 @@ configure_target() [ "${payload_uboot}" != "y" ] && \ for configfile in "${targetdir}/config/"*; do [ -e "${configfile}" ] || continue - err "target '${board}' defines no payload" + $err "target '${board}' defines no payload" done [ "$payload_uboot" != "n" ] && [ "$payload_uboot" != "y" ] && \ @@ -149,7 +149,7 @@ build_grub_payload() keymaps="${keymaps} ${keymapfile}" done [ -z "$_keyboard" ] || [ -f "$grubcfgsdir/keymap/$_keyboard.gkb" ] || \ - err "build_grub_payload: $_keyboard layout not defined" + $err "build_grub_payload: $_keyboard layout not defined" [ -n "$_keyboard" ] && keymaps="${grubcfgsdir}/keymap/${_keyboard}.gkb" [ -f "$grubelf" ] && return 0 [ -f "src/grub/grub-mkstandalone" ] || x_ ./update trees -b grub @@ -164,7 +164,7 @@ build_grub_payload() --install-modules="${grub_install_modules}" \ "/boot/grub/grub.cfg=${grubcfgsdir}/config/grub_memdisk.cfg" \ "/boot/grub/grub_default.cfg=${grubcfgsdir}/config/grub.cfg" || \ - err "could not generate grub.elf" + $err "could not generate grub.elf" } build_uboot_payload() @@ -175,12 +175,12 @@ build_uboot_payload() [ ! -f "${ubootelf}" ] && [ -f "${ubdir}/u-boot" ] && \ ubootelf="${ubdir}/u-boot" [ -f "${ubootelf}" ] && return 0 - err "Can't find u-boot build for board, $board"; + $err "Can't find u-boot build for board, $board"; } build_target_mainboard() { - rm -f "${romdir}/"* || err "!prepare, rm files, ${romdir}" + rm -f "${romdir}/"* || $err "!prepare, rm files, ${romdir}" for x in "normal" "vgarom" "libgfxinit"; do initmode="${x}" @@ -237,7 +237,7 @@ build_seabios_roms() x_ build_grub_roms "${t}" "seabios_withgrub" else t=$(mkSeabiosRom "${cbrom}" "fallback/payload") || \ - err "build_seabios_roms: cannot build tmprom" + $err "build_seabios_roms: cannot build tmprom" newrom="${romdir}/seabios_${board}_${initmode}_${displaymode}" [ "${initmode}" = "normal" ] && newrom="${romdir}/seabios" \ && newrom="${newrom}_${board}_${initmode}" @@ -256,13 +256,13 @@ build_grub_roms() if [ "$payload1" = "grub" ] && [ "$payload_grub_withseabios" = "y" ] then _tmpmvrom=$(mkSeabiosRom "$tmprom" "seabios.elf") || \ - err "build_grub_roms 1 $board: can't build tmprom" + $err "build_grub_roms 1 $board: can't build tmprom" x_ mv "$_tmpmvrom" "$tmprom" elif [ "$payload1" != "grub" ] && [ "$payload_seabios_withgrub" = "y" ] then grub_cbfs="img/grub2" _tmpmvrom=$(mkSeabiosRom "$tmprom" fallback/payload) || \ - err "build_grub_roms 2 $board: can't build tmprom" + $err "build_grub_roms 2 $board: can't build tmprom" x_ mv "$_tmpmvrom" "$tmprom" fi @@ -276,16 +276,16 @@ build_grub_roms() backgroundfile="config/grub/background/${grub_background}" "${cbfstool}" "${tmprom}" add -f ${backgroundfile} \ -n background.png -t raw || \ - err "insert background, ${backgroundfile}" + $err "insert background, ${backgroundfile}" fi tmpcfg=$(mktemp -t coreboot_rom.XXXXXXXXXX) printf "set grub_scan_disk=\"%s\"\n" "$grub_scan_disk" >"$tmpcfg" \ - || err "set grub_scandisk, $grub_scan_disk, $tmpcfg" + || $err "set grub_scandisk, $grub_scan_disk, $tmpcfg" [ "${grub_scan_disk}" = "both" ] || \ x_ "$cbfstool" "$tmprom" add -f "$tmpcfg" -n scan.cfg -t raw printf "set timeout=%s\n" "${grub_timeout}" > "${tmpcfg}" || \ - err "set timeout, ${grub_timeout}, ${tmpcfg}" + $err "set timeout, ${grub_timeout}, ${tmpcfg}" [ -z "${grub_timeout}" ] || x_ "${cbfstool}" "${tmprom}" add \ -f "${tmpcfg}" -n timeout.cfg -t raw x_ rm -f "${tmpcfg}" @@ -344,7 +344,7 @@ mkSeabiosGrubonlyRom() tmpbootorder=$(mktemp -t coreboot_rom.XXXXXXXXXX) # only load grub, by inserting a custom bootorder file - printf "/rom@img/grub2\n" > "$tmpbootorder" || err "printf bootorder" + printf "/rom@img/grub2\n" > "$tmpbootorder" || $err "printf bootorder" x_ "${cbfstool}" "${_grubrom}" \ add -f "${tmpbootorder}" -n bootorder -t raw x_ rm -f "${tmpbootorder}" @@ -356,7 +356,7 @@ mkSeabiosGrubonlyRom() build_uboot_roms() { tmprom=$(mkUbootRom "${cbrom}" "fallback/payload") || \ - err "build_uboot_roms $board: could not create tmprom" + $err "build_uboot_roms $board: could not create tmprom" newrom="${romdir}/uboot_payload_${board}_${initmode}_${displaymode}.rom" x_ moverom "${tmprom}" "${newrom}" x_ rm -f "${tmprom}" @@ -370,7 +370,7 @@ mkUbootRom() { _ubdir="elf/u-boot/${board}/${uboot_config}" _ubootelf="${_ubdir}/u-boot.elf" [ -f "${_ubootelf}" ] || _ubootelf="${_ubdir}/u-boot" - [ -f "$_ubootelf" ] || err "mkUbootRom: $board: cant find u-boot" + [ -f "$_ubootelf" ] || $err "mkUbootRom: $board: cant find u-boot" tmprom=$(mktemp -t coreboot_rom.XXXXXXXXXX) diff --git a/script/build/serprog b/script/build/serprog index 8b003add..ea2c02bf 100755 --- a/script/build/serprog +++ b/script/build/serprog @@ -17,8 +17,8 @@ usage="usage: ./build firmware serprog [board]" main() { - [ -z "${1+x}" ] && err "${usage}" - [ "$1" != "rp2040" ] && [ "$1" != "stm32" ] && err "$usage" + [ -z "${1+x}" ] && $err "${usage}" + [ "$1" != "rp2040" ] && [ "$1" != "stm32" ] && $err "$usage" if [ "${1}" = "rp2040" ]; then boards_dir=${pico_sdk_dir}/src/boards/include/boards [ -d "$pico_src_dir" ] || x_ ./update trees -f "pico-serprog" @@ -71,7 +71,7 @@ print_boards() list_boards() { - basename -a -s .h "${1}/"*.h || err "list_boards $1: can't list boards" + basename -a -s .h "${1}/"*.h || $err "list_boards $1: can't list boards" } main $@ diff --git a/script/update/release b/script/update/release index 357840c2..c4101b5a 100755 --- a/script/update/release +++ b/script/update/release @@ -13,11 +13,11 @@ main() { vdir="release" while getopts d:m: option; do - [ -z "${OPTARG}" ] && err "Empty argument not allowed" + [ -z "${OPTARG}" ] && $err "Empty argument not allowed" case "${option}" in d) vdir="${OPTARG}" ;; m) mode="${OPTARG}" ;; - *) err "Invalid option" ;; + *) $err "Invalid option" ;; esac done @@ -29,7 +29,7 @@ main() src_dirname="${relname}_src" srcdir="${vdir}/${src_dirname}" - [ -e "${vdir}" ] && err "already exists: \"${vdir}\"" + [ -e "${vdir}" ] && $err "already exists: \"${vdir}\"" mkvdir build_release @@ -39,45 +39,45 @@ main() mkvdir() { - mkdir -p "${vdir}" || err "mkvdir: !mkdir -p \"${vdir}\"" - git clone . "${srcdir}" || err "mkdir: !gitclone \"${srcdir}\"" - insert_version_files "$srcdir" || err "mkvdir $srcdir: versionfile" + mkdir -p "${vdir}" || $err "mkvdir: !mkdir -p \"${vdir}\"" + git clone . "${srcdir}" || $err "mkdir: !gitclone \"${srcdir}\"" + insert_version_files "$srcdir" || $err "mkvdir $srcdir: versionfile" } build_release() { _xm="build_release ${vdir}" ( - cd "${srcdir}" || err "${_xm}: !cd \"${srcdir}\"" + cd "${srcdir}" || $err "${_xm}: !cd \"${srcdir}\"" fetch_trees [ "${mode}" = "u-boot" ] || x_ mv src/docs docs - ) || err "can't create release files" + ) || $err "can't create release files" git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \ --abbrev-commit > "${srcdir}/CHANGELOG" || \ - err "build_release $srcdir: couldn't generate changelog" + $err "build_release $srcdir: couldn't generate changelog" ( if [ "${mode}" = "u-boot" ]; then - cd "${srcdir}/src/" || err "${_xm}: mktarball \"${srcdir}\"" + cd "${srcdir}/src/" || $err "${_xm}: mktarball \"${srcdir}\"" mktarball u-boot "../../${srcdir##*/}.tar.xz" || \ - err "$_xm: mksrc" + $err "$_xm: mksrc" # make a src archive containing only u-boot else - cd "${srcdir%/*}" || err "${_xm}: mktarball \"${srcdir}\"" + cd "${srcdir%/*}" || $err "${_xm}: mktarball \"${srcdir}\"" mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || \ - err "$_xm: mksrc" + $err "$_xm: mksrc" fi - ) || err "can't create src tarball" + ) || $err "can't create src tarball" [ "${mode}" = "src" ] && return 0 [ "${mode}" = "u-boot" ] && return 0 ( - cd "${srcdir}" || err "${_xm}: 2 !cd \"${srcdir}\"" + cd "${srcdir}" || $err "${_xm}: 2 !cd \"${srcdir}\"" mkrom_images - ) || err "can't build rom images" + ) || $err "can't build rom images" - rm -Rf "${srcdir}" || err "!rm -Rf ${srcdir}" + rm -Rf "${srcdir}" || $err "!rm -Rf ${srcdir}" } fetch_trees() @@ -85,7 +85,7 @@ fetch_trees() for x in config/git/*; do [ "${mode}" = "u-boot" ] && break [ ! -f "${x}" ] || ./update trees -f "${x#config/git/}" || \ - err "${_xm}: fetch ${x#config/git/}" + $err "${_xm}: fetch ${x#config/git/}" done [ "${mode}" = "u-boot" ] && x_ ./update trees -f u-boot @@ -93,56 +93,56 @@ fetch_trees() [ -f "${x}" ] || continue xp="${x#*/}"; xp="${xp%/*}" [ -L "${xp}" ] || rm -Rf "src/${xp}/${xp}" || \ - err "!rm -Rf \"src/${xp}/${xp}\"" + $err "!rm -Rf \"src/${xp}/${xp}\"" done - find . -name ".git" -exec rm -Rf {} + || err "$_xm: rm .git" - find . -name ".gitmodules" -exec rm -Rf {} + || err "$_xm: rm .gitmod" + find . -name ".git" -exec rm -Rf {} + || $err "$_xm: rm .git" + find . -name ".gitmodules" -exec rm -Rf {} + || $err "$_xm: rm .gitmod" x_ rm -Rf tmp .git } mkrom_images() { - ./build roms all || err "${_xm}: roms-all" - ./build serprog rp2040 || err "${_xm}: rp2040" - ./build serprog stm32 || err "${_xm}: stm32" + ./build roms all || $err "${_xm}: roms-all" + ./build serprog rp2040 || $err "${_xm}: rp2040" + ./build serprog stm32 || $err "${_xm}: stm32" for rombuild in bin/*; do [ -d "${rombuild}" ] || continue handle_rom_archive "${rombuild}" done - mv "release/${version}/roms/" ../roms || err "${_xm}: copy roms/" + mv "release/${version}/roms/" ../roms || $err "${_xm}: copy roms/" } handle_rom_archive() { builddir="${1}" romdir="tmp/romdir" - rm -Rf "${romdir}" || err "!rm romdir, handle_rom_archive" + rm -Rf "${romdir}" || $err "!rm romdir, handle_rom_archive" target="${builddir##*/}" if [ ! -f "config/coreboot/${target}/target.cfg" ]; then # No config, just make a tarball tarball="release/${version}/roms/${relname}_${target}.tar.xz" insert_copying_files "${builddir}" || \ - err "!insert copy, handle, ${builddir}" + $err "!insert copy, handle, ${builddir}" mktarball "${builddir}" "${tarball}" return 0 fi romdir="${romdir}/bin/${target}" - mkdir -p "${romdir}" || err "!mkdir -p romdir, handle_rom_archive" - cp "$builddir/"* "$romdir" || err "!cp romdir, handle_rom_archive" + mkdir -p "${romdir}" || $err "!mkdir -p romdir, handle_rom_archive" + cp "$builddir/"* "$romdir" || $err "!cp romdir, handle_rom_archive" nukerom printf "Generating release/%s/roms/%s-%s_%s.tar.xz\n" \ "${version}" "${projectname}" "${version}" "${target##*/}" insert_version_files "${romdir}" || \ - err "mkrom_tarball ${romdir}: versionfile" + $err "mkrom_tarball ${romdir}: versionfile" - insert_copying_files "$romdir" || err "!insert copy, handle 2, $romdir" + insert_copying_files "$romdir" || $err "!insert copy, handle 2, $romdir" mkrom_tarball } @@ -152,18 +152,18 @@ nukerom() # Hash the images before removing vendor files # which "./vendor inject" uses for verification - rm -f "${romdir}/vendorhashes" || err "!rm ${romdir}/vendorhashes" - touch "${romdir}/vendorhashes" || err "!touch ${romdir}/vendorhashes" + rm -f "${romdir}/vendorhashes" || $err "!rm ${romdir}/vendorhashes" + touch "${romdir}/vendorhashes" || $err "!touch ${romdir}/vendorhashes" ( - cd "${romdir}" || err "!cd romdir ${romdir}, nukerom" + cd "${romdir}" || $err "!cd romdir ${romdir}, nukerom" sha512sum ./*.rom >> vendorhashes || \ - err "!create vendorhashes, nukerom" - ) || err "can't create vendor hashes" + $err "!create vendorhashes, nukerom" + ) || $err "can't create vendor hashes" for romfile in "${romdir}"/*.rom; do [ -f "${romfile}" ] || continue ./vendor inject -r "$romfile" -b "$target" -n nuke || \ - err "!vendor inject (nuke) ${romfile}, nukerom" + $err "!vendor inject (nuke) ${romfile}, nukerom" done } @@ -188,13 +188,13 @@ mkrom_tarball() { archivename="${relname}_${target##*/}" f="release/${version}/roms/${archivename}" - mkdir -p "${f%/*}" || err "mkrom_tarball: !mkdir -p ${f%/*}" + mkdir -p "${f%/*}" || $err "mkrom_tarball: !mkdir -p ${f%/*}" ( - cd "${romdir%"/bin/$target"}" || err "!cd ${romdir%"/bin/$target"}" + cd "${romdir%"/bin/$target"}" || $err "!cd ${romdir%"/bin/$target"}" mktarball "bin/${target}" "${archivename}.tar.xz" - ) || err "can't create rom tarball" + ) || $err "can't create rom tarball" mv "${romdir%"/bin/${target}"}/${archivename}.tar.xz"* "${f%/*}" || \ - err "mktar ${f%/*}/${romdir%"/bin/$target"}/$archivename.tar.xz" + $err "mktar ${f%/*}/${romdir%"/bin/$target"}/$archivename.tar.xz" printf "Created ROM archive: %s" "${f%/*}/${archivename}.tar.xz" } @@ -212,20 +212,20 @@ mktarball() tar_implementation=$(tar --version | head -n1) || : [ "${2%/*}" = "${2}" ] || \ - mkdir -p "${2%/*}" || err "mk, !mkdir -p \"${2%/*}\"" + mkdir -p "${2%/*}" || $err "mk, !mkdir -p \"${2%/*}\"" if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then tar --sort=name --owner=root:0 --group=root:0 \ --mtime="UTC 2024-02-25" -c "$1" | xz -T0 -9e > "$2" || \ - err "mktarball 1, ${1}" + $err "mktarball 1, ${1}" else # TODO: reproducible tarballs on non-GNU systems - tar -c "$1" | xz -T0 -9e > "$2" || err "mktarball 2, $1" + tar -c "$1" | xz -T0 -9e > "$2" || $err "mktarball 2, $1" fi ( [ "${2%/*}" != "${2}" ] && x_ cd "${2%/*}" sha512sum "${2##*/}" > "${2##*/}.sha512" || \ - err "!sha512sum \"${2##*/}\" > \"${2##*/}.sha512\"" - ) || err "failed to create tarball checksum" + $err "!sha512sum \"${2##*/}\" > \"${2##*/}.sha512\"" + ) || $err "failed to create tarball checksum" } main $@ diff --git a/script/update/trees b/script/update/trees index 51ea821c..40ff1878 100755 --- a/script/update/trees +++ b/script/update/trees @@ -28,12 +28,12 @@ main() -s) mode="savedefconfig" ;; -l) mode="olddefconfig" ;; -n) mode="nconfig" ;; - *) err "Invalid option" ;; + *) $err "Invalid option" ;; esac shift; project="${OPTARG#src/}"; shift done - [ -z "$_f" ] && err "missing flag (-m/-u/-b/-c/-x/-f/-s/-l/-n)" - [ -z "$project" ] && err "project name not specified" + [ -z "$_f" ] && $err "missing flag (-m/-u/-b/-c/-x/-f/-s/-l/-n)" + [ -z "$project" ] && $err "project name not specified" elfdir="elf/${project}" cfgsdir="config/${project}" @@ -66,17 +66,17 @@ build_targets() [ "$elfdir" = "elf/coreboot" ] && \ elfdir="elf/coreboot_nopayload_DO_NOT_FLASH" - [ -d "$cfgsdir" ] || err "directory, $cfgsdir, does not exist" + [ -d "$cfgsdir" ] || $err "directory, $cfgsdir, does not exist" listfile="${cfgsdir}/build.list" - [ -f "$listfile" ] || err "list file, $listfile, does not exist" + [ -f "$listfile" ] || $err "list file, $listfile, does not exist" # Build for all targets if no argument is given [ $# -gt 0 ] && target1="$1" [ "$target1" = "utils" ] && [ "$project" = "coreboot" ] && \ shift 1 targets=$(items "$cfgsdir") || \ - err "Cannot get options for $cfgsdir" + $err "Cannot get options for $cfgsdir" [ $# -gt 0 ] && targets=$@ [ -z "$mode" ] && x_ mkdir -p "$elfdir" @@ -130,7 +130,7 @@ handle_src_tree() x_ mkdir -p "${elfdir}/${target}" - [ -z "$tree" ] && err "handle_src_tree $project/$tree: tree unset" + [ -z "$tree" ] && $err "handle_src_tree $project/$tree: tree unset" codedir="src/${project}/${tree}" @@ -155,7 +155,7 @@ load_project_config() [ -f "${1}/target.cfg" ] || return 0 . "${1}/target.cfg" || \ - err "load_project_config ${1}: cannot load target.cfg"; return 0 + $err "load_project_config ${1}: cannot load target.cfg"; return 0 } check_cross_compiler() @@ -178,7 +178,7 @@ check_cross_compiler() check_config() { - [ -f "$config" ] || err "check_config: ${project}/${target}: no config" + [ -f "$config" ] || $err "check_config: ${project}/${target}: no config" dest_dir="${elfdir}/${target}/${config_name}" # TODO: very hacky check. do it properly (based on build.list) @@ -197,7 +197,7 @@ handle_makefile() [ -n "$mode" ] || make -C "$codedir" silentoldconfig || \ make -C "$codedir" oldconfig || : - run_make_command || err "handle_makefile $codedir: no makefile!" + run_make_command || $err "handle_makefile $codedir: no makefile!" if [ -e "${codedir}/.git" ] && [ "$project" = "u-boot" ] && \ [ "$mode" = "distclean" ]; then @@ -220,7 +220,7 @@ run_make_command() printf "%s\n" "${version%%-*}" > "$codedir/.coreboot-version" make $mode -j$(nproc) $makeargs -C "$codedir" || \ - err "run_make $codedir: !make $mode" + $err "run_make $codedir: !make $mode" [ "$mode" != "clean" ] && return 0 make -C "$codedir" distclean 2>/dev/null || : @@ -232,9 +232,9 @@ check_cmake() check_makefile "${1}" || \ cmake -B "${1}" "${1}/${cmakedir}" || \ check_makefile "${1}" || \ - err "check_cmake ${1}: can't cmake ${cmakedir}" + $err "check_cmake ${1}: can't cmake ${cmakedir}" [ -z "${cmakedir}" ] || check_makefile "${1}" || \ - err "check_cmake ${1}: could not generate Makefile" + $err "check_cmake ${1}: could not generate Makefile" return 0 } @@ -242,11 +242,11 @@ check_autoconf() { ( _cfgopt="" - cd "${1}" || err "!cd $1" + cd "${1}" || $err "!cd $1" [ -f "bootstrap" ] && x_ ./bootstrap $bootstrapargs [ -f "autogen.sh" ] && x_ ./autogen.sh ${autogenargs} [ -f "configure" ] && x_ ./configure $autoconfargs; return 0 - ) || err "can't bootstrap project: $1" + ) || $err "can't bootstrap project: $1" } check_makefile() diff --git a/script/vendor/download b/script/vendor/download index 42cb16ab..b40810cc 100755 --- a/script/vendor/download +++ b/script/vendor/download @@ -25,14 +25,14 @@ eval "$(setvars "" _b _dl EC_url EC_url_bkup EC_hash DL_hash DL_url DL_url_bkup main() { - [ $# -gt 0 ] || err "No argument given" + [ $# -gt 0 ] || $err "No argument given" board="${1}" boarddir="${cbcfgsdir}/${board}" _b="${board%%_*mb}" # shorthand (no duplication per rom size) check_defconfig "${boarddir}" && exit 0 detect_firmware && exit 0 - scan_config "${_b}" "config/vendor" "err" + scan_config "${_b}" "config/vendor" build_dependencies download_vendorfiles @@ -49,7 +49,7 @@ detect_firmware() set -- "${boarddir}/config/"* . "${1}" 2>/dev/null . "${boarddir}/target.cfg" 2>/dev/null - [ -z "$tree" ] && err "detect_firmware $boarddir: tree undefined" + [ -z "$tree" ] && $err "detect_firmware $boarddir: tree undefined" cbdir="src/coreboot/$tree" cbfstool="cbutils/$tree/cbfstool" @@ -110,8 +110,8 @@ fetch() dl_bkup="${3}" dlsum="${4}" [ "${5}" = "/dev/null" ] && return 0 - [ "${5# }" = "$5" ] || err "fetch: space not allowed in _dest: '$5'" - [ "${5#/}" = "$5" ] || err "fetch: absolute path not allowed: '$5'" + [ "${5# }" = "$5" ] || $err "fetch: space not allowed in _dest: '$5'" + [ "${5#/}" = "$5" ] || $err "fetch: absolute path not allowed: '$5'" _dest="${5##*../}" _dl="${vendir}/cache/${dlsum}" dl_fail="n" @@ -129,14 +129,14 @@ fetch() vendor_checksum "${dlsum}" "${_dl}" || dl_fail="n" done [ "${dl_fail}" = "y" ] && \ - err "fetch ${dlsum}: matched file unavailable" + $err "fetch ${dlsum}: matched file unavailable" x_ rm -Rf "${_dl}_extracted" mkdirs "${_dest}" "extract_${dl_type}" || return 0 eval "extract_${dl_type}" [ -f "${_dest}" ] && return 0 - err "extract_${dl_type} (fetch): missing file: '${_dest}'" + $err "extract_${dl_type} (fetch): missing file: '${_dest}'" } vendor_checksum() @@ -152,17 +152,17 @@ mkdirs() printf "mkdirs %s %s: already downloaded\n" "$1" "$2" 1>&2 return 1 fi - mkdir -p "${1%/*}" || err "mkdirs: !mkdir -p ${1%/*}" + mkdir -p "${1%/*}" || $err "mkdirs: !mkdir -p ${1%/*}" remkdir "${appdir}" extract_archive "${_dl}" "${appdir}" || \ [ "${2}" = "extract_e6400vga" ] || \ - err "mkdirs ${1} ${2}: !extract" + $err "mkdirs ${1} ${2}: !extract" } extract_intel_me() { [ ! -f "$mecleaner" ] && \ - err "extract_intel_me $cbdir: me_cleaner missing" + $err "extract_intel_me $cbdir: me_cleaner missing" _me="${PWD}/${_dest}" # must always be an absolute path cdir="${PWD}/${appdir}" # must always be an absolute path @@ -170,10 +170,10 @@ extract_intel_me() [ -f "${_me}" ] && return 0 sdir="$(mktemp -d)" - mkdir -p "$sdir" || err "extract_intel_me: !mkdir -p \"$sdir\"" + mkdir -p "$sdir" || $err "extract_intel_me: !mkdir -p \"$sdir\"" ( [ "${cdir#/a}" != "$cdir" ] && cdir="${cdir#/}" - cd "$cdir" || err "extract_intel_me: !cd \"$cdir\"" + cd "$cdir" || $err "extract_intel_me: !cd \"$cdir\"" for i in *; do [ -f "$_me" ] && break [ -L "$i" ] && continue @@ -195,7 +195,7 @@ extract_intel_me() cd "${cdir}" || : done ) - rm -Rf "${sdir}" || err "extract_intel_me: !rm -Rf ${sdir}" + rm -Rf "${sdir}" || $err "extract_intel_me: !rm -Rf ${sdir}" } extract_archive() @@ -207,44 +207,44 @@ extract_archive() extract_kbc1126ec() { [ ! -f "$kbc1126_ec_dump" ] && \ - err "extract_kbc1126ec $cbdir: kbc1126_ec_dump missing" + $err "extract_kbc1126ec $cbdir: kbc1126_ec_dump missing" ( x_ cd "${appdir}/" mv Rompaq/68*.BIN ec.bin || : if [ ! -f ec.bin ]; then unar -D ROM.CAB Rom.bin || unar -D Rom.CAB Rom.bin || \ - unar -D 68*.CAB Rom.bin || err "can't extract Rom.bin" + unar -D 68*.CAB Rom.bin || $err "can't extract Rom.bin" x_ mv Rom.bin ec.bin fi - [ -f ec.bin ] || err "extract_kbc1126_ec ${board}: can't extract" + [ -f ec.bin ] || $err "extract_kbc1126_ec ${board}: can't extract" "${kbc1126_ec_dump}" ec.bin || \ - err "extract_kbc1126_ec ${board}: can't extract ecfw1/2.bin" - ) || err "can't extract kbc1126 ec firmware" + $err "extract_kbc1126_ec ${board}: can't extract ecfw1/2.bin" + ) || $err "can't extract kbc1126 ec firmware" ec_ex="y" for i in 1 2; do [ -f "${appdir}/ec.bin.fw${i}" ] || ec_ex="n" done [ "${ec_ex}" = "y" ] || \ - err "extract_kbc1126_ec ${board}: didn't extract ecfw1/2.bin" + $err "extract_kbc1126_ec ${board}: didn't extract ecfw1/2.bin" cp "${appdir}/"ec.bin.fw* "${_dest%/*}/" || \ - err "extract_kbc1126_ec ${board}: can't copy ec binaries" + $err "extract_kbc1126_ec ${board}: can't copy ec binaries" } extract_e6400vga() { for v in E6400_VGA_offset E6400_VGA_romname; do - eval "[ -z \"\$$v\" ] && err \"extract_e6400vga: $v undefined\"" + eval "[ -z \"\$$v\" ] && $err \"extract_e6400vga: $v undefined\"" done tail -c +$E6400_VGA_offset "$_dl" | gunzip > "$appdir/bios.bin" || : ( x_ cd "${appdir}" - [ -f "bios.bin" ] || err "extract_e6400vga: can't extract bios.bin" + [ -f "bios.bin" ] || $err "extract_e6400vga: can't extract bios.bin" "${e6400_unpack}" bios.bin || printf "TODO: fix dell extract util\n" [ -f "${E6400_VGA_romname}" ] || \ - err "extract_e6400vga: can't extract vga rom from bios.bin" - ) || err "can't extract e6400 vga rom" + $err "extract_e6400vga: can't extract vga rom from bios.bin" + ) || $err "can't extract e6400 vga rom" cp "${appdir}/${E6400_VGA_romname}" "${_dest}" || \ - err "extract_e6400vga ${board}: can't copy vga rom to ${_dest}" + $err "extract_e6400vga ${board}: can't copy vga rom to ${_dest}" } extract_sch5545ec() @@ -258,9 +258,9 @@ extract_sch5545ec() # this makes the file defined by _sch5545ec_fw available to copy "${uefiextract}" "${_bios}" || \ - err "extract_sch5545ec: cannot extract from uefi image" + $err "extract_sch5545ec: cannot extract from uefi image" cp "${_sch5545ec_fw}" "${_dest}" || \ - err "extract_sch5545ec: cannot copy sch5545ec firmware file" + $err "extract_sch5545ec: cannot copy sch5545ec firmware file" } main $@ diff --git a/script/vendor/inject b/script/vendor/inject index 4ac2753f..dc12d7b5 100755 --- a/script/vendor/inject +++ b/script/vendor/inject @@ -13,7 +13,7 @@ eval "$(setvars "" archive rom modifygbe nukemode release new_mac tree)" main() { - [ $# -lt 1 ] && err "No options specified." + [ $# -lt 1 ] && $err "No options specified." [ "${1}" = "listboards" ] && eval "items config/coreboot || :; exit 0" archive="${1}" @@ -42,8 +42,8 @@ check_board() failcheck="n" check_release "${archive}" || failcheck="y" if [ "${failcheck}" = "y" ]; then - [ -f "$rom" ] || err "check_board \"$rom\": invalid path" - [ -z "${rom+x}" ] && err "check_board: no rom specified" + [ -f "$rom" ] || $err "check_board \"$rom\": invalid path" + [ -z "${rom+x}" ] && $err "check_board: no rom specified" [ -n "${board+x}" ] || board=$(detect_board "${rom}") else release="y" @@ -51,11 +51,11 @@ check_board() fi boarddir="${cbcfgsdir}/${board}" - [ -d "$boarddir" ] || err "check_board: board $board missing" + [ -d "$boarddir" ] || $err "check_board: board $board missing" [ -f "$boarddir/target.cfg" ] || \ - err "check_board $board: target.cfg missing" + $err "check_board $board: target.cfg missing" . "$boarddir/target.cfg" 2>/dev/null - [ -z "$tree" ] && err "check_board $board: tree undefined"; return 0 + [ -z "$tree" ] && $err "check_board $board: tree undefined"; return 0 } check_release() @@ -80,7 +80,7 @@ detect_board() _stripped_prefix=${filename#*_} board="${_stripped_prefix%.tar.xz}" ;; *) - err "detect_board $filename: could not detect board type" + $err "detect_board $filename: could not detect board type" esac printf "%s\n" "${board}" } @@ -109,7 +109,7 @@ patch_release_roms() _tmpdir="tmp/romdir" remkdir "${_tmpdir}" tar -xf "${archive}" -C "${_tmpdir}" || \ - err "patch_release_roms: !tar -xf \"$archive\" -C \"$_tmpdir\"" + $err "patch_release_roms: !tar -xf \"$archive\" -C \"$_tmpdir\"" for x in "${_tmpdir}"/bin/*/*.rom ; do printf "patching rom: %s\n" "$x" @@ -118,14 +118,14 @@ patch_release_roms() ( cd "${_tmpdir}/bin/"* || \ - err "patch_release_roms: !cd ${_tmpdir}/bin/*" + $err "patch_release_roms: !cd ${_tmpdir}/bin/*" # NOTE: For compatibility with older rom releases, defer to sha1 [ "${nukemode}" = "nuke" ] || sha512sum --status -c vendorhashes || \ sha1sum --status -c vendorhashes || sha512sum --status -c \ blobhashes || sha1sum --status -c blobhashes || \ - err "patch_release_roms: ROMs did not match expected hashes" - ) || err "can't verify vendor hashes" + $err "patch_release_roms: ROMs did not match expected hashes" + ) || $err "can't verify vendor hashes" [ "${modifygbe}" = "true" ] && \ for x in "${_tmpdir}"/bin/*/*.rom ; do @@ -143,7 +143,7 @@ patch_rom() { rom="${1}" - check_defconfig "$boarddir" && err "patch_rom $boarddir: no configs" + check_defconfig "$boarddir" && $err "patch_rom $boarddir: no configs" set -- "${boarddir}/config/"* . "${1}" 2>/dev/null @@ -174,18 +174,18 @@ patch_rom() inject() { [ $# -lt 3 ] && \ - err "inject $@, $rom: usage: inject name path type (offset)" + $err "inject $@, $rom: usage: inject name path type (offset)" eval "$(setvars "" cbfsname _dest _t _offset)" cbfsname="${1}" _dest="${2##*../}" _t="${3}" [ $# -gt 3 ] && _offset="-b ${4}" && [ -z "${4}" ] && \ - err "inject $@, $rom: offset passed, but empty (not defined)" + $err "inject $@, $rom: offset passed, but empty (not defined)" - [ -z "${_dest}" ] && err "inject $@, ${rom}: empty destination path" + [ -z "${_dest}" ] && $err "inject $@, ${rom}: empty destination path" [ ! -f "${_dest}" ] && [ "${nukemode}" != "nuke" ] && \ - err "inject_${dl_type}: file missing, ${_dest}" + $err "inject_${dl_type}: file missing, ${_dest}" [ "$nukemode" = "nuke" ] || \ printf "Inserting %s/%s in file: %s\n" "$cbfsname" "$_t" "$rom" @@ -193,18 +193,18 @@ inject() if [ "${_t}" = "GbE" ]; then x_ mkdir -p tmp cp "${_dest}" "tmp/gbe.bin" || \ - err "inject: !cp \"${_dest}\" \"tmp/gbe.bin\"" + $err "inject: !cp \"${_dest}\" \"tmp/gbe.bin\"" _dest="tmp/gbe.bin" "${nvmutil}" "${_dest}" setmac "${new_mac}" || \ - err "inject ${_dest}: can't change mac address" + $err "inject ${_dest}: can't change mac address" fi if [ "${cbfsname}" = "IFD" ]; then if [ "${nukemode}" != "nuke" ]; then "$ifdtool" -i ${_t}:${_dest} "$rom" -O "$rom" || \ - err "inject: can't insert $_t ($dest) into $rom" + $err "inject: can't insert $_t ($dest) into $rom" else "$ifdtool" --nuke $_t "$rom" -O "$rom" || \ - err "inject $rom: can't nuke $_t in IFD" + $err "inject $rom: can't nuke $_t in IFD" fi else if [ "${nukemode}" != "nuke" ]; then @@ -214,11 +214,11 @@ inject() else "$cbfstool" "$rom" add -f "$_dest" \ -n "$cbfsname" -t $_t $_offset || \ - err "$rom: can't insert $_t file $_dest" + $err "$rom: can't insert $_t file $_dest" fi else "$cbfstool" "$rom" remove -n "$cbfsname" || \ - err "inject $rom: can't remove $cbfsname" + $err "inject $rom: can't remove $cbfsname" fi fi } From 332778973c3bca867dd2aa608b89a017a2e44b77 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 27 Mar 2024 07:14:47 +0000 Subject: [PATCH 0009/1319] allow users to specify number of build threads lbmk otherwise uses nproc to set the number of build threads, in these places: * generic make commands in script/update/trees * crossgcc make command in script/update/trees the -T0 option is also used in script/update/release, when running tar. with this change, you can do: export LBMK_THREADS=x where x is the number of threads. when you then run lbmk, your chosen number of threads will override the default. this may be useful on a host that does not have a lot of memory. Signed-off-by: Leah Rowe --- include/option.sh | 8 ++++++++ script/update/release | 7 ++++--- script/update/trees | 4 ++-- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/include/option.sh b/include/option.sh index 64442d15..8fc80aaa 100755 --- a/include/option.sh +++ b/include/option.sh @@ -22,6 +22,14 @@ eval "$(setvars "" CONFIG_BOARD_DELL_E6400 CONFIG_HAVE_MRC CONFIG_HAVE_ME_BIN \ CONFIG_IFD_BIN_PATH CONFIG_MRC_FILE _dest board boarddir \ CONFIG_HAVE_REFCODE_BLOB CONFIG_REFCODE_BLOB_FILE)" +threads= +set | grep LBMK_THREADS 1>/dev/null 2>/dev/null || threads=$(nproc) || : +[ -z "$threads" ] && threads=$LBMK_THREADS +[ -z "$threads" ] && threads=1 # LBMK_THREADS not set, and nproc failed + +expr "X$threads" : "X-\{0,1\}[0123456789][0123456789]*$" \ + 1>/dev/null 2>/dev/null || threads=1 # user specified a non-integer + items() { rval=1 diff --git a/script/update/release b/script/update/release index c4101b5a..25ada9da 100755 --- a/script/update/release +++ b/script/update/release @@ -215,11 +215,12 @@ mktarball() mkdir -p "${2%/*}" || $err "mk, !mkdir -p \"${2%/*}\"" if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then tar --sort=name --owner=root:0 --group=root:0 \ - --mtime="UTC 2024-02-25" -c "$1" | xz -T0 -9e > "$2" || \ - $err "mktarball 1, ${1}" + --mtime="UTC 2024-02-25" -c "$1" | xz -T$threads -9e \ + > "$2" || $err "mktarball 1, ${1}" else # TODO: reproducible tarballs on non-GNU systems - tar -c "$1" | xz -T0 -9e > "$2" || $err "mktarball 2, $1" + tar -c "$1" | xz -T$threads -9e > "$2" || \ + $err "mktarball 2, $1" fi ( [ "${2%/*}" != "${2}" ] && x_ cd "${2%/*}" diff --git a/script/update/trees b/script/update/trees index 40ff1878..ac5743be 100755 --- a/script/update/trees +++ b/script/update/trees @@ -172,7 +172,7 @@ check_cross_compiler() [ -n "${xlang}" ] && export BUILD_LANGUAGES="$xlang" [ -d "${cbdir}/util/crossgcc/xgcc/${_xarch}/" ] && continue - x_ make -C "$cbdir" crossgcc-${_xarch%-*} CPUS=$(nproc) + x_ make -C "$cbdir" crossgcc-${_xarch%-*} CPUS=$threads done } @@ -219,7 +219,7 @@ run_make_command() [ "$project" = "coreboot" ] && [ -z "$mode" ] && x_ \ printf "%s\n" "${version%%-*}" > "$codedir/.coreboot-version" - make $mode -j$(nproc) $makeargs -C "$codedir" || \ + make $mode -j$threads $makeargs -C "$codedir" || \ $err "run_make $codedir: !make $mode" [ "$mode" != "clean" ] && return 0 From 5cb17795c647407ae36db82dbd03f7a3ed978735 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 30 Mar 2024 06:06:09 +0000 Subject: [PATCH 0010/1319] fix sata slots on dell 9020 sff and mt 3rd sata slot (of 3) broken on 9020 sff, and the 3rd and 4th (of 4) slots are broken on 9020 mt this patch fixes them on both, so that all ports work properly Signed-off-by: Leah Rowe --- ...x-sata-ports-on-dell-9020-sff-and-mt.patch | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch diff --git a/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch b/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch new file mode 100644 index 00000000..f4c3939c --- /dev/null +++ b/config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch @@ -0,0 +1,66 @@ +From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 30 Mar 2024 05:57:54 +0000 +Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt + +mate kukri has a patch under review on coreboot that sets +sata port map to 0x7 on sff and 0xf on mt. + +see: intel 8 series pch datasheet, section 13.1.35 + +basically, the 6 least significant bits enable the sata +slots; 1 for enable and 0 for disable. there can be up +to 6 ports. least significant bit is port 0, then next +is port 1, and so on. + +coreboot currently enables ports 0, 1, 4 and 5, making this +value 0x33 (converted to binary: 00110011). sff has ports +0, 1 and 2 wired, so mate changed that to 0x7 (00000111). + +on mt, the blue ports are ports 0 and 1, but the two white +ports don't work, but coreboot enables 4 and 5; it is +likely that the blue ports are in fact 0 and 1, and the +white ports are 2 and 3, but we've not tested this! + +it could be that the blue ports are ports 4 and 5, and +the white ports are 2 and 3! we have not yet determined +this, but mate set it to 0xf, meaning ports 0 1 2 and 3 +are enabled, in his patch under review. the chance that +it's 2, 3, 4 and 5 on the board is unlikely, but it is +theoretically possible and has not been confirmed. + +therefore, for now, i will set the value to 0x3f, which +in binary is 00111111, thus enabling all 6 slots. the two +that aren't physically wired don't really matter. enabling +ports (from the pch) that electrically aren't there and +then powering on is electrically equivalent to those ports +being actually being wired, but with no devices plugged +into them. therefore, 0x3f is an effective shotgun fix. + +i'll remove this patch and use mate's fix when the latter +has been tested on MT; it has already been tested on SFF. + +this patch fixes the 3rd sata slot on 9020 sff, and the 3rd +and 4th sata slots on 9020 MT + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index c0b17a15ff..7bfa6736a6 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -23,7 +23,7 @@ chip northbridge/intel/haswell + register "gen2_dec" = "0x007c0901" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x001c0901" +- register "sata_port_map" = "0x33" ++ register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # Management Engine interface 1 +-- +2.39.2 + From f7283fa10dad76f20ec4ed2841dbbbb00ee9c865 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 5 Apr 2024 23:44:06 +0100 Subject: [PATCH 0011/1319] grub xhci support see: https://github.com/9elements/grub/commits/xhci-module-upstreaming-squash_v4/ grub only supports xhci on bios/uefi targets, but not coreboot. some newer machines don't have ps/2 controllers, and boot in a way where ehci isn't available at startup; the controller can't be used by ehci code, there must be xhci support. the code is from Patrick Rudolph working on behalf of 9elements. the code was also sent here for review: https://lists.gnu.org/archive/html/grub-devel/2020-12/msg00111.html however, upstream never merged these patches. libreboot will have to maintain these from now on. the patches have been rebased for use with grub 2.12. Signed-off-by: Leah Rowe --- config/grub/modules.list | 1 + ...b-Parse-SuperSpeed-companion-descrip.patch | 245 ++ .../0002-usb-Add-enum-for-xHCI.patch | 29 + ...rans-Set-default-maximum-packet-size.patch | 33 + ...b-Add-function-pointer-for-attach-de.patch | 121 + ...b-usbhub-Add-new-private-fields-for-.patch | 77 + ...6-grub-core-bus-usb-Add-xhci-support.patch | 2814 +++++++++++++++++ ...b-usbhub-Add-xHCI-non-root-hub-suppo.patch | 127 + .../0008-Fix-compilation-on-x86_64.patch | 90 + 9 files changed, 3537 insertions(+) create mode 100644 config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch create mode 100644 config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch create mode 100644 config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch create mode 100644 config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch create mode 100644 config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch create mode 100644 config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch create mode 100644 config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch create mode 100644 config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch diff --git a/config/grub/modules.list b/config/grub/modules.list index 40bfd339..f3768adb 100644 --- a/config/grub/modules.list +++ b/config/grub/modules.list @@ -36,6 +36,7 @@ crypto \ cryptodisk \ diskfilter \ echo \ +xhci \ ehci \ eval \ exfat \ diff --git a/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch b/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch new file mode 100644 index 00000000..f533269f --- /dev/null +++ b/config/grub/patches/0005-xhci/0001-grub-core-bus-usb-Parse-SuperSpeed-companion-descrip.patch @@ -0,0 +1,245 @@ +From 90c9011f2e0350a97e3df44b0fc6dd022e04c276 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:00:27 +0100 +Subject: [PATCH 1/8] grub-core/bus/usb: Parse SuperSpeed companion descriptors + +Parse the SS_ENDPOINT_COMPANION descriptor, which is only present on USB 3.0 +capable devices and xHCI controllers. Make the descendp an array of pointers +to the endpoint descriptor as it's no longer an continous array. + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/serial/common.c | 2 +- + grub-core/bus/usb/usb.c | 44 +++++++++++++++++++------------ + grub-core/bus/usb/usbhub.c | 22 ++++++++++++---- + grub-core/commands/usbtest.c | 2 +- + grub-core/disk/usbms.c | 2 +- + grub-core/term/usb_keyboard.c | 2 +- + include/grub/usb.h | 2 +- + include/grub/usbdesc.h | 11 +++++++- + 8 files changed, 59 insertions(+), 28 deletions(-) + +diff --git a/grub-core/bus/usb/serial/common.c b/grub-core/bus/usb/serial/common.c +index e9c995a0a..fc847d66d 100644 +--- a/grub-core/bus/usb/serial/common.c ++++ b/grub-core/bus/usb/serial/common.c +@@ -72,7 +72,7 @@ grub_usbserial_attach (grub_usb_device_t usbdev, int configno, int interfno, + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &usbdev->config[0].interf[interfno].descendp[j]; ++ endp = usbdev->config[0].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && (endp->attrib & 3) == 2 + && (in_endp == GRUB_USB_SERIAL_ENDPOINT_LAST_MATCHING +diff --git a/grub-core/bus/usb/usb.c b/grub-core/bus/usb/usb.c +index 7bd49d201..e578af793 100644 +--- a/grub-core/bus/usb/usb.c ++++ b/grub-core/bus/usb/usb.c +@@ -118,7 +118,7 @@ grub_usb_device_initialize (grub_usb_device_t dev) + struct grub_usb_desc_device *descdev; + struct grub_usb_desc_config config; + grub_usb_err_t err; +- int i; ++ int i, j; + + /* First we have to read first 8 bytes only and determine + * max. size of packet */ +@@ -152,6 +152,7 @@ grub_usb_device_initialize (grub_usb_device_t dev) + int currif; + char *data; + struct grub_usb_desc *desc; ++ struct grub_usb_desc_endp *endp; + + /* First just read the first 4 bytes of the configuration + descriptor, after that it is known how many bytes really have +@@ -201,24 +202,27 @@ grub_usb_device_initialize (grub_usb_device_t dev) + = (struct grub_usb_desc_if *) &data[pos]; + pos += dev->config[i].interf[currif].descif->length; + ++ dev->config[i].interf[currif].descendp = grub_malloc ( ++ dev->config[i].interf[currif].descif->endpointcnt * ++ sizeof(struct grub_usb_desc_endp)); ++ ++ j = 0; + while (pos < config.totallen) + { + desc = (struct grub_usb_desc *)&data[pos]; +- if (desc->type == GRUB_USB_DESCRIPTOR_ENDPOINT) +- break; +- if (!desc->length) +- { +- err = GRUB_USB_ERR_BADDEVICE; +- goto fail; +- } +- pos += desc->length; +- } +- +- /* Point to the first endpoint. */ +- dev->config[i].interf[currif].descendp +- = (struct grub_usb_desc_endp *) &data[pos]; +- pos += (sizeof (struct grub_usb_desc_endp) +- * dev->config[i].interf[currif].descif->endpointcnt); ++ if (desc->type == GRUB_USB_DESCRIPTOR_ENDPOINT) { ++ endp = (struct grub_usb_desc_endp *) &data[pos]; ++ dev->config[i].interf[currif].descendp[j++] = endp; ++ pos += desc->length; ++ } else { ++ if (!desc->length) ++ { ++ err = GRUB_USB_ERR_BADDEVICE; ++ goto fail; ++ } ++ pos += desc->length; ++ } ++ } + } + } + +@@ -226,8 +230,14 @@ grub_usb_device_initialize (grub_usb_device_t dev) + + fail: + +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ + grub_free (dev->config[i].descconf); ++ } + + return err; + } +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index f5608e330..2ae29cba1 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -82,8 +82,14 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + if (i == GRUB_USBHUB_MAX_DEVICES) + { + grub_error (GRUB_ERR_IO, "can't assign address to USB device"); +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) +- grub_free (dev->config[i].descconf); ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ ++ grub_free (dev->config[i].descconf); ++ } + grub_free (dev); + return NULL; + } +@@ -96,8 +102,14 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + i, 0, 0, NULL); + if (err) + { +- for (i = 0; i < GRUB_USB_MAX_CONF; i++) +- grub_free (dev->config[i].descconf); ++ for (i = 0; i < GRUB_USB_MAX_CONF; i++) { ++ int currif; ++ ++ for (currif = 0; currif < dev->config[i].descconf->numif; currif++) ++ grub_free (dev->config[i].interf[currif].descendp); ++ ++ grub_free (dev->config[i].descconf); ++ } + grub_free (dev); + return NULL; + } +@@ -176,7 +188,7 @@ grub_usb_add_hub (grub_usb_device_t dev) + i++) + { + struct grub_usb_desc_endp *endp = NULL; +- endp = &dev->config[0].interf[0].descendp[i]; ++ endp = dev->config[0].interf[0].descendp[i]; + + if ((endp->endp_addr & 128) && grub_usb_get_ep_type(endp) + == GRUB_USB_EP_INTERRUPT) +diff --git a/grub-core/commands/usbtest.c b/grub-core/commands/usbtest.c +index 2c6d93fe6..55a657635 100644 +--- a/grub-core/commands/usbtest.c ++++ b/grub-core/commands/usbtest.c +@@ -185,7 +185,7 @@ usb_iterate (grub_usb_device_t dev, void *data __attribute__ ((unused))) + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &dev->config[0].interf[i].descendp[j]; ++ endp = dev->config[0].interf[i].descendp[j]; + + grub_printf ("Endpoint #%d: %s, max packed size: %d, transfer type: %s, latency: %d\n", + endp->endp_addr & 15, +diff --git a/grub-core/disk/usbms.c b/grub-core/disk/usbms.c +index b81e3ad9d..b1512dc12 100644 +--- a/grub-core/disk/usbms.c ++++ b/grub-core/disk/usbms.c +@@ -184,7 +184,7 @@ grub_usbms_attach (grub_usb_device_t usbdev, int configno, int interfno) + for (j = 0; j < interf->endpointcnt; j++) + { + struct grub_usb_desc_endp *endp; +- endp = &usbdev->config[0].interf[interfno].descendp[j]; ++ endp = usbdev->config[0].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && (endp->attrib & 3) == 2) + /* Bulk IN endpoint. */ +diff --git a/grub-core/term/usb_keyboard.c b/grub-core/term/usb_keyboard.c +index 7322d8dff..d590979f5 100644 +--- a/grub-core/term/usb_keyboard.c ++++ b/grub-core/term/usb_keyboard.c +@@ -175,7 +175,7 @@ grub_usb_keyboard_attach (grub_usb_device_t usbdev, int configno, int interfno) + for (j = 0; j < usbdev->config[configno].interf[interfno].descif->endpointcnt; + j++) + { +- endp = &usbdev->config[configno].interf[interfno].descendp[j]; ++ endp = usbdev->config[configno].interf[interfno].descendp[j]; + + if ((endp->endp_addr & 128) && grub_usb_get_ep_type(endp) + == GRUB_USB_EP_INTERRUPT) +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 0f346af12..688c11f6d 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -153,7 +153,7 @@ struct grub_usb_interface + { + struct grub_usb_desc_if *descif; + +- struct grub_usb_desc_endp *descendp; ++ struct grub_usb_desc_endp **descendp; + + /* A driver is handling this interface. Do we need to support multiple drivers + for single interface? +diff --git a/include/grub/usbdesc.h b/include/grub/usbdesc.h +index aac5ab05a..bb2ab2e27 100644 +--- a/include/grub/usbdesc.h ++++ b/include/grub/usbdesc.h +@@ -29,7 +29,8 @@ typedef enum { + GRUB_USB_DESCRIPTOR_INTERFACE, + GRUB_USB_DESCRIPTOR_ENDPOINT, + GRUB_USB_DESCRIPTOR_DEBUG = 10, +- GRUB_USB_DESCRIPTOR_HUB = 0x29 ++ GRUB_USB_DESCRIPTOR_HUB = 0x29, ++ GRUB_USB_DESCRIPTOR_SS_ENDPOINT_COMPANION = 0x30 + } grub_usb_descriptor_t; + + struct grub_usb_desc +@@ -105,6 +106,14 @@ struct grub_usb_desc_endp + grub_uint8_t interval; + } GRUB_PACKED; + ++struct grub_usb_desc_ssep { ++ grub_uint8_t length; ++ grub_uint8_t type; ++ grub_uint8_t maxburst; ++ grub_uint8_t attrib; ++ grub_uint16_t interval; ++} GRUB_PACKED; ++ + struct grub_usb_desc_str + { + grub_uint8_t length; +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch b/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch new file mode 100644 index 00000000..d61da615 --- /dev/null +++ b/config/grub/patches/0005-xhci/0002-usb-Add-enum-for-xHCI.patch @@ -0,0 +1,29 @@ +From e111983ca5e2a52bfe2bdc5cd639b06bb2f7902d Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:47:06 +0100 +Subject: [PATCH 2/8] usb: Add enum for xHCI + +Will be used in future patches. + +Signed-off-by: Patrick Rudolph +--- + include/grub/usb.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 688c11f6d..ea6ee8c2c 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -51,7 +51,8 @@ typedef enum + GRUB_USB_SPEED_NONE, + GRUB_USB_SPEED_LOW, + GRUB_USB_SPEED_FULL, +- GRUB_USB_SPEED_HIGH ++ GRUB_USB_SPEED_HIGH, ++ GRUB_USB_SPEED_SUPER + } grub_usb_speed_t; + + typedef int (*grub_usb_iterate_hook_t) (grub_usb_device_t dev, void *data); +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch b/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch new file mode 100644 index 00000000..70e73ca2 --- /dev/null +++ b/config/grub/patches/0005-xhci/0003-usbtrans-Set-default-maximum-packet-size.patch @@ -0,0 +1,33 @@ +From 3e25c83a1d1c6e149c7e9f0660ddadb2beca2476 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:48:03 +0100 +Subject: [PATCH 3/8] usbtrans: Set default maximum packet size + +Set the maximum packet size to 512 for SuperSpeed devices. + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/usbtrans.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/grub-core/bus/usb/usbtrans.c b/grub-core/bus/usb/usbtrans.c +index c5680b33a..c1080bb33 100644 +--- a/grub-core/bus/usb/usbtrans.c ++++ b/grub-core/bus/usb/usbtrans.c +@@ -128,8 +128,12 @@ grub_usb_control_msg (grub_usb_device_t dev, + setupdata_addr = grub_dma_get_phys (setupdata_chunk); + + /* Determine the maximum packet size. */ +- if (dev->descdev.maxsize0) ++ if (dev->descdev.maxsize0 && dev->speed != GRUB_USB_SPEED_SUPER) + max = dev->descdev.maxsize0; ++ else if (dev->descdev.maxsize0 && dev->speed == GRUB_USB_SPEED_SUPER) ++ max = 1UL << dev->descdev.maxsize0; ++ else if (dev->speed == GRUB_USB_SPEED_SUPER) ++ max = 512; + else + max = 64; + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch b/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch new file mode 100644 index 00000000..a090e0ea --- /dev/null +++ b/config/grub/patches/0005-xhci/0004-grub-core-bus-usb-Add-function-pointer-for-attach-de.patch @@ -0,0 +1,121 @@ +From 89701aba00caa81bb566ab10da0c89264393be30 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:51:42 +0100 +Subject: [PATCH 4/8] grub-core/bus/usb: Add function pointer for attach/detach + events + +The xHCI code needs to be called for attaching or detaching a device. +Introduce two functions pointers and call it from the USB hub code. + +Will be used in future commits, currently this doesn't change any functionality. + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/ehci.c | 2 ++ + grub-core/bus/usb/ohci.c | 2 ++ + grub-core/bus/usb/uhci.c | 2 ++ + grub-core/bus/usb/usbhub.c | 19 +++++++++++++++++++ + include/grub/usb.h | 4 ++++ + 5 files changed, 29 insertions(+) + +diff --git a/grub-core/bus/usb/ehci.c b/grub-core/bus/usb/ehci.c +index 9abebc6bd..953b851c0 100644 +--- a/grub-core/bus/usb/ehci.c ++++ b/grub-core/bus/usb/ehci.c +@@ -1812,6 +1812,8 @@ static struct grub_usb_controller_dev usb_controller = { + .hubports = grub_ehci_hubports, + .portstatus = grub_ehci_portstatus, + .detect_dev = grub_ehci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = GRUB_EHCI_N_TD * 3 / 4 + }; +diff --git a/grub-core/bus/usb/ohci.c b/grub-core/bus/usb/ohci.c +index 5363a61f6..7a3f3e154 100644 +--- a/grub-core/bus/usb/ohci.c ++++ b/grub-core/bus/usb/ohci.c +@@ -1440,6 +1440,8 @@ static struct grub_usb_controller_dev usb_controller = + .hubports = grub_ohci_hubports, + .portstatus = grub_ohci_portstatus, + .detect_dev = grub_ohci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = GRUB_OHCI_TDS * 3 / 4 + }; +diff --git a/grub-core/bus/usb/uhci.c b/grub-core/bus/usb/uhci.c +index 0fdea4c1e..03c4605b2 100644 +--- a/grub-core/bus/usb/uhci.c ++++ b/grub-core/bus/usb/uhci.c +@@ -845,6 +845,8 @@ static struct grub_usb_controller_dev usb_controller = + .hubports = grub_uhci_hubports, + .portstatus = grub_uhci_portstatus, + .detect_dev = grub_uhci_detect_dev, ++ .attach_dev = NULL, ++ .detach_dev = NULL, + /* estimated max. count of TDs for one bulk transfer */ + .max_bulk_tds = N_TD * 3 / 4 + }; +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index 2ae29cba1..8e963e84b 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -66,6 +66,15 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + dev->split_hubport = split_hubport; + dev->split_hubaddr = split_hubaddr; + ++ if (controller->dev->attach_dev) { ++ err = controller->dev->attach_dev (controller, dev); ++ if (err) ++ { ++ grub_free (dev); ++ return NULL; ++ } ++ } ++ + err = grub_usb_device_initialize (dev); + if (err) + { +@@ -405,6 +414,8 @@ static void + detach_device (grub_usb_device_t dev) + { + unsigned i; ++ grub_usb_err_t err; ++ + int k; + if (!dev) + return; +@@ -425,6 +436,14 @@ detach_device (grub_usb_device_t dev) + if (inter && inter->detach_hook) + inter->detach_hook (dev, i, k); + } ++ if (dev->controller.dev->detach_dev) { ++ err = dev->controller.dev->detach_dev (&dev->controller, dev); ++ if (err) ++ { ++ // XXX ++ } ++ } ++ + grub_usb_devs[dev->addr] = 0; + } + +diff --git a/include/grub/usb.h b/include/grub/usb.h +index ea6ee8c2c..4dd179db2 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -126,6 +126,10 @@ struct grub_usb_controller_dev + + grub_usb_speed_t (*detect_dev) (grub_usb_controller_t dev, int port, int *changed); + ++ grub_usb_err_t (*attach_dev) (grub_usb_controller_t ctrl, grub_usb_device_t dev); ++ ++ grub_usb_err_t (*detach_dev) (grub_usb_controller_t ctrl, grub_usb_device_t dev); ++ + /* Per controller flag - port reset pending, don't do another reset */ + grub_uint64_t pending_reset; + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch b/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch new file mode 100644 index 00000000..7d69c3a6 --- /dev/null +++ b/config/grub/patches/0005-xhci/0005-grub-core-bus-usb-usbhub-Add-new-private-fields-for-.patch @@ -0,0 +1,77 @@ +From 5e5d74a4531770258e21dedd45c33f1a9d3afa6b Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:54:40 +0100 +Subject: [PATCH 5/8] grub-core/bus/usb/usbhub: Add new private fields for xHCI + controller + +Store the root port number, the route, consisting out of the port ID +in each nibble, and a pointer to driver private data. + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/usbhub.c | 11 ++++++++--- + include/grub/usb.h | 5 +++++ + 2 files changed, 13 insertions(+), 3 deletions(-) + +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index 8e963e84b..b4b3a1a61 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -49,7 +49,9 @@ static grub_usb_controller_dev_t grub_usb_list; + static grub_usb_device_t + grub_usb_hub_add_dev (grub_usb_controller_t controller, + grub_usb_speed_t speed, +- int split_hubport, int split_hubaddr) ++ int split_hubport, int split_hubaddr, ++ int root_portno, ++ grub_uint32_t route) + { + grub_usb_device_t dev; + int i; +@@ -65,6 +67,8 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + dev->speed = speed; + dev->split_hubport = split_hubport; + dev->split_hubaddr = split_hubaddr; ++ dev->root_port = root_portno; ++ dev->route = route; + + if (controller->dev->attach_dev) { + err = controller->dev->attach_dev (controller, dev); +@@ -245,7 +249,7 @@ attach_root_port (struct grub_usb_hub *hub, int portno, + and full/low speed device connected to OHCI/UHCI needs not + transaction translation - e.g. hubport and hubaddr should be + always none (zero) for any device connected to any root hub. */ +- dev = grub_usb_hub_add_dev (hub->controller, speed, 0, 0); ++ dev = grub_usb_hub_add_dev (hub->controller, speed, 0, 0, portno, 0); + hub->controller->dev->pending_reset = 0; + npending--; + if (! dev) +@@ -676,7 +680,8 @@ poll_nonroot_hub (grub_usb_device_t dev) + + /* Add the device and assign a device address to it. */ + next_dev = grub_usb_hub_add_dev (&dev->controller, speed, +- split_hubport, split_hubaddr); ++ split_hubport, split_hubaddr, dev->root_port, ++ dev->route << 4 | (i & 0xf)); + if (dev->controller.dev->pending_reset) + { + dev->controller.dev->pending_reset = 0; +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 4dd179db2..609faf7d0 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -237,6 +237,11 @@ struct grub_usb_device + int split_hubport; + + int split_hubaddr; ++ ++ /* xHCI specific information */ ++ int root_port; ++ grub_uint32_t route; ++ void *xhci_priv; + }; + + +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch b/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch new file mode 100644 index 00000000..11df42d8 --- /dev/null +++ b/config/grub/patches/0005-xhci/0006-grub-core-bus-usb-Add-xhci-support.patch @@ -0,0 +1,2814 @@ +From fe3a0bce527e059e9121eb5ad2c3cc099f07a4bf Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Sun, 15 Nov 2020 19:59:25 +0100 +Subject: [PATCH 6/8] grub-core/bus/usb: Add xhci support + +Add support for xHCI USB controllers. +The code is based on seabios implementation, but has been heavily +modified to match grubs internals. + +Changes done in version 2: +* Code cleanup +* Code style fixes +* Don't leak memory buffers +* Compile without warnings +* Add more defines +* Add more helper functions +* Don't assume a 1:1 virtual to physical mapping +* Flush cachelines after writing buffers +* Don't use hardcoded page size +* Proper scratchpad register setup +* xHCI bios ownership handoff + +Changes done in version 3: +* Fixed a race condition detecting events, which doesn't appear on + qemu based xHCI controllers +* Don't accidently disable USB3.0 devices after first command +* Support arbitrary protocol speed IDs +* Coding style cleanup + +Tested: +* Qemu system x86_64 + * virtual USB HID keyboard (usb-kbd) + * virtual USB HID mass storage (usb-storage) +* init Supermicro X11SSH-F + * iKVM HID keyboard + * USB3 HID mass storage (controller root port) + * USB HID keyboard + +TODO: + * Test on more hardware + * Test on USB3 hubs + * Support for USB 3.1 and USB 3.2 controllers + +Tested on qemu using coreboot and grub as payload: + +qemu-system-x86_64 -M q35 -bios $firmware -device qemu-xhci,id=xhci -accel kvm -m 1024M \ + -device usb-storage,drive=thumbdrive,bus=xhci.0,port=3 \ + -drive if=none,format=raw,id=thumbdrive,file=ubuntu-20.04.1-desktop-amd64.iso \ + -device usb-kbd,bus=xhci.0 + +Signed-off-by: Patrick Rudolph +Signed-off-by: sylv +--- + Makefile.am | 2 +- + grub-core/Makefile.core.def | 7 + + grub-core/bus/usb/xhci-pci.c | 195 +++ + grub-core/bus/usb/xhci.c | 2496 ++++++++++++++++++++++++++++++++++ + include/grub/usb.h | 4 + + 5 files changed, 2703 insertions(+), 1 deletion(-) + create mode 100644 grub-core/bus/usb/xhci-pci.c + create mode 100644 grub-core/bus/usb/xhci.c + +diff --git a/Makefile.am b/Makefile.am +index 43635d5ff..65016f856 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -434,7 +434,7 @@ if COND_i386_coreboot + FS_PAYLOAD_MODULES ?= $(shell cat grub-core/fs.lst) + default_payload.elf: grub-mkstandalone grub-mkimage FORCE + test -f $@ && rm $@ || true +- pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(FS_PAYLOAD_MODULES) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg ++ pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata xhci ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(FS_PAYLOAD_MODULES) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg + endif + + endif +diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def +index fb6078a34..64c3806ab 100644 +--- a/grub-core/Makefile.core.def ++++ b/grub-core/Makefile.core.def +@@ -667,6 +667,13 @@ module = { + enable = arm_coreboot; + }; + ++module = { ++ name = xhci; ++ common = bus/usb/xhci.c; ++ pci = bus/usb/xhci-pci.c; ++ enable = pci; ++}; ++ + module = { + name = pci; + common = bus/pci.c; +diff --git a/grub-core/bus/usb/xhci-pci.c b/grub-core/bus/usb/xhci-pci.c +new file mode 100644 +index 000000000..a5bd3c97d +--- /dev/null ++++ b/grub-core/bus/usb/xhci-pci.c +@@ -0,0 +1,195 @@ ++/* xhci.c - XHCI Support. */ ++/* ++ * GRUB -- GRand Unified Bootloader ++ * Copyright (C) 2020 9elements Cyber Security ++ * ++ * GRUB is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * GRUB is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with GRUB. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GRUB_XHCI_PCI_SBRN_REG 0x60 ++#define GRUB_XHCI_ADDR_MEM_MASK (~0xff) ++ ++/* USBLEGSUP bits and related OS OWNED byte offset */ ++enum ++{ ++ GRUB_XHCI_BIOS_OWNED = (1 << 16), ++ GRUB_XHCI_OS_OWNED = (1 << 24) ++}; ++ ++/* PCI iteration function... */ ++static int ++grub_xhci_pci_iter (grub_pci_device_t dev, grub_pci_id_t pciid, ++ void *data __attribute__ ((unused))) ++{ ++ volatile grub_uint32_t *regs; ++ grub_uint32_t base, base_h; ++ grub_uint32_t eecp_offset; ++ grub_uint32_t usblegsup = 0; ++ grub_uint64_t maxtime; ++ grub_uint32_t interf; ++ grub_uint32_t subclass; ++ grub_uint32_t class; ++ grub_uint8_t release; ++ grub_uint32_t class_code; ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: begin\n"); ++ ++ if (pciid == GRUB_CS5536_PCIID) ++ { ++ grub_dprintf ("xhci", "CS5536 not supported\n"); ++ return 0; ++ } ++ else ++ { ++ grub_pci_address_t addr; ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_CLASS); ++ class_code = grub_pci_read (addr) >> 8; ++ interf = class_code & 0xFF; ++ subclass = (class_code >> 8) & 0xFF; ++ class = class_code >> 16; ++ ++ /* If this is not an XHCI controller, just return. */ ++ if (class != 0x0c || subclass != 0x03 || interf != 0x30) ++ return 0; ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: class OK\n"); ++ ++ /* Check Serial Bus Release Number */ ++ addr = grub_pci_make_address (dev, GRUB_XHCI_PCI_SBRN_REG); ++ release = grub_pci_read_byte (addr); ++ if (release != 0x30) ++ { ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: Wrong SBRN: %0x\n", ++ release); ++ return 0; ++ } ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: bus rev. num. OK\n"); ++ ++ /* Determine XHCI XHCC registers base address. */ ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0); ++ base = grub_pci_read (addr); ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG1); ++ base_h = grub_pci_read (addr); ++ /* Stop if registers are mapped above 4G - GRUB does not currently ++ * work with registers mapped above 4G */ ++ if (((base & GRUB_PCI_ADDR_MEM_TYPE_MASK) != GRUB_PCI_ADDR_MEM_TYPE_32) ++ && (base_h != 0)) ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: registers above 4G are not supported\n"); ++ return 0; ++ } ++ base &= GRUB_PCI_ADDR_MEM_MASK; ++ if (!base) ++ { ++ grub_dprintf ("xhci", ++ "XHCI: XHCI is not mapped\n"); ++ return 0; ++ } ++ ++ /* Set bus master - needed for coreboot, VMware, broken BIOSes etc. */ ++ addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND); ++ grub_pci_write_word(addr, ++ GRUB_PCI_COMMAND_MEM_ENABLED ++ | GRUB_PCI_COMMAND_BUS_MASTER ++ | grub_pci_read_word(addr)); ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: 32-bit XHCI OK\n"); ++ } ++ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: iobase of XHCC: %08x\n", ++ (base & GRUB_XHCI_ADDR_MEM_MASK)); ++ ++ regs = grub_pci_device_map_range (dev, ++ (base & GRUB_XHCI_ADDR_MEM_MASK), ++ 0x100); ++ ++ /* Is there EECP ? */ ++ eecp_offset = (grub_le_to_cpu32 (regs[2]) >> 8) & 0xff; ++ ++ /* Determine and change ownership. */ ++ /* EECP offset valid in HCCPARAMS */ ++ /* Ownership can be changed via EECP only */ ++ if (pciid != GRUB_CS5536_PCIID && eecp_offset >= 0x40) ++ { ++ grub_pci_address_t pciaddr_eecp; ++ pciaddr_eecp = grub_pci_make_address (dev, eecp_offset); ++ ++ usblegsup = grub_pci_read (pciaddr_eecp); ++ if (usblegsup & GRUB_XHCI_BIOS_OWNED) ++ { ++ grub_boot_time ("Taking ownership of XHCI controller"); ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: XHCI owned by: BIOS\n"); ++ /* Ownership change - set OS_OWNED bit */ ++ grub_pci_write (pciaddr_eecp, usblegsup | GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ ++ /* Wait for finish of ownership change, XHCI specification ++ * doesn't say how long it can take... */ ++ maxtime = grub_get_time_ms () + 1000; ++ while ((grub_pci_read (pciaddr_eecp) & GRUB_XHCI_BIOS_OWNED) ++ && (grub_get_time_ms () < maxtime)); ++ if (grub_pci_read (pciaddr_eecp) & GRUB_XHCI_BIOS_OWNED) ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_xhci_pci_iter: XHCI change ownership timeout"); ++ /* Change ownership in "hard way" - reset BIOS ownership */ ++ grub_pci_write (pciaddr_eecp, GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ } ++ else if (usblegsup & GRUB_XHCI_OS_OWNED) ++ /* XXX: What to do in this case - nothing ? Can it happen ? */ ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: XHCI owned by: OS\n"); ++ else ++ { ++ grub_dprintf ("xhci", ++ "XHCI grub_Xhci_pci_iter: XHCI owned by: NONE\n"); ++ /* XXX: What to do in this case ? Can it happen ? ++ * Is code below correct ? */ ++ /* Ownership change - set OS_OWNED bit */ ++ grub_pci_write (pciaddr_eecp, GRUB_XHCI_OS_OWNED); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ ++ /* Disable SMI, just to be sure. */ ++ pciaddr_eecp = grub_pci_make_address (dev, eecp_offset + 4); ++ grub_pci_write (pciaddr_eecp, 0); ++ /* Ensure PCI register is written */ ++ grub_pci_read (pciaddr_eecp); ++ } ++ ++ grub_dprintf ("xhci", "inithw: XHCI grub_xhci_pci_iter: ownership OK\n"); ++ ++ grub_xhci_init_device (regs); ++ return 0; ++} ++ ++void ++grub_xhci_pci_scan (void) ++{ ++ grub_pci_iterate (grub_xhci_pci_iter, NULL); ++} +diff --git a/grub-core/bus/usb/xhci.c b/grub-core/bus/usb/xhci.c +new file mode 100644 +index 000000000..f4591ffb5 +--- /dev/null ++++ b/grub-core/bus/usb/xhci.c +@@ -0,0 +1,2496 @@ ++/* xhci.c - XHCI Support. */ ++/* ++ * GRUB -- GRand Unified Bootloader ++ * Copyright (C) 2020 9elements Cyber Security ++ * ++ * GRUB is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * GRUB is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with GRUB. If not, see . ++ * ++ * Big parts of this software are inspired by seabios XHCI implementation ++ * Released under LGPLv3. Credits to: ++ * ++ * Copyright (C) 2013 Gerd Hoffmann ++ * Copyright (C) 2014 Kevin O'Connor ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++GRUB_MOD_LICENSE ("GPLv3+"); ++ ++/* This simple GRUB implementation of XHCI driver */ ++/* Based on the specification ++ * "eXtensible Host Controller Interface for Universal Serial Bus" Revision 1.2 ++ */ ++ ++ ++#define xhci_get_field(data, field) \ ++ (((data) >> field##_SHIFT) & field##_MASK) ++#define XHCI_PORTSC_PLS_MASK 0xf ++#define XHCI_PORTSC_PLS_SHIFT 5 ++#define XHCI_PORTSC_SPEED_MASK 0xf ++#define XHCI_PORTSC_SPEED_SHIFT 10 ++ ++enum ++{ ++ XHCI_USB_FULLSPEED = 1, ++ XHCI_USB_LOWSPEED, ++ XHCI_USB_HIGHSPEED, ++ XHCI_USB_SUPERSPEED ++}; ++ ++/* Chapter 5.3 Host Controller Capability Registers */ ++struct grub_xhci_caps { ++ grub_uint8_t caplength; ++ grub_uint8_t reserved_01; ++ grub_uint16_t hciversion; ++ grub_uint32_t hcsparams1; ++ grub_uint32_t hcsparams2; ++ grub_uint32_t hcsparams3; ++ grub_uint32_t hccparams; ++ grub_uint32_t dboff; ++ grub_uint32_t rtsoff; ++ grub_uint32_t hccparams2; ++} GRUB_PACKED; ++ ++/* extended capabilities */ ++struct grub_xhci_xcap { ++ grub_uint32_t cap; ++ grub_uint32_t data[]; ++} GRUB_PACKED; ++ ++#define XHCI_CAP_LEGACY_SUPPORT 1 ++#define XHCI_CAP_SUPPORTED_PROTOCOL 2 ++ ++struct xhci_portmap { ++ grub_uint8_t start; ++ grub_uint8_t count; ++} GRUB_PACKED; ++ ++struct grub_xhci_op { ++ grub_uint32_t usbcmd; ++ grub_uint32_t usbsts; ++ grub_uint32_t pagesize; ++ grub_uint32_t reserved_01[2]; ++ grub_uint32_t dnctl; ++ grub_uint32_t crcr_low; ++ grub_uint32_t crcr_high; ++ grub_uint32_t reserved_02[4]; ++ grub_uint32_t dcbaap_low; ++ grub_uint32_t dcbaap_high; ++ grub_uint32_t config; ++} GRUB_PACKED; ++ ++enum ++{ ++ GRUB_XHCI_CMD_RS = (1<<0), ++ GRUB_XHCI_CMD_HCRST = (1<<1), ++ GRUB_XHCI_CMD_INTE = (1<<2), ++ GRUB_XHCI_CMD_HSEE = (1<<3), ++ GRUB_XHCI_CMD_LHCRST = (1<<7), ++ GRUB_XHCI_CMD_CSS = (1<<8), ++ GRUB_XHCI_CMD_CRS = (1<<9), ++ GRUB_XHCI_CMD_EWE = (1<<10), ++ GRUB_XHCI_CMD_EU3S = (1<<11) ++}; ++ ++enum ++{ ++ GRUB_XHCI_STS_HCH = (1<<0), ++ GRUB_XHCI_STS_HSE = (1<<2), ++ GRUB_XHCI_STS_EINT = (1<<3), ++ GRUB_XHCI_STS_PCD = (1<<4), ++ GRUB_XHCI_STS_SSS = (1<<8), ++ GRUB_XHCI_STS_RSS = (1<<9), ++ GRUB_XHCI_STS_SRE = (1<<10), ++ GRUB_XHCI_STS_CNR = (1<<11), ++ GRUB_XHCI_STS_HCE = (1<<12) ++}; ++ ++ ++/* Port Registers Offset */ ++#define GRUB_XHCI_PR_OFFSET 0x400 ++/* Interrupter Registers Offset */ ++#define GRUB_XHCI_IR_OFFSET 0x20 ++ ++/* Port Status and Control registers offsets */ ++ ++/* Chapter 6 Data Structures */ ++#define ALIGN_SPBA 64 ++#define ALIGN_DCBAA 64 ++#define ALIGN_CMD_RING_SEG 64 ++#define ALIGN_EVT_RING_SEG 64 ++#define ALIGN_EVT_RING_TABLE 64 ++#define ALIGN_TRB 16 ++#define ALIGN_INCTX 64 ++#define ALIGN_SLOTCTX 32 ++ ++#define BOUNDARY_RING 0x10000 ++ ++enum ++{ ++ GRUB_XHCI_PORTSC_CCS = (1<<0), ++ GRUB_XHCI_PORTSC_PED = (1<<1), ++ GRUB_XHCI_PORTSC_OCA = (1<<3), ++ GRUB_XHCI_PORTSC_PR = (1<<4), ++ GRUB_XHCI_PORTSC_PP = (1<<9), ++ GRUB_XHCI_PORTSC_SPEED_FULL = (1<<10), ++ GRUB_XHCI_PORTSC_SPEED_LOW = (2<<10), ++ GRUB_XHCI_PORTSC_SPEED_HIGH = (3<<10), ++ GRUB_XHCI_PORTSC_SPEED_SUPER = (4<<10), ++ GRUB_XHCI_PORTSC_LWS = (1<<16), ++ GRUB_XHCI_PORTSC_CSC = (1<<17), ++ GRUB_XHCI_PORTSC_PEC = (1<<18), ++ GRUB_XHCI_PORTSC_WRC = (1<<19), ++ GRUB_XHCI_PORTSC_OCC = (1<<20), ++ GRUB_XHCI_PORTSC_PRC = (1<<21), ++ GRUB_XHCI_PORTSC_PLC = (1<<22), ++ GRUB_XHCI_PORTSC_CEC = (1<<23), ++ GRUB_XHCI_PORTSC_CAS = (1<<24), ++ GRUB_XHCI_PORTSC_WCE = (1<<25), ++ GRUB_XHCI_PORTSC_WDE = (1<<26), ++ GRUB_XHCI_PORTSC_WOE = (1<<27), ++ GRUB_XHCI_PORTSC_DR = (1<<30), ++ GRUB_XHCI_PORTSC_WPR = (1<<31) ++}; ++ ++/* XHCI memory data structs */ ++#define GRUB_XHCI_MAX_ENDPOINTS 32 ++ ++#define GRUB_XHCI_RING_ITEMS 128 ++#define GRUB_XHCI_RING_SIZE (GRUB_XHCI_RING_ITEMS*sizeof(struct grub_xhci_trb)) ++/* ++ * xhci_ring structs are allocated with XHCI_RING_SIZE alignment, ++ * then we can get it from a trb pointer (provided by evt ring). ++ */ ++#define XHCI_RING(_trb) \ ++ ((struct grub_xhci_ring*)((grub_uint32_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) ++ ++/* slot context */ ++struct grub_xhci_slotctx { ++ grub_uint32_t ctx[4]; ++ grub_uint32_t reserved_01[4]; ++} GRUB_PACKED; ++ ++/* endpoint context */ ++struct grub_xhci_epctx { ++ grub_uint32_t ctx[2]; ++ grub_uint32_t deq_low; ++ grub_uint32_t deq_high; ++ grub_uint32_t length; ++ grub_uint32_t reserved_01[3]; ++} GRUB_PACKED; ++ ++/* device context array element */ ++struct grub_xhci_devlist { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++} GRUB_PACKED; ++ ++/* input context */ ++struct grub_xhci_inctx { ++ grub_uint32_t del; ++ grub_uint32_t add; ++ grub_uint32_t reserved_01[6]; ++} GRUB_PACKED; ++ ++/* transfer block (ring element) */ ++struct grub_xhci_trb { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++ grub_uint32_t status; ++ grub_uint32_t control; ++} GRUB_PACKED; ++ ++#define TRB_C (1<<0) ++#define TRB_TYPE_SHIFT 10 ++#define TRB_TYPE_MASK 0x3f ++#define TRB_TYPE(t) (((t) >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) ++ ++#define TRB_EV_ED (1<<2) ++ ++#define TRB_TR_ENT (1<<1) ++#define TRB_TR_ISP (1<<2) ++#define TRB_TR_NS (1<<3) ++#define TRB_TR_CH (1<<4) ++#define TRB_TR_IOC (1<<5) ++#define TRB_TR_IDT (1<<6) ++#define TRB_TR_TBC_SHIFT 7 ++#define TRB_TR_TBC_MASK 0x3 ++#define TRB_TR_BEI (1<<9) ++#define TRB_TR_TLBPC_SHIFT 16 ++#define TRB_TR_TLBPC_MASK 0xf ++#define TRB_TR_FRAMEID_SHIFT 20 ++#define TRB_TR_FRAMEID_MASK 0x7ff ++#define TRB_TR_SIA (1<<31) ++ ++#define TRB_TR_DIR (1<<16) ++ ++#define TRB_CR_SLOTID_SHIFT 24 ++#define TRB_CR_SLOTID_MASK 0xff ++#define TRB_CR_EPID_SHIFT 16 ++#define TRB_CR_EPID_MASK 0x1f ++ ++#define TRB_CR_BSR (1<<9) ++#define TRB_CR_DC (1<<9) ++ ++#define TRB_LK_TC (1<<1) ++ ++#define TRB_INTR_SHIFT 22 ++#define TRB_INTR_MASK 0x3ff ++#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) ++ ++typedef enum TRBType { ++ TRB_RESERVED = 0, ++ TR_NORMAL, ++ TR_SETUP, ++ TR_DATA, ++ TR_STATUS, ++ TR_ISOCH, ++ TR_LINK, ++ TR_EVDATA, ++ TR_NOOP, ++ CR_ENABLE_SLOT, ++ CR_DISABLE_SLOT, ++ CR_ADDRESS_DEVICE, ++ CR_CONFIGURE_ENDPOINT, ++ CR_EVALUATE_CONTEXT, ++ CR_RESET_ENDPOINT, ++ CR_STOP_ENDPOINT, ++ CR_SET_TR_DEQUEUE, ++ CR_RESET_DEVICE, ++ CR_FORCE_EVENT, ++ CR_NEGOTIATE_BW, ++ CR_SET_LATENCY_TOLERANCE, ++ CR_GET_PORT_BANDWIDTH, ++ CR_FORCE_HEADER, ++ CR_NOOP, ++ ER_TRANSFER = 32, ++ ER_COMMAND_COMPLETE, ++ ER_PORT_STATUS_CHANGE, ++ ER_BANDWIDTH_REQUEST, ++ ER_DOORBELL, ++ ER_HOST_CONTROLLER, ++ ER_DEVICE_NOTIFICATION, ++ ER_MFINDEX_WRAP, ++} TRBType; ++ ++typedef enum TRBCCode { ++ CC_INVALID = 0, ++ CC_SUCCESS, ++ CC_DATA_BUFFER_ERROR, ++ CC_BABBLE_DETECTED, ++ CC_USB_TRANSACTION_ERROR, ++ CC_TRB_ERROR, ++ CC_STALL_ERROR, ++ CC_RESOURCE_ERROR, ++ CC_BANDWIDTH_ERROR, ++ CC_NO_SLOTS_ERROR, ++ CC_INVALID_STREAM_TYPE_ERROR, ++ CC_SLOT_NOT_ENABLED_ERROR, ++ CC_EP_NOT_ENABLED_ERROR, ++ CC_SHORT_PACKET, ++ CC_RING_UNDERRUN, ++ CC_RING_OVERRUN, ++ CC_VF_ER_FULL, ++ CC_PARAMETER_ERROR, ++ CC_BANDWIDTH_OVERRUN, ++ CC_CONTEXT_STATE_ERROR, ++ CC_NO_PING_RESPONSE_ERROR, ++ CC_EVENT_RING_FULL_ERROR, ++ CC_INCOMPATIBLE_DEVICE_ERROR, ++ CC_MISSED_SERVICE_ERROR, ++ CC_COMMAND_RING_STOPPED, ++ CC_COMMAND_ABORTED, ++ CC_STOPPED, ++ CC_STOPPED_LENGTH_INVALID, ++ CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, ++ CC_ISOCH_BUFFER_OVERRUN = 31, ++ CC_EVENT_LOST_ERROR, ++ CC_UNDEFINED_ERROR, ++ CC_INVALID_STREAM_ID_ERROR, ++ CC_SECONDARY_BANDWIDTH_ERROR, ++ CC_SPLIT_TRANSACTION_ERROR ++} TRBCCode; ++ ++enum { ++ PLS_U0 = 0, ++ PLS_U1 = 1, ++ PLS_U2 = 2, ++ PLS_U3 = 3, ++ PLS_DISABLED = 4, ++ PLS_RX_DETECT = 5, ++ PLS_INACTIVE = 6, ++ PLS_POLLING = 7, ++ PLS_RECOVERY = 8, ++ PLS_HOT_RESET = 9, ++ PLS_COMPILANCE_MODE = 10, ++ PLS_TEST_MODE = 11, ++ PLS_RESUME = 15, ++}; ++ ++/* event ring segment */ ++struct grub_xhci_er_seg { ++ grub_uint32_t ptr_low; ++ grub_uint32_t ptr_high; ++ grub_uint32_t size; ++ grub_uint32_t reserved_01; ++} GRUB_PACKED; ++ ++struct grub_xhci_ring { ++ struct grub_xhci_trb ring[GRUB_XHCI_RING_ITEMS]; ++ struct grub_xhci_trb evt; ++ grub_uint32_t eidx; ++ grub_uint32_t nidx; ++ grub_uint32_t cs; ++}; ++ ++/* port registers */ ++struct grub_xhci_pr { ++ grub_uint32_t portsc; ++ grub_uint32_t portpmsc; ++ grub_uint32_t portli; ++ grub_uint32_t reserved_01; ++} GRUB_PACKED; ++ ++/* doorbell registers */ ++struct grub_xhci_db { ++ grub_uint32_t doorbell; ++} GRUB_PACKED; ++ ++/* runtime registers */ ++struct grub_xhci_rts { ++ grub_uint32_t mfindex; ++} GRUB_PACKED; ++ ++/* interrupter registers */ ++struct grub_xhci_ir { ++ grub_uint32_t iman; ++ grub_uint32_t imod; ++ grub_uint32_t erstsz; ++ grub_uint32_t reserved_01; ++ grub_uint32_t erstba_low; ++ grub_uint32_t erstba_high; ++ grub_uint32_t erdp_low; ++ grub_uint32_t erdp_high; ++} GRUB_PACKED; ++ ++struct grub_xhci_psid { ++ grub_uint8_t id; ++ grub_uint8_t psie; ++ grub_uint16_t psim; ++ grub_uint64_t bitrate; ++ grub_usb_speed_t grub_usb_speed; ++}; ++ ++struct grub_xhci_psids { ++ grub_uint8_t major; ++ grub_uint8_t minor; ++ struct grub_xhci_psid psids[16]; ++}; ++ ++struct grub_xhci ++{ ++ grub_uint8_t shutdown; /* 1 if preparing shutdown of controller */ ++ /* xhci registers */ ++ volatile struct grub_xhci_caps *caps; /* Capability registers */ ++ volatile struct grub_xhci_op *op; /* Operational registers */ ++ volatile struct grub_xhci_pr *pr; /* Port Registers */ ++ volatile struct grub_xhci_db *db; /* doorbell */ ++ volatile struct grub_xhci_ir *ir; /* Interrupt Registers */ ++ /* devinfo */ ++ grub_uint32_t xcap; ++ grub_uint32_t ports; ++ grub_uint32_t slots; ++ grub_uint8_t flag64; ++ grub_uint16_t spb; ++ grub_uint32_t pagesize; ++ struct xhci_portmap usb2; ++ struct xhci_portmap usb3; ++ struct grub_xhci_psids *psids; ++ /* xhci data structures */ ++ struct grub_pci_dma_chunk *devs_dma; ++ volatile struct grub_xhci_devlist *devs; ++ struct grub_pci_dma_chunk *cmds_dma; ++ volatile struct grub_xhci_ring *cmds; ++ struct grub_pci_dma_chunk *evts_dma; ++ volatile struct grub_xhci_ring *evts; ++ struct grub_pci_dma_chunk *eseg_dma; ++ volatile struct grub_xhci_er_seg *eseg; ++ struct grub_pci_dma_chunk *spba_dma; ++ struct grub_pci_dma_chunk *spad_dma; ++ ++ struct grub_xhci *next; ++}; ++ ++struct grub_xhci_priv { ++ grub_uint8_t slotid; ++ grub_uint32_t max_packet; ++ struct grub_pci_dma_chunk *enpoint_trbs_dma[32]; ++ volatile struct grub_xhci_ring *enpoint_trbs[32]; ++ struct grub_pci_dma_chunk *slotctx_dma; ++}; ++ ++struct grub_xhci_port { ++ grub_uint32_t portsc; ++ grub_uint32_t portpmsc; ++ grub_uint32_t portli; ++ grub_uint32_t reserved_01; ++}; ++ ++struct grub_xhci_transfer_controller_data { ++ grub_uint32_t transfer_size; ++}; ++ ++static struct grub_xhci *xhci; ++ ++/**************************************************************** ++ * general access functions ++ ****************************************************************/ ++ ++static inline void ++grub_xhci_write32(volatile void *addr, grub_uint32_t val) { ++ *(volatile grub_uint32_t *)addr = val; ++} ++static inline void ++grub_xhci_write16(volatile void *addr, grub_uint16_t val) { ++ *(volatile grub_uint16_t *)addr = val; ++} ++static inline void ++grub_xhci_write8(void *addr, grub_uint8_t val) { ++ *(volatile grub_uint8_t *)addr = val; ++} ++ ++static inline grub_uint32_t ++grub_xhci_read32(volatile void *addr) { ++ return grub_le_to_cpu32 (*((volatile grub_uint32_t *)addr)); ++} ++ ++static inline grub_uint16_t ++grub_xhci_read16(volatile void *addr) { ++ return grub_le_to_cpu16 (*((volatile grub_uint32_t *)addr)); ++} ++static inline grub_uint8_t ++grub_xhci_read8(volatile void *addr) { ++ return (*((volatile grub_uint32_t *)addr)); ++} ++ ++static inline grub_uint32_t ++grub_xhci_port_read (struct grub_xhci *x, grub_uint32_t port) ++{ ++ return grub_xhci_read32(&x->pr[port].portsc); ++} ++ ++static inline void ++grub_xhci_port_write (struct grub_xhci *x, grub_uint32_t port, ++ grub_uint32_t and_mask, grub_uint32_t or_mask) ++{ ++ grub_uint32_t reg = grub_xhci_port_read(x, port); ++ reg &= and_mask; ++ reg |= or_mask; ++ ++ grub_xhci_write32(&x->pr[port].portsc, reg); ++} ++ ++/**************************************************************** ++ * xhci status and support functions ++ ****************************************************************/ ++ ++static grub_uint32_t xhci_get_pagesize(struct grub_xhci *x) ++{ ++ /* Chapter 5.4.3 Page Size Register (PAGESIZE) */ ++ for (grub_uint8_t i = 0; i < 16; i++) ++ { ++ if (grub_xhci_read32(&x->op->pagesize) & (1 << i)) ++ return 1 << (12 + i); ++ } ++ return 0; ++} ++ ++static grub_uint8_t xhci_is_halted(struct grub_xhci *x) ++{ ++ return !!(grub_xhci_read32(&x->op->usbsts) & 1); ++} ++ ++/* Just for debugging */ ++static void xhci_check_status(struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ ++ reg = grub_xhci_read32(&x->op->usbsts); ++ if (reg & 1) ++ grub_dprintf("xhci", "%s: xHCI halted\n", __func__); ++ if (reg & 2) ++ grub_dprintf("xhci", "%s: Host system error detected\n", __func__); ++ if (reg & (1 << 12)) ++ grub_dprintf("xhci", "%s: Internal error detected\n", __func__); ++ reg = grub_xhci_read32(&x->op->crcr_low); ++ if (reg & (1 << 3)) ++ grub_dprintf("xhci", "%s: Command ring running\n", __func__); ++} ++ ++/* xhci_memalign_dma32 allocates DMA memory satisfying alignment and boundary ++ * requirements without wasting to much memory */ ++static struct grub_pci_dma_chunk * ++xhci_memalign_dma32(grub_size_t align, ++ grub_size_t size, ++ grub_size_t boundary) ++{ ++ struct grub_pci_dma_chunk *tmp; ++ const grub_uint32_t mask = boundary - 1; ++ grub_uint32_t start, end; ++ ++ /* Allocate some memory and check if it doesn't cross boundary */ ++ tmp = grub_memalign_dma32(align, size); ++ start = grub_dma_get_phys(tmp); ++ end = start + size - 1; ++ if ((start & mask) == (end & mask)) ++ return tmp; ++ /* Buffer isn't usable, allocate bigger one */ ++ grub_dma_free(tmp); ++ ++ return grub_memalign_dma32(boundary, size); ++} ++ ++/**************************************************************** ++ * helper functions for in context DMA buffer ++ ****************************************************************/ ++ ++static int ++grub_xhci_inctx_size(struct grub_xhci *x) ++{ ++ const grub_uint8_t cnt = GRUB_XHCI_MAX_ENDPOINTS + 1; ++ return (sizeof(struct grub_xhci_inctx) * cnt) << x->flag64; ++} ++ ++static void ++grub_xhci_inctx_sync_dma_caches(struct grub_xhci *x, struct grub_pci_dma_chunk *inctx) ++{ ++ grub_arch_sync_dma_caches(inctx, grub_xhci_inctx_size(x)); ++} ++ ++static struct grub_pci_dma_chunk * ++grub_xhci_alloc_inctx(struct grub_xhci *x, int maxepid, ++ struct grub_usb_device *dev) ++{ ++ int size = grub_xhci_inctx_size(x); ++ struct grub_pci_dma_chunk *dma = xhci_memalign_dma32(ALIGN_INCTX, size, ++ x->pagesize); ++ if (!dma) ++ return NULL; ++ ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(dma); ++ grub_memset((void *)in, 0, size); ++ ++ struct grub_xhci_slotctx *slot = (void*)&in[1 << x->flag64]; ++ slot->ctx[0] |= maxepid << 27; /* context entries */ ++ grub_dprintf("xhci", "%s: speed=%d root_port=%d\n", __func__, dev->speed, dev->root_port); ++ switch (dev->speed) { ++ case GRUB_USB_SPEED_FULL: ++ slot->ctx[0] |= XHCI_USB_FULLSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_HIGH: ++ slot->ctx[0] |= XHCI_USB_HIGHSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_LOW: ++ slot->ctx[0] |= XHCI_USB_LOWSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_SUPER: ++ slot->ctx[0] |= XHCI_USB_SUPERSPEED << 20; ++ break; ++ case GRUB_USB_SPEED_NONE: ++ slot->ctx[0] |= 0 << 20; ++ break; ++ } ++ ++ /* Route is greater zero on devices that are connected to a non root hub */ ++ if (dev->route) ++ { ++ /* FIXME: Implement this code for non SuperSpeed hub devices */ ++ } ++ slot->ctx[0] |= dev->route; ++ slot->ctx[1] |= (dev->root_port+1) << 16; ++ ++ grub_arch_sync_dma_caches(in, size); ++ ++ return dma; ++} ++ ++/**************************************************************** ++ * xHCI event processing ++ ****************************************************************/ ++ ++/* Dequeue events on the XHCI event ring generated by the hardware */ ++static void xhci_process_events(struct grub_xhci *x) ++{ ++ volatile struct grub_xhci_ring *evts = x->evts; ++ /* XXX invalidate caches */ ++ ++ for (;;) { ++ /* check for event */ ++ grub_uint32_t nidx = grub_xhci_read32(&evts->nidx); ++ grub_uint32_t cs = grub_xhci_read32(&evts->cs); ++ volatile struct grub_xhci_trb *etrb = evts->ring + nidx; ++ grub_uint32_t control = grub_xhci_read32(&etrb->control); ++ if ((control & TRB_C) != (cs ? 1 : 0)) ++ return; ++ ++ /* process event */ ++ grub_uint32_t evt_type = TRB_TYPE(control); ++ grub_uint32_t evt_cc = (grub_xhci_read32(&etrb->status) >> 24) & 0xff; ++ ++ switch (evt_type) ++ { ++ case ER_TRANSFER: ++ case ER_COMMAND_COMPLETE: ++ { ++ struct grub_xhci_trb *rtrb = (void*)grub_xhci_read32(&etrb->ptr_low); ++ struct grub_xhci_ring *ring = XHCI_RING(rtrb); ++ volatile struct grub_xhci_trb *evt = &ring->evt; ++ grub_uint32_t eidx = rtrb - ring->ring + 1; ++ grub_dprintf("xhci", "%s: ring %p [trb %p, evt %p, type %d, eidx %d, cc %d]\n", ++ __func__, ring, rtrb, evt, evt_type, eidx, evt_cc); ++ *evt = *etrb; ++ grub_xhci_write32(&ring->eidx, eidx); ++ break; ++ } ++ case ER_PORT_STATUS_CHANGE: ++ { ++ /* Nothing to do here. grub_xhci_detect_dev will handle it */ ++ break; ++ } ++ default: ++ { ++ grub_dprintf("xhci", "%s: unknown event, type %d, cc %d\n", ++ __func__, evt_type, evt_cc); ++ break; ++ } ++ } ++ ++ /* move ring index, notify xhci */ ++ nidx++; ++ if (nidx == GRUB_XHCI_RING_ITEMS) ++ { ++ nidx = 0; ++ cs = cs ? 0 : 1; ++ grub_xhci_write32(&evts->cs, cs); ++ } ++ grub_xhci_write32(&evts->nidx, nidx); ++ volatile struct grub_xhci_ir *ir = x->ir; ++ grub_uint32_t erdp = (grub_uint32_t)(evts->ring + nidx); ++ grub_xhci_write32(&ir->erdp_low, erdp); ++ grub_xhci_write32(&ir->erdp_high, 0); ++ } ++} ++ ++/**************************************************************** ++ * TRB handling ++ ****************************************************************/ ++ ++/* Signal the hardware to process events on a TRB ring */ ++static void xhci_doorbell(struct grub_xhci *x, grub_uint32_t slotid, grub_uint32_t value) ++{ ++ xhci_check_status(x); ++ grub_dprintf("xhci", "%s: slotid %d, epid %d\n", __func__, slotid, value); ++ grub_xhci_write32(&x->db[slotid].doorbell, value); ++} ++ ++/* Check if a ring has any pending TRBs */ ++static int xhci_ring_busy(volatile struct grub_xhci_ring *ring) ++{ ++ grub_uint32_t eidx = grub_xhci_read32(&ring->eidx); ++ grub_uint32_t nidx = grub_xhci_read32(&ring->nidx); ++ ++ return (eidx != nidx); ++} ++ ++/* Returns free space in ring */ ++static int xhci_ring_free_space(volatile struct grub_xhci_ring *ring) ++{ ++ grub_uint32_t eidx = grub_xhci_read32(&ring->eidx); ++ grub_uint32_t nidx = grub_xhci_read32(&ring->nidx); ++ ++ /* nidx is never 0, so reduce ring buffer size by one */ ++ return (eidx > nidx) ? eidx-nidx ++ : (ARRAY_SIZE(ring->ring) - 1) - nidx + eidx; ++} ++ ++/* Check if a ring is full */ ++static int xhci_ring_full(volatile struct grub_xhci_ring *ring) ++{ ++ /* Might need to insert one link TRB */ ++ return xhci_ring_free_space(ring) <= 1; ++} ++ ++/* Check if a ring is almost full */ ++static int xhci_ring_almost_full(volatile struct grub_xhci_ring *ring) ++{ ++ /* Might need to insert one link TRB */ ++ return xhci_ring_free_space(ring) <= 2; ++} ++ ++/* Wait for a ring to empty (all TRBs processed by hardware) */ ++static int xhci_event_wait(struct grub_xhci *x, ++ volatile struct grub_xhci_ring *ring, ++ grub_uint32_t timeout) ++{ ++ grub_uint32_t end = grub_get_time_ms () + timeout; ++ ++ for (;;) ++ { ++ xhci_check_status(x); ++ xhci_process_events(x); ++ if (!xhci_ring_busy(ring)) ++ { ++ grub_uint32_t status = ring->evt.status; ++ return (status >> 24) & 0xff; ++ } ++ if (grub_get_time_ms () > end) ++ { ++ xhci_check_status(x); ++ grub_dprintf("xhci", "%s: Timeout waiting for event\n", __func__); ++ return -1; ++ } ++ } ++} ++ ++/* Add a TRB to the given ring, either regular or inline */ ++static void xhci_trb_fill(volatile struct grub_xhci_ring *ring, ++ grub_uint64_t ptr, grub_uint32_t xferlen, ++ grub_uint32_t flags) ++{ ++ volatile struct grub_xhci_trb *dst = &ring->ring[ring->nidx]; ++ dst->ptr_low = ptr & 0xffffffff; ++ dst->ptr_high = ptr >> 32; ++ dst->status = xferlen; ++ dst->control = flags | (ring->cs ? TRB_C : 0); ++ ++ grub_arch_sync_dma_caches(dst, sizeof(ring->ring[0])); ++} ++ ++/* ++ * Queue a TRB onto a ring. ++ * ++ * The caller must pass a pointer to the data in physical address-space or the ++ * data itself (but no more than 8 bytes) in data_or_addr. Inline data must have ++ * the flag TRB_TR_IDT set. ++ */ ++static void xhci_trb_queue(volatile struct grub_xhci_ring *ring, ++ grub_uint64_t data_or_addr, ++ grub_uint32_t xferlen, grub_uint32_t flags) ++{ ++ grub_dprintf("xhci", "%s: ring %p data %llx len %d flags 0x%x remain 0x%x\n", __func__, ++ ring, data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); ++ ++ if (xhci_ring_full(ring)) ++ { ++ grub_dprintf("xhci", "%s: ERROR: ring %p is full, discarding TRB\n", ++ __func__, ring); ++ return; ++ } ++ ++ if (ring->nidx >= ARRAY_SIZE(ring->ring) - 1) ++ { ++ /* Reset to command buffer pointer to the first element */ ++ xhci_trb_fill(ring, (grub_addr_t)ring->ring, 0, (TR_LINK << 10) | TRB_LK_TC); ++ ring->nidx = 0; ++ ring->cs ^= 1; ++ grub_dprintf("xhci", "%s: ring %p [linked]\n", __func__, ring); ++ } ++ ++ xhci_trb_fill(ring, data_or_addr, xferlen, flags); ++ ring->nidx++; ++ grub_dprintf("xhci", "%s: ring %p [nidx %d, len %d]\n", ++ __func__, ring, ring->nidx, xferlen); ++} ++ ++/* ++ * Queue a TRB onto a ring and flush it if necessary. ++ * ++ * The caller must pass a pointer to the data in physical address-space or the ++ * data itself (but no more than 8 bytes) in data_or_addr. Inline data must have ++ * the flag TRB_TR_IDT set. ++ */ ++static int xhci_trb_queue_and_flush(struct grub_xhci *x, ++ grub_uint32_t slotid, ++ grub_uint32_t epid, ++ volatile struct grub_xhci_ring *ring, ++ grub_uint64_t data_or_addr, ++ grub_uint32_t xferlen, grub_uint32_t flags) ++{ ++ grub_uint8_t submit = 0; ++ if (xhci_ring_almost_full(ring)) ++ { ++ grub_dprintf("xhci", "%s: almost full e %d n %d\n", __func__, ring->eidx, ring->nidx); ++ flags |= TRB_TR_IOC; ++ submit = 1; ++ } ++ /* Note: xhci_trb_queue might queue on or two elements, if the end of the TRB ++ * has been reached. The caller must account for that when filling the TRB. */ ++ xhci_trb_queue(ring, data_or_addr, xferlen, flags); ++ /* Submit if less no free slot is remaining, we might need an additional ++ * one on the next call to this function. */ ++ if (submit) ++ { ++ xhci_doorbell(x, slotid, epid); ++ int rc = xhci_event_wait(x, ring, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ return rc; ++ } ++ return 0; ++} ++ ++/**************************************************************** ++ * xHCI command functions ++ ****************************************************************/ ++ ++/* Submit a command to the xHCI command TRB */ ++static int xhci_cmd_submit(struct grub_xhci *x, ++ struct grub_pci_dma_chunk *inctx_dma, ++ grub_uint32_t flags) ++{ ++ volatile struct grub_xhci_inctx *inctx; ++ /* Don't submit if halted, it will fail */ ++ if (xhci_is_halted(x)) ++ return -1; ++ ++ if (inctx_dma) ++ { ++ grub_xhci_inctx_sync_dma_caches(x, inctx_dma); ++ ++ inctx = grub_dma_get_virt(inctx_dma); ++ ++ struct grub_xhci_slotctx *slot = (void*)&inctx[1 << x->flag64]; ++ grub_uint32_t port = ((slot->ctx[1] >> 16) & 0xff) - 1; ++ grub_uint32_t portsc = grub_xhci_port_read(x, port); ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ { ++ grub_dprintf("xhci", "%s: root port %d no longer connected\n", ++ __func__, port); ++ return -1; ++ } ++ xhci_trb_queue(x->cmds, grub_dma_get_phys(inctx_dma), 0, flags); ++ } ++ else ++ { ++ xhci_trb_queue(x->cmds, 0, 0, flags); ++ } ++ ++ xhci_doorbell(x, 0, 0); ++ int rc = xhci_event_wait(x, x->cmds, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ ++ return rc; ++} ++ ++static int xhci_cmd_enable_slot(struct grub_xhci *x) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_ENABLE_SLOT << 10); ++ ++ grub_dprintf("xhci", "%s:\n", __func__); ++ int cc = xhci_cmd_submit(x, NULL, flags); ++ if (cc != CC_SUCCESS) ++ return -1; ++ grub_dprintf("xhci", "%s: %p\n", __func__, &x->cmds->evt.control); ++ grub_dprintf("xhci", "%s: %x\n", __func__, grub_xhci_read32(&x->cmds->evt.control)); ++ ++ return (grub_xhci_read32(&x->cmds->evt.control) >> 24) & 0xff; ++} ++ ++static int xhci_cmd_disable_slot(struct grub_xhci *x, grub_uint32_t slotid) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_DISABLE_SLOT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_stop_endpoint(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_uint32_t suspend) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_STOP_ENDPOINT << 10); ++ flags |= (epid << 16); ++ flags |= (suspend << 23) ; ++ flags |= (slotid << 24); ++ ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_reset_endpoint(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_uint32_t preserve) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (preserve << 9); ++ flags |= (CR_RESET_ENDPOINT << 10); ++ flags |= (epid << 16); ++ flags |= (slotid << 24); ++ ++ return xhci_cmd_submit(x, NULL, flags); ++} ++ ++static int xhci_cmd_set_dequeue_pointer(struct grub_xhci *x, grub_uint32_t slotid ++ , grub_uint32_t epid ++ , grub_addr_t tr_deque_pointer) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_SET_TR_DEQUEUE << 10); ++ flags |= (epid << 16); ++ flags |= (slotid << 24); ++ ++ xhci_trb_queue(x->cmds, tr_deque_pointer, 0, flags); ++ ++ xhci_doorbell(x, 0, 0); ++ int rc = xhci_event_wait(x, x->cmds, 1000); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ ++ return rc; ++} ++ ++static int xhci_cmd_address_device(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_ADDRESS_DEVICE << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++static int xhci_cmd_configure_endpoint(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_CONFIGURE_ENDPOINT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++static int xhci_cmd_evaluate_context(struct grub_xhci *x, grub_uint32_t slotid, ++ struct grub_pci_dma_chunk *inctx_dma) ++{ ++ grub_uint32_t flags = 0; ++ flags |= (CR_EVALUATE_CONTEXT << 10); ++ flags |= (slotid << 24); ++ ++ grub_dprintf("xhci", "%s: slotid %d\n", __func__, slotid); ++ return xhci_cmd_submit(x, inctx_dma, flags); ++} ++ ++/**************************************************************** ++ * xHCI host controller initialization ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_reset (struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ grub_uint32_t end; ++ ++ reg = grub_xhci_read32(&x->op->usbcmd); ++ if (reg & GRUB_XHCI_CMD_RS) ++ { ++ reg &= ~GRUB_XHCI_CMD_RS; ++ grub_xhci_write32(&x->op->usbcmd, reg); ++ ++ end = grub_get_time_ms () + 32; ++ while (grub_xhci_read32(&x->op->usbcmd) & GRUB_XHCI_STS_HCH) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ } ++ ++ grub_dprintf("xhci", "grub_xhci_reset: resetting HC\n"); ++ grub_xhci_write32(&x->op->usbcmd, GRUB_XHCI_CMD_HCRST); ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ while (grub_xhci_read32(&x->op->usbcmd) & GRUB_XHCI_CMD_HCRST) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ while (grub_xhci_read32(&x->op->usbsts) & GRUB_XHCI_STS_CNR) ++ { ++ if (grub_get_time_ms () > end) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ grub_millisleep(1); ++ } ++ ++ grub_xhci_write32(&x->op->config, x->slots); ++ grub_xhci_write32(&x->op->dcbaap_low, grub_dma_get_phys(x->devs_dma)); ++ grub_xhci_write32(&x->op->dcbaap_high, 0); ++ grub_xhci_write32(&x->op->crcr_low, grub_dma_get_phys(x->cmds_dma)| 1); ++ grub_xhci_write32(&x->op->crcr_high, 0); ++ x->cmds->cs = 1; ++ ++ grub_arch_sync_dma_caches(x->cmds, sizeof(*x->cmds)); ++ ++ x->eseg->ptr_low = grub_dma_get_phys(x->evts_dma); ++ x->eseg->ptr_high = 0; ++ x->eseg->size = GRUB_XHCI_RING_ITEMS; ++ ++ grub_arch_sync_dma_caches(x->eseg, sizeof(*x->eseg)); ++ ++ grub_xhci_write32(&x->ir->erstsz, 1); ++ grub_xhci_write32(&x->ir->erdp_low, grub_dma_get_phys(x->evts_dma)); ++ grub_xhci_write32(&x->ir->erdp_high, 0); ++ grub_xhci_write32(&x->ir->erstba_low, grub_dma_get_phys(x->eseg_dma)); ++ grub_xhci_write32(&x->ir->erstba_high, 0); ++ x->evts->cs = 1; ++ ++ grub_arch_sync_dma_caches(x->evts, sizeof(*x->eseg)); ++ ++ xhci_check_status(x); ++ ++ grub_dprintf ("xhci", "XHCI OP COMMAND: %08x\n", ++ grub_xhci_read32 (&x->op->usbcmd)); ++ grub_dprintf ("xhci", "XHCI OP STATUS: %08x\n", ++ grub_xhci_read32 (&x->op->usbsts)); ++ grub_dprintf ("xhci", "XHCI OP PAGESIZE: %08x\n", ++ grub_xhci_read32 (&x->op->pagesize)); ++ grub_dprintf ("xhci", "XHCI OP DNCTRL: %08x\n", ++ grub_xhci_read32 (&x->op->dnctl)); ++ grub_dprintf ("xhci", "XHCI OP CRCR_LOW: %08x\n", ++ grub_xhci_read32 (&x->op->crcr_low)); ++ grub_dprintf ("xhci", "XHCI OP CRCR_HIGH: %08x\n", ++ grub_xhci_read32 (&x->op->crcr_high)); ++ grub_dprintf ("xhci", "XHCI OP DCBAAP_LOW: %08x\n", ++ grub_xhci_read32 (&x->op->dcbaap_low)); ++ grub_dprintf ("xhci", "XHCI OP DCBAAP_HIGH: %08x\n", ++ grub_xhci_read32 (&x->op->dcbaap_high)); ++ grub_dprintf ("xhci", "XHCI OP CONFIG: %08x\n", ++ grub_xhci_read32 (&x->op->config)); ++ grub_dprintf ("xhci", "XHCI IR ERSTSZ: %08x\n", ++ grub_xhci_read32 (&x->ir->erstsz)); ++ grub_dprintf ("xhci", "XHCI IR ERDP: %08x\n", ++ grub_xhci_read32 (&x->ir->erdp_low)); ++ grub_dprintf ("xhci", "XHCI IR ERSTBA: %08x\n", ++ grub_xhci_read32 (&x->ir->erstba_low)); ++ ++ xhci_check_status(x); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_request_legacy_handoff(volatile struct grub_xhci_xcap *xcap) ++{ ++ grub_uint32_t end; ++ ++ end = grub_get_time_ms () + 10; ++ for (;;) ++ { ++ grub_uint32_t cap = grub_xhci_read32(&xcap->cap); ++ if (cap & (1 << 16)) ++ grub_xhci_write32(&xcap->cap, cap | (1 << 24)); ++ else ++ break; ++ ++ if (grub_get_time_ms () > end) ++ { ++ grub_dprintf ("xhci","ERROR: %s TIMEOUT\n", __func__); ++ return GRUB_USB_ERR_TIMEOUT; ++ } ++ grub_millisleep(1); ++ } ++ return GRUB_USB_ERR_NONE; ++} ++ ++static void ++grub_xhci_fill_default_speed_mapping(struct grub_xhci_psids *ids) ++{ ++ /* Chapter 7.2.2.1.1 "Default USB Speed ID Mapping" */ ++ ids->psids[0].id = 1; ++ ids->psids[0].psie = 2; ++ ids->psids[0].psim = 12; ++ ids->psids[1].id = 2; ++ ids->psids[1].psie = 1; ++ ids->psids[1].psim = 1500; ++ ids->psids[2].id = 3; ++ ids->psids[2].psie = 2; ++ ids->psids[2].psim = 480; ++ ids->psids[3].id = 4; ++ ids->psids[3].psie = 3; ++ ids->psids[3].psim = 5; ++ ids->psids[4].id = 5; ++ ids->psids[4].psie = 3; ++ ids->psids[4].psim = 10; ++ ids->psids[5].id = 6; ++ ids->psids[5].psie = 3; ++ ids->psids[5].psim = 10; ++ ids->psids[6].id = 7; ++ ids->psids[6].psie = 3; ++ ids->psids[6].psim = 20; ++} ++ ++static void ++grub_xhci_calc_speed_mapping(struct grub_xhci_psids *ids) ++{ ++ const grub_uint64_t mult[4] = {1ULL, 1000ULL, 1000000ULL, 1000000000ULL}; ++ ++ for (grub_uint8_t i = 0; i < 16; i++) ++ { ++ if (ids->psids[i].id == 0) ++ continue; ++ ids->psids[i].bitrate = mult[ids->psids[i].psie & 3] * (grub_uint64_t)ids->psids[i].psim; ++ if (ids->psids[i].bitrate < 12000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_LOW; ++ else if (ids->psids[i].bitrate < 480000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_FULL; ++ else if (ids->psids[i].bitrate > 1200000000ULL) ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_SUPER; ++ else ++ ids->psids[i].grub_usb_speed = GRUB_USB_SPEED_HIGH; ++ } ++} ++ ++ ++/* PCI iteration function... */ ++void ++grub_xhci_init_device (volatile void *regs) ++{ ++ struct grub_xhci *x; ++ grub_uint32_t hcs1, hcc, reg; ++ ++ /* Allocate memory for the controller and fill basic values. */ ++ x = grub_zalloc (sizeof (*x)); ++ if (!x) ++ { ++ grub_dprintf("xhci", "Failed to allocate memory\n"); ++ return; ++ } ++ x->caps = (volatile struct grub_xhci_caps *) regs; ++ x->op = (volatile struct grub_xhci_op *) (((grub_uint8_t *)regs) + ++ grub_xhci_read8(&x->caps->caplength)); ++ x->pr = (volatile struct grub_xhci_pr *) (((grub_uint8_t *)x->op) + ++ GRUB_XHCI_PR_OFFSET); ++ x->db = (volatile struct grub_xhci_db *) (((grub_uint8_t *)regs) + ++ grub_xhci_read32(&x->caps->dboff)); ++ x->ir = (volatile struct grub_xhci_ir *) (((grub_uint8_t *)regs) + ++ grub_xhci_read32(&x->caps->rtsoff) + GRUB_XHCI_IR_OFFSET); ++ ++ grub_dprintf ("xhci", "XHCI init: CAPLENGTH: 0x%02x\n", ++ grub_xhci_read8 (&x->caps->caplength)); ++ grub_dprintf ("xhci", "XHCI init: HCIVERSION: 0x%04x\n", ++ grub_xhci_read16 (&x->caps->hciversion)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS1: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams1)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS2: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams2)); ++ grub_dprintf ("xhci", "XHCI init: HCSPARAMS3: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams3)); ++ grub_dprintf ("xhci", "XHCI init: HCCPARAMS: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->hcsparams3)); ++ grub_dprintf ("xhci", "XHCI init: DBOFF: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->dboff)); ++ grub_dprintf ("xhci", "XHCI init: RTOFF: 0x%08x\n", ++ grub_xhci_read32 (&x->caps->rtsoff)); ++ ++ hcs1 = grub_xhci_read32(&x->caps->hcsparams1); ++ hcc = grub_xhci_read32(&x->caps->hccparams); ++ x->ports = (grub_uint32_t) ((hcs1 >> 24) & 0xff); ++ x->slots = (grub_uint32_t) (hcs1 & 0xff); ++ x->xcap = (grub_uint32_t) ((hcc >> 16) & 0xffff) * sizeof(grub_uint32_t); ++ x->flag64 = (grub_uint8_t) ((hcc & 0x04) ? 1 : 0); ++ grub_dprintf("xhci", "XHCI init: %d ports, %d slots, %d byte contexts\n" ++ , x->ports, x->slots, x->flag64 ? 64 : 32); ++ ++ x->psids = grub_zalloc (sizeof (struct grub_xhci_psids) * x->ports); ++ if (x->xcap) ++ { ++ grub_uint32_t off; ++ volatile grub_uint8_t *addr = (grub_uint8_t *) x->caps + x->xcap; ++ do ++ { ++ volatile struct grub_xhci_xcap *xcap = (void *)addr; ++ grub_uint32_t ports, name, cap = grub_xhci_read32(&xcap->cap); ++ switch (cap & 0xff) { ++ case XHCI_CAP_LEGACY_SUPPORT: ++ { ++ if (grub_xhci_request_legacy_handoff(xcap) != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "XHCI init: Failed to get xHCI ownership\n"); ++ goto fail; ++ } ++ break; ++ } ++ case XHCI_CAP_SUPPORTED_PROTOCOL: ++ { ++ name = grub_xhci_read32(&xcap->data[0]); ++ ports = grub_xhci_read32(&xcap->data[1]); ++ const grub_uint8_t major = (cap >> 24) & 0xff; ++ const grub_uint8_t minor = (cap >> 16) & 0xff; ++ const grub_uint8_t psic = (ports >> 28) & 0xf; ++ const grub_uint8_t count = (ports >> 8) & 0xff; ++ const grub_uint8_t start = (ports >> 0) & 0xff; ++ grub_dprintf("xhci", "XHCI init: protocol %c%c%c%c %x.%02x" ++ ", %d ports (offset %d), def %x, psic %d\n" ++ , (name >> 0) & 0xff ++ , (name >> 8) & 0xff ++ , (name >> 16) & 0xff ++ , (name >> 24) & 0xff ++ , major, minor ++ , count, start ++ , ports >> 16 ++ , psic); ++ if (name == 0x20425355 /* "USB " */) ++ { ++ if (major == 2) ++ { ++ x->usb2.start = start; ++ x->usb2.count = count; ++ } ++ else if (major == 3) ++ { ++ x->usb3.start = start; ++ x->usb3.count = count; ++ } ++ ++ for (grub_uint32_t p = start - 1; p < start + count - 1UL; p++) ++ { ++ x->psids[p].major = major; ++ x->psids[p].minor = minor; ++ grub_xhci_fill_default_speed_mapping(&x->psids[p]); ++ for (grub_uint8_t i = 0; i < psic; i++) ++ { ++ grub_uint32_t psid = grub_xhci_read32(&xcap->data[3 + i]); ++ x->psids[p].psids[i].id = (psid >> 0) & 0xf; ++ x->psids[p].psids[i].psie = (psid >> 4) & 0x3; ++ x->psids[p].psids[i].psim = (psid >> 16) & 0xfffff; ++ } ++ grub_xhci_calc_speed_mapping(&x->psids[p]); ++ } ++ } ++ ++ break; ++ } ++ default: ++ { ++ grub_dprintf("xhci", "XHCI extcap 0x%x @ %p\n", cap & 0xff, addr); ++ break; ++ } ++ } ++ off = (cap >> 8) & 0xff; ++ addr += off << 2; ++ } ++ while (off > 0); ++ } ++ ++ x->pagesize = xhci_get_pagesize(x); ++ grub_dprintf("xhci", "XHCI init: Minimum supported page size 0x%x\n", ++ x->pagesize); ++ ++ /* Chapter 6.1 Device Context Base Address Array */ ++ x->devs_dma = xhci_memalign_dma32(ALIGN_DCBAA, ++ sizeof(*x->devs) * (x->slots + 1), ++ x->pagesize); ++ if (!x->devs_dma) ++ goto fail; ++ x->devs = grub_dma_get_virt(x->devs_dma); ++ grub_memset((void *)x->devs, 0, sizeof(*x->devs) * (x->slots + 1)); ++ grub_arch_sync_dma_caches(x->devs, sizeof(*x->devs) * (x->slots + 1)); ++ grub_dprintf ("xhci", "XHCI init: device memory %p (%x)\n", ++ grub_dma_get_virt(x->devs_dma), ++ grub_dma_get_phys(x->devs_dma)); ++ ++ /* Chapter 6.5 Event Ring Segment Table */ ++ x->eseg_dma = xhci_memalign_dma32(ALIGN_EVT_RING_TABLE, sizeof(*x->eseg), 0); ++ if (!x->eseg_dma) ++ goto fail; ++ x->eseg = grub_dma_get_virt(x->eseg_dma); ++ grub_memset((void *)x->eseg, 0, sizeof(*x->eseg)); ++ grub_arch_sync_dma_caches(x->eseg, sizeof(*x->eseg)); ++ grub_dprintf ("xhci", "XHCI init: event ring table memory %p (%x)\n", ++ grub_dma_get_virt(x->eseg_dma), ++ grub_dma_get_phys(x->eseg_dma)); ++ ++ x->cmds_dma = xhci_memalign_dma32(ALIGN_CMD_RING_SEG, sizeof(*x->cmds), ++ BOUNDARY_RING); ++ if (!x->cmds_dma) ++ goto fail; ++ x->cmds = grub_dma_get_virt(x->cmds_dma); ++ grub_memset((void *)x->cmds, 0, sizeof(*x->cmds)); ++ grub_arch_sync_dma_caches(x->cmds, sizeof(*x->cmds)); ++ grub_dprintf ("xhci", "XHCI init: command ring memory %p (%x)\n", ++ grub_dma_get_virt(x->cmds_dma), ++ grub_dma_get_phys(x->cmds_dma)); ++ ++ x->evts_dma = xhci_memalign_dma32(ALIGN_EVT_RING_SEG, sizeof(*x->evts), ++ BOUNDARY_RING); ++ if (!x->evts_dma) ++ goto fail; ++ x->evts = grub_dma_get_virt(x->evts_dma); ++ grub_memset((void *)x->evts, 0, sizeof(*x->evts)); ++ grub_arch_sync_dma_caches(x->evts, sizeof(*x->evts)); ++ grub_dprintf ("xhci", "XHCI init: event ring memory %p (%x)\n", ++ grub_dma_get_virt(x->evts_dma), ++ grub_dma_get_phys(x->evts_dma)); ++ ++ /* Chapter 4.20 Scratchpad Buffers */ ++ reg = grub_xhci_read32(&x->caps->hcsparams2); ++ x->spb = (reg >> 21 & 0x1f) << 5 | reg >> 27; ++ if (x->spb) ++ { ++ volatile grub_uint64_t *spba; ++ grub_dprintf("xhci", "XHCI init: set up %d scratch pad buffers\n", ++ x->spb); ++ x->spba_dma = xhci_memalign_dma32(ALIGN_SPBA, sizeof(*spba) * x->spb, ++ x->pagesize); ++ if (!x->spba_dma) ++ goto fail; ++ ++ x->spad_dma = xhci_memalign_dma32(x->pagesize, x->pagesize * x->spb, ++ x->pagesize); ++ if (!x->spad_dma) ++ { ++ grub_dma_free(x->spba_dma); ++ goto fail; ++ } ++ ++ spba = grub_dma_get_virt(x->spba_dma); ++ for (grub_uint32_t i = 0; i < x->spb; i++) ++ spba[i] = (grub_addr_t)grub_dma_get_phys(x->spad_dma) + (i * x->pagesize); ++ grub_arch_sync_dma_caches(x->spba_dma, sizeof(*spba) * x->spb); ++ ++ x->devs[0].ptr_low = grub_dma_get_phys(x->spba_dma); ++ x->devs[0].ptr_high = 0; ++ grub_arch_sync_dma_caches(x->devs_dma, sizeof(x->devs[0])); ++ grub_dprintf ("xhci", "XHCI init: Allocated %d scratch buffers of size 0x%x\n", ++ x->spb, x->pagesize); ++ } ++ ++ grub_xhci_reset(x); ++ ++ /* Set the running bit */ ++ reg = grub_xhci_read32 (&x->op->usbcmd); ++ reg |= GRUB_XHCI_CMD_RS; ++ grub_xhci_write32 (&x->op->usbcmd, reg); ++ ++ ++ /* Link to xhci now that initialisation is successful. */ ++ x->next = xhci; ++ xhci = x; ++ ++ return; ++ ++fail: ++ grub_dprintf ("xhci", "XHCI grub_xhci_pci_iter: FAILED!\n"); ++ if (x) ++ { ++ if (x->devs_dma) ++ grub_dma_free (x->devs_dma); ++ if (x->eseg_dma) ++ grub_dma_free (x->eseg_dma); ++ if (x->cmds_dma) ++ grub_dma_free (x->cmds_dma); ++ if (x->evts_dma) ++ grub_dma_free (x->evts_dma); ++ if (x->spad_dma) ++ grub_dma_free (x->spad_dma); ++ if (x->spba_dma) ++ grub_dma_free (x->spba_dma); ++ } ++ grub_free (x); ++ ++ return; ++} ++ ++static int ++grub_xhci_iterate (grub_usb_controller_iterate_hook_t hook, void *hook_data) ++{ ++ struct grub_xhci *x; ++ struct grub_usb_controller dev; ++ ++ for (x = xhci; x; x = x->next) ++ { ++ dev.data = x; ++ if (hook (&dev, hook_data)) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/**************************************************************** ++ * xHCI maintainance functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_update_hub_portcount (struct grub_xhci *x, ++ grub_usb_transfer_t transfer, ++ grub_uint32_t slotid) ++{ ++ struct grub_pci_dma_chunk *in_dma; ++ volatile struct grub_xhci_slotctx *hdslot; ++ grub_uint32_t epid = 0; ++ ++ if (!transfer || !transfer->dev || !transfer->dev->nports) ++ return GRUB_USB_ERR_NONE; ++ ++ hdslot = grub_dma_phys2virt(x->devs[slotid].ptr_low, x->devs_dma); ++ if ((hdslot->ctx[3] >> 27) == 3) ++ /* Already configured */ ++ return 0; ++ ++ grub_dprintf("xhci", "%s: updating hub config to %d ports\n", __func__, ++ transfer->dev->nports); ++ ++ xhci_check_status(x); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, transfer->dev); ++ if (!in_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ ++ in->add = (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ ep->ctx[0] |= 1 << 26; ++ ep->ctx[1] |= transfer->dev->nports << 24; ++ ++ int cc = xhci_cmd_configure_endpoint(x, slotid, in_dma); ++ grub_dma_free(in_dma); ++ ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: reconf ctl endpoint: failed (cc %d)\n", ++ __func__, cc); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_update_max_paket_size (struct grub_xhci *x, ++ grub_usb_transfer_t transfer, ++ grub_uint32_t slotid, ++ grub_uint32_t max_packet) ++{ ++ struct grub_pci_dma_chunk *in_dma; ++ grub_uint32_t epid = 1; ++ ++ if (!transfer || !transfer->dev || !max_packet) ++ return GRUB_USB_ERR_NONE; ++ ++ grub_dprintf("xhci", "%s: updating max packet size to 0x%x\n", __func__, ++ max_packet); ++ ++ xhci_check_status(x); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, transfer->dev); ++ if (!in_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ in->add = (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ ep->ctx[1] |= max_packet << 16; ++ ++ int cc = xhci_cmd_evaluate_context(x, slotid, in_dma); ++ grub_dma_free(in_dma); ++ ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: reconf ctl endpoint: failed (cc %d)\n", ++ __func__, cc); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI endpoint enablement functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_prepare_endpoint (struct grub_xhci *x, ++ struct grub_usb_device *dev, ++ grub_uint8_t endpoint, ++ grub_transfer_type_t dir, ++ grub_transaction_type_t type, ++ grub_uint32_t maxpaket, ++ struct grub_xhci_priv *priv) ++{ ++ grub_uint32_t epid; ++ struct grub_pci_dma_chunk *reqs_dma; ++ struct grub_pci_dma_chunk *in_dma; ++ volatile struct grub_xhci_ring *reqs; ++ volatile struct grub_xhci_slotctx *slotctx; ++ ++ if (!x || !priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ xhci_check_status(x); ++ ++ if (endpoint == 0) ++ { ++ epid = 1; ++ } ++ else ++ { ++ epid = (endpoint & 0x0f) * 2; ++ epid += (dir == GRUB_USB_TRANSFER_TYPE_IN) ? 1 : 0; ++ } ++ grub_dprintf("xhci", "%s: epid %d\n", __func__, epid); ++ ++ /* Test if already prepared */ ++ if (priv->slotid > 0 && priv->enpoint_trbs[epid] != NULL) ++ return GRUB_USB_ERR_NONE; ++ ++ /* Allocate DMA buffer as endpoint cmd TRB */ ++ reqs_dma = xhci_memalign_dma32(ALIGN_TRB, sizeof(*reqs), ++ BOUNDARY_RING); ++ if (!reqs_dma) ++ return GRUB_USB_ERR_INTERNAL; ++ reqs = grub_dma_get_virt(reqs_dma); ++ grub_memset((void *)reqs, 0, sizeof(*reqs)); ++ reqs->cs = 1; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Allocate input context and initialize endpoint info. */ ++ in_dma = grub_xhci_alloc_inctx(x, epid, dev); ++ if (!in_dma) ++ { ++ grub_dma_free(reqs_dma); ++ return GRUB_USB_ERR_INTERNAL; ++ } ++ volatile struct grub_xhci_inctx *in = grub_dma_get_virt(in_dma); ++ in->add = 0x01 | (1 << epid); ++ ++ struct grub_xhci_epctx *ep = (void*)&in[(epid+1) << x->flag64]; ++ switch (type) ++ { ++ case GRUB_USB_TRANSACTION_TYPE_CONTROL: ++ ep->ctx[1] |= 0 << 3; ++ break; ++ case GRUB_USB_TRANSACTION_TYPE_BULK: ++ ep->ctx[1] |= 2 << 3; ++ break; ++ } ++ if (dir == GRUB_USB_TRANSFER_TYPE_IN ++ || type== GRUB_USB_TRANSACTION_TYPE_CONTROL) ++ ep->ctx[1] |= 1 << 5; ++ ep->ctx[1] |= maxpaket << 16; ++ ep->deq_low = grub_dma_get_phys(reqs_dma); ++ ep->deq_low |= 1; /* dcs */ ++ ep->length = maxpaket; ++ ++ grub_dprintf("xhci", "%s: ring %p, epid %d, max %d\n", __func__, ++ reqs, epid, maxpaket); ++ if (epid == 1 || priv->slotid == 0) { ++ /* Enable slot. */ ++ int slotid = xhci_cmd_enable_slot(x); ++ if (slotid < 0) ++ { ++ grub_dprintf("xhci", "%s: enable slot: failed\n", __func__); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ grub_dprintf("xhci", "%s: get slot %d assigned\n", __func__, slotid); ++ ++ grub_uint32_t size = (sizeof(struct grub_xhci_slotctx) * GRUB_XHCI_MAX_ENDPOINTS) << x->flag64; ++ ++ /* Allocate memory for the device specific slot context */ ++ priv->slotctx_dma = xhci_memalign_dma32(ALIGN_SLOTCTX, size, ++ x->pagesize); ++ if (!priv->slotctx_dma) ++ { ++ grub_dprintf("xhci", "%s: grub_memalign_dma32 failed\n", __func__); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_INTERNAL; ++ } ++ slotctx = grub_dma_get_virt(priv->slotctx_dma); ++ ++ grub_dprintf("xhci", "%s: enable slot: got slotid %d\n", __func__, slotid); ++ grub_memset((void *)slotctx, 0, size); ++ grub_arch_sync_dma_caches(slotctx, size); ++ ++ x->devs[slotid].ptr_low = grub_dma_get_phys(priv->slotctx_dma); ++ x->devs[slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[slotid], sizeof(x->devs[0])); ++ ++ /* Send set_address command. */ ++ int cc = xhci_cmd_address_device(x, slotid, in_dma); ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci","%s: address device: failed (cc %d)\n", __func__, cc); ++ cc = xhci_cmd_disable_slot(x, slotid); ++ if (cc != CC_SUCCESS) { ++ grub_dprintf("xhci", "%s: disable failed (cc %d)\n", __func__, cc); ++ } else { ++ x->devs[slotid].ptr_low = 0; ++ x->devs[slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[slotid], sizeof(x->devs[0])); ++ } ++ grub_dma_free(priv->slotctx_dma); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ priv->enpoint_trbs[epid] = reqs; ++ priv->enpoint_trbs_dma[epid] = reqs_dma; ++ priv->slotid = slotid; ++ priv->max_packet = 0; ++ } ++ if (epid != 1) ++ { ++ /* Send configure command. */ ++ int cc = xhci_cmd_configure_endpoint(x, priv->slotid, in_dma); ++ if (cc != CC_SUCCESS) ++ { ++ grub_dprintf("xhci", "%s: configure endpoint: failed (cc %d)\n", ++ __func__, cc); ++ grub_dma_free(reqs_dma); ++ grub_dma_free(in_dma); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ priv->enpoint_trbs[epid] = reqs; ++ priv->enpoint_trbs_dma[epid] = reqs_dma; ++ } ++ ++ grub_dprintf("xhci", "%s: done\n", __func__); ++ grub_dma_free(in_dma); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++ ++/**************************************************************** ++ * xHCI transfer helper functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_usb_to_grub_err (unsigned char status) ++{ ++ if (status != CC_SUCCESS) ++ grub_dprintf("xhci", "%s: xfer failed (cc %d)\n", __func__, status); ++ else ++ grub_dprintf("xhci", "%s: xfer done (cc %d)\n", __func__, status); ++ ++ if (status == CC_BABBLE_DETECTED) ++ return GRUB_USB_ERR_BABBLE; ++ else if (status == CC_DATA_BUFFER_ERROR) ++ return GRUB_USB_ERR_DATA; ++ else if (status == CC_STALL_ERROR) ++ return GRUB_USB_ERR_STALL; ++ else if (status != CC_SUCCESS) ++ return GRUB_USB_ERR_NAK; ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static int ++grub_xhci_transfer_is_zlp(grub_usb_transfer_t transfer, int idx) ++{ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ grub_usb_transaction_t tr = &transfer->transactions[idx]; ++ ++ return (tr->size == 0) && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN)); ++} ++ ++static int ++grub_xhci_transfer_is_last(grub_usb_transfer_t transfer, int idx) ++{ ++ return (idx + 1) == transfer->transcnt; ++} ++ ++static int ++grub_xhci_transfer_is_data(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ if (tr->size == 0 || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_SETUP)) ++ return 0; ++ ++ /* If there's are no DATA pakets before it's a DATA paket */ ++ for (int i = idx - 1; i >= 0; i--) ++ { ++ tr = &transfer->transactions[i]; ++ if (tr->size > 0 && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN))) ++ return 0; ++ } ++ return 1; ++} ++ ++static int ++grub_xhci_transfer_is_in(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ ++ return tr->pid == GRUB_USB_TRANSFER_TYPE_IN; ++} ++ ++static int ++grub_xhci_transfer_is_normal(grub_usb_transfer_t transfer, int idx) ++{ ++ grub_usb_transaction_t tr; ++ ++ if (idx >= transfer->transcnt) ++ return 0; ++ ++ tr = &transfer->transactions[idx]; ++ if (tr->size == 0 || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_SETUP)) ++ return 0; ++ ++ /* If there's at least one DATA paket before it's a normal */ ++ for (int i = idx - 1; i >= 0; i--) ++ { ++ tr = &transfer->transactions[i]; ++ if (tr->size > 0 && ++ ((tr->pid == GRUB_USB_TRANSFER_TYPE_OUT) || ++ (tr->pid == GRUB_USB_TRANSFER_TYPE_IN))) ++ return 1; ++ ++ } ++ return 0; ++} ++ ++static int ++grub_xhci_transfer_next_is_normal(grub_usb_transfer_t transfer, int idx) ++{ ++ return grub_xhci_transfer_is_normal(transfer, idx + 1); ++} ++ ++static int ++grub_xhci_transfer_next_is_in(grub_usb_transfer_t transfer, int idx) ++{ ++ return grub_xhci_transfer_is_in(transfer, idx + 1); ++} ++ ++static grub_uint8_t grub_xhci_epid_from_transfer(grub_usb_transfer_t transfer) ++{ ++ grub_uint8_t epid; ++ ++ if (transfer->endpoint == 0) { ++ epid = 1; ++ } else { ++ epid = (transfer->endpoint & 0x0f) * 2; ++ epid += (transfer->dir == GRUB_USB_TRANSFER_TYPE_IN) ? 1 : 0; ++ } ++ return epid; ++} ++ ++/**************************************************************** ++ * xHCI transfer functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_setup_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer) ++{ ++ struct grub_xhci_transfer_controller_data *cdata; ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint8_t epid; ++ grub_usb_err_t err; ++ volatile struct grub_xhci_ring *reqs; ++ int rc; ++ struct grub_xhci_priv *priv; ++ ++ xhci_check_status(x); ++ ++ if (!dev || !transfer || !transfer->dev || !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ priv = transfer->dev->xhci_priv; ++ err = grub_xhci_prepare_endpoint(x, transfer->dev, ++ transfer->endpoint, ++ transfer->dir, ++ transfer->type, ++ transfer->max, ++ priv); ++ ++ if (err != GRUB_USB_ERR_NONE) ++ return err; ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ /* Update the max packet size once descdev.maxsize0 is valid */ ++ if (epid == 1 && ++ (priv->max_packet == 0) && ++ (transfer->dev->descdev.maxsize0 > 0)) ++ { ++ if (transfer->dev->speed == GRUB_USB_SPEED_SUPER) ++ priv->max_packet = 1UL << transfer->dev->descdev.maxsize0; ++ else ++ priv->max_packet = transfer->dev->descdev.maxsize0; ++ err = grub_xhci_update_max_paket_size(x, transfer, priv->slotid, priv->max_packet); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "%s: Updating max paket size failed\n", __func__); ++ return err; ++ } ++ } ++ if (epid == 1 && ++ transfer->dev->descdev.class == 9 && ++ transfer->dev->nports > 0) ++ { ++ err = grub_xhci_update_hub_portcount(x, transfer, priv->slotid); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ grub_dprintf("xhci", "%s: Updating max paket size failed\n", __func__); ++ return err; ++ } ++ } ++ ++ /* Allocate private data for the transfer */ ++ cdata = grub_zalloc(sizeof(*cdata)); ++ if (!cdata) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ reqs = priv->enpoint_trbs[epid]; ++ ++ transfer->controller_data = cdata; ++ ++ /* Now queue the transfer onto the TRB */ ++ if (transfer->type == GRUB_USB_TRANSACTION_TYPE_CONTROL) ++ { ++ volatile struct grub_usb_packet_setup *setupdata; ++ setupdata = (void *)transfer->transactions[0].data; ++ grub_dprintf("xhci", "%s: CONTROLL TRANS req %d\n", __func__, setupdata->request); ++ grub_dprintf("xhci", "%s: CONTROLL TRANS length %d\n", __func__, setupdata->length); ++ ++ if (setupdata && setupdata->request == GRUB_USB_REQ_SET_ADDRESS) ++ return GRUB_USB_ERR_NONE; ++ ++ if (transfer->transcnt < 2) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ for (int i = 0; i < transfer->transcnt; i++) ++ { ++ grub_uint32_t flags = 0; ++ grub_uint64_t inline_data; ++ grub_usb_transaction_t tr = &transfer->transactions[i]; ++ ++ switch (tr->pid) ++ { ++ case GRUB_USB_TRANSFER_TYPE_SETUP: ++ { ++ grub_dprintf("xhci", "%s: SETUP PKG\n", __func__); ++ grub_dprintf("xhci", "%s: transfer->size %d\n", __func__, transfer->size); ++ grub_dprintf("xhci", "%s: tr->size %d SETUP PKG\n", __func__, tr->size); ++ ++ flags |= (TR_SETUP << 10); ++ flags |= TRB_TR_IDT; ++ ++ if (transfer->size > 0) ++ { ++ if (grub_xhci_transfer_next_is_in(transfer, i)) ++ flags |= (3 << 16); /* TRT IN */ ++ else ++ flags |= (2 << 16); /* TRT OUT */ ++ } ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_OUT: ++ { ++ grub_dprintf("xhci", "%s: OUT PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_IN: ++ { ++ grub_dprintf("xhci", "%s: IN PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ flags |= TRB_TR_DIR; ++ break; ++ } ++ } ++ ++ if (grub_xhci_transfer_is_normal(transfer, i)) ++ flags |= (TR_NORMAL << 10); ++ else if (grub_xhci_transfer_is_data(transfer, i)) ++ flags |= (TR_DATA << 10); ++ else if (grub_xhci_transfer_is_zlp(transfer, i)) ++ flags |= (TR_STATUS << 10); ++ ++ if (grub_xhci_transfer_next_is_normal(transfer, i)) ++ flags |= TRB_TR_CH; ++ ++ if (grub_xhci_transfer_is_last(transfer, i)) ++ flags |= TRB_TR_IOC; ++ ++ /* Assume the ring has enough free space for all TRBs */ ++ if (flags & TRB_TR_IDT && tr->size <= (int)sizeof(inline_data)) ++ { ++ grub_memcpy(&inline_data, (void *)tr->data, tr->size); ++ xhci_trb_queue(reqs, inline_data, tr->size, flags); ++ } ++ else ++ { ++ xhci_trb_queue(reqs, tr->data, tr->size, flags); ++ } ++ } ++ } ++ else if (transfer->type == GRUB_USB_TRANSACTION_TYPE_BULK) ++ { ++ for (int i = 0; i < transfer->transcnt; i++) ++ { ++ grub_uint32_t flags = (TR_NORMAL << 10); ++ grub_usb_transaction_t tr = &transfer->transactions[i]; ++ switch (tr->pid) ++ { ++ case GRUB_USB_TRANSFER_TYPE_OUT: ++ { ++ grub_dprintf("xhci", "%s: OUT PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_IN: ++ { ++ grub_dprintf("xhci", "%s: IN PKG\n", __func__); ++ cdata->transfer_size += tr->size; ++ flags |= TRB_TR_DIR; ++ break; ++ } ++ case GRUB_USB_TRANSFER_TYPE_SETUP: ++ break; ++ } ++ if (grub_xhci_transfer_is_last(transfer, i)) ++ flags |= TRB_TR_IOC; ++ ++ /* The ring might be to small, submit while adding new entries */ ++ rc = xhci_trb_queue_and_flush(x, priv->slotid, epid, ++ reqs, tr->data, tr->size, flags); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ else if (rc > 1) ++ return grub_xhci_usb_to_grub_err(rc); ++ ++ } ++ } ++ xhci_doorbell(x, priv->slotid, epid); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++static grub_usb_err_t ++grub_xhci_check_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer, grub_size_t * actual) ++{ ++ grub_uint32_t status; ++ grub_uint32_t remaining; ++ grub_uint8_t epid; ++ volatile struct grub_xhci_ring *reqs; ++ grub_usb_err_t err; ++ int rc; ++ ++ if (!dev->data || !transfer->controller_data || !transfer->dev || ++ !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ ++ struct grub_xhci_priv *priv = transfer->dev->xhci_priv; ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ struct grub_xhci_transfer_controller_data *cdata = ++ transfer->controller_data; ++ ++ xhci_check_status(x); ++ xhci_process_events(x); ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ reqs = priv->enpoint_trbs[epid]; ++ ++ /* XXX: invalidate caches */ ++ ++ /* Get current status from event ring buffer */ ++ status = (reqs->evt.status>> 24) & 0xff; ++ remaining = reqs->evt.status & 0xffffff; ++ ++ if (status != CC_STOPPED_LENGTH_INVALID) ++ *actual = cdata->transfer_size - remaining; ++ else ++ *actual = 0; ++ ++ if (xhci_ring_busy(reqs)) ++ return GRUB_USB_ERR_WAIT; ++ ++ grub_free(cdata); ++ ++ grub_dprintf("xhci", "%s: xfer done\n", __func__); ++ ++ err = grub_xhci_usb_to_grub_err(status); ++ if (err != GRUB_USB_ERR_NONE) ++ { ++ if (status == CC_STALL_ERROR) ++ { ++ /* Clear the stall by resetting the endpoint */ ++ rc = xhci_cmd_reset_endpoint(x, priv->slotid, epid, 1); ++ ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ return GRUB_USB_ERR_STALL; ++ } ++ else if (remaining > 0) ++ { ++ return GRUB_USB_ERR_DATA; ++ } ++ } ++ ++ return err; ++} ++ ++static grub_usb_err_t ++grub_xhci_cancel_transfer (grub_usb_controller_t dev, ++ grub_usb_transfer_t transfer) ++{ ++ grub_uint8_t epid; ++ volatile struct grub_xhci_ring *reqs; ++ struct grub_pci_dma_chunk *enpoint_trbs_dma; ++ grub_addr_t deque_pointer; ++ int rc; ++ ++ if (!dev->data || !transfer->controller_data || !transfer->dev || ++ !transfer->dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ struct grub_xhci_transfer_controller_data *cdata = ++ transfer->controller_data; ++ struct grub_xhci_priv *priv = transfer->dev->xhci_priv; ++ ++ epid = grub_xhci_epid_from_transfer(transfer); ++ ++ enpoint_trbs_dma = priv->enpoint_trbs_dma[epid]; ++ reqs = priv->enpoint_trbs[epid]; ++ ++ /* Abort current command */ ++ rc = xhci_cmd_stop_endpoint(x, priv->slotid, epid, 0); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ /* Reset state */ ++ reqs->nidx = 0; ++ reqs->eidx = 0; ++ reqs->cs = 1; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Reset the dequeue pointer to the begging of the TRB */ ++ deque_pointer = grub_dma_get_phys(enpoint_trbs_dma); ++ rc = xhci_cmd_set_dequeue_pointer(x, priv->slotid, epid, deque_pointer| 1 ); ++ if (rc < 0) ++ return GRUB_USB_ERR_TIMEOUT; ++ ++ reqs->evt.ptr_low = 0; ++ reqs->evt.ptr_high = 0; ++ reqs->evt.control = 0; ++ reqs->evt.status = 0; ++ ++ grub_arch_sync_dma_caches(reqs, sizeof(*reqs)); ++ ++ /* Restart ring buffer processing */ ++ xhci_doorbell(x, priv->slotid, epid); ++ ++ grub_free (cdata); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI port status functions ++ ****************************************************************/ ++ ++static int ++grub_xhci_hubports (grub_usb_controller_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portinfo; ++ ++ portinfo = x->ports; ++ grub_dprintf ("xhci", "root hub ports=%d\n", portinfo); ++ return portinfo; ++} ++ ++static grub_usb_err_t ++grub_xhci_portstatus (grub_usb_controller_t dev, ++ unsigned int port, unsigned int enable) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portsc, pls; ++ grub_uint32_t end; ++ ++ portsc = grub_xhci_port_read(x, port); ++ pls = xhci_get_field(portsc, XHCI_PORTSC_PLS); ++ ++ grub_dprintf("xhci", "grub_xhci_portstatus port #%d: 0x%08x,%s%s pls %d enable %d\n", ++ port, portsc, ++ (portsc & GRUB_XHCI_PORTSC_PP) ? " powered," : "", ++ (portsc & GRUB_XHCI_PORTSC_PED) ? " enabled," : "", ++ pls, enable); ++ xhci_check_status(x); ++ ++ if ((enable && (portsc & GRUB_XHCI_PORTSC_PED)) || ++ (!enable && !(portsc & GRUB_XHCI_PORTSC_PED))) ++ return GRUB_USB_ERR_NONE; ++ ++ if (!enable) ++ { ++ /* Disable port */ ++ grub_xhci_port_write(x, port, ~0, GRUB_XHCI_PORTSC_PED); ++ return GRUB_USB_ERR_NONE; ++ } ++ ++ grub_dprintf ("xhci", "portstatus: XHCI STATUS: %08x\n", ++ grub_xhci_read32(&x->op->usbsts)); ++ grub_dprintf ("xhci", ++ "portstatus: begin, iobase=%p, port=%d, status=0x%08x\n", ++ x->caps, port, portsc); ++ ++ switch (pls) ++ { ++ case PLS_U0: ++ /* A USB3 port - controller automatically performs reset */ ++ break; ++ case PLS_POLLING: ++ /* A USB2 port - perform device reset */ ++ grub_xhci_port_write(x, port, ~GRUB_XHCI_PORTSC_PED, GRUB_XHCI_PORTSC_PR); ++ break; ++ default: ++ return GRUB_USB_ERR_NONE; ++ } ++ ++ /* Wait for device to complete reset and be enabled */ ++ end = grub_get_time_ms () + 100; ++ for (;;) ++ { ++ portsc = grub_xhci_port_read(x, port); ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ { ++ /* Device disconnected during reset */ ++ grub_dprintf ("xhci","ERROR: %s device disconnected\n", __func__); ++ return GRUB_USB_ERR_BADDEVICE; ++ } ++ if (portsc & GRUB_XHCI_PORTSC_PED) ++ /* Reset complete */ ++ break; ++ if (grub_get_time_ms () > end) ++ { ++ grub_dprintf ("xhci","ERROR: %s TIMEOUT\n", __func__); ++ return GRUB_USB_ERR_TIMEOUT; ++ } ++ } ++ xhci_check_status(x); ++ ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI detect device functions ++ ****************************************************************/ ++ ++static grub_usb_speed_t ++grub_xhci_detect_dev (grub_usb_controller_t dev, int port, int *changed) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) dev->data; ++ grub_uint32_t portsc, speed; ++ ++ *changed = 0; ++ grub_dprintf("xhci", "%s: dev=%p USB%d_%d port %d\n", __func__, dev, ++ x->psids[port-1].major, x->psids[port-1].minor, port); ++ ++ /* On shutdown advertise all ports as disconnected. This will trigger ++ * a gracefull detatch. */ ++ if (x->shutdown) ++ { ++ *changed = 1; ++ return GRUB_USB_SPEED_NONE; ++ } ++ ++ /* Don't advertise new devices, connecting will fail if halted */ ++ if (xhci_is_halted(x)) ++ return GRUB_USB_SPEED_NONE; ++ ++ portsc = grub_xhci_port_read(x, port); ++ speed = xhci_get_field(portsc, XHCI_PORTSC_SPEED); ++ grub_uint8_t pls = xhci_get_field(portsc, XHCI_PORTSC_PLS); ++ ++ grub_dprintf("xhci", "grub_xhci_portstatus port #%d: 0x%08x,%s%s pls %d\n", ++ port, portsc, ++ (portsc & GRUB_XHCI_PORTSC_PP) ? " powered," : "", ++ (portsc & GRUB_XHCI_PORTSC_PED) ? " enabled," : "", ++ pls); ++ ++ /* Connect Status Change bit - it detects change of connection */ ++ if (portsc & GRUB_XHCI_PORTSC_CSC) ++ { ++ *changed = 1; ++ ++ grub_xhci_port_write(x, port, ~GRUB_XHCI_PORTSC_PED, GRUB_XHCI_PORTSC_CSC); ++ } ++ ++ if (!(portsc & GRUB_XHCI_PORTSC_CCS)) ++ return GRUB_USB_SPEED_NONE; ++ ++ for (grub_uint8_t i = 0; i < 16 && x->psids[port-1].psids[i].id > 0; i++) ++ { ++ if (x->psids[port-1].psids[i].id == speed) ++ { ++ grub_dprintf("xhci", "%s: grub_usb_speed = %d\n", __func__, ++ x->psids[port-1].psids[i].grub_usb_speed ); ++ return x->psids[port-1].psids[i].grub_usb_speed; ++ } ++ } ++ ++ return GRUB_USB_SPEED_NONE; ++} ++ ++/**************************************************************** ++ * xHCI attach/detach functions ++ ****************************************************************/ ++ ++static grub_usb_err_t ++grub_xhci_attach_dev (grub_usb_controller_t ctrl, grub_usb_device_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) ctrl->data; ++ grub_usb_err_t err; ++ grub_uint32_t max; ++ ++ grub_dprintf("xhci", "%s: dev=%p\n", __func__, dev); ++ ++ if (!dev || !x) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ dev->xhci_priv = grub_zalloc (sizeof (struct grub_xhci_priv)); ++ if (!dev->xhci_priv) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ ++ switch (dev->speed) ++ { ++ case GRUB_USB_SPEED_LOW: ++ { ++ max = 8; ++ break; ++ } ++ case GRUB_USB_SPEED_FULL: ++ case GRUB_USB_SPEED_HIGH: ++ { ++ max = 64; ++ break; ++ } ++ case GRUB_USB_SPEED_SUPER: ++ { ++ max = 512; ++ break; ++ } ++ default: ++ case GRUB_USB_SPEED_NONE: ++ { ++ max = 0; ++ } ++ } ++ ++ /* Assign a slot, assign an address and configure endpoint 0 */ ++ err = grub_xhci_prepare_endpoint(x, dev, ++ 0, ++ 0, ++ GRUB_USB_TRANSACTION_TYPE_CONTROL, ++ max, ++ dev->xhci_priv); ++ ++ return err; ++} ++ ++static grub_usb_err_t ++grub_xhci_detach_dev (grub_usb_controller_t ctrl, grub_usb_device_t dev) ++{ ++ struct grub_xhci *x = (struct grub_xhci *) ctrl->data; ++ struct grub_xhci_priv *priv; ++ int cc = CC_SUCCESS; ++ ++ grub_dprintf("xhci", "%s: dev=%p\n", __func__, dev); ++ ++ if (!dev) ++ return GRUB_USB_ERR_INTERNAL; ++ ++ if (dev->xhci_priv) ++ { ++ priv = dev->xhci_priv; ++ /* Stop endpoints and free ring buffer */ ++ for (int i = 0; i < GRUB_XHCI_MAX_ENDPOINTS; i++) ++ { ++ if (priv->enpoint_trbs[i] != NULL) ++ { ++ cc = xhci_cmd_stop_endpoint(x, priv->slotid, i, 1); ++ if (cc != CC_SUCCESS) ++ grub_dprintf("xhci", "Failed to disable EP%d on slot %d\n", i, ++ priv->slotid); ++ ++ grub_dprintf("xhci", "grub_dma_free[%d]\n", i); ++ ++ grub_dma_free(priv->enpoint_trbs_dma[i]); ++ priv->enpoint_trbs[i] = NULL; ++ priv->enpoint_trbs_dma[i] = NULL; ++ } ++ } ++ ++ cc = xhci_cmd_disable_slot(x, priv->slotid); ++ if (cc == CC_SUCCESS) ++ { ++ if (priv->slotctx_dma) ++ grub_dma_free(priv->slotctx_dma); ++ x->devs[priv->slotid].ptr_low = 0; ++ x->devs[priv->slotid].ptr_high = 0; ++ grub_arch_sync_dma_caches(&x->devs[priv->slotid], sizeof(x->devs[0])); ++ } ++ else ++ grub_dprintf("xhci", "Failed to disable slot %d\n", priv->slotid); ++ ++ grub_free(dev->xhci_priv); ++ } ++ ++ dev->xhci_priv = NULL; ++ ++ if (cc != CC_SUCCESS) ++ return GRUB_USB_ERR_BADDEVICE; ++ return GRUB_USB_ERR_NONE; ++} ++ ++/**************************************************************** ++ * xHCI terminate functions ++ ****************************************************************/ ++ ++static void ++grub_xhci_halt(struct grub_xhci *x) ++{ ++ grub_uint32_t reg; ++ ++ /* Halt the command ring */ ++ reg = grub_xhci_read32(&x->op->crcr_low); ++ grub_xhci_write32(&x->op->crcr_low, reg | 4); ++ ++ int rc = xhci_event_wait(x, x->cmds, 100); ++ grub_dprintf("xhci", "%s: xhci_event_wait = %d\n", __func__, rc); ++ if (rc < 0) ++ return; ++ ++ /* Stop the controller */ ++ reg = grub_xhci_read32(&x->op->usbcmd); ++ if (reg & GRUB_XHCI_CMD_RS) ++ { ++ reg &= ~GRUB_XHCI_CMD_RS; ++ grub_xhci_write32(&x->op->usbcmd, reg); ++ } ++ ++ return; ++} ++ ++static grub_err_t ++grub_xhci_fini_hw (int noreturn __attribute__ ((unused))) ++{ ++ struct grub_xhci *x; ++ ++ /* We should disable all XHCI HW to prevent any DMA access etc. */ ++ for (x = xhci; x; x = x->next) ++ { ++ x->shutdown = 1; ++ ++ /* Gracefully detach active devices */ ++ grub_usb_poll_devices(0); ++ ++ /* Check if xHCI is halted and halt it if not */ ++ grub_xhci_halt (x); ++ ++ /* Reset xHCI */ ++ if (grub_xhci_reset (x) != GRUB_USB_ERR_NONE) ++ return GRUB_ERR_BAD_DEVICE; ++ } ++ ++ return GRUB_ERR_NONE; ++} ++ ++static struct grub_usb_controller_dev usb_controller = { ++ .name = "xhci", ++ .iterate = grub_xhci_iterate, ++ .setup_transfer = grub_xhci_setup_transfer, ++ .check_transfer = grub_xhci_check_transfer, ++ .cancel_transfer = grub_xhci_cancel_transfer, ++ .hubports = grub_xhci_hubports, ++ .portstatus = grub_xhci_portstatus, ++ .detect_dev = grub_xhci_detect_dev, ++ .attach_dev = grub_xhci_attach_dev, ++ .detach_dev = grub_xhci_detach_dev, ++ /* estimated max. count of TDs for one bulk transfer */ ++ .max_bulk_tds = GRUB_XHCI_RING_ITEMS - 3 ++}; ++ ++GRUB_MOD_INIT (xhci) ++{ ++ grub_stop_disk_firmware (); ++ ++ grub_boot_time ("Initing XHCI hardware"); ++ grub_xhci_pci_scan (); ++ grub_boot_time ("Registering XHCI driver"); ++ grub_usb_controller_dev_register (&usb_controller); ++ grub_boot_time ("XHCI driver registered"); ++} ++ ++GRUB_MOD_FINI (xhci) ++{ ++ grub_xhci_fini_hw (0); ++ grub_usb_controller_dev_unregister (&usb_controller); ++} +diff --git a/include/grub/usb.h b/include/grub/usb.h +index 609faf7d0..eb71fa1c7 100644 +--- a/include/grub/usb.h ++++ b/include/grub/usb.h +@@ -338,6 +338,10 @@ grub_usb_cancel_transfer (grub_usb_transfer_t trans); + void + grub_ehci_init_device (volatile void *regs); + void ++grub_xhci_init_device (volatile void *regs); ++void + grub_ehci_pci_scan (void); ++void ++grub_xhci_pci_scan (void); + + #endif /* GRUB_USB_H */ +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch b/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch new file mode 100644 index 00000000..a37bbd6b --- /dev/null +++ b/config/grub/patches/0005-xhci/0007-grub-core-bus-usb-usbhub-Add-xHCI-non-root-hub-suppo.patch @@ -0,0 +1,127 @@ +From 2a2c64f6ea62337c1263a70f6ca9a9bade66b78b Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Thu, 3 Dec 2020 13:44:55 +0100 +Subject: [PATCH 7/8] grub-core/bus/usb/usbhub: Add xHCI non root hub support + +Tested on Intel PCH C246, the USB3 hub can be configured by grub. + +Issues: +* USB3 devices connected behind that hub are sometimes not detected. + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/usbhub.c | 38 +++++++++++++++++++++++++++++++++----- + include/grub/usbdesc.h | 1 + + include/grub/usbtrans.h | 4 ++++ + 3 files changed, 38 insertions(+), 5 deletions(-) + +diff --git a/grub-core/bus/usb/usbhub.c b/grub-core/bus/usb/usbhub.c +index b4b3a1a61..e96505aa9 100644 +--- a/grub-core/bus/usb/usbhub.c ++++ b/grub-core/bus/usb/usbhub.c +@@ -148,19 +148,32 @@ grub_usb_hub_add_dev (grub_usb_controller_t controller, + return dev; + } + +- ++static grub_usb_err_t ++grub_usb_set_hub_depth(grub_usb_device_t dev, grub_uint8_t depth) ++{ ++ return grub_usb_control_msg (dev, (GRUB_USB_REQTYPE_OUT ++ | GRUB_USB_REQTYPE_CLASS ++ | GRUB_USB_REQTYPE_TARGET_DEV), ++ GRUB_USB_HUB_REQ_SET_HUB_DEPTH, depth, ++ 0, 0, NULL); ++} ++ + static grub_usb_err_t + grub_usb_add_hub (grub_usb_device_t dev) + { + struct grub_usb_usb_hubdesc hubdesc; + grub_usb_err_t err; ++ grub_uint16_t req; + int i; + ++ req = (dev->speed == GRUB_USB_SPEED_SUPER) ? GRUB_USB_DESCRIPTOR_SS_HUB : ++ GRUB_USB_DESCRIPTOR_HUB; ++ + err = grub_usb_control_msg (dev, (GRUB_USB_REQTYPE_IN + | GRUB_USB_REQTYPE_CLASS + | GRUB_USB_REQTYPE_TARGET_DEV), +- GRUB_USB_REQ_GET_DESCRIPTOR, +- (GRUB_USB_DESCRIPTOR_HUB << 8) | 0, ++ GRUB_USB_REQ_GET_DESCRIPTOR, ++ (req << 8) | 0, + 0, sizeof (hubdesc), (char *) &hubdesc); + if (err) + return err; +@@ -183,6 +196,19 @@ grub_usb_add_hub (grub_usb_device_t dev) + return GRUB_USB_ERR_INTERNAL; + } + ++ if (dev->speed == GRUB_USB_SPEED_SUPER) ++ { ++ grub_uint8_t depth; ++ grub_uint32_t route; ++ /* Depth maximum value is 5, but root hubs doesn't count */ ++ for (depth = 0, route = dev->route; (route & 0xf) > 0; route >>= 4) ++ depth++; ++ ++ err = grub_usb_set_hub_depth(dev, depth); ++ if (err) ++ return err; ++ } ++ + /* Power on all Hub ports. */ + for (i = 1; i <= hubdesc.portcnt; i++) + { +@@ -637,7 +663,9 @@ poll_nonroot_hub (grub_usb_device_t dev) + int split_hubaddr = 0; + + /* Determine the device speed. */ +- if (status & GRUB_USB_HUB_STATUS_PORT_LOWSPEED) ++ if (dev->speed == GRUB_USB_SPEED_SUPER) ++ speed = GRUB_USB_SPEED_SUPER; ++ else if (status & GRUB_USB_HUB_STATUS_PORT_LOWSPEED) + speed = GRUB_USB_SPEED_LOW; + else + { +@@ -651,7 +679,7 @@ poll_nonroot_hub (grub_usb_device_t dev) + grub_millisleep (10); + + /* Find correct values for SPLIT hubport and hubaddr */ +- if (speed == GRUB_USB_SPEED_HIGH) ++ if (speed == GRUB_USB_SPEED_HIGH || speed == GRUB_USB_SPEED_SUPER) + { + /* HIGH speed device needs not transaction translation */ + split_hubport = 0; +diff --git a/include/grub/usbdesc.h b/include/grub/usbdesc.h +index bb2ab2e27..1697aa465 100644 +--- a/include/grub/usbdesc.h ++++ b/include/grub/usbdesc.h +@@ -30,6 +30,7 @@ typedef enum { + GRUB_USB_DESCRIPTOR_ENDPOINT, + GRUB_USB_DESCRIPTOR_DEBUG = 10, + GRUB_USB_DESCRIPTOR_HUB = 0x29, ++ GRUB_USB_DESCRIPTOR_SS_HUB = 0x2a, + GRUB_USB_DESCRIPTOR_SS_ENDPOINT_COMPANION = 0x30 + } grub_usb_descriptor_t; + +diff --git a/include/grub/usbtrans.h b/include/grub/usbtrans.h +index 039ebed65..d6c3f71dc 100644 +--- a/include/grub/usbtrans.h ++++ b/include/grub/usbtrans.h +@@ -110,6 +110,10 @@ enum + GRUB_USB_REQ_SET_INTERFACE = 0x0B, + GRUB_USB_REQ_SYNC_FRAME = 0x0C + }; ++enum ++ { ++ GRUB_USB_HUB_REQ_SET_HUB_DEPTH = 0x0C, ++ }; + + #define GRUB_USB_FEATURE_ENDP_HALT 0x00 + #define GRUB_USB_FEATURE_DEV_REMOTE_WU 0x01 +-- +2.39.2 + diff --git a/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch b/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch new file mode 100644 index 00000000..af79c3d0 --- /dev/null +++ b/config/grub/patches/0005-xhci/0008-Fix-compilation-on-x86_64.patch @@ -0,0 +1,90 @@ +From 871d768f8c5c960cb0d9761a9028b16882e1a7d3 Mon Sep 17 00:00:00 2001 +From: Patrick Rudolph +Date: Wed, 24 Feb 2021 08:25:41 +0100 +Subject: [PATCH 8/8] Fix compilation on x86_64 + +Signed-off-by: Patrick Rudolph +--- + grub-core/bus/usb/xhci.c | 24 ++++++++++++++++-------- + 1 file changed, 16 insertions(+), 8 deletions(-) + +diff --git a/grub-core/bus/usb/xhci.c b/grub-core/bus/usb/xhci.c +index f4591ffb5..3495bb919 100644 +--- a/grub-core/bus/usb/xhci.c ++++ b/grub-core/bus/usb/xhci.c +@@ -184,7 +184,7 @@ enum + * then we can get it from a trb pointer (provided by evt ring). + */ + #define XHCI_RING(_trb) \ +- ((struct grub_xhci_ring*)((grub_uint32_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) ++ ((struct grub_xhci_ring*)((grub_addr_t)(_trb) & ~(GRUB_XHCI_RING_SIZE-1))) + + /* slot context */ + struct grub_xhci_slotctx { +@@ -495,6 +495,14 @@ grub_xhci_read8(volatile void *addr) { + return (*((volatile grub_uint32_t *)addr)); + } + ++static inline void * ++grub_xhci_read_etrb_ptr(volatile struct grub_xhci_trb *trb) { ++ grub_uint64_t tmp; ++ tmp = (grub_uint64_t)grub_xhci_read32(&trb->ptr_low); ++ tmp |= ((grub_uint64_t)grub_xhci_read32(&trb->ptr_high)) << 32; ++ return (void *)(grub_addr_t)tmp; ++} ++ + static inline grub_uint32_t + grub_xhci_port_read (struct grub_xhci *x, grub_uint32_t port) + { +@@ -664,7 +672,7 @@ static void xhci_process_events(struct grub_xhci *x) + case ER_TRANSFER: + case ER_COMMAND_COMPLETE: + { +- struct grub_xhci_trb *rtrb = (void*)grub_xhci_read32(&etrb->ptr_low); ++ struct grub_xhci_trb *rtrb = grub_xhci_read_etrb_ptr(etrb); + struct grub_xhci_ring *ring = XHCI_RING(rtrb); + volatile struct grub_xhci_trb *evt = &ring->evt; + grub_uint32_t eidx = rtrb - ring->ring + 1; +@@ -697,9 +705,9 @@ static void xhci_process_events(struct grub_xhci *x) + } + grub_xhci_write32(&evts->nidx, nidx); + volatile struct grub_xhci_ir *ir = x->ir; +- grub_uint32_t erdp = (grub_uint32_t)(evts->ring + nidx); +- grub_xhci_write32(&ir->erdp_low, erdp); +- grub_xhci_write32(&ir->erdp_high, 0); ++ grub_uint64_t erdp = (grub_addr_t)(void *)(&evts->ring[nidx]); ++ grub_xhci_write32(&ir->erdp_low, erdp & 0xffffffff); ++ grub_xhci_write32(&ir->erdp_high, erdp >> 32); + } + } + +@@ -800,7 +808,7 @@ static void xhci_trb_queue(volatile struct grub_xhci_ring *ring, + grub_uint32_t xferlen, grub_uint32_t flags) + { + grub_dprintf("xhci", "%s: ring %p data %llx len %d flags 0x%x remain 0x%x\n", __func__, +- ring, data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); ++ ring, (unsigned long long)data_or_addr, xferlen & 0x1ffff, flags, xferlen >> 17); + + if (xhci_ring_full(ring)) + { +@@ -1907,7 +1915,7 @@ grub_xhci_setup_transfer (grub_usb_controller_t dev, + if (transfer->type == GRUB_USB_TRANSACTION_TYPE_CONTROL) + { + volatile struct grub_usb_packet_setup *setupdata; +- setupdata = (void *)transfer->transactions[0].data; ++ setupdata = (void *)(grub_addr_t)transfer->transactions[0].data; + grub_dprintf("xhci", "%s: CONTROLL TRANS req %d\n", __func__, setupdata->request); + grub_dprintf("xhci", "%s: CONTROLL TRANS length %d\n", __func__, setupdata->length); + +@@ -1974,7 +1982,7 @@ grub_xhci_setup_transfer (grub_usb_controller_t dev, + /* Assume the ring has enough free space for all TRBs */ + if (flags & TRB_TR_IDT && tr->size <= (int)sizeof(inline_data)) + { +- grub_memcpy(&inline_data, (void *)tr->data, tr->size); ++ grub_memcpy(&inline_data, (void *)(grub_addr_t)tr->data, tr->size); + xhci_trb_queue(reqs, inline_data, tr->size, flags); + } + else +-- +2.39.2 + From 4134a883d0d8dd4020f2ddca7416e0b9f82b8843 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 5 Apr 2024 23:53:03 +0100 Subject: [PATCH 0012/1319] add 9020 sff/mt targets that use broadwell mrc broadwell mrc has better peg handling and can support 16gb modules on broadwell machines - the blob can be used on haswell machines too, instead of haswell mrc, and it might support 16gb modules on these machines (not yet tested, but using broadwell mrc does at least boot as reliably as haswell mrc anyway) one little quirk with haswell mrc is that it actually handles vga decode, disabling the igpu entirely, when a dgpu is used. the broadwell mrc enables both GPUs and does not handle vga decoding, so we must handle this the usual way; my patch for this was merged upstream and i'm also adding it to libreboot, which currently uses an older coreboot revision. this is needed for dgpu to work. see patch: 0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch broadwell mrc may also make dealing with nvidia optimus setups more reliable, on laptops that have nvidia GPUs, but this patch does not add bmrc configs for t440p/w541 NOTE: on t440p/w541 laptops with nvidia graphics, the video output is wired to intel but rendering can be offloaded to nvidia. in this setup, we want vga decode to be done on intel, so i've set these configs to enable CONFIG_ONBOARD_VGA_IS_PRIMARY (set it to y) Signed-off-by: Leah Rowe --- ...swell-Disable-iGPU-when-dGPU-is-used.patch | 54 ++ ...Fully-disable-iGPU-when-dGPU-is-used.patch | 51 ++ .../config/libgfxinit_corebootfb | 636 ++++++++++++++++++ .../config/libgfxinit_txtmode | 633 +++++++++++++++++ .../coreboot/dell9020mtbmrc_12mb/target.cfg | 7 + .../config/libgfxinit_corebootfb | 636 ++++++++++++++++++ .../config/libgfxinit_txtmode | 633 +++++++++++++++++ .../coreboot/dell9020sffbmrc_12mb/target.cfg | 7 + .../config/libgfxinit_corebootfb | 2 +- .../t440pmrc_12mb/config/libgfxinit_txtmode | 2 +- .../w541mrc_12mb/config/libgfxinit_corebootfb | 2 +- .../w541mrc_12mb/config/libgfxinit_txtmode | 2 +- config/vendor/sources | 13 + 13 files changed, 2674 insertions(+), 4 deletions(-) create mode 100644 config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch create mode 100644 config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch create mode 100644 config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/dell9020mtbmrc_12mb/target.cfg create mode 100644 config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/dell9020sffbmrc_12mb/target.cfg diff --git a/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..7a02d902 --- /dev/null +++ b/config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,54 @@ +From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 23 Feb 2024 13:33:31 +0000 +Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used + +This is usually is handled by Haswell mrc.bin, disabling VGA +decode on the iGPU when a dGPU is installed. However, Broadwell +mrc.bin does not, so the iGPU and dGPU are both enabled. + +This patch disables legacy VGA cycles for iGPU, under such +conditions. It has been tested on Broadwell mrc.bin when +using a graphics card on Dell OptiPlex 9020 SFF (currently +under review at this time of writing, submitted by Mate +Kukri). + +This patch has also been tested when Haswell mrc.bin is used, +and there are seemingly no breaking changes caused by it. + +Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b +Signed-off-by: Leah Rowe +Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717 +Tested-by: build bot (Jenkins) +Reviewed-by: Nico Huber +--- + src/northbridge/intel/haswell/gma.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 6e6948b70f..48a0ba54c7 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev) + drivers_intel_gma_displays_ssdt_generate(&chip->gfx); + } + ++static void gma_func0_disable(struct device *dev) ++{ ++ /* Disable VGA decode */ ++ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++} ++ + static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .acpi_fill_ssdt = gma_generate_ssdt, ++ .vga_disable = gma_func0_disable, + .ops_pci = &pci_dev_ops_pci, + }; + +-- +2.39.2 + diff --git a/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..bc8fd55c --- /dev/null +++ b/config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,51 @@ +From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 6 Apr 2024 01:22:47 +0100 +Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used + +My earlier patch disabled decode *and* disabled the iGPU itself, but +a subsequent revision disabled only VGA decode. Upon revisiting, I +found that, actually, yes, you also need to disable the iGPU entirely. + +Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. +With this patch, the iGPU is completely disabled when you install a +graphics card, but the iGPU is available to use when no graphics card +is present. + +For more context, see: + +Author: Leah Rowe +Date: Fri Feb 23 13:33:31 2024 +0000 + + nb/haswell: Disable iGPU when dGPU is used + +And look at the Gerrit comments: + +https://review.coreboot.org/c/coreboot/+/80717/ + +So, my original submission on change 80717 was actually correct. +This patch fixes the issue. I tested on iGPU and dGPU, with both +broadwell and haswell mrc.bin. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/gma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 48a0ba54c7..f0b848852d 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev) + { + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++ ++ /* Required or else the graphics card doesn't work */ ++ dev->enabled = 0; + } + + static struct device_operations gma_func0_ops = { +-- +2.39.2 + diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..953901cd --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,636 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..682c9e99 --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,633 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg new file mode 100644 index 00000000..e6d3bec6 --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..c4995430 --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,636 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..dc3d337d --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,633 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set +# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg new file mode 100644 index 00000000..e6d3bec6 --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="default" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb index f2067194..d7124b0f 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb @@ -119,7 +119,7 @@ CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t440p" diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode index 9fa0abac..fc7db117 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode @@ -117,7 +117,7 @@ CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t440p" diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb index 314dbbc9..3f0cf31a 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb @@ -119,7 +119,7 @@ CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="w541" diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode index 8f09ec77..e0d0c538 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode @@ -117,7 +117,7 @@ CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="w541" diff --git a/config/vendor/sources b/config/vendor/sources index b87953e8..ba59a994 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -21,6 +21,18 @@ DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe } +# haswell boards, but use broadwell mrc.bin. uses me9 and +# the broadwell mrc, but without broadwell refcode +{dell9020sffbmrc dell9020mtbmrc}{ + DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998 + DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe + DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe + MRC_url https://dl.google.com/dl/edgedl/chromeos/recovery/chromeos_13904.77.0_samus_recovery_stable-channel_mp-v3.bin.zip + MRC_url_bkup https://web.archive.org/web/20220310155922/https://dl.google.com/dl/edgedl/chromeos/recovery/chromeos_13904.77.0_samus_recovery_stable-channel_mp-v3.bin.zip + MRC_hash 3ff1599c52539f0707a07a8664a84ce51cd3fed1569df4bb7aa6722fc8dec0af1754250333b6ca1a9794d970a4de7b29a5cf2499f5b61e4c3eab64d1314aaea9 + MRC_board samus +} + # NOTE: google's manifest for archives containing mrc.bin, used here: # https://web.archive.org/web/20210211071412/https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf {t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff}{ @@ -33,6 +45,7 @@ MRC_board peppy } +# broadwell mrc, and use me10 plus broadwell refcode {hp820g2}{ DL_hash 1ac05a3e4f46426eeb77f89c4aca25ed1ad64479d8fcba6a3ab63a944512bacbc5d148cc7b9c4ff4b8c90a1fb1de4776e46f14aca8021900e0df37246aa0b717 DL_url https://download.lenovo.com/pccbbs/mobiles/n10rg50w.exe From e9c591a5547f48b2fce3337a502e87da6833d6d5 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 6 Apr 2024 02:09:04 +0100 Subject: [PATCH 0013/1319] add t440p/w541 configs using broadwell mrc broadwell mrc enables both igpu and dgpu to be enabled at any given time. if the onboard (intel) gpu is set as primary, the logic to disable it is not executed within coreboot; instead, the igpu is used for vga decode. on some t440p/w541 thinkpads, both an intel and nvidia gpu are present. in this setup, the intel gpu must be used for vga, and all output, but rendering can be offloaded to the nvidia gpu (nvidia optimus). optimus would never work on haswell mrc.bin, because it always disables the igpu when a dgpu is present, so a hack exists in coreboot that hides the dgpu from mrc, so that the igpu remains enabled. broadwell mrc doesn't do this, so the option to hide PEG devices has been disabled in these configs. the broadwell mrc has better peg device handling, and can support 16gb modules on broadwell hardware; it may well support these modules on haswell hardware too, though ddr3 sodimms are very hard to find (and expensive). (and currently untested, with this patch) Signed-off-by: Leah Rowe --- .../config/libgfxinit_corebootfb | 659 ++++++++++++++++++ .../t440pbmrc_12mb/config/libgfxinit_txtmode | 656 +++++++++++++++++ config/coreboot/t440pbmrc_12mb/target.cfg | 7 + .../config/libgfxinit_corebootfb | 659 ++++++++++++++++++ .../w541bmrc_12mb/config/libgfxinit_txtmode | 656 +++++++++++++++++ config/coreboot/w541bmrc_12mb/target.cfg | 7 + config/vendor/sources | 2 +- 7 files changed, 2645 insertions(+), 1 deletion(-) create mode 100644 config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/t440pbmrc_12mb/target.cfg create mode 100644 config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/w541bmrc_12mb/target.cfg diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..5026c68e --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,659 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..a6b1bf70 --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,656 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_NULL=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440pbmrc_12mb/target.cfg b/config/coreboot/t440pbmrc_12mb/target.cfg new file mode 100644 index 00000000..8688df3f --- /dev/null +++ b/config/coreboot/t440pbmrc_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="default" +xarch="i386-elf" +payload_grub="y" +payload_grub_withseabios="y" +payload_seabios="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..a5342fbb --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,659 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..60686a0f --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode @@ -0,0 +1,656 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0x800000 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_TPM_PIRQ=0x0 +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X220_EDP is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_EHCI_BAR=0xd8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin" +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_USE_BROADWELL_MRC=y +# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_USE_PC_CMOS_ALTCENTURY=y +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y +CONFIG_HEAP_SIZE=0x100000 + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541bmrc_12mb/target.cfg b/config/coreboot/w541bmrc_12mb/target.cfg new file mode 100644 index 00000000..8688df3f --- /dev/null +++ b/config/coreboot/w541bmrc_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="default" +xarch="i386-elf" +payload_grub="y" +payload_grub_withseabios="y" +payload_seabios="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/vendor/sources b/config/vendor/sources index ba59a994..2d54bd44 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -23,7 +23,7 @@ # haswell boards, but use broadwell mrc.bin. uses me9 and # the broadwell mrc, but without broadwell refcode -{dell9020sffbmrc dell9020mtbmrc}{ +{dell9020sffbmrc dell9020mtbmrc t440pbmrc w541bmrc}{ DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998 DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe From 831954899c2080a9d0e3e34932afa55b25bc8fdc Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 6 Apr 2024 16:00:57 +0100 Subject: [PATCH 0014/1319] enable grub payload on libremrc w541/t440p the grub payload was previously disabled, because the libre mrc code sets up xhci rather than ehci, and grub did not have xhci support (not natively). libreboot now has xhci support in the grub payload, so enable grub on these configurations. Signed-off-by: Leah Rowe --- config/coreboot/t440plibremrc_12mb/target.cfg | 5 +++-- config/coreboot/w541_12mb/target.cfg | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/config/coreboot/t440plibremrc_12mb/target.cfg b/config/coreboot/t440plibremrc_12mb/target.cfg index d36486ab..8bb575a9 100644 --- a/config/coreboot/t440plibremrc_12mb/target.cfg +++ b/config/coreboot/t440plibremrc_12mb/target.cfg @@ -1,6 +1,7 @@ tree="haswell" xarch="i386-elf" -payload_grub="n" -payload_grub_withseabios="n" +payload_grub="y" +payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/w541_12mb/target.cfg b/config/coreboot/w541_12mb/target.cfg index d36486ab..8bb575a9 100644 --- a/config/coreboot/w541_12mb/target.cfg +++ b/config/coreboot/w541_12mb/target.cfg @@ -1,6 +1,7 @@ tree="haswell" xarch="i386-elf" -payload_grub="n" -payload_grub_withseabios="n" +payload_grub="y" +payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" +grub_scan_disk="ahci" From 6da91df6b9473628b02f4d5a1e0a801a49a2e6da Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 7 Apr 2024 03:45:32 +0100 Subject: [PATCH 0015/1319] add mate's patch for 9020 sff/mt fan controls see: https://review.coreboot.org/c/coreboot/+/81529 what i've merged is patchset 4. i had to rebase it slightly, because the libreboot version has the iommu toggle on cmos configs, which are files that mate's patch also changes, leading to merge conflict. Signed-off-by: Leah Rowe --- ..._9020-Implement-late-HWM-initializat.patch | 594 ++++++++++++++++++ 1 file changed, 594 insertions(+) create mode 100644 config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch new file mode 100644 index 00000000..f6bd1940 --- /dev/null +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -0,0 +1,594 @@ +From f6340f3fe21e948ba94d0429467882c2fb90b77e Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Sat, 6 Apr 2024 23:25:15 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization + +There are 4 different chassis types specified by vendor firmware, each +with a slightly different HWM configuration. + +The chassis type to use is determined at runtime by reading a set of +4 PCH GPIOs: 70, 38, 17, and 0. + +Additionally vendor firmware also provides an option to run the fans at +full speed. This is substituted with a coreboot nvram option in this +implementation. + +This was tested to make fan control work on my OptiPlex 7020 SFF. + +NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 +however the OptiPlex 9020's SCH5555 does not use externally +programmed EC firmware. + +Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 +Signed-off-by: Mate Kukri +--- + src/mainboard/dell/optiplex_9020/Makefile.inc | 3 +- + src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- + src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 + + 7 files changed, 455 insertions(+), 22 deletions(-) + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc +index 6ca2f2afaa..08e2e53577 100644 +--- a/src/mainboard/dell/optiplex_9020/Makefile.inc ++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc +@@ -2,4 +2,5 @@ + + romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +-bootblock-y += bootblock.c ++ramstage-y += sch5555_ec.c ++bootblock-y += bootblock.c sch5555_ec.c +diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c +index 2837cf9cf1..e5e759273e 100644 +--- a/src/mainboard/dell/optiplex_9020/bootblock.c ++++ b/src/mainboard/dell/optiplex_9020/bootblock.c +@@ -4,29 +4,14 @@ + #include + #include + #include +- +-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) +-{ +- // Clear EC-to-Host mailbox +- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); +- outb(tmp, SCH555x_EMI_IOBASE + 1); +- +- // Send address and value to the EC +- sch555x_emi_write16(0, (addr1 * 2) | 0x101); +- sch555x_emi_write32(4, val | (addr2 << 16)); +- +- // Wait for acknowledgement message from EC +- outb(1, SCH555x_EMI_IOBASE); +- size_t timeout = 0; +- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); +-} ++#include "sch5555_ec.h" + + struct ec_init_entry { + uint16_t addr; + uint8_t val; + }; + +-static void ec_init(void) ++static void bootblock_ec_init(void) + { + /* + * Tables from CORE_PEI +@@ -108,9 +93,9 @@ void mainboard_config_superio(void) + outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); + outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); + +- // Magic EC init +- ec_init(); ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); + +- // Magic EC init is needed for UART1 initialization to work ++ // Bootblock EC initialization is required for UART1 to work + sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index 7bccc80e51..1909abcb9f 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,3 +3,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + iommu=Disable ++fan_full_speed=Disable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index 72ff9c4bee..4a1496a878 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -22,7 +22,10 @@ entries + 409 2 e 5 power_on_after_fail + + # turn iommu on or off +-412 1 e 6 iommu ++411 1 e 6 iommu ++ ++# coreboot config options: EC ++412 1 e 1 fan_full_speed + + # coreboot config options: check sums + 984 16 h 0 check_sum +diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c +index c834fea5d3..10b8aaca0e 100644 +--- a/src/mainboard/dell/optiplex_9020/mainboard.c ++++ b/src/mainboard/dell/optiplex_9020/mainboard.c +@@ -1,7 +1,12 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include ++#include + #include + #include ++#include ++#include ++#include "sch5555_ec.h" + + static void mainboard_enable(struct device *dev) + { +@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev) + struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + }; ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++struct hwm_tab_entry HWM_TAB3[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x8a, 0, 0x0010 }, ++ { 0x086, 0x4c, 0, 0x0010 }, ++ { 0x08a, 0x66, 0, 0x0010 }, ++ { 0x08b, 0x5b, 0, 0x0010 }, ++ { 0x090, 0x65, 0, 0xffff }, ++ { 0x091, 0x70, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x99, 0, 0xffff }, ++ { 0x280, 0xa0, 0, 0x0010 }, ++ { 0x281, 0x0f, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x68, 0, 0x0010 }, ++ { 0x289, 0x10, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB4[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x99, 0, 0x0020 }, ++ { 0x085, 0xad, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x8b, 0, 0x0010 }, ++ { 0x090, 0x5e, 0, 0xffff }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB5[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x66, 0, 0x0020 }, ++ { 0x085, 0x5d, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x80, 0, 0x0010 }, ++ { 0x090, 0x5d, 0, 0x0020 }, ++ { 0x090, 0x5e, 0, 0x0010 }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa3, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x08, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x98, 0, 0x0020 }, ++ { 0x1be, 0x90, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB6[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x98, 0, 0xffff }, ++ { 0x086, 0x3c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x3d, 0, 0x0010 }, ++ { 0x08b, 0x44, 0, 0x0020 }, ++ { 0x08b, 0x51, 0, 0x0010 }, ++ { 0x090, 0x61, 0, 0xffff }, ++ { 0x091, 0x6d, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0x9f, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9b, 0, 0x0020 }, ++ { 0x0b0, 0x98, 0, 0x0010 }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x9a, 0, 0x0020 }, ++ { 0x1be, 0x96, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0x0020 }, ++ { 0x289, 0x11, 0, 0x0020 }, ++ { 0x288, 0x94, 0, 0x0010 }, ++ { 0x289, 0x11, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++static uint8_t get_chassis_type(void) ++{ ++ uint8_t gpio_chassis_type; ++ ++ // Read chassis type from GPIO ++ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | ++ get_gpio(17) << 1 | get_gpio(0); ++ ++ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); ++ ++ // Turn it into internal chassis index ++ switch (gpio_chassis_type) { ++ case 0x08: ++ case 0x0a: ++ return 4; ++ case 0x0b: ++ return 3; ++ case 0x0c: ++ return 5; ++ case 0x0d: // SFF ++ case 0x0e: ++ case 0x0f: ++ return 6; ++ default: ++ die("Unknown GPIO chassis type\n"); ++ } ++ ++} ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; ++ if (rapl_power_unit) ++ rapl_power_unit = 2 << (rapl_power_unit - 1); ++ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; ++ if (pkg_power_info / rapl_power_unit > 0x41) ++ return 32; ++ else ++ return 16; ++} ++ ++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ ec_write(1, arr[i].addr, val); ++ ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t chassis_type, saved_2fc; ++ ++ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); ++ ++ saved_2fc = ec_read(1, 0x2fc); ++ ec_write(1, 0x2fc, 0xa0); ++ ec_write(1, 0x2fd, 0x32); ++ ++ // Apply HWM table based on chassis type ++ chassis_type = get_chassis_type(); ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ switch (chassis_type) { ++ case 3: ++ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); ++ break; ++ case 4: ++ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); ++ break; ++ case 5: ++ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); ++ break; ++ case 6: ++ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); ++ break; ++ default: ++ die("Unknown chassis type\n"); ++ } ++ ++ if (CONFIG_MAX_CPUS > 2) { ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); ++ } ++ ++ ec_write(1, 0x2fc, saved_2fc); ++ ++ // Apply full speed fan config if requested ++ if (get_uint_option("fan_full_speed", 0)) { ++ printk(BIOS_DEBUG, "Setting full fan speed\n"); ++ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); ++ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); ++ } ++ ++ ec_read(1, 0xb8); ++ ++ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { ++ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); ++ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); ++ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); ++ ec_write(1, 0x8a, 0x99); ++ ec_write(1, 0x8b, 0x47); ++ ec_write(1, 0x8c, 0x91); ++ } ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +new file mode 100644 +index 0000000000..92244da9ab +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "sch5555_ec.h" ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +new file mode 100644 +index 0000000000..6e703ff865 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +@@ -0,0 +1,7 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#pragma once ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2); ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); +-- +2.39.2 + From 9e3b217cfdce5e32c6c6d6e1c79786555ee4eb1c Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 20 Apr 2024 21:50:56 +0100 Subject: [PATCH 0016/1319] update coreboot/haswell (NRI) the t440p/w541 configs were re-done from scratch, because the coreboot revisions are nearly two years apart. i also added corebootfb configs. hell updated their patchset. this patchset uses the following patch: https://review.coreboot.org/c/coreboot/+/81948/1 it uses this, along with parent patches in the haswell nri patch series Signed-off-by: Leah Rowe --- ...-clamp.h-Add-more-clamping-functions.patch | 54 -- ...=> 0001-haswell-NRI-Initialise-MPLL.patch} | 34 +- ...l-NRI-Post-process-selected-timings.patch} | 24 +- ...-Introduce-option-to-not-use-MRC.bin.patch | 143 ---- ...l-NRI-Configure-initial-MC-settings.patch} | 32 +- ...aswell-lynxpoint-Add-native-DMI-init.patch | 615 -------------- ...NRI-Add-timings-refresh-programming.patch} | 12 +- ...l-lynxpoint-Add-native-early-ME-init.patch | 148 ---- ...0005-haswell-NRI-Program-memory-map.patch} | 16 +- ...-intel-lynxpoint-Add-native-USB-init.patch | 783 ----------------- ...l-NRI-Add-DDR3-JEDEC-reset-and-init.patch} | 54 +- ...el-lynxpoint-Add-native-thermal-init.patch | 128 --- ...-haswell-NRI-Add-pre-training-steps.patch} | 34 +- ...-intel-lynxpoint-Add-native-PCH-init.patch | 785 ------------------ ...swell-NRI-Add-REUT-I-O-test-library.patch} | 36 +- ...swell-Add-native-raminit-scaffolding.patch | 407 --------- ...well-NRI-Add-range-tracking-library.patch} | 12 +- ...-nri-Only-do-CPU-replacement-check-o.patch | 57 -- ...l-NRI-Add-library-to-change-margins.patch} | 20 +- .../0010-haswell-NRI-Collect-SPD-info.patch | 344 -------- ...0011-haswell-NRI-Add-RcvEn-training.patch} | 16 +- ...-NRI-Add-function-to-change-margins.patch} | 12 +- ...3-haswell-NRI-Add-read-MPR-training.patch} | 29 +- ...0014-haswell-NRI-Add-write-leveling.patch} | 31 +- ...haswell-NRI-Add-final-raminit-steps.patch} | 26 +- ...Haswell-NRI-Implement-fast-boot-path.patch | 722 ++++++++++++++++ ...I-Do-sense-amplifier-offset-training.patch | 476 +++++++++++ ...r-coreboot-images-built-without-a-p.patch} | 19 +- ...-mirrorservice.org-for-gcc-downloads.patch | 36 + ...ool-add-nuke-flag-all-0xFF-on-region.patch | 204 +++++ ...oreboot-haswell-fix-acpica-downloads.patch | 30 - ...-mirrorservice.org-for-gcc-downloads.patch | 36 - .../patches/0029-ifdtool-nuke-option.patch | 194 ----- config/coreboot/haswell/target.cfg | 2 +- .../config/libgfxinit_corebootfb | 668 +++++++++++++++ .../config/libgfxinit_txtmode | 182 ++-- .../w541_12mb/config/libgfxinit_corebootfb | 667 +++++++++++++++ .../w541_12mb/config/libgfxinit_txtmode | 161 ++-- 38 files changed, 3164 insertions(+), 4085 deletions(-) delete mode 100644 config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch rename config/coreboot/haswell/patches/{0011-haswell-NRI-Initialise-MPLL.patch => 0001-haswell-NRI-Initialise-MPLL.patch} (92%) rename config/coreboot/haswell/patches/{0012-haswell-NRI-Post-process-selected-timings.patch => 0002-haswell-NRI-Post-process-selected-timings.patch} (92%) delete mode 100644 config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch rename config/coreboot/haswell/patches/{0013-haswell-NRI-Configure-initial-MC-settings.patch => 0003-haswell-NRI-Configure-initial-MC-settings.patch} (98%) delete mode 100644 config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch rename config/coreboot/haswell/patches/{0014-haswell-NRI-Add-timings-refresh-programming.patch => 0004-haswell-NRI-Add-timings-refresh-programming.patch} (98%) delete mode 100644 config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch rename config/coreboot/haswell/patches/{0015-haswell-NRI-Program-memory-map.patch => 0005-haswell-NRI-Program-memory-map.patch} (95%) delete mode 100644 config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch rename config/coreboot/haswell/patches/{0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch => 0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch} (95%) delete mode 100644 config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch rename config/coreboot/haswell/patches/{0017-haswell-NRI-Add-pre-training-steps.patch => 0007-haswell-NRI-Add-pre-training-steps.patch} (93%) delete mode 100644 config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch rename config/coreboot/haswell/patches/{0018-haswell-NRI-Add-REUT-I-O-test-library.patch => 0008-haswell-NRI-Add-REUT-I-O-test-library.patch} (97%) delete mode 100644 config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch rename config/coreboot/haswell/patches/{0019-haswell-NRI-Add-range-tracking-library.patch => 0009-haswell-NRI-Add-range-tracking-library.patch} (94%) delete mode 100644 config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch rename config/coreboot/haswell/patches/{0020-haswell-NRI-Add-library-to-change-margins.patch => 0010-haswell-NRI-Add-library-to-change-margins.patch} (94%) delete mode 100644 config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch rename config/coreboot/haswell/patches/{0021-haswell-NRI-Add-RcvEn-training.patch => 0011-haswell-NRI-Add-RcvEn-training.patch} (98%) rename config/coreboot/haswell/patches/{0022-haswell-NRI-Add-function-to-change-margins.patch => 0012-haswell-NRI-Add-function-to-change-margins.patch} (96%) rename config/coreboot/haswell/patches/{0023-haswell-NRI-Add-read-MPR-training.patch => 0013-haswell-NRI-Add-read-MPR-training.patch} (93%) rename config/coreboot/haswell/patches/{0024-haswell-NRI-Add-write-leveling.patch => 0014-haswell-NRI-Add-write-leveling.patch} (96%) rename config/coreboot/haswell/patches/{0025-haswell-NRI-Add-final-raminit-steps.patch => 0015-haswell-NRI-Add-final-raminit-steps.patch} (96%) create mode 100644 config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch create mode 100644 config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch rename config/coreboot/haswell/patches/{0026-Remove-warning-for-coreboot-images-built-without-a-p.patch => 0018-Remove-warning-for-coreboot-images-built-without-a-p.patch} (74%) create mode 100644 config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch create mode 100644 config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch delete mode 100644 config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch delete mode 100644 config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch delete mode 100644 config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch create mode 100644 config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/w541_12mb/config/libgfxinit_corebootfb diff --git a/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch b/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch deleted file mode 100644 index 96e4c14d..00000000 --- a/config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch +++ /dev/null @@ -1,54 +0,0 @@ -From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Sat, 7 May 2022 20:36:10 +0200 -Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions - -Add more clamping functions that work with different types. - -Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b -Signed-off-by: Angel Pons ---- - src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++-------- - 1 file changed, 18 insertions(+), 8 deletions(-) - -diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h -index e01a107ed4..526185195c 100644 ---- a/src/commonlib/include/commonlib/clamp.h -+++ b/src/commonlib/include/commonlib/clamp.h -@@ -8,15 +8,25 @@ - /* - * Clamp a value, so that it is between a lower and an upper bound. - */ --static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max) --{ -- if (val > max) -- return max; -+#define __MAKE_CLAMP_FUNC(type) \ -+ static inline type clamp_##type(const type min, const type val, const type max) \ -+ { \ -+ if (val > max) \ -+ return max; \ -+ if (val < min) \ -+ return min; \ -+ return val; \ -+ } \ - -- if (val < min) -- return min; -+__MAKE_CLAMP_FUNC(s8) /* clamp_s8 */ -+__MAKE_CLAMP_FUNC(u8) /* clamp_u8 */ -+__MAKE_CLAMP_FUNC(s16) /* clamp_s16 */ -+__MAKE_CLAMP_FUNC(u16) /* clamp_u16 */ -+__MAKE_CLAMP_FUNC(s32) /* clamp_s32 */ -+__MAKE_CLAMP_FUNC(u32) /* clamp_u32 */ -+__MAKE_CLAMP_FUNC(s64) /* clamp_s64 */ -+__MAKE_CLAMP_FUNC(u64) /* clamp_u64 */ - -- return val; --} -+#undef __MAKE_CLAMP_FUNC - - #endif /* COMMONLIB_CLAMP_H */ --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch b/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch similarity index 92% rename from config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch rename to config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch index 1fec2e38..0de1a4ec 100644 --- a/config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch +++ b/config/coreboot/haswell/patches/0001-haswell-NRI-Initialise-MPLL.patch @@ -1,7 +1,7 @@ -From 77a89d55ab7a715dc20c34a6edacaaf781b56087 Mon Sep 17 00:00:00 2001 +From cce5392f272b0acc493f47f9b5ca3cf90ce901e8 Mon Sep 17 00:00:00 2001 From: Angel Pons -Date: Sat, 7 May 2022 14:36:10 +0200 -Subject: [PATCH 11/26] haswell NRI: Initialise MPLL +Date: Thu, 11 Apr 2024 17:25:07 +0200 +Subject: [PATCH 01/20] haswell NRI: Initialise MPLL Add code to initialise the MPLL (Memory PLL). The procedure is similar to the one for Sandy/Ivy Bridge, but it is not worth factoring out. @@ -9,20 +9,20 @@ to the one for Sandy/Ivy Bridge, but it is not worth factoring out. Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 2 + + .../intel/haswell/native_raminit/Makefile.mk | 2 + .../intel/haswell/native_raminit/init_mpll.c | 210 ++++++++++++++++++ .../haswell/native_raminit/io_comp_control.c | 22 ++ - .../haswell/native_raminit/raminit_main.c | 1 + + .../haswell/native_raminit/raminit_main.c | 3 +- .../haswell/native_raminit/raminit_native.h | 11 + .../intel/haswell/registers/mchbar.h | 3 + - 6 files changed, 249 insertions(+) + 6 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index ebf7abc6ec..c125d84f0b 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -33,13 +33,13 @@ index ebf7abc6ec..c125d84f0b 100644 romstage-y += spd_bitmunching.c diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c new file mode 100644 -index 0000000000..2faa183724 +index 0000000000..1f3f2c29a9 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include ++#include +#include +#include +#include @@ -249,13 +249,13 @@ index 0000000000..2faa183724 +} diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c new file mode 100644 -index 0000000000..7e96c08938 +index 0000000000..d45b608dd3 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include ++#include +#include +#include +#include @@ -276,13 +276,15 @@ index 0000000000..7e96c08938 + return RAMINIT_STATUS_POLL_TIMEOUT; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 2d2cfa48bb..09545422c0 100644 +index 19ec5859ac..bf745e943f 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -21,6 +21,7 @@ struct task_entry { +@@ -19,7 +19,8 @@ struct task_entry { + }; static const struct task_entry cold_boot[] = { - { collect_spd_info, true, "PROCSPD", }, +- { collect_spd_info, true, "PROCSPD", }, ++ { collect_spd_info, true, "PROCSPD", }, + { initialise_mpll, true, "INITMPLL", }, }; diff --git a/config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch b/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch similarity index 92% rename from config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch rename to config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch index e38f8e57..0cc95cdd 100644 --- a/config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch +++ b/config/coreboot/haswell/patches/0002-haswell-NRI-Post-process-selected-timings.patch @@ -1,7 +1,7 @@ -From faabed9ca8974b2e7192c55b59a9d28d75e72df6 Mon Sep 17 00:00:00 2001 +From 42b21fdce8c8bade53d9d86515f88b0665a4c1b1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 16:29:55 +0200 -Subject: [PATCH 12/26] haswell NRI: Post-process selected timings +Subject: [PATCH 02/20] haswell NRI: Post-process selected timings Once the MPLL has been initialised, convert the timings from the SPD to be in DCLKs, which is what the hardware expects. In addition, calculate @@ -10,7 +10,7 @@ the values for tREFI and tXP. Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/lookup_timings.c | 62 +++++++++++ .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 8 ++ @@ -18,10 +18,10 @@ Signed-off-by: Angel Pons 5 files changed, 172 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index c125d84f0b..2769e0bbb4 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -31,13 +31,13 @@ index c125d84f0b..2769e0bbb4 100644 romstage-y += raminit_main.c diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c new file mode 100644 -index 0000000000..038686c844 +index 0000000000..8b81c7c341 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include ++#include +#include + +#include "raminit_native.h" @@ -98,10 +98,10 @@ index 0000000000..038686c844 + return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut)); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 09545422c0..5f2be980d4 100644 +index bf745e943f..2fea658415 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -22,6 +22,7 @@ struct task_entry { +@@ -21,6 +21,7 @@ struct task_entry { static const struct task_entry cold_boot[] = { { collect_spd_info, true, "PROCSPD", }, { initialise_mpll, true, "INITMPLL", }, @@ -137,7 +137,7 @@ index a54581abc7..01e5ed1bd6 100644 + #endif diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -index dbe02c72d0..becbea0725 100644 +index 2dab8504c4..7d98341a7e 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl) @@ -221,7 +221,7 @@ index dbe02c72d0..becbea0725 100644 + */ + + /* tCK is special */ -+ printk(BIOS_DEBUG, "Selected tCK : %u ns\n", ctrl->tCK / 256); ++ printk(BIOS_DEBUG, "Selected tCK : %u ps\n", ctrl->tCK * 1000 / 256); + + /* Primary timings */ + printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA); diff --git a/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch b/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch deleted file mode 100644 index 35d5c89e..00000000 --- a/config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch +++ /dev/null @@ -1,143 +0,0 @@ -From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 21:12:14 +0200 -Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin - -Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow -booting coreboot on Haswell mainboards without the need of the closed -source MRC.bin. For now, this option does not work at all; the needed -magic will be implemented in subsequent commits. Add a config file to -make sure the newly-introduced option gets build-tested. - -Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e -Signed-off-by: Angel Pons ---- - configs/config.asrock_b85m_pro4.native_raminit | 5 +++++ - src/northbridge/intel/haswell/Kconfig | 13 +++++++++++++ - src/northbridge/intel/haswell/Makefile.inc | 7 ++++++- - .../intel/haswell/native_raminit/Makefile.inc | 3 +++ - .../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++ - 5 files changed, 42 insertions(+), 1 deletion(-) - create mode 100644 configs/config.asrock_b85m_pro4.native_raminit - create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c - -diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit -new file mode 100644 -index 0000000000..2de538926f ---- /dev/null -+++ b/configs/config.asrock_b85m_pro4.native_raminit -@@ -0,0 +1,5 @@ -+# Configuration used to build-test native raminit -+CONFIG_VENDOR_ASROCK=y -+CONFIG_BOARD_ASROCK_B85M_PRO4=y -+CONFIG_USE_NATIVE_RAMINIT=y -+CONFIG_DEBUG_RAM_SETUP=y -diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index 50acb09a91..b659bf6d98 100644 ---- a/src/northbridge/intel/haswell/Kconfig -+++ b/src/northbridge/intel/haswell/Kconfig -@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL - - if NORTHBRIDGE_INTEL_HASWELL - -+config USE_NATIVE_RAMINIT -+ bool "[NOT WORKING] Use native raminit" -+ default n -+ select HAVE_DEBUG_RAM_SETUP -+ help -+ Select if you want to use coreboot implementation of raminit rather than -+ MRC.bin. Currently incomplete and does not boot. -+ - config HASWELL_VBOOT_IN_BOOTBLOCK - depends on VBOOT - bool "Start verstage in bootblock" -@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE - - config DCACHE_RAM_SIZE - hex -+ default 0x40000 if USE_NATIVE_RAMINIT - default 0x10000 - help - The size of the cache-as-ram region required during bootblock -@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE - - config DCACHE_RAM_MRC_VAR_SIZE - hex -+ default 0x0 if USE_NATIVE_RAMINIT - default 0x30000 - help - The amount of cache-as-ram region required by the reference code. - - config DCACHE_BSP_STACK_SIZE - hex -+ default 0x20000 if USE_NATIVE_RAMINIT - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and -@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE - - config HAVE_MRC - bool "Add a System Agent binary" -+ depends on !USE_NATIVE_RAMINIT - help - Select this option to add a System Agent binary to - the resulting coreboot image. -@@ -82,6 +94,7 @@ config MRC_FILE - - config HASWELL_HIDE_PEG_FROM_MRC - bool "Hide PEG devices from MRC to work around hardcoded MRC behavior" -+ depends on !USE_NATIVE_RAMINIT - default y - help - If set, hides all PEG devices from MRC. This allows the iGPU -diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc -index 2d1532be05..329f1f7ffe 100644 ---- a/src/northbridge/intel/haswell/Makefile.inc -+++ b/src/northbridge/intel/haswell/Makefile.inc -@@ -19,6 +19,11 @@ romstage-y += report_platform.c - - postcar-y += memmap.c - --subdirs-y += haswell_mrc -+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -+subdirs-y += native_raminit -+ -+else -+subdirs-y += haswell_mrc -+endif - - endif -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -new file mode 100644 -index 0000000000..8cfb4fb33e ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -0,0 +1,3 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+romstage-y += raminit_native.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -new file mode 100644 -index 0000000000..1aafdf8659 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+ -+void perform_raminit(const int s3resume) -+{ -+ /* -+ * See, this function's name is a lie. There are more things to -+ * do that memory initialisation, but they are relatively easy. -+ */ -+ -+ /** TODO: Implement the required magic **/ -+ die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch b/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch similarity index 98% rename from config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch rename to config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch index b1c33328..f44eb029 100644 --- a/config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch +++ b/config/coreboot/haswell/patches/0003-haswell-NRI-Configure-initial-MC-settings.patch @@ -1,7 +1,7 @@ -From 1b0b17d85256193de825fa7ff0e04767c818f2fc Mon Sep 17 00:00:00 2001 +From 574f4965976b56f98a825dea71e919fefb2c8547 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 17:22:07 +0200 -Subject: [PATCH 13/26] haswell NRI: Configure initial MC settings +Subject: [PATCH 03/20] haswell NRI: Configure initial MC settings Program initial memory controller settings. Many of these values will be adjusted later during training. @@ -9,7 +9,7 @@ adjusted later during training. Change-Id: If33846b51cb1bab5d0458fe626e13afb1bdc900e Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 2 + + .../intel/haswell/native_raminit/Makefile.mk | 2 + .../haswell/native_raminit/configure_mc.c | 822 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 2 + .../haswell/native_raminit/raminit_native.h | 101 +++ @@ -21,10 +21,10 @@ Signed-off-by: Angel Pons create mode 100644 src/northbridge/intel/haswell/native_raminit/reg_structs.h create mode 100644 src/northbridge/intel/haswell/native_raminit/timings_refresh.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 2769e0bbb4..fc55277a65 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,8 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -38,14 +38,14 @@ index 2769e0bbb4..fc55277a65 100644 +romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c new file mode 100644 -index 0000000000..2a667b075b +index 0000000000..88249725a7 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c @@ -0,0 +1,822 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include -+#include ++#include +#include +#include +#include @@ -131,22 +131,22 @@ index 0000000000..2a667b075b + +static const uint8_t rxb_trad[2][5][4] = { + { /* Vdd low */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, 1867 MHz, 2133 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, 1867 MT/s, 2133 MT/s, */ + {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {5, 4, 4, 3}, + }, + { /* Vdd hi */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, 1867 MHz, 2133 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, 1867 MT/s, 2133 MT/s, */ + {4, 3, 3, 2}, {4, 4, 3, 2}, {5, 4, 3, 3}, {5, 4, 4, 3}, {4, 4, 3, 3}, + }, +}; + +static const uint8_t rxb_ultx[2][3][4] = { + { /* Vdd low */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, */ + {5, 6, 6, 5}, {5, 6, 6, 5}, {4, 6, 6, 6}, + }, + { /* Vdd hi */ -+ /* 1067 MHz, 1333 MHz, 1600 MHz, */ ++ /* 1067 MT/s, 1333 MT/s, 1600 MT/s, */ + {7, 6, 6, 5}, {7, 6, 6, 5}, {7, 6, 6, 6}, + }, +}; @@ -277,7 +277,7 @@ index 0000000000..2a667b075b + const int16_t coding[] = {0, -125, -62, -31, 250, 125, 62, 31}; + *best_a = 0; + *best_b = 0; -+ int16_t best_err = slope; ++ int16_t best_err = slope; + for (uint8_t b = 0; b < ARRAY_SIZE(coding); b++) { + for (uint8_t a = b; a < ARRAY_SIZE(coding); a++) { + int16_t error = slope - (coding[a] + coding[b]); @@ -865,10 +865,10 @@ index 0000000000..2a667b075b + return RAMINIT_STATUS_SUCCESS; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 5f2be980d4..3a773cfa19 100644 +index 2fea658415..fcc981ad04 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = { +@@ -22,6 +22,7 @@ static const struct task_entry cold_boot[] = { { collect_spd_info, true, "PROCSPD", }, { initialise_mpll, true, "INITMPLL", }, { convert_timings, true, "CONVTIM", }, @@ -876,7 +876,7 @@ index 5f2be980d4..3a773cfa19 100644 }; /* Return a generic stepping value to make stepping checks simpler */ -@@ -54,6 +55,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) +@@ -53,6 +54,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) ctrl->cpu = cpu_get_cpuid(); ctrl->stepping = get_stepping(ctrl->cpu); diff --git a/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch b/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch deleted file mode 100644 index 4e70407c..00000000 --- a/config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch +++ /dev/null @@ -1,615 +0,0 @@ -From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 21:56:48 +0200 -Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init - -Implement native DMI init for Haswell and Lynx Point. This is only -needed on non-ULT platforms, and only when MRC.bin is not used. - -TEST=Verify DMI initialises correctly on Asrock B85M Pro4. - -Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa -Signed-off-by: Angel Pons ---- - src/northbridge/intel/haswell/Makefile.inc | 1 + - src/northbridge/intel/haswell/early_dmi.c | 96 ++++++++++++ - src/northbridge/intel/haswell/early_pcie.c | 121 ++++++++++++++ - src/northbridge/intel/haswell/haswell.h | 3 + - .../haswell/native_raminit/raminit_native.c | 15 ++ - src/northbridge/intel/haswell/vcu_mailbox.c | 147 ++++++++++++++++++ - src/northbridge/intel/haswell/vcu_mailbox.h | 16 ++ - src/southbridge/intel/lynxpoint/Makefile.inc | 2 + - .../intel/lynxpoint/early_pch_native.c | 52 +++++++ - src/southbridge/intel/lynxpoint/pch.h | 20 ++- - 10 files changed, 472 insertions(+), 1 deletion(-) - create mode 100644 src/northbridge/intel/haswell/early_dmi.c - create mode 100644 src/northbridge/intel/haswell/early_pcie.c - create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c - create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h - create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c - -diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc -index 329f1f7ffe..df0b097296 100644 ---- a/src/northbridge/intel/haswell/Makefile.inc -+++ b/src/northbridge/intel/haswell/Makefile.inc -@@ -20,6 +20,7 @@ romstage-y += report_platform.c - postcar-y += memmap.c - - ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) -+romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c - subdirs-y += native_raminit - - else -diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c -new file mode 100644 -index 0000000000..9941242fd5 ---- /dev/null -+++ b/src/northbridge/intel/haswell/early_dmi.c -@@ -0,0 +1,96 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+ -+static void dmi_print_link_status(int loglevel) -+{ -+ const uint16_t dmilsts = dmibar_read16(DMILSTS); -+ printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f); -+} -+ -+#define RETRAIN (1 << 5) -+ -+#define LTRN (1 << 11) -+ -+static void dmi_setup_physical_layer(void) -+{ -+ /* Program DMI AFE settings, which are needed for DMI to work */ -+ peg_dmi_recipe(false, 0); -+ -+ /* Additional DMI programming steps */ -+ dmibar_setbits32(0x258, 1 << 29); -+ dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5); -+ dmibar_clrsetbits32(0x22c, 0xffff, 0x2020); -+ -+ /* Write SA reference code version */ -+ dmibar_write32(0x71c, 0x0000000f); -+ dmibar_write32(0x720, 0x01060200); -+ -+ /* We also have to bring up the PCH side of the DMI link */ -+ pch_dmi_setup_physical_layer(); -+ -+ /* Write-once settings */ -+ dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0); -+ -+ printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n"); -+ dmi_print_link_status(BIOS_DEBUG); -+ -+ /* Retrain link */ -+ dmibar_setbits16(DMILCTL, RETRAIN); -+ do {} while (dmibar_read16(DMILSTS) & LTRN); -+ dmi_print_link_status(BIOS_DEBUG); -+ -+ /* Retrain link again for DMI Gen2 speeds */ -+ dmibar_setbits16(DMILCTL, RETRAIN); -+ do {} while (dmibar_read16(DMILSTS) & LTRN); -+ dmi_print_link_status(BIOS_INFO); -+} -+ -+#define VC_ACTIVE (1U << 31) -+ -+#define VCNEGPND (1 << 1) -+ -+#define DMI_VC_CFG(vcid, tcmap) (VC_ACTIVE | ((vcid) << 24) | (tcmap)) -+ -+static void dmi_tc_vc_mapping(void) -+{ -+ printk(BIOS_DEBUG, "Programming SA DMI VC/TC mappings...\n"); -+ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ dmibar_setbits8(0xa78, 1 << 1); -+ -+ /* Each TC is mapped to one and only one VC */ -+ const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0)); -+ const u32 vc1 = DMI_VC_CFG(1, (1 << 1)); -+ const u32 vcp = DMI_VC_CFG(2, (1 << 2)); -+ const u32 vcm = DMI_VC_CFG(7, (1 << 7)); -+ dmibar_write32(DMIVC0RCTL, vc0); -+ dmibar_write32(DMIVC1RCTL, vc1); -+ dmibar_write32(DMIVCPRCTL, vcp); -+ dmibar_write32(DMIVCMRCTL, vcm); -+ -+ /* Set Extended VC Count (EVCC) to 1 if VC1 is active */ -+ dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE)); -+ -+ /* -+ * We also have to program the PCH side of the DMI link. Since both ends -+ * must use the same Virtual Channel settings, we pass them as arguments. -+ */ -+ pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm); -+ -+ printk(BIOS_DEBUG, "Waiting for SA DMI VC negotiation... "); -+ do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND); -+ do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND); -+ printk(BIOS_DEBUG, "done!\n"); -+} -+ -+void dmi_early_init(void) -+{ -+ dmi_setup_physical_layer(); -+ dmi_tc_vc_mapping(); -+} -diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c -new file mode 100644 -index 0000000000..d3940e3fac ---- /dev/null -+++ b/src/northbridge/intel/haswell/early_pcie.c -@@ -0,0 +1,121 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PEG_DEV(func) PCI_DEV(0, 1, func) -+ -+#define MAX_PEG_FUNC 3 -+ -+static void peg_dmi_unset_and_set_mask_pcicfg( -+ volatile union pci_bank *const bank, -+ const uint32_t offset, -+ const uint32_t unset_mask, -+ const uint32_t set_mask, -+ const uint32_t shift, -+ const bool valid) -+{ -+ if (!valid) -+ return; -+ -+ volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)]; -+ clrsetbits32(addr, unset_mask << shift, set_mask << shift); -+} -+ -+static void peg_dmi_unset_and_set_mask_common( -+ const bool is_peg, -+ const uint32_t offset, -+ const uint32_t unset, -+ const uint32_t set, -+ const uint32_t shift, -+ const bool valid) -+{ -+ const uint32_t unset_mask = unset << shift; -+ const uint32_t set_mask = set << shift; -+ if (is_peg) { -+ for (uint8_t i = 0; i < MAX_PEG_FUNC; i++) -+ pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask); -+ } else { -+ dmibar_clrsetbits32(offset, unset_mask, set_mask); -+ } -+} -+ -+static void peg_dmi_unset_and_set_mask_vcu_mmio( -+ const uint32_t addr, -+ const uint32_t unset_mask, -+ const uint32_t set_mask, -+ const uint32_t shift, -+ const bool valid) -+{ -+ if (!valid) -+ return; -+ -+ vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift); -+} -+ -+#define BUNDLE_STEP 0x20 -+ -+static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; -+ -+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev) -+{ -+ const bool always = true; -+ const bool is_dmi = !is_peg; -+ -+ /* Treat DMIBAR and PEG devices the same way */ -+ volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar; -+ -+ const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP; -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) { -+ /* These are actually per-lane */ -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c, 0, always); -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c, 0, always); -+ } -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02, 0, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03, 5, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09, 5, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08, 6, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always); -+ -+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg); -+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi); -+ -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always); -+ -+ peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00, 6, always); -+ peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02, 0, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg); -+ -+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) -+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg); -+} -diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h -index 1b29f6baf0..30b4abd0a7 100644 ---- a/src/northbridge/intel/haswell/haswell.h -+++ b/src/northbridge/intel/haswell/haswell.h -@@ -34,6 +34,9 @@ void haswell_early_initialization(void); - void haswell_late_initialization(void); - void haswell_unhide_peg(void); - -+void dmi_early_init(void); -+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev); -+ - void report_platform_info(void); - - struct acpi_rsdp; -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 1aafdf8659..0938e026e3 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,7 +1,19 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include -+#include - #include -+#include -+ -+static bool early_init_native(int s3resume) -+{ -+ printk(BIOS_DEBUG, "Starting native platform initialisation\n"); -+ -+ if (!CONFIG(INTEL_LYNXPOINT_LP)) -+ dmi_early_init(); -+ -+ return false; -+} - - void perform_raminit(const int s3resume) - { -@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume) - * See, this function's name is a lie. There are more things to - * do that memory initialisation, but they are relatively easy. - */ -+ const bool cpu_replaced = early_init_native(s3resume); -+ -+ (void)cpu_replaced; - - /** TODO: Implement the required magic **/ - die("NATIVE RAMINIT: More Magic (tm) required.\n"); -diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c -new file mode 100644 -index 0000000000..aead144023 ---- /dev/null -+++ b/src/northbridge/intel/haswell/vcu_mailbox.c -@@ -0,0 +1,147 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * This is a library for the VCU (Validation Control Unit) mailbox. This -+ * mailbox is primarily used to adjust some magic PCIe tuning parameters. -+ * -+ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell -+ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs -+ * are early Engineering Samples with undocumented errata, and most likely -+ * need special microcode updates to boot. Thus, the code does not support -+ * VCU mailbox Rev1, because no one should need it anymore. -+ */ -+ -+#define VCU_MAILBOX_INTERFACE 0x6c00 -+#define VCU_MAILBOX_DATA 0x6c04 -+ -+#define VCU_RUN_BUSY (1 << 31) -+ -+enum vcu_opcode { -+ VCU_OPCODE_READ_VCU_API_VER_ID = 0x01, -+ VCU_OPCODE_OPEN_SEQ = 0x02, -+ VCU_OPCODE_CLOSE_SEQ = 0x03, -+ VCU_OPCODE_READ_DATA = 0x07, -+ VCU_OPCODE_WRITE_DATA = 0x08, -+ VCU_OPCODE_READ_CSR = 0x13, -+ VCU_OPCODE_WRITE_CSR = 0x14, -+ VCU_OPCODE_READ_MMIO = 0x15, -+ VCU_OPCODE_WRITE_MMIO = 0x16, -+}; -+ -+enum vcu_sequence { -+ SEQ_ID_READ_CSR = 0x1, -+ SEQ_ID_WRITE_CSR = 0x2, -+ SEQ_ID_READ_MMIO = 0x3, -+ SEQ_ID_WRITE_MMIO = 0x4, -+}; -+ -+#define VCU_RESPONSE_MASK 0xffff -+#define VCU_RESPONSE_SUCCESS 0x40 -+#define VCU_RESPONSE_BUSY 0x80 -+#define VCU_RESPONSE_THREAD_UNAVAILABLE 0x82 -+#define VCU_RESPONSE_ILLEGAL 0x90 -+ -+/* FIXME: Use timer API */ -+static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data) -+{ -+ for (unsigned int i = 0; i < 10; i++) { -+ mchbar_write32(VCU_MAILBOX_DATA, data); -+ mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY); -+ uint32_t vcu_interface; -+ for (unsigned int j = 0; j < 100; j++) { -+ vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE); -+ if (!(vcu_interface & VCU_RUN_BUSY)) -+ break; -+ -+ udelay(10); -+ } -+ if (vcu_interface & VCU_RUN_BUSY) -+ continue; -+ -+ if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS) -+ return; -+ } -+ printk(BIOS_ERR, "VCU: Failed to send command\n"); -+} -+ -+static enum vcu_opcode get_register_opcode(enum vcu_sequence seq) -+{ -+ switch (seq) { -+ case SEQ_ID_READ_CSR: -+ return VCU_OPCODE_READ_CSR; -+ case SEQ_ID_WRITE_CSR: -+ return VCU_OPCODE_WRITE_CSR; -+ case SEQ_ID_READ_MMIO: -+ return VCU_OPCODE_READ_MMIO; -+ case SEQ_ID_WRITE_MMIO: -+ return VCU_OPCODE_WRITE_MMIO; -+ default: -+ return dead_code_t(enum vcu_opcode); -+ } -+} -+ -+static enum vcu_opcode get_data_opcode(enum vcu_sequence seq) -+{ -+ switch (seq) { -+ case SEQ_ID_READ_CSR: -+ case SEQ_ID_READ_MMIO: -+ return VCU_OPCODE_READ_DATA; -+ case SEQ_ID_WRITE_CSR: -+ case SEQ_ID_WRITE_MMIO: -+ return VCU_OPCODE_WRITE_DATA; -+ default: -+ return dead_code_t(enum vcu_opcode); -+ } -+} -+ -+static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data) -+{ -+ send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq); -+ -+ send_vcu_command(get_register_opcode(seq), addr); -+ -+ send_vcu_command(get_data_opcode(seq), wr_data); -+ -+ const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA); -+ -+ send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq); -+ -+ return rd_data; -+} -+ -+uint32_t vcu_read_csr(uint32_t addr) -+{ -+ return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0); -+} -+ -+void vcu_write_csr(uint32_t addr, uint32_t data) -+{ -+ send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data); -+} -+ -+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue) -+{ -+ vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue); -+} -+ -+uint32_t vcu_read_mmio(uint32_t addr) -+{ -+ return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0); -+} -+ -+void vcu_write_mmio(uint32_t addr, uint32_t data) -+{ -+ send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data); -+} -+ -+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue) -+{ -+ vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue); -+} -diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h -new file mode 100644 -index 0000000000..ba0a62e486 ---- /dev/null -+++ b/src/northbridge/intel/haswell/vcu_mailbox.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef HASWELL_VCU_MAILBOX_H -+#define HASWELL_VCU_MAILBOX_H -+ -+#include -+ -+uint32_t vcu_read_csr(uint32_t addr); -+void vcu_write_csr(uint32_t addr, uint32_t data); -+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue); -+ -+uint32_t vcu_read_mmio(uint32_t addr); -+void vcu_write_mmio(uint32_t addr, uint32_t data); -+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue); -+ -+#endif /* HASWELL_VCU_MAILBOX_H */ -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index 02022d348d..b8503ac8bc 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,6 +37,8 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c -+ - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c - ramstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c -new file mode 100644 -index 0000000000..c28ddfcf5d ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c -@@ -0,0 +1,52 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+ -+void pch_dmi_setup_physical_layer(void) -+{ -+ /* FIXME: We need to make sure the SA supports Gen2 as well */ -+ if ((RCBA32(0x21a4) & 0x0f) == 0x02) { -+ /* Set Gen 2 Common Clock N_FTS */ -+ RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16); -+ -+ /* Set Target Link Speed to DMI Gen2 */ -+ RCBA8_AND_OR(DLCTL2, ~0x07, 0x02); -+ } -+} -+ -+#define VC_ACTIVE (1U << 31) -+ -+#define VCNEGPND (1 << 1) -+ -+void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) -+{ -+ printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n"); -+ -+ RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20); -+ if (vcp & VC_ACTIVE) -+ RCBA32_OR(CIR0050, 1 << 19 | 1 << 17); -+ -+ RCBA32(CIR0050); /* Posted Write */ -+ -+ /* Use the same virtual channel mapping on both ends of the DMI link */ -+ RCBA32(V0CTL) = vc0; -+ RCBA32(V1CTL) = vc1; -+ RCBA32(V1CTL); /* Posted Write */ -+ RCBA32(VPCTL) = vcp; -+ RCBA32(VPCTL); /* Posted Write */ -+ RCBA32(VMCTL) = vcm; -+ -+ /* Lock the registers */ -+ RCBA32_OR(CIR0050, 1U << 31); -+ RCBA32(CIR0050); /* Posted Write */ -+ -+ printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... "); -+ do {} while (RCBA16(V0STS) & VCNEGPND); -+ do {} while (RCBA16(V1STS) & VCNEGPND); -+ do {} while (RCBA16(VPSTS) & VCNEGPND); -+ do {} while (RCBA16(VMSTS) & VCNEGPND); -+ printk(BIOS_DEBUG, "done!\n"); -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 7d9fc6d6af..b5e0c2a830 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -113,6 +113,9 @@ enum pch_platform_type { - PCH_TYPE_ULT = 5, - }; - -+void pch_dmi_setup_physical_layer(void); -+void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); -+ - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); - void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -@@ -406,9 +409,10 @@ void mainboard_config_rcba(void); - - /* Southbridge IO BARs */ - -+#define PMBASE 0x40 - #define GPIOBASE 0x48 - --#define PMBASE 0x40 -+#define CIR0050 0x0050 /* 32bit */ - - #define RPC 0x0400 /* 32bit */ - #define RPFN 0x0404 /* 32bit */ -@@ -431,6 +435,20 @@ void mainboard_config_rcba(void); - #define IOTR2 0x1e90 /* 64bit */ - #define IOTR3 0x1e98 /* 64bit */ - -+#define V0CTL 0x2014 /* 32bit */ -+#define V0STS 0x201a /* 16bit */ -+ -+#define V1CTL 0x2020 /* 32bit */ -+#define V1STS 0x2026 /* 16bit */ -+ -+#define VPCTL 0x2030 /* 32bit */ -+#define VPSTS 0x2038 /* 16bit */ -+ -+#define VMCTL 0x2040 /* 32bit */ -+#define VMSTS 0x2048 /* 16bit */ -+ -+#define DLCTL2 0x21b0 -+ - #define TCTL 0x3000 /* 8bit */ - - #define NOINT 0 --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch b/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch similarity index 98% rename from config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch rename to config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch index 1b88f350..74c21227 100644 --- a/config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch +++ b/config/coreboot/haswell/patches/0004-haswell-NRI-Add-timings-refresh-programming.patch @@ -1,7 +1,7 @@ -From b64d728bfe7c8ee44af252338257e95d87864659 Mon Sep 17 00:00:00 2001 +From d94843c7c0e25cb6da4040b845556034fdb0e2c3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 20:59:58 +0200 -Subject: [PATCH 14/26] haswell NRI: Add timings/refresh programming +Subject: [PATCH 04/20] haswell NRI: Add timings/refresh programming Program the registers with timing and refresh parameters. @@ -16,7 +16,7 @@ Signed-off-by: Angel Pons 5 files changed, 452 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c -index 038686c844..afe2c615d2 100644 +index 8b81c7c341..b8d6c1ef40 100644 --- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c +++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c @@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz) @@ -262,14 +262,14 @@ index d11cda4b3d..70487e1640 100644 struct __packed { uint32_t enable_cmd_limit : 1; // Bits 0:0 diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c -index a9d960f31b..20a05b359b 100644 +index a9d960f31b..54fee0121d 100644 --- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c +++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c @@ -1,13 +1,242 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include -+#include ++#include +#include +#include +#include @@ -458,7 +458,7 @@ index a9d960f31b..20a05b359b 100644 { - /** TODO: Stub **/ + if (ctrl->lpddr) -+ die("%s: Missing support for LPDDR\n"); ++ die("%s: Missing support for LPDDR\n", __func__); + + const uint8_t odt_stretch = get_odt_stretch(ctrl); + const union tc_bank_reg tc_bank = make_tc_bank(ctrl); diff --git a/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch b/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch deleted file mode 100644 index 28dbc02a..00000000 --- a/config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 22:18:21 +0200 -Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init - -Implement native early ME init for Lynx Point. This is only needed when -MRC.bin is not used. - -Change-Id: If416e2078f139f26b4742c564b70e018725bf003 -Signed-off-by: Angel Pons ---- - .../haswell/native_raminit/raminit_native.c | 17 ++++++++++- - src/southbridge/intel/lynxpoint/early_me.c | 30 ++++++++++++++++++- - src/southbridge/intel/lynxpoint/me.h | 7 +++-- - 3 files changed, 50 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 0938e026e3..6a002548c1 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,18 +1,24 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include -+#include - #include - #include -+#include - #include - - static bool early_init_native(int s3resume) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); - -+ intel_early_me_init(); -+ /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ -+ const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); -+ - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); - -- return false; -+ return cpu_replaced; - } - - void perform_raminit(const int s3resume) -@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume) - - (void)cpu_replaced; - -+ /** TODO: Move after raminit */ -+ if (intel_early_me_uma_size() > 0) { -+ /** TODO: Update status once raminit is implemented **/ -+ uint8_t me_status = ME_INIT_STATUS_ERROR; -+ intel_early_me_init_done(me_status); -+ } -+ -+ intel_early_me_status(); -+ - /** TODO: Implement the required magic **/ - die("NATIVE RAMINIT: More Magic (tm) required.\n"); - } -diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c -index 947c570e16..07013c5539 100644 ---- a/src/southbridge/intel/lynxpoint/early_me.c -+++ b/src/southbridge/intel/lynxpoint/early_me.c -@@ -1,11 +1,12 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ - - #include -+#include - #include - #include - #include - #include -- -+#include - #include "me.h" - #include "pch.h" - -@@ -60,6 +61,33 @@ int intel_early_me_init(void) - return 0; - } - -+bool intel_early_me_cpu_replacement_check(void) -+{ -+ printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... "); -+ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 50); -+ -+ union me_hfs2 hfs2; -+ do { -+ hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2); -+ if (stopwatch_expired(&timer)) { -+ /* Assume CPU was replaced just in case */ -+ printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n"); -+ return true; -+ } -+ udelay(ME_DELAY); -+ } while (!hfs2.cpu_replaced_valid); -+ -+ if (hfs2.warm_reset_request) { -+ printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n"); -+ system_reset(); -+ } -+ -+ printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not "); -+ return hfs2.cpu_replaced_sts; -+} -+ - int intel_early_me_uma_size(void) - { - union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) }; -diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h -index fe8b0260c4..6990322651 100644 ---- a/src/southbridge/intel/lynxpoint/me.h -+++ b/src/southbridge/intel/lynxpoint/me.h -@@ -177,14 +177,16 @@ union me_did { - union me_hfs2 { - struct __packed { - u32 bist_in_progress: 1; -- u32 reserved1: 2; -+ u32 icc_prog_sts: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; -- u32 reserved2: 4; -+ u32 reserved: 2; -+ u32 fw_upd_ipu: 1; -+ u32 reserved2: 1; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; -@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); - - void intel_early_me_status(void); - int intel_early_me_init(void); -+bool intel_early_me_cpu_replacement_check(void); - int intel_early_me_uma_size(void); - int intel_early_me_init_done(u8 status); - --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch b/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch similarity index 95% rename from config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch rename to config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch index ad8527b2..e095417c 100644 --- a/config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch +++ b/config/coreboot/haswell/patches/0005-haswell-NRI-Program-memory-map.patch @@ -1,7 +1,7 @@ -From 89ff35083af68d1b24c1633886202ecc153af67d Mon Sep 17 00:00:00 2001 +From b872fb9fc10d1789989072b8533b797152e6cb54 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 21:24:50 +0200 -Subject: [PATCH 15/26] haswell NRI: Program memory map +Subject: [PATCH 05/20] haswell NRI: Program memory map This is very similar to Sandy/Ivy Bridge, except that there's several registers to program in GDXCBAR. One of these GDXCBAR registers has a @@ -12,7 +12,7 @@ bit was the only reason why native raminit did not work. Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 1 + @@ -20,10 +20,10 @@ Signed-off-by: Angel Pons 5 files changed, 188 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index fc55277a65..37d527e972 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += configure_mc.c romstage-y += lookup_timings.c romstage-y += init_mpll.c @@ -222,10 +222,10 @@ index 0000000000..e3aded2b37 + return 0; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 3a773cfa19..136a8ba989 100644 +index fcc981ad04..559dfc3a4e 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = { +@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = { { initialise_mpll, true, "INITMPLL", }, { convert_timings, true, "CONVTIM", }, { configure_mc, true, "CONFMC", }, diff --git a/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch b/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch deleted file mode 100644 index d9c2570b..00000000 --- a/config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch +++ /dev/null @@ -1,783 +0,0 @@ -From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 23:17:39 +0200 -Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init - -Implement native USB initialisation for Lynx Point. This is only needed -when MRC.bin is not used. - -TO DO: Figure out how to deal with the FIXME's and TODO's lying around. - -Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373 -Signed-off-by: Angel Pons ---- - .../haswell/native_raminit/raminit_native.c | 3 + - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- - src/southbridge/intel/lynxpoint/early_usb.c | 11 - - .../intel/lynxpoint/early_usb_native.c | 584 ++++++++++++++++++ - src/southbridge/intel/lynxpoint/pch.h | 49 ++ - 5 files changed, 637 insertions(+), 12 deletions(-) - create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 6a002548c1..ef61d4ee09 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -5,6 +5,7 @@ - #include - #include - #include -+#include - #include - - static bool early_init_native(int s3resume) -@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -+ early_usb_init(); -+ - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); - -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index b8503ac8bc..0e1f2fe4eb 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,7 +37,7 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - --romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c -index a753681ce0..52e8ac17f8 100644 ---- a/src/southbridge/intel/lynxpoint/early_usb.c -+++ b/src/southbridge/intel/lynxpoint/early_usb.c -@@ -4,17 +4,6 @@ - #include - #include "pch.h" - --/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index -- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. -- */ --#if CONFIG_USBDEBUG_HCD_INDEX != 2 --#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR --#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) --#else --#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR --#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) --#endif -- - /* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. -diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c -new file mode 100644 -index 0000000000..cb6f6ee8e6 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/early_usb_native.c -@@ -0,0 +1,584 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static unsigned int is_usbr_enabled(void) -+{ -+ return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5)); -+} -+ -+static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0; -+ -+static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar) -+{ -+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar); -+ -+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/ -+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ -+ char *const mem_bar = (char *)ehci_bar; -+ -+ /** -+ * Shared EHCI/XHCI ports w/a. -+ * This step is required when some of the ports are routed to EHCI -+ * and other ports are routed XHCI at the same time. -+ * -+ * FIXME: Under which conditions should this be done? -+ */ -+ pci_and_config16(dev, 0x78, ~0x03); -+ -+ /* Skip reset if usbdebug is enabled */ -+ if (!CONFIG(USBDEBUG_IN_PRE_RAM)) -+ setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET); -+ -+ /* 2: Configure number of controllers and ports */ -+ pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE); -+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0); -+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 0, 2 + is_usbr_enabled()); -+ pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE); -+ -+ pci_or_config16(dev, 0x78, BIT(2)); -+ pci_or_config16(dev, 0x7c, BIT(14) | BIT(7)); -+ pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8)); -+ pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17)); -+} -+ -+static inline unsigned int physical_port_count(void) -+{ -+ return MAX_USB2_PORTS; -+} -+ -+static unsigned int hs_port_count(void) -+{ -+ /** TODO: Apparently, WPT-LP has 10 USB2 ports **/ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ return 8; -+ -+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) { -+ case 3: -+ return 8; -+ case 2: -+ return 10; -+ case 1: -+ return 12; -+ case 0: -+ default: -+ return 14; -+ } -+} -+ -+static unsigned int ss_port_count(void) -+{ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) -+ return 4; -+ -+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) { -+ case 3: -+ return 0; -+ case 2: -+ return 2; -+ case 1: -+ return 4; -+ case 0: -+ default: -+ return 6; -+ } -+} -+ -+static void common_ehci_hcs_init(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); -+ if (!is_lp) -+ ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); -+ -+ pch_iobp_update(0xe5007f04, 0, 0x00004481); -+ -+ for (unsigned int port = 0; port < physical_port_count(); port++) -+ pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0); -+ -+ pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19)); -+ -+ if (is_lp) -+ pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22)); -+} -+ -+static void xhci_open_memory_space(void) -+{ -+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/ -+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar); -+ pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+} -+ -+static void xhci_close_memory_space(void) -+{ -+ pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); -+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0); -+} -+ -+static void common_xhci_hc_init(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ if (!is_lp) { -+ const unsigned int max_ports = 15 + ss_port_count(); -+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28); -+ } -+ -+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a); -+ clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9)); -+ -+ if (!is_lp) -+ clrsetbits32(xhci_bar + 0x8008, BIT(19), 0); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16)); -+ else -+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20)); -+ -+ clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18)); -+ clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8)); -+ clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14)); -+ clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6)); -+ clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9)); -+ clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25)); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11)); -+ else -+ clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11)); -+ -+ if (is_lp) -+ write32(xhci_bar + 0x8140, 0xff00f03c); -+ else -+ write32(xhci_bar + 0x8140, 0xff03c132); -+ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13)); -+ else -+ clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0); -+ -+ clrsetbits32(xhci_bar + 0x8154, BIT(3), 0); -+ -+ if (is_lp) { -+ clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0)); -+ write32(xhci_bar + 0x8174, 0x01400c0a); -+ write32(xhci_bar + 0x817c, 0x033200a3); -+ write32(xhci_bar + 0x8180, 0x00cb0028); -+ write32(xhci_bar + 0x8184, 0x0064001e); -+ } -+ -+ /* -+ * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once. -+ * We use these weird partial accesses here to avoid locking bit 31. -+ */ -+ pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0)); -+ pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f); -+ -+ /* LPT-LP >= B0 */ -+ if (is_lp) -+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24)); -+ -+ /* LPT-H >= C0 */ -+ if (!is_lp) -+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(24)); -+} -+ -+static inline bool is_mem_sr(void) -+{ -+ return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR; -+} -+ -+static bool should_restore_xhci_smart_auto(void) -+{ -+ if (!is_mem_sr()) -+ return false; -+ -+ return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO; -+} -+ -+enum usb_port_route { -+ ROUTE_TO_EHCI, -+ ROUTE_TO_XHCI, -+}; -+ -+/* Returns whether port reset was successful */ -+static bool reset_usb2_ports(const unsigned int ehci_ports) -+{ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ /* Initiate port reset for all USB2 ports */ -+ clrsetbits32( -+ xhci_bar + XHCI_USB2_PORTSC(port), -+ XHCI_USB2_PORTSC_PED, -+ XHCI_USB2_PORTSC_PR); -+ } -+ /* Poll for port reset bit to be cleared or time out at 100ms */ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 100); -+ uint32_t reg32; -+ do { -+ reg32 = 0; -+ for (unsigned int port = 0; port < ehci_ports; port++) -+ reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port)); -+ -+ reg32 &= XHCI_USB2_PORTSC_PR; -+ if (!reg32) { -+ const long elapsed_time = stopwatch_duration_usecs(&timer); -+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time); -+ return true; -+ } -+ /* Reference code has a 10 ms delay here, but a smaller delay works too */ -+ udelay(100); -+ } while (!stopwatch_expired(&timer)); -+ printk(BIOS_ERR, "%s: timed out\n", __func__); -+ return !reg32; -+} -+ -+/* Returns whether warm reset was successful */ -+static bool warm_reset_usb3_ports(const unsigned int xhci_ports) -+{ -+ for (unsigned int port = 0; port < xhci_ports; port++) { -+ /* Initiate warm reset for all USB3 ports */ -+ clrsetbits32( -+ xhci_bar + XHCI_USB3_PORTSC(port), -+ XHCI_USB3_PORTSC_PED, -+ XHCI_USB3_PORTSC_WPR); -+ } -+ /* Poll for port reset bit to be cleared or time out at 100ms */ -+ struct stopwatch timer; -+ stopwatch_init_msecs_expire(&timer, 100); -+ uint32_t reg32; -+ do { -+ reg32 = 0; -+ for (unsigned int port = 0; port < xhci_ports; port++) -+ reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port)); -+ -+ reg32 &= XHCI_USB3_PORTSC_PR; -+ if (!reg32) { -+ const long elapsed_time = stopwatch_duration_usecs(&timer); -+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time); -+ return true; -+ } -+ /* Reference code has a 10 ms delay here, but a smaller delay works too */ -+ udelay(100); -+ } while (!stopwatch_expired(&timer)); -+ printk(BIOS_ERR, "%s: timed out\n", __func__); -+ return !reg32; -+} -+ -+static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route) -+{ -+ const pci_devfn_t dev = PCH_XHCI_DEV; -+ -+ const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled(); -+ const unsigned int xhci_ports = ss_port_count(); -+ -+ const uint32_t ehci_mask = BIT(ehci_ports) - 1; -+ const uint32_t xhci_mask = BIT(xhci_ports) - 1; -+ -+ /** TODO: Handle USBr port? How, though? **/ -+ pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask); -+ pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN, xhci_mask); -+ -+ /* -+ * Workaround for USB2PR / USB3PR value not surviving warm reset. -+ * Restore USB Port Routing registers if OS HC Switch driver has been executed. -+ */ -+ if (should_restore_xhci_smart_auto()) { -+ /** FIXME: Derive values from mainboard code instead? **/ -+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask); -+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_mask); -+ } -+ -+ /* Later stages shouldn't need the value of this bit */ -+ pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO); -+ -+ /** -+ * FIXME: Things here depend on the chosen routing mode. -+ * For now, implement both functions. -+ */ -+ -+ /* Route to EHCI if xHCI disabled or auto mode */ -+ if (usb_route == ROUTE_TO_EHCI) { -+ if (!reset_usb2_ports(ehci_ports)) -+ printk(BIOS_ERR, "USB2 port reset timed out\n"); -+ -+ pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL); -+ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ clrsetbits32( -+ xhci_bar + XHCI_USB2_PORTSC(port), -+ XHCI_USB2_PORTSC_PED, -+ XHCI_USB2_PORTSC_CHST); -+ } -+ -+ if (!warm_reset_usb3_ports(xhci_ports)) -+ printk(BIOS_ERR, "USB3 warm reset timed out\n"); -+ -+ /* FIXME: BWG says this should be inside the warm reset function */ -+ pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN); -+ -+ for (unsigned int port = 0; port < ehci_ports; port++) { -+ clrsetbits32( -+ xhci_bar + XHCI_USB3_PORTSC(port), -+ XHCI_USB3_PORTSC_PED, -+ XHCI_USB3_PORTSC_CHST); -+ } -+ -+ setbits32(xhci_bar + XHCI_USBCMD, BIT(0)); -+ clrbits32(xhci_bar + XHCI_USBCMD, BIT(0)); -+ } -+ -+ /* Route to xHCI if xHCI enabled */ -+ if (usb_route == ROUTE_TO_XHCI) { -+ if (is_mem_sr()) { -+ if (!warm_reset_usb3_ports(xhci_ports)) -+ printk(BIOS_ERR, "USB3 warm reset timed out\n"); -+ } -+ -+ const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f; -+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask); -+ -+ const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff; -+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask); -+ } -+} -+ -+/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */ -+#define PORT_TO_OC_SHIFT(port, oc) ((oc) * 8 + (port)) -+ -+/* Avoid shifting into undefined behaviour */ -+static inline bool shift_ok(const int shift) -+{ -+ return shift >= 0 && shift < 32; -+} -+ -+static void usb_overcurrent_mapping(void) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ uint32_t ehci_1_ocmap = 0; -+ uint32_t ehci_2_ocmap = 0; -+ uint32_t xhci_1_ocmap = 0; -+ uint32_t xhci_2_ocmap = 0; -+ -+ /* -+ * EHCI -+ */ -+ for (unsigned int idx = 0; idx < physical_port_count(); idx++) { -+ const struct usb2_port_config *const port = &mainboard_usb2_ports[idx]; -+ printk(BIOS_DEBUG, "USB2 port %u => ", idx); -+ if (!port->enable) { -+ printk(BIOS_DEBUG, "disabled\n"); -+ continue; -+ } -+ const unsigned short oc_pin = port->oc_pin; -+ if (oc_pin == USB_OC_PIN_SKIP) { -+ printk(BIOS_DEBUG, "not mapped to OC pin\n"); -+ continue; -+ } -+ /* Ports 0 .. 7 => OC 0 .. 3 */ -+ if (idx < 8 && oc_pin <= 3) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ ehci_1_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ /* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */ -+ if (!is_lp && idx >= 8 && oc_pin >= 4) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ ehci_2_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx); -+ } -+ printk(BIOS_DEBUG, "\n"); -+ pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap); -+ if (!is_lp) -+ pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap); -+ -+ /* -+ * xHCI -+ */ -+ for (unsigned int idx = 0; idx < ss_port_count(); idx++) { -+ const struct usb3_port_config *const port = &mainboard_usb3_ports[idx]; -+ printk(BIOS_DEBUG, "USB3 port %u => ", idx); -+ if (!port->enable) { -+ printk(BIOS_DEBUG, "disabled\n"); -+ continue; -+ } -+ const unsigned short oc_pin = port->oc_pin; -+ if (oc_pin == USB_OC_PIN_SKIP) { -+ printk(BIOS_DEBUG, "not mapped to OC pin\n"); -+ continue; -+ } -+ /* Ports 0 .. 5 => OC 0 .. 3 */ -+ if (oc_pin <= 3) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ xhci_1_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ /* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */ -+ if (!is_lp && oc_pin >= 4) { -+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4); -+ if (shift_ok(shift)) { -+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin); -+ xhci_2_ocmap |= 1 << shift; -+ continue; -+ } -+ } -+ printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx); -+ } -+ printk(BIOS_DEBUG, "\n"); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap); -+ if (!is_lp) { -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap); -+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap); -+ } -+} -+ -+static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ const enum pch_platform_type plat_type = get_pch_platform_type(); -+ const enum usb2_port_location location = port->location; -+ const uint16_t length = port->length; -+ if (!is_lp) { -+ if (plat_type == PCH_TYPE_DESKTOP) { -+ if (location == USB_PORT_BACK_PANEL) -+ return 4; /* Back Panel */ -+ else -+ return 3; /* Front Panel */ -+ -+ } else if (plat_type == PCH_TYPE_MOBILE) { -+ if (location == USB_PORT_INTERNAL) -+ return 5; /* Internal Topology */ -+ else if (location == USB_PORT_DOCK) -+ return 4; /* Dock */ -+ else if (length < 0x70) -+ return 5; /* Back Panel, less than 7" */ -+ else -+ return 6; /* Back Panel, 7" or more */ -+ } -+ } else { -+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) { -+ if (length < 0x70) -+ return 5; /* Back Panel, less than 7" */ -+ else -+ return 6; /* Back Panel, 7" or more */ -+ } else if (location == USB_PORT_DOCK) { -+ return 4; /* Dock */ -+ } else { -+ return 5; /* Internal Topology */ -+ } -+ } -+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__); -+ return 0; -+} -+ -+static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port) -+{ -+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP); -+ -+ const enum pch_platform_type plat_type = get_pch_platform_type(); -+ const enum usb2_port_location location = port->location; -+ const uint16_t length = port->length; -+ if (!is_lp) { -+ if (plat_type == PCH_TYPE_DESKTOP) { -+ if (location == USB_PORT_BACK_PANEL) { -+ if (length < 0x80) -+ return 2; /* Back Panel, less than 8" */ -+ else if (length < 0x130) -+ return 3; /* Back Panel, 8"-13" */ -+ else -+ return 4; /* Back Panel, 13" or more */ -+ } else { -+ return 2; /* Front Panel */ -+ } -+ -+ } else if (plat_type == PCH_TYPE_MOBILE) { -+ if (location == USB_PORT_INTERNAL) { -+ return 2; /* Internal Topology */ -+ } else if (location == USB_PORT_DOCK) { -+ if (length < 0x50) -+ return 1; /* Dock, less than 5" */ -+ else -+ return 2; /* Dock, 5" or more */ -+ } else { -+ if (length < 0x100) -+ return 2; /* Back Panel, less than 10" */ -+ else -+ return 3; /* Back Panel, 10" or more */ -+ } -+ } -+ } else { -+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) { -+ if (length < 0x100) -+ return 2; /* Back Panel, less than 10" */ -+ else -+ return 3; /* Back Panel, 10" or more */ -+ } else if (location == USB_PORT_DOCK) { -+ if (length < 0x50) -+ return 1; /* Dock, less than 5" */ -+ else -+ return 2; /* Dock, 5" or more */ -+ } else { -+ return 2; /* Internal Topology */ -+ } -+ } -+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__); -+ return 0; -+} -+ -+static void program_ehci_port_length(void) -+{ -+ for (unsigned int port = 0; port < physical_port_count(); port++) { -+ if (!mainboard_usb2_ports[port].enable) -+ continue; -+ const uint32_t addr = 0xe5004000 + (port + 1) * 0x100; -+ const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]); -+ const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]); -+ pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8); -+ } -+} -+ -+void early_usb_init(void) -+{ -+ /** TODO: Make this configurable? How do the modes affect usbdebug? **/ -+ const enum usb_port_route usb_route = ROUTE_TO_XHCI; -+ ///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI; -+ -+ common_ehci_hcs_init(); -+ xhci_open_memory_space(); -+ common_xhci_hc_init(); -+ perform_xhci_ehci_switching_flow(usb_route); -+ usb_overcurrent_mapping(); -+ program_ehci_port_length(); -+ /** FIXME: USB per port control is missing, is it needed? **/ -+ xhci_close_memory_space(); -+ /** TODO: Close EHCI memory space? **/ -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index b5e0c2a830..ad983d86cf 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -115,6 +115,7 @@ enum pch_platform_type { - - void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); -+void early_usb_init(void); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -@@ -202,6 +203,8 @@ void mainboard_config_rcba(void); - #define GEN_PMCON_1 0xa0 - #define SMI_LOCK (1 << 4) - #define GEN_PMCON_2 0xa2 -+#define GEN_PMCON_2_DISB (1 << 7) -+#define GEN_PMCON_2_MEM_SR (1 << 5) - #define SYSTEM_RESET_STS (1 << 4) - #define THERMTRIP_STS (1 << 3) - #define SYSPWR_FLR (1 << 1) -@@ -215,6 +218,7 @@ void mainboard_config_rcba(void); - #define PMIR 0xac - #define PMIR_CF9LOCK (1 << 31) - #define PMIR_CF9GR (1 << 20) -+#define PMIR_XHCI_SMART_AUTO (1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */ - - /* GEN_PMCON_3 bits */ - #define RTC_BATTERY_DEAD (1 << 2) -@@ -282,6 +286,20 @@ void mainboard_config_rcba(void); - #define SATA_DTLE_DATA_SHIFT 24 - #define SATA_DTLE_EDGE_SHIFT 16 - -+/* -+ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index -+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. -+ */ -+#if CONFIG_USBDEBUG_HCD_INDEX != 2 -+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR -+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) -+#else -+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR -+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) -+#endif -+ -+#define PCH_XHCI_TEMP_BAR0 0xe8100000 -+ - /* EHCI PCI Registers */ - #define EHCI_PWR_CTL_STS 0x54 - #define PWR_CTL_SET_MASK 0x3 -@@ -289,10 +307,15 @@ void mainboard_config_rcba(void); - #define PWR_CTL_SET_D3 0x3 - #define PWR_CTL_ENABLE_PME (1 << 8) - #define PWR_CTL_STATUS_PME (1 << 15) -+#define EHCI_OCMAP 0x74 -+#define EHCI_ACCESS_CNTL 0x80 -+#define ACCESS_CNTL_ENABLE (1 << 0) - - /* EHCI Memory Registers */ -+#define EHCI_HCS_PARAMS 0x04 - #define EHCI_USB_CMD 0x20 - #define EHCI_USB_CMD_RUN (1 << 0) -+#define EHCI_USB_CMD_HCRESET (1 << 1) - #define EHCI_USB_CMD_PSE (1 << 4) - #define EHCI_USB_CMD_ASE (1 << 5) - #define EHCI_PORTSC(port) (0x64 + (port) * 4) -@@ -301,6 +324,10 @@ void mainboard_config_rcba(void); - - /* XHCI PCI Registers */ - #define XHCI_PWR_CTL_STS 0x74 -+#define XHCI_U2OCM1 0xc0 -+#define XHCI_U2OCM2 0xc4 -+#define XHCI_U3OCM1 0xc8 -+#define XHCI_U3OCM2 0xcc - #define XHCI_USB2PR 0xd0 - #define XHCI_USB2PRM 0xd4 - #define XHCI_USB2PR_HCSEL 0x7fff -@@ -313,6 +340,27 @@ void mainboard_config_rcba(void); - #define XHCI_USB3PDO 0xe8 - - /* XHCI Memory Registers */ -+#define XHCI_HCS_PARAMS_1 0x04 -+#define XHCI_HCS_PARAMS_2 0x08 -+#define XHCI_HCS_PARAMS_3 0x0c -+#define XHCI_HCC_PARAMS 0x10 -+#define XHCI_USBCMD 0x80 -+#define XHCI_USB2_PORTSC(port) (0x480 + ((port) * 0x10)) -+#define XHCI_USB2_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -+#define XHCI_USB2_PORTSC_CEC (1 << 23) /* Port Config Error Change */ -+#define XHCI_USB2_PORTSC_PLC (1 << 22) /* Port Link State Change */ -+#define XHCI_USB2_PORTSC_PRC (1 << 21) /* Port Reset Change */ -+#define XHCI_USB2_PORTSC_OCC (1 << 20) /* Over-current Change */ -+#define XHCI_USB2_PORTSC_WRC (1 << 19) /* Warm Port Reset Change */ -+#define XHCI_USB2_PORTSC_PEC (1 << 18) /* Port Enabled Disabled Change */ -+#define XHCI_USB2_PORTSC_CSC (1 << 17) /* Connect Status Change */ -+#define XHCI_USB2_PORTSC_CHST (0x7f << 17) -+#define XHCI_USB2_PORTSC_LWS (1 << 16) /* Port Link State Write Strobe */ -+#define XHCI_USB2_PORTSC_PP (1 << 9) -+#define XHCI_USB2_PORTSC_PR (1 << 4) /* Port Reset */ -+#define XHCI_USB2_PORTSC_PED (1 << 1) /* Port Enable/Disabled */ -+#define XHCI_USB2_PORTSC_CCS (1 << 0) /* Current Connect Status */ -+ - #define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10)) - #define XHCI_USB3_PORTSC_CHST (0x7f << 17) - #define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -@@ -320,6 +368,7 @@ void mainboard_config_rcba(void); - #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ - #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ - #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -+#define XHCI_USB3_PORTSC_PR (1 << 4) /* Port Reset */ - #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ - #define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ - #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch b/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch similarity index 95% rename from config/coreboot/haswell/patches/0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch rename to config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch index c321d239..ea46364f 100644 --- a/config/coreboot/haswell/patches/0016-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch +++ b/config/coreboot/haswell/patches/0006-haswell-NRI-Add-DDR3-JEDEC-reset-and-init.patch @@ -1,7 +1,7 @@ -From d24def01ec15f41a48331ef1e236270b2df90b84 Mon Sep 17 00:00:00 2001 +From 1ea9b05694da7ee61d49d9cd2b7e533a98e42321 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 21:49:40 +0200 -Subject: [PATCH 16/26] haswell NRI: Add DDR3 JEDEC reset and init +Subject: [PATCH 06/20] haswell NRI: Add DDR3 JEDEC reset and init Implement JEDEC reset and init sequence for DDR3. The MRS commands are issued through the REUT (Robust Electrical Unified Testing) hardware. @@ -9,25 +9,25 @@ issued through the REUT (Robust Electrical Unified Testing) hardware. Change-Id: I2a0c066537021b587599228086727cb1e041bff5 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 3 + + .../intel/haswell/native_raminit/Makefile.mk | 3 + .../intel/haswell/native_raminit/ddr3.c | 217 ++++++++++++++++++ .../haswell/native_raminit/io_comp_control.c | 19 ++ .../haswell/native_raminit/jedec_reset.c | 120 ++++++++++ .../haswell/native_raminit/raminit_main.c | 2 + - .../haswell/native_raminit/raminit_native.h | 101 ++++++++ + .../haswell/native_raminit/raminit_native.h | 99 ++++++++ .../haswell/native_raminit/reg_structs.h | 154 +++++++++++++ .../intel/haswell/native_raminit/reut.c | 196 ++++++++++++++++ .../intel/haswell/registers/mchbar.h | 21 ++ src/southbridge/intel/lynxpoint/pch.h | 2 + - 10 files changed, 835 insertions(+) + 10 files changed, 833 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/ddr3.c create mode 100644 src/northbridge/intel/haswell/native_raminit/jedec_reset.c create mode 100644 src/northbridge/intel/haswell/native_raminit/reut.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 37d527e972..e9212df9e6 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,11 +1,14 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -267,7 +267,7 @@ index 0000000000..6ddb11488b + return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT); +} diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c -index 7e96c08938..ad8c848e57 100644 +index d45b608dd3..8a55fd81b2 100644 --- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c +++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c @@ -8,6 +8,25 @@ @@ -423,10 +423,10 @@ index 0000000000..de0f676758 + return status; +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 136a8ba989..73ff180b8c 100644 +index 559dfc3a4e..94b268468c 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -25,6 +25,7 @@ static const struct task_entry cold_boot[] = { +@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = { { convert_timings, true, "CONVTIM", }, { configure_mc, true, "CONFMC", }, { configure_memory_map, true, "MEMMAP", }, @@ -434,7 +434,7 @@ index 136a8ba989..73ff180b8c 100644 }; /* Return a generic stepping value to make stepping checks simpler */ -@@ -58,6 +59,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) +@@ -57,6 +58,7 @@ static void initialize_ctrl(struct sysinfo *ctrl) ctrl->stepping = get_stepping(ctrl->cpu); ctrl->vdd_mv = is_hsw_ult() ? 1350 : 1500; /** FIXME: Hardcoded, does it matter? **/ ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved; @@ -443,7 +443,7 @@ index 136a8ba989..73ff180b8c 100644 } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 4763b25e8d..e3cf4254a0 100644 +index 4763b25e8d..4bc2a4955f 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -27,6 +27,30 @@ @@ -498,25 +498,23 @@ index 4763b25e8d..e3cf4254a0 100644 union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS]; union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS]; + -+ uint16_t mr0[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS]; -+ uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS]; ++ uint16_t mr0[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr1[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr2[NUM_CHANNELS][NUM_SLOTS]; ++ uint16_t mr3[NUM_CHANNELS][NUM_SLOTS]; }; static inline bool is_hsw_ult(void) -@@ -196,6 +227,55 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) +@@ -196,6 +227,53 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl) memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train)); } +/* Number of ticks to wait in units of 69.841279 ns (citation needed) */ +static inline void tick_delay(const uint32_t delay) +{ -+ volatile uint32_t junk; -+ + /* Just perform reads to a random register */ + for (uint32_t start = 0; start <= delay; start++) -+ junk = mchbar_read32(REUT_ERR_DATA_STATUS); ++ mchbar_read32(REUT_ERR_DATA_STATUS); +} + +/* @@ -561,7 +559,7 @@ index 4763b25e8d..e3cf4254a0 100644 void raminit_main(enum raminit_boot_mode bootmode); enum raminit_status collect_spd_info(struct sysinfo *ctrl); -@@ -203,6 +283,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); +@@ -203,6 +281,7 @@ enum raminit_status initialise_mpll(struct sysinfo *ctrl); enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); @@ -569,7 +567,7 @@ index 4763b25e8d..e3cf4254a0 100644 void configure_timings(struct sysinfo *ctrl); void configure_refresh(struct sysinfo *ctrl); -@@ -215,8 +296,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); +@@ -215,8 +294,28 @@ uint32_t get_tXS_offset(uint32_t mem_clock_mhz); uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr); uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr); @@ -779,7 +777,7 @@ index 70487e1640..9929f617fe 100644 struct __packed { diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c new file mode 100644 -index 0000000000..c55cdd9c7e +index 0000000000..31019f74a1 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/reut.c @@ -0,0 +1,196 @@ @@ -938,9 +936,9 @@ index 0000000000..c55cdd9c7e +{ + /** TODO: Issuing ZQ commands differs for LPDDR **/ + if (ctrl->lpddr) -+ die("%s: LPDDR not yet supported in ZQ calibration\n"); ++ die("%s: LPDDR not yet supported in ZQ calibration\n", __func__); + -+ uint8_t opcode; /* NOTE: Only used for LPDDR */ ++ __maybe_unused uint8_t opcode; /* NOTE: Only used for LPDDR */ + uint16_t zq = 0; + switch (zq_type) { + case ZQ_INIT: @@ -958,7 +956,7 @@ index 0000000000..c55cdd9c7e + opcode = 0xc3; + break; + default: -+ die("%s: ZQ type %u is invalid\n", zq_type); ++ die("%s: ZQ type %u is invalid\n", __func__, zq_type); + } + + /* ZQCS on single-channel needs a longer delay */ @@ -1021,7 +1019,7 @@ index 2acc5cbbc8..4fc78a7f43 100644 /* MCDECS */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 74b4d50017..16bef5032a 100644 +index 07f4b9dc16..5b3696347c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -586,6 +586,8 @@ void mainboard_config_rcba(void); diff --git a/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch b/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch deleted file mode 100644 index 157d2999..00000000 --- a/config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 23:22:11 +0200 -Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init - -Implement native thermal initialisation for Lynx Point. This is only -needed when MRC.bin is not used. - -Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd -Signed-off-by: Angel Pons ---- - .../haswell/native_raminit/raminit_native.c | 1 + - src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- - src/southbridge/intel/lynxpoint/pch.h | 1 + - src/southbridge/intel/lynxpoint/thermal.c | 64 +++++++++++++++++++ - 4 files changed, 67 insertions(+), 1 deletion(-) - create mode 100644 src/southbridge/intel/lynxpoint/thermal.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index ef61d4ee09..dd1f1ec14e 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -+ early_thermal_init(); - early_usb_init(); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index 0e1f2fe4eb..a9a9b153d6 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -37,7 +37,7 @@ bootblock-y += early_pch.c - romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - --romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c -+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index ad983d86cf..38a9349220 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -116,6 +116,7 @@ enum pch_platform_type { - void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); - void early_usb_init(void); -+void early_thermal_init(void); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c -new file mode 100644 -index 0000000000..e71969ea0c ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/thermal.c -@@ -0,0 +1,64 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+ -+#define TBARB_TEMP 0x40000000 -+ -+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6) -+ -+/* Early thermal init, it may need to be done prior to giving ME its memory */ -+void early_thermal_init(void) -+{ -+ /* Program address for temporary BAR */ -+ pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP); -+ pci_write_config32(THERMAL_DEV, 0x44, 0); -+ -+ /* Activate temporary BAR */ -+ pci_or_config32(THERMAL_DEV, 0x40, 1); -+ -+ /* -+ * BWG section 17.3.1 says: -+ * -+ * ### Initializing Lynx Point Thermal Sensors ### -+ * -+ * The System BIOS must perform the following steps to initialize the Lynx -+ * Point thermal subsystem device, D31:F6. The System BIOS is required to -+ * repeat this process on a resume from Sx. BIOS may enable any or all of -+ * the registers below based on OEM's platform configuration. Intel does -+ * not recommend a value on some of the registers, since each platform has -+ * different temperature trip points and one may enable a trip to cause an -+ * SMI while another platform would cause an interrupt instead. -+ * -+ * The recommended flow for enabling thermal sensor is by setting up various -+ * temperature trip points first, followed by enabling the desired trip -+ * alert method and then enable the actual sensors from TSEL registers. -+ * If this flow is not followed, software will need to take special care -+ * to handle false events during setting up those registers. -+ */ -+ -+ /* Step 1: Program CTT */ -+ write16p(TBARB_TEMP + 0x10, 0x0154); -+ -+ /* Step 2: Clear trip status from TSS and TAS */ -+ write8p(TBARB_TEMP + 0x06, 0xff); -+ write8p(TBARB_TEMP + 0x80, 0xff); -+ -+ /* Step 3: Program TSGPEN and TSPIEN to zero */ -+ write8p(TBARB_TEMP + 0x84, 0x00); -+ write8p(TBARB_TEMP + 0x82, 0x00); -+ -+ /* -+ * Step 4: If thermal reporting to an EC over SMBus is supported, -+ * then write 0x01 to TSREL, else leave at default. -+ */ -+ write8p(TBARB_TEMP + 0x0a, 0x01); -+ -+ /* Disable temporary BAR */ -+ pci_and_config32(THERMAL_DEV, 0x40, ~1); -+ -+ /* Clear temporary BAR address */ -+ pci_write_config32(THERMAL_DEV, 0x40, 0); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch b/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch similarity index 93% rename from config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch rename to config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch index e4cea123..8b73df88 100644 --- a/config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch +++ b/config/coreboot/haswell/patches/0007-haswell-NRI-Add-pre-training-steps.patch @@ -1,7 +1,7 @@ -From 42e43eb210bbb172af8e5ad064326c4570be8654 Mon Sep 17 00:00:00 2001 +From 936d432822fcd9aa2f018444cdc89e48e6d257d5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 7 May 2022 23:12:18 +0200 -Subject: [PATCH 17/26] haswell NRI: Add pre-training steps +Subject: [PATCH 07/20] haswell NRI: Add pre-training steps Implement pre-training steps, which consist of enabling ECC I/O and filling the WDB (Write Data Buffer, stores test patterns) through a @@ -10,19 +10,19 @@ magic LDAT port. Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 34 ++++ + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/raminit_main.c | 35 ++++ .../haswell/native_raminit/raminit_native.h | 24 +++ .../haswell/native_raminit/reg_structs.h | 45 +++++ .../intel/haswell/native_raminit/setup_wdb.c | 159 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 9 + - 6 files changed, 272 insertions(+) + 6 files changed, 273 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index e9212df9e6..8d7d4e4db0 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -10,5 +10,6 @@ romstage-y += memory_map.c romstage-y += raminit_main.c romstage-y += raminit_native.c @@ -31,10 +31,18 @@ index e9212df9e6..8d7d4e4db0 100644 romstage-y += spd_bitmunching.c romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 73ff180b8c..5e4674957d 100644 +index 94b268468c..5e4674957d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -13,6 +13,39 @@ +@@ -3,6 +3,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -12,6 +13,39 @@ #include "raminit_native.h" @@ -74,7 +82,7 @@ index 73ff180b8c..5e4674957d 100644 struct task_entry { enum raminit_status (*task)(struct sysinfo *); bool is_enabled; -@@ -26,6 +59,7 @@ static const struct task_entry cold_boot[] = { +@@ -25,6 +59,7 @@ static const struct task_entry cold_boot[] = { { configure_mc, true, "CONFMC", }, { configure_memory_map, true, "MEMMAP", }, { do_jedec_init, true, "JEDECINIT", }, @@ -83,7 +91,7 @@ index 73ff180b8c..5e4674957d 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index e3cf4254a0..f29c2ec366 100644 +index 4bc2a4955f..1971b44b66 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -35,6 +35,13 @@ @@ -100,7 +108,7 @@ index e3cf4254a0..f29c2ec366 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -318,6 +325,23 @@ void reut_issue_mrs_all( +@@ -316,6 +323,23 @@ void reut_issue_mrs_all( enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type); diff --git a/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch b/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch deleted file mode 100644 index 74427f5d..00000000 --- a/config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch +++ /dev/null @@ -1,785 +0,0 @@ -From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Fri, 6 May 2022 23:43:46 +0200 -Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init - -Implement native PCH initialisation for Lynx Point. This is only needed -when MRC.bin is not used. - -Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561 -Signed-off-by: Angel Pons ---- - .../haswell/native_raminit/raminit_native.c | 3 +- - src/southbridge/intel/lynxpoint/Makefile.inc | 1 + - .../intel/lynxpoint/early_pch_native.c | 123 +++++++++ - .../intel/lynxpoint/hsio/Makefile.inc | 8 + - src/southbridge/intel/lynxpoint/hsio/common.c | 52 ++++ - src/southbridge/intel/lynxpoint/hsio/hsio.h | 46 ++++ - .../intel/lynxpoint/hsio/lpt_h_cx.c | 244 ++++++++++++++++++ - .../intel/lynxpoint/hsio/lpt_lp_bx.c | 180 +++++++++++++ - src/southbridge/intel/lynxpoint/pch.h | 6 + - 9 files changed, 661 insertions(+), 2 deletions(-) - create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc - create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c - create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h - create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c - create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index dd1f1ec14e..b6efb6b40d 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume) - /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ - const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - -- early_thermal_init(); -- early_usb_init(); -+ early_pch_init_native(s3resume); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); -diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc -index a9a9b153d6..63243ecc86 100644 ---- a/src/southbridge/intel/lynxpoint/Makefile.inc -+++ b/src/southbridge/intel/lynxpoint/Makefile.inc -@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c - romstage-y += pmutil.c - - romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c -+subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio - - ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) - romstage-y += lp_gpio.c -diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c -index c28ddfcf5d..421821fa5d 100644 ---- a/src/southbridge/intel/lynxpoint/early_pch_native.c -+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c -@@ -1,10 +1,133 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - - #include -+#include - #include -+#include - #include - #include - -+static void early_sata_init(const uint8_t pch_revision) -+{ -+ const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP; -+ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner); -+ -+ /* BWG Step 2 */ -+ pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183); -+ -+ /* BWG Step 3: Set OOB Retry Mode */ -+ pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15); -+ -+ /* BWG Step 4: Program the SATA mPHY tables */ -+ if (pch_is_lp()) { -+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) { -+ program_hsio_sata_lpt_lp_bx(is_mobile); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision); -+ } -+ } else { -+ if (pch_revision >= LPT_H_STEP_C0) { -+ program_hsio_sata_lpt_h_cx(is_mobile); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision); -+ } -+ } -+ -+ /** FIXME: Program SATA RxEq tables **/ -+ -+ /* BWG Step 5 */ -+ /** FIXME: Only for desktop and mobile (skip this on workstation and server) **/ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22)); -+ -+ /* BWG Step 6 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19)); -+ -+ /* BWG Step 7 */ -+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7); -+ -+ /* BWG Step 8 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20)); -+ -+ /* BWG Step 9 */ -+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5); -+ -+ /* BWG Step 10 */ -+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18)); -+ -+ /* Enable SATA ports */ -+ uint8_t sata_pcs = 0; -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ for (uint8_t i = 0; i < 4; i++) { -+ if ((lane_owner & BIT(7 - i)) == 0) { -+ sata_pcs |= BIT(i); -+ } -+ } -+ } else { -+ sata_pcs |= 0x0f; -+ for (uint8_t i = 4; i < 6; i++) { -+ if ((lane_owner & BIT(i)) == 0) { -+ sata_pcs |= BIT(i); -+ } -+ } -+ } -+ printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs); -+ pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs); -+} -+ -+void early_pch_init_native(int s3resume) -+{ -+ const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); -+ -+ RCBA16(DISPBDF) = 0x0010; -+ RCBA32_OR(FD2, PCH_ENABLE_DBDF); -+ -+ /** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/ -+ -+ RCBA32(PRSTS) = BIT(4); -+ -+ early_sata_init(pch_revision); -+ -+ pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1); -+ pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1)); -+ -+ /** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/ -+ -+ /** FIXME: GbE handling? **/ -+ -+ pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0); -+ -+ for (uint8_t i = 0; i < 8; i++) -+ pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0); -+ -+ pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7); -+ -+ pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0); -+ pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0); -+ -+ /** FIXME: Disable SATA2 device? **/ -+ -+ if (pch_is_lp()) { -+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) { -+ program_hsio_xhci_lpt_lp_bx(); -+ program_hsio_igbe_lpt_lp_bx(); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision); -+ } -+ } else { -+ if (pch_revision >= LPT_H_STEP_C0) { -+ program_hsio_xhci_lpt_h_cx(); -+ program_hsio_igbe_lpt_h_cx(); -+ } else { -+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision); -+ } -+ } -+ -+ early_thermal_init(); -+ early_usb_init(); -+} -+ - void pch_dmi_setup_physical_layer(void) - { - /* FIXME: We need to make sure the SA supports Gen2 as well */ -diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc -new file mode 100644 -index 0000000000..6b74997511 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc -@@ -0,0 +1,8 @@ -+## SPDX-License-Identifier: GPL-2.0-or-later -+ -+romstage-y += common.c -+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) -+romstage-y += lpt_lp_bx.c -+else -+romstage-y += lpt_h_cx.c -+endif -diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c -new file mode 100644 -index 0000000000..9935ca347a ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/common.c -@@ -0,0 +1,52 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+ -+/* -+ * FIXME: Ask Intel whether all lanes need to be programmed as specified -+ * in the PCH BWG. If not, make separate tables and only check this once. -+ */ -+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ -+ if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4))) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5))) -+ return; -+ -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6))) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7))) -+ return; -+ } -+ hsio_update(addr, and, or); -+} -+ -+/* -+ * FIXME: Ask Intel whether all lanes need to be programmed as specified -+ * in the PCH BWG. If not, make separate tables and only check this once. -+ */ -+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ if (CONFIG(INTEL_LYNXPOINT_LP)) { -+ if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2) -+ return; -+ } else { -+ if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2) -+ return; -+ -+ if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2) -+ return; -+ } -+ hsio_update(addr, and, or); -+} -diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h -new file mode 100644 -index 0000000000..689ef4a05b ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H -+#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H -+ -+#include -+#include -+ -+struct hsio_table_row { -+ uint32_t addr; -+ uint32_t and; -+ uint32_t or; -+}; -+ -+static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or) -+{ -+ pch_iobp_update(addr, and, or); -+} -+ -+static inline void hsio_update_row(const struct hsio_table_row row) -+{ -+ hsio_update(row.addr, row.and, row.or); -+} -+ -+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or); -+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or); -+ -+static inline void hsio_sata_shared_update_row(const struct hsio_table_row row) -+{ -+ hsio_sata_shared_update(row.addr, row.and, row.or); -+} -+ -+static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row) -+{ -+ hsio_xhci_shared_update(row.addr, row.and, row.or); -+} -+ -+void program_hsio_sata_lpt_h_cx(const bool is_mobile); -+void program_hsio_xhci_lpt_h_cx(void); -+void program_hsio_igbe_lpt_h_cx(void); -+ -+void program_hsio_sata_lpt_lp_bx(const bool is_mobile); -+void program_hsio_xhci_lpt_lp_bx(void); -+void program_hsio_igbe_lpt_lp_bx(void); -+ -+#endif -diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c -new file mode 100644 -index 0000000000..b5dd402742 ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c -@@ -0,0 +1,244 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+ -+const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = { -+ { 0xea002008, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002208, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002038, ~0x3f00000f, 0x0700000d }, -+ { 0xea002238, ~0x3f00000f, 0x0700000d }, -+ { 0xea00202c, ~0x00020f00, 0x00020100 }, -+ { 0xea00222c, ~0x00020f00, 0x00020100 }, -+ { 0xea002040, ~0x1f000000, 0x01000000 }, -+ { 0xea002240, ~0x1f000000, 0x01000000 }, -+ { 0xea002010, ~0xffff0000, 0x0d510000 }, -+ { 0xea002210, ~0xffff0000, 0x0d510000 }, -+ { 0xea002018, ~0xffff0300, 0x38250100 }, -+ { 0xea002218, ~0xffff0300, 0x38250100 }, -+ { 0xea002000, ~0xcf030000, 0xcf030000 }, -+ { 0xea002200, ~0xcf030000, 0xcf030000 }, -+ { 0xea002028, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002228, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00201c, ~0x00007c00, 0x00002400 }, -+ { 0xea00221c, ~0x00007c00, 0x00002400 }, -+ { 0xea00208c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00228c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0020a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0022a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0020ac, ~0x00000030, 0x00000020 }, -+ { 0xea0022ac, ~0x00000030, 0x00000020 }, -+ { 0xea002140, ~0x00ffffff, 0x00140718 }, -+ { 0xea002340, ~0x00ffffff, 0x00140718 }, -+ { 0xea002144, ~0x00ffffff, 0x00140998 }, -+ { 0xea002344, ~0x00ffffff, 0x00140998 }, -+ { 0xea002148, ~0x00ffffff, 0x00140998 }, -+ { 0xea002348, ~0x00ffffff, 0x00140998 }, -+ { 0xea00217c, ~0x03000000, 0x03000000 }, -+ { 0xea00237c, ~0x03000000, 0x03000000 }, -+ { 0xea002178, ~0x00001f00, 0x00001800 }, -+ { 0xea002378, ~0x00001f00, 0x00001800 }, -+ { 0xea00210c, ~0x0038000f, 0x00000005 }, -+ { 0xea00230c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_sata_lpt_h_cx[] = { -+ { 0xea008008, ~0xff000000, 0x1c000000 }, -+ { 0xea002408, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002608, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea000808, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea000a08, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002438, ~0x3f00000f, 0x0700000d }, -+ { 0xea002638, ~0x3f00000f, 0x0700000d }, -+ { 0xea000838, ~0x3f00000f, 0x0700000d }, -+ { 0xea000a38, ~0x3f00000f, 0x0700000d }, -+ { 0xea002440, ~0x1f000000, 0x01000000 }, -+ { 0xea002640, ~0x1f000000, 0x01000000 }, -+ { 0xea000840, ~0x1f000000, 0x01000000 }, -+ { 0xea000a40, ~0x1f000000, 0x01000000 }, -+ { 0xea002410, ~0xffff0000, 0x0d510000 }, -+ { 0xea002610, ~0xffff0000, 0x0d510000 }, -+ { 0xea000810, ~0xffff0000, 0x0d510000 }, -+ { 0xea000a10, ~0xffff0000, 0x0d510000 }, -+ { 0xea00242c, ~0x00020800, 0x00020000 }, -+ { 0xea00262c, ~0x00020800, 0x00020000 }, -+ { 0xea00082c, ~0x00020800, 0x00020000 }, -+ { 0xea000a2c, ~0x00020800, 0x00020000 }, -+ { 0xea002418, ~0xffff0300, 0x38250100 }, -+ { 0xea002618, ~0xffff0300, 0x38250100 }, -+ { 0xea000818, ~0xffff0300, 0x38250100 }, -+ { 0xea000a18, ~0xffff0300, 0x38250100 }, -+ { 0xea002400, ~0xcf030000, 0xcf030000 }, -+ { 0xea002600, ~0xcf030000, 0xcf030000 }, -+ { 0xea000800, ~0xcf030000, 0xcf030000 }, -+ { 0xea000a00, ~0xcf030000, 0xcf030000 }, -+ { 0xea002428, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002628, ~0xff1f0000, 0x580e0000 }, -+ { 0xea000828, ~0xff1f0000, 0x580e0000 }, -+ { 0xea000a28, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00241c, ~0x00007c00, 0x00002400 }, -+ { 0xea00261c, ~0x00007c00, 0x00002400 }, -+ { 0xea00081c, ~0x00007c00, 0x00002400 }, -+ { 0xea000a1c, ~0x00007c00, 0x00002400 }, -+ { 0xea00248c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00268c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00088c, ~0x00ff0000, 0x00800000 }, -+ { 0xea000a8c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0024a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0026a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0008a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea000aa4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0024ac, ~0x00000030, 0x00000020 }, -+ { 0xea0026ac, ~0x00000030, 0x00000020 }, -+ { 0xea0008ac, ~0x00000030, 0x00000020 }, -+ { 0xea000aac, ~0x00000030, 0x00000020 }, -+ { 0xea002540, ~0x00ffffff, 0x00140718 }, -+ { 0xea002740, ~0x00ffffff, 0x00140718 }, -+ { 0xea000940, ~0x00ffffff, 0x00140718 }, -+ { 0xea000b40, ~0x00ffffff, 0x00140718 }, -+ { 0xea002544, ~0x00ffffff, 0x00140998 }, -+ { 0xea002744, ~0x00ffffff, 0x00140998 }, -+ { 0xea000944, ~0x00ffffff, 0x00140998 }, -+ { 0xea000b44, ~0x00ffffff, 0x00140998 }, -+ { 0xea002548, ~0x00ffffff, 0x00140998 }, -+ { 0xea002748, ~0x00ffffff, 0x00140998 }, -+ { 0xea000948, ~0x00ffffff, 0x00140998 }, -+ { 0xea000b48, ~0x00ffffff, 0x00140998 }, -+ { 0xea00257c, ~0x03000000, 0x03000000 }, -+ { 0xea00277c, ~0x03000000, 0x03000000 }, -+ { 0xea00097c, ~0x03000000, 0x03000000 }, -+ { 0xea000b7c, ~0x03000000, 0x03000000 }, -+ { 0xea002578, ~0x00001f00, 0x00001800 }, -+ { 0xea002778, ~0x00001f00, 0x00001800 }, -+ { 0xea000978, ~0x00001f00, 0x00001800 }, -+ { 0xea000b78, ~0x00001f00, 0x00001800 }, -+ { 0xea00250c, ~0x0038000f, 0x00000005 }, -+ { 0xea00270c, ~0x0038000f, 0x00000005 }, -+ { 0xea00090c, ~0x0038000f, 0x00000005 }, -+ { 0xea000b0c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = { -+ { 0xe9002c2c, ~0x00000700, 0x00000100 }, -+ { 0xe9002e2c, ~0x00000700, 0x00000100 }, -+ { 0xe9002dcc, ~0x00001407, 0x00001407 }, -+ { 0xe9002fcc, ~0x00001407, 0x00001407 }, -+ { 0xe9002d68, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002f68, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002d6c, ~0x000000ff, 0x0000003f }, -+ { 0xe9002f6c, ~0x000000ff, 0x0000003f }, -+ { 0xe9002d4c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002f4c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002d14, ~0x38000700, 0x00000100 }, -+ { 0xe9002f14, ~0x38000700, 0x00000100 }, -+ { 0xe9002d64, ~0x0000f000, 0x00005000 }, -+ { 0xe9002f64, ~0x0000f000, 0x00005000 }, -+ { 0xe9002d70, ~0x00000018, 0x00000000 }, -+ { 0xe9002f70, ~0x00000018, 0x00000000 }, -+ { 0xe9002c38, ~0x3f00000f, 0x0700000b }, -+ { 0xe9002e38, ~0x3f00000f, 0x0700000b }, -+ { 0xe9002d40, ~0x00800000, 0x00000000 }, -+ { 0xe9002f40, ~0x00800000, 0x00000000 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_lpt_h_cx[] = { -+ { 0xe90031cc, ~0x00001407, 0x00001407 }, -+ { 0xe90033cc, ~0x00001407, 0x00001407 }, -+ { 0xe90015cc, ~0x00001407, 0x00001407 }, -+ { 0xe90017cc, ~0x00001407, 0x00001407 }, -+ { 0xe9003168, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9003368, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9001568, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9001768, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900316c, ~0x000000ff, 0x0000003f }, -+ { 0xe900336c, ~0x000000ff, 0x0000003f }, -+ { 0xe900156c, ~0x000000ff, 0x0000003f }, -+ { 0xe900176c, ~0x000000ff, 0x0000003f }, -+ { 0xe900314c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900334c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900154c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900174c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9003114, ~0x38000700, 0x00000100 }, -+ { 0xe9003314, ~0x38000700, 0x00000100 }, -+ { 0xe9001514, ~0x38000700, 0x00000100 }, -+ { 0xe9001714, ~0x38000700, 0x00000100 }, -+ { 0xe9003164, ~0x0000f000, 0x00005000 }, -+ { 0xe9003364, ~0x0000f000, 0x00005000 }, -+ { 0xe9001564, ~0x0000f000, 0x00005000 }, -+ { 0xe9001764, ~0x0000f000, 0x00005000 }, -+ { 0xe9003170, ~0x00000018, 0x00000000 }, -+ { 0xe9003370, ~0x00000018, 0x00000000 }, -+ { 0xe9001570, ~0x00000018, 0x00000000 }, -+ { 0xe9001770, ~0x00000018, 0x00000000 }, -+ { 0xe9003038, ~0x3f00000f, 0x0700000b }, -+ { 0xe9003238, ~0x3f00000f, 0x0700000b }, -+ { 0xe9001438, ~0x3f00000f, 0x0700000b }, -+ { 0xe9001638, ~0x3f00000f, 0x0700000b }, -+ { 0xe9003140, ~0x00800000, 0x00000000 }, -+ { 0xe9003340, ~0x00800000, 0x00000000 }, -+ { 0xe9001540, ~0x00800000, 0x00000000 }, -+ { 0xe9001740, ~0x00800000, 0x00000000 }, -+}; -+ -+void program_hsio_sata_lpt_h_cx(const bool is_mobile) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_sata_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_sata_lpt_h_cx); -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_sata_shared_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx); -+ for (size_t i = 0; i < len; i++) -+ hsio_sata_shared_update_row(pch_hsio_table[i]); -+ -+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67; -+ -+ hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value); -+ hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value); -+ -+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value); -+} -+ -+void program_hsio_xhci_lpt_h_cx(void) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_xhci_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_xhci_lpt_h_cx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_xhci_shared_lpt_h_cx; -+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_xhci_shared_update_row(pch_hsio_table[i]); -+} -+ -+void program_hsio_igbe_lpt_h_cx(void) -+{ -+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc); -+ if (!(strpfusecfg1 & (1 << 19))) -+ return; -+ -+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7; -+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410); -+ if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1) -+ return; -+ -+ if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1) -+ return; -+ -+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8; -+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100); -+} -diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c -new file mode 100644 -index 0000000000..24679e791a ---- /dev/null -+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c -@@ -0,0 +1,180 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+ -+const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = { -+ { 0xea008008, ~0xff000000, 0x1c000000 }, -+ { 0xea002008, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002208, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002408, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002608, ~0xfffc6108, 0xea6c6108 }, -+ { 0xea002038, ~0x0000000f, 0x0000000d }, -+ { 0xea002238, ~0x0000000f, 0x0000000d }, -+ { 0xea002438, ~0x0000000f, 0x0000000d }, -+ { 0xea002638, ~0x0000000f, 0x0000000d }, -+ { 0xea00202c, ~0x00020f00, 0x00020100 }, -+ { 0xea00222c, ~0x00020f00, 0x00020100 }, -+ { 0xea00242c, ~0x00020f00, 0x00020100 }, -+ { 0xea00262c, ~0x00020f00, 0x00020100 }, -+ { 0xea002040, ~0x1f000000, 0x01000000 }, -+ { 0xea002240, ~0x1f000000, 0x01000000 }, -+ { 0xea002440, ~0x1f000000, 0x01000000 }, -+ { 0xea002640, ~0x1f000000, 0x01000000 }, -+ { 0xea002010, ~0xffff0000, 0x55510000 }, -+ { 0xea002210, ~0xffff0000, 0x55510000 }, -+ { 0xea002410, ~0xffff0000, 0x55510000 }, -+ { 0xea002610, ~0xffff0000, 0x55510000 }, -+ { 0xea002140, ~0x00ffffff, 0x00140718 }, -+ { 0xea002340, ~0x00ffffff, 0x00140718 }, -+ { 0xea002540, ~0x00ffffff, 0x00140718 }, -+ { 0xea002740, ~0x00ffffff, 0x00140718 }, -+ { 0xea002144, ~0x00ffffff, 0x00140998 }, -+ { 0xea002344, ~0x00ffffff, 0x00140998 }, -+ { 0xea002544, ~0x00ffffff, 0x00140998 }, -+ { 0xea002744, ~0x00ffffff, 0x00140998 }, -+ { 0xea002148, ~0x00ffffff, 0x00140998 }, -+ { 0xea002348, ~0x00ffffff, 0x00140998 }, -+ { 0xea002548, ~0x00ffffff, 0x00140998 }, -+ { 0xea002748, ~0x00ffffff, 0x00140998 }, -+ { 0xea00217c, ~0x03000000, 0x03000000 }, -+ { 0xea00237c, ~0x03000000, 0x03000000 }, -+ { 0xea00257c, ~0x03000000, 0x03000000 }, -+ { 0xea00277c, ~0x03000000, 0x03000000 }, -+ { 0xea00208c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00228c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00248c, ~0x00ff0000, 0x00800000 }, -+ { 0xea00268c, ~0x00ff0000, 0x00800000 }, -+ { 0xea0020a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0022a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0024a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0026a4, ~0x0030ff00, 0x00308300 }, -+ { 0xea0020ac, ~0x00000030, 0x00000020 }, -+ { 0xea0022ac, ~0x00000030, 0x00000020 }, -+ { 0xea0024ac, ~0x00000030, 0x00000020 }, -+ { 0xea0026ac, ~0x00000030, 0x00000020 }, -+ { 0xea002018, ~0xffff0300, 0x38250100 }, -+ { 0xea002218, ~0xffff0300, 0x38250100 }, -+ { 0xea002418, ~0xffff0300, 0x38250100 }, -+ { 0xea002618, ~0xffff0300, 0x38250100 }, -+ { 0xea002000, ~0xcf030000, 0xcf030000 }, -+ { 0xea002200, ~0xcf030000, 0xcf030000 }, -+ { 0xea002400, ~0xcf030000, 0xcf030000 }, -+ { 0xea002600, ~0xcf030000, 0xcf030000 }, -+ { 0xea002028, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002228, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002428, ~0xff1f0000, 0x580e0000 }, -+ { 0xea002628, ~0xff1f0000, 0x580e0000 }, -+ { 0xea00201c, ~0x00007c00, 0x00002400 }, -+ { 0xea00221c, ~0x00007c00, 0x00002400 }, -+ { 0xea00241c, ~0x00007c00, 0x00002400 }, -+ { 0xea00261c, ~0x00007c00, 0x00002400 }, -+ { 0xea002178, ~0x00001f00, 0x00001800 }, -+ { 0xea002378, ~0x00001f00, 0x00001800 }, -+ { 0xea002578, ~0x00001f00, 0x00001800 }, -+ { 0xea002778, ~0x00001f00, 0x00001800 }, -+ { 0xea00210c, ~0x0038000f, 0x00000005 }, -+ { 0xea00230c, ~0x0038000f, 0x00000005 }, -+ { 0xea00250c, ~0x0038000f, 0x00000005 }, -+ { 0xea00270c, ~0x0038000f, 0x00000005 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = { -+ { 0xe90025cc, ~0x00001407, 0x00001407 }, -+ { 0xe90027cc, ~0x00001407, 0x00001407 }, -+ { 0xe9002568, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002768, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900242c, ~0x00000700, 0x00000100 }, -+ { 0xe900262c, ~0x00000700, 0x00000100 }, -+ { 0xe900256c, ~0x000000ff, 0x0000003f }, -+ { 0xe900276c, ~0x000000ff, 0x0000003f }, -+ { 0xe900254c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900274c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002564, ~0x0000f000, 0x00005000 }, -+ { 0xe9002764, ~0x0000f000, 0x00005000 }, -+ { 0xe9002570, ~0x00000018, 0x00000000 }, -+ { 0xe9002770, ~0x00000018, 0x00000000 }, -+ { 0xe9002514, ~0x38000700, 0x00000100 }, -+ { 0xe9002714, ~0x38000700, 0x00000100 }, -+ { 0xe9002438, ~0x0000000f, 0x0000000b }, -+ { 0xe9002638, ~0x0000000f, 0x0000000b }, -+ { 0xe9002414, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002614, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002540, ~0x00800000, 0x00000000 }, -+ { 0xe9002740, ~0x00800000, 0x00000000 }, -+}; -+ -+const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = { -+ { 0xe90021cc, ~0x00001407, 0x00001407 }, -+ { 0xe90023cc, ~0x00001407, 0x00001407 }, -+ { 0xe9002168, ~0x01000f3c, 0x00000a28 }, -+ { 0xe9002368, ~0x01000f3c, 0x00000a28 }, -+ { 0xe900216c, ~0x000000ff, 0x0000003f }, -+ { 0xe900236c, ~0x000000ff, 0x0000003f }, -+ { 0xe900214c, ~0x00ffff00, 0x00120500 }, -+ { 0xe900234c, ~0x00ffff00, 0x00120500 }, -+ { 0xe9002164, ~0x0000f000, 0x00005000 }, -+ { 0xe9002364, ~0x0000f000, 0x00005000 }, -+ { 0xe9002170, ~0x00000018, 0x00000000 }, -+ { 0xe9002370, ~0x00000018, 0x00000000 }, -+ { 0xe9002114, ~0x38000700, 0x00000100 }, -+ { 0xe9002314, ~0x38000700, 0x00000100 }, -+ { 0xe9002038, ~0x0000000f, 0x0000000b }, -+ { 0xe9002238, ~0x0000000f, 0x0000000b }, -+ { 0xe9002014, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002214, ~0x0000fe00, 0x00006600 }, -+ { 0xe9002140, ~0x00800000, 0x00000000 }, -+ { 0xe9002340, ~0x00800000, 0x00000000 }, -+}; -+ -+void program_hsio_sata_lpt_lp_bx(const bool is_mobile) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_sata_shared_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx); -+ for (size_t i = 0; i < len; i++) -+ hsio_sata_shared_update_row(pch_hsio_table[i]); -+ -+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67; -+ -+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value); -+ hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value); -+} -+ -+void program_hsio_xhci_lpt_lp_bx(void) -+{ -+ const struct hsio_table_row *pch_hsio_table; -+ size_t len; -+ -+ pch_hsio_table = hsio_xhci_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_update_row(pch_hsio_table[i]); -+ -+ pch_hsio_table = hsio_xhci_shared_lpt_lp_bx; -+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx); -+ -+ for (size_t i = 0; i < len; i++) -+ hsio_xhci_shared_update_row(pch_hsio_table[i]); -+} -+ -+void program_hsio_igbe_lpt_lp_bx(void) -+{ -+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc); -+ if (!(strpfusecfg1 & (1 << 19))) -+ return; -+ -+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7; -+ if (gbe_port > 5) -+ return; -+ -+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8; -+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100); -+} -diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h -index 38a9349220..74b4d50017 100644 ---- a/src/southbridge/intel/lynxpoint/pch.h -+++ b/src/southbridge/intel/lynxpoint/pch.h -@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void); - void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm); - void early_usb_init(void); - void early_thermal_init(void); -+void early_pch_init_native(int s3resume); - - void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); - void usb_ehci_disable(pci_devfn_t dev); -@@ -271,6 +272,10 @@ void mainboard_config_rcba(void); - #define IDE_DECODE_ENABLE (1 << 15) - #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ - -+#define SATA_MAP 0x90 -+#define SATA_PCS 0x92 -+#define SATA_SCLKG 0x94 -+ - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ - #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ - #define SATA_SP 0xd0 /* Scratchpad */ -@@ -580,6 +585,7 @@ void mainboard_config_rcba(void); - #define D19IR 0x3168 /* 16bit */ - #define ACPIIRQEN 0x31e0 /* 32bit */ - #define OIC 0x31fe /* 16bit */ -+#define PRSTS 0x3310 /* 32bit */ - #define PMSYNC_CONFIG 0x33c4 /* 32bit */ - #define PMSYNC_CONFIG2 0x33cc /* 32bit */ - #define SOFT_RESET_CTRL 0x38f4 --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0018-haswell-NRI-Add-REUT-I-O-test-library.patch b/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch similarity index 97% rename from config/coreboot/haswell/patches/0018-haswell-NRI-Add-REUT-I-O-test-library.patch rename to config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch index 5df22ed3..2225f18c 100644 --- a/config/coreboot/haswell/patches/0018-haswell-NRI-Add-REUT-I-O-test-library.patch +++ b/config/coreboot/haswell/patches/0008-haswell-NRI-Add-REUT-I-O-test-library.patch @@ -1,25 +1,25 @@ -From f4dd460d609276de7cb7db91f145a404451a2301 Mon Sep 17 00:00:00 2001 +From 49a7ef2401922a8492ba577a43235bcfba7ea822 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 00:11:29 +0200 -Subject: [PATCH 18/26] haswell NRI: Add REUT I/O test library +Subject: [PATCH 08/20] haswell NRI: Add REUT I/O test library Implement a library to run I/O tests using the REUT hardware. Change-Id: Id7b207cd0a3989ddd23c88c6b1f0cfa79d2c861f Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_native.h | 110 +++ .../haswell/native_raminit/reg_structs.h | 121 +++ - .../intel/haswell/native_raminit/testing_io.c | 742 ++++++++++++++++++ + .../intel/haswell/native_raminit/testing_io.c | 744 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 30 + - 5 files changed, 1004 insertions(+) + 5 files changed, 1006 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/testing_io.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 8d7d4e4db0..6e1b365602 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -12,4 +12,5 @@ romstage-y += raminit_native.c romstage-y += reut.c romstage-y += setup_wdb.c @@ -27,7 +27,7 @@ index 8d7d4e4db0..6e1b365602 100644 +romstage-y += testing_io.c romstage-y += timings_refresh.c diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index f29c2ec366..56df36ca8d 100644 +index 1971b44b66..7f19fde4cc 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -58,6 +58,88 @@ enum { @@ -120,9 +120,9 @@ index f29c2ec366..56df36ca8d 100644 CT_ITERATION_CLOCK = 0, CT_ITERATION_CMD_NORTH, @@ -199,6 +281,10 @@ struct sysinfo { - uint16_t mr1[NUM_CHANNELS][NUM_SLOTRANKS]; - uint16_t mr2[NUM_CHANNELS][NUM_SLOTRANKS]; - uint16_t mr3[NUM_CHANNELS][NUM_SLOTRANKS]; + uint16_t mr1[NUM_CHANNELS][NUM_SLOTS]; + uint16_t mr2[NUM_CHANNELS][NUM_SLOTS]; + uint16_t mr3[NUM_CHANNELS][NUM_SLOTS]; + + uint8_t dq_pat; + @@ -130,7 +130,7 @@ index f29c2ec366..56df36ca8d 100644 }; static inline bool is_hsw_ult(void) -@@ -342,6 +428,30 @@ void write_wdb_va_pat( +@@ -340,6 +426,30 @@ void write_wdb_va_pat( void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup); void setup_wdb(const struct sysinfo *ctrl); @@ -309,10 +309,10 @@ index 7aa8d8c8b2..b943259b91 100644 uint32_t start_test : 1; // Bits 0:0 diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c new file mode 100644 -index 0000000000..7716fc4285 +index 0000000000..2632c238f8 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c -@@ -0,0 +1,742 @@ +@@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include @@ -535,8 +535,10 @@ index 0000000000..7716fc4285 + const uint8_t en_cadb, + const uint8_t subseq_wait) +{ -+ if (!chanmask) -+ die("\n%s: invalid chanmask\n", __func__, chanmask); ++ if (!chanmask) { ++ printk(BIOS_ERR, "\n%s: chanmask is invalid\n", __func__); ++ return; ++ } + + /* + * Prepare variables needed for both channels. diff --git a/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch b/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch deleted file mode 100644 index 6df828eb..00000000 --- a/config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 46cdec8cbce15ca11ad9a49a3ee415a78f781997 Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Sat, 7 May 2022 00:26:10 +0200 -Subject: [PATCH 08/26] nb/intel/haswell: Add native raminit scaffolding - -Implement some scaffolding for Haswell native raminit, like bootmode -selection, handling of MRC cache and CPU detection. - -Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b -Signed-off-by: Angel Pons ---- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 104 ++++++++++ - .../haswell/native_raminit/raminit_native.c | 189 +++++++++++++++++- - .../haswell/native_raminit/raminit_native.h | 34 ++++ - 4 files changed, 322 insertions(+), 6 deletions(-) - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_main.c - create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.h - -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -index 8cfb4fb33e..90af951c5a 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -1,3 +1,4 @@ - ## SPDX-License-Identifier: GPL-2.0-or-later - -+romstage-y += raminit_main.c - romstage-y += raminit_native.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -new file mode 100644 -index 0000000000..9b42c25b40 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -0,0 +1,104 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "raminit_native.h" -+ -+struct task_entry { -+ enum raminit_status (*task)(struct sysinfo *); -+ bool is_enabled; -+ const char *name; -+}; -+ -+static const struct task_entry cold_boot[] = { -+}; -+ -+/* Return a generic stepping value to make stepping checks simpler */ -+static enum generic_stepping get_stepping(const uint32_t cpuid) -+{ -+ switch (cpuid) { -+ case CPUID_HASWELL_A0: -+ die("Haswell stepping A0 is not supported\n"); -+ case CPUID_HASWELL_B0: -+ case CPUID_HASWELL_ULT_B0: -+ case CPUID_CRYSTALWELL_B0: -+ return STEPPING_B0; -+ case CPUID_HASWELL_C0: -+ case CPUID_HASWELL_ULT_C0: -+ case CPUID_CRYSTALWELL_C0: -+ return STEPPING_C0; -+ default: -+ /** TODO: Add Broadwell support someday **/ -+ die("Unknown CPUID 0x%x\n", cpuid); -+ } -+} -+ -+static void initialize_ctrl(struct sysinfo *ctrl) -+{ -+ const struct northbridge_intel_haswell_config *cfg = config_of_soc(); -+ const enum raminit_boot_mode bootmode = ctrl->bootmode; -+ -+ memset(ctrl, 0, sizeof(*ctrl)); -+ -+ ctrl->cpu = cpu_get_cpuid(); -+ ctrl->stepping = get_stepping(ctrl->cpu); -+ ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved; -+ ctrl->bootmode = bootmode; -+} -+ -+static enum raminit_status try_raminit(struct sysinfo *ctrl) -+{ -+ const struct task_entry *const schedule = cold_boot; -+ const size_t length = ARRAY_SIZE(cold_boot); -+ -+ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; -+ -+ for (size_t i = 0; i < length; i++) { -+ const struct task_entry *const entry = &schedule[i]; -+ assert(entry); -+ assert(entry->name); -+ if (!entry->is_enabled) -+ continue; -+ -+ assert(entry->task); -+ printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name); -+ status = entry->task(ctrl); -+ printk(RAM_DEBUG, "\n"); -+ if (status) { -+ printk(BIOS_ERR, "raminit failed on step %s\n", entry->name); -+ break; -+ } -+ } -+ -+ return status; -+} -+ -+void raminit_main(const enum raminit_boot_mode bootmode) -+{ -+ /* -+ * The mighty_ctrl struct. Will happily nuke the pre-RAM stack -+ * if left unattended. Make it static and pass pointers to it. -+ */ -+ static struct sysinfo mighty_ctrl; -+ -+ mighty_ctrl.bootmode = bootmode; -+ initialize_ctrl(&mighty_ctrl); -+ -+ /** TODO: Try more than once **/ -+ enum raminit_status status = try_raminit(&mighty_ctrl); -+ -+ if (status != RAMINIT_STATUS_SUCCESS) -+ die("Memory initialization was met with utmost failure and misery\n"); -+ -+ /** TODO: Implement the required magic **/ -+ die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+} -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index b6efb6b40d..0869db3902 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -1,13 +1,45 @@ - /* SPDX-License-Identifier: GPL-2.0-or-later */ - -+#include -+#include -+#include -+#include - #include -+#include - #include -+#include -+#include - #include - #include - #include - #include - #include - -+#include "raminit_native.h" -+ -+static void wait_txt_clear(void) -+{ -+ const struct cpuid_result cpuid = cpuid_ext(1, 0); -+ -+ /* Check if TXT is supported */ -+ if (!(cpuid.ecx & BIT(6))) -+ return; -+ -+ /* Some TXT public bit */ -+ if (!(read32p(0xfed30010) & 1)) -+ return; -+ -+ /* Wait for TXT clear */ -+ do {} while (!(read8p(0xfed40000) & (1 << 7))); -+} -+ -+static enum raminit_boot_mode get_boot_mode(void) -+{ -+ const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2); -+ const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR; -+ return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD; -+} -+ - static bool early_init_native(int s3resume) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); -@@ -24,6 +56,120 @@ static bool early_init_native(int s3resume) - return cpu_replaced; - } - -+#define MRC_CACHE_VERSION 1 -+ -+struct mrc_data { -+ const void *buffer; -+ size_t buffer_len; -+}; -+ -+static void save_mrc_data(struct mrc_data *md) -+{ -+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len); -+} -+ -+static struct mrc_data prepare_mrc_cache(void) -+{ -+ struct mrc_data md = {0}; -+ md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, -+ MRC_CACHE_VERSION, -+ &md.buffer_len); -+ return md; -+} -+ -+static const char *const bm_names[] = { -+ "BOOTMODE_COLD", -+ "BOOTMODE_WARM", -+ "BOOTMODE_S3", -+ "BOOTMODE_FAST", -+}; -+ -+static void clear_disb(void) -+{ -+ pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB); -+} -+ -+static void raminit_reset(void) -+{ -+ clear_disb(); -+ system_reset(); -+} -+ -+static enum raminit_boot_mode do_actual_raminit( -+ struct mrc_data *md, -+ const bool s3resume, -+ const bool cpu_replaced, -+ const enum raminit_boot_mode orig_bootmode) -+{ -+ enum raminit_boot_mode bootmode = orig_bootmode; -+ -+ bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/ -+ -+ if (s3resume) { -+ if (bootmode == BOOTMODE_COLD) { -+ printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n"); -+ printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n"); -+ raminit_reset(); -+ } -+ /* Only a true mad hatter would replace a CPU in S3 */ -+ if (cpu_replaced) { -+ printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n"); -+ /* -+ * No reason to continue, memory consistency is most likely lost -+ * and ME will probably request a reset through DID response too. -+ */ -+ /** TODO: Figure out why past self commented this out **/ -+ //raminit_reset(); -+ } -+ bootmode = BOOTMODE_S3; -+ if (!save_data_valid) { -+ printk(BIOS_EMERG, "No training data, S3 resume is impossible\n"); -+ /* Failed S3 resume, reset to come up cleanly */ -+ raminit_reset(); -+ } -+ } -+ if (!s3resume && cpu_replaced) { -+ printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n"); -+ /* -+ * Looks like the ME will get angry if raminit takes too long. -+ * It will report that the CPU has been replaced on next boot. -+ * Try to continue anyway. This should not happen in most cases. -+ */ -+ /** TODO: Figure out why past self commented this out **/ -+ //save_data_valid = false; -+ } -+ if (bootmode == BOOTMODE_COLD) { -+ /* If possible, promote to a fast boot */ -+ if (save_data_valid) -+ bootmode = BOOTMODE_FAST; -+ -+ clear_disb(); -+ } else if (bootmode == BOOTMODE_WARM) { -+ /* If a warm reset happened before raminit is done, force a cold boot */ -+ if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) { -+ printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n"); -+ save_data_valid = false; -+ } -+ if (!save_data_valid) -+ bootmode = BOOTMODE_COLD; -+ } -+ assert(save_data_valid != (bootmode == BOOTMODE_COLD)); -+ if (save_data_valid) { -+ printk(BIOS_INFO, "Using cached memory parameters\n"); -+ die("RAMINIT: Fast boot is not yet implemented\n"); -+ } -+ printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]); -+ printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]); -+ -+ /* -+ * And now, the actual memory initialization thing. -+ */ -+ printk(RAM_DEBUG, "\nStarting native raminit\n"); -+ raminit_main(bootmode); -+ -+ return bootmode; -+} -+ - void perform_raminit(const int s3resume) - { - /* -@@ -32,17 +178,48 @@ void perform_raminit(const int s3resume) - */ - const bool cpu_replaced = early_init_native(s3resume); - -- (void)cpu_replaced; -+ wait_txt_clear(); -+ wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); -+ -+ const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -+ -+ struct mrc_data md = prepare_mrc_cache(); -+ -+ const enum raminit_boot_mode bootmode = -+ do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode); -+ -+ /** TODO: report_memory_config **/ - -- /** TODO: Move after raminit */ - if (intel_early_me_uma_size() > 0) { -- /** TODO: Update status once raminit is implemented **/ -- uint8_t me_status = ME_INIT_STATUS_ERROR; -+ /* -+ * The 'other' success value is to report loss of memory -+ * consistency to ME if warm boot was downgraded to cold. -+ */ -+ uint8_t me_status; -+ if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode) -+ me_status = ME_INIT_STATUS_SUCCESS_OTHER; -+ else -+ me_status = ME_INIT_STATUS_SUCCESS; -+ -+ /** TODO: Remove this once raminit is implemented **/ -+ me_status = ME_INIT_STATUS_ERROR; - intel_early_me_init_done(me_status); - } - -+ post_code(0x3b); -+ - intel_early_me_status(); - -- /** TODO: Implement the required magic **/ -- die("NATIVE RAMINIT: More Magic (tm) required.\n"); -+ const bool cbmem_was_initted = !cbmem_recovery(s3resume); -+ if (s3resume && !cbmem_was_initted) { -+ /* Failed S3 resume, reset to come up cleanly */ -+ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); -+ system_reset(); -+ } -+ -+ /* Save training data on non-S3 resumes */ -+ if (!s3resume) -+ save_mrc_data(&md); -+ -+ /** TODO: setup_sdram_meminfo **/ - } -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -new file mode 100644 -index 0000000000..885f0184f4 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#ifndef HASWELL_RAMINIT_NATIVE_H -+#define HASWELL_RAMINIT_NATIVE_H -+ -+enum raminit_boot_mode { -+ BOOTMODE_COLD, -+ BOOTMODE_WARM, -+ BOOTMODE_S3, -+ BOOTMODE_FAST, -+}; -+ -+enum raminit_status { -+ RAMINIT_STATUS_SUCCESS = 0, -+ RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ -+}; -+ -+enum generic_stepping { -+ STEPPING_A0 = 1, -+ STEPPING_B0 = 2, -+ STEPPING_C0 = 3, -+}; -+ -+struct sysinfo { -+ enum raminit_boot_mode bootmode; -+ enum generic_stepping stepping; -+ uint32_t cpu; /* CPUID value */ -+ -+ bool dq_pins_interleaved; -+}; -+ -+void raminit_main(enum raminit_boot_mode bootmode); -+ -+#endif --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch b/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch similarity index 94% rename from config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch rename to config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch index f433b043..9c3fe1c9 100644 --- a/config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch +++ b/config/coreboot/haswell/patches/0009-haswell-NRI-Add-range-tracking-library.patch @@ -1,7 +1,7 @@ -From 9fba0468e75877cbda62f5eaeef1946d6489a8f9 Mon Sep 17 00:00:00 2001 +From 7f5c3f8c6c8960d1c374b9c95821c19f230fa34f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 00:56:00 +0200 -Subject: [PATCH 19/26] haswell NRI: Add range tracking library +Subject: [PATCH 09/20] haswell NRI: Add range tracking library Implement a small library used to keep track of passing ranges. This will be used by 1D training algorithms when margining some parameter. @@ -9,17 +9,17 @@ will be used by 1D training algorithms when margining some parameter. Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../intel/haswell/native_raminit/ranges.c | 109 ++++++++++++++++++ .../intel/haswell/native_raminit/ranges.h | 68 +++++++++++ 3 files changed, 178 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 6e1b365602..2da950771d 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -9,6 +9,7 @@ romstage-y += io_comp_control.c romstage-y += memory_map.c romstage-y += raminit_main.c diff --git a/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch b/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch deleted file mode 100644 index 07525d18..00000000 --- a/config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 731216aef3129ae27ad5adc7266cb8a58090c9fc Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Sun, 26 Jun 2022 10:32:12 +0200 -Subject: [PATCH 09/26] nb/intel/haswell/nri: Only do CPU replacement check on - cold boots - -CPU replacement check should only be done on cold boots. - -Change-Id: I98efa105f4df755b23febe12dd7b356787847852 -Signed-off-by: Angel Pons ---- - .../intel/haswell/native_raminit/raminit_native.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index 0869db3902..bd9bc8e692 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -40,15 +40,14 @@ static enum raminit_boot_mode get_boot_mode(void) - return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD; - } - --static bool early_init_native(int s3resume) -+static bool early_init_native(enum raminit_boot_mode bootmode) - { - printk(BIOS_DEBUG, "Starting native platform initialisation\n"); - - intel_early_me_init(); -- /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ -- const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); -+ bool cpu_replaced = bootmode == BOOTMODE_COLD && intel_early_me_cpu_replacement_check(); - -- early_pch_init_native(s3resume); -+ early_pch_init_native(bootmode == BOOTMODE_S3); - - if (!CONFIG(INTEL_LYNXPOINT_LP)) - dmi_early_init(); -@@ -176,13 +175,13 @@ void perform_raminit(const int s3resume) - * See, this function's name is a lie. There are more things to - * do that memory initialisation, but they are relatively easy. - */ -- const bool cpu_replaced = early_init_native(s3resume); -+ const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -+ -+ const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode); - - wait_txt_clear(); - wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); - -- const enum raminit_boot_mode orig_bootmode = get_boot_mode(); -- - struct mrc_data md = prepare_mrc_cache(); - - const enum raminit_boot_mode bootmode = --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch b/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch similarity index 94% rename from config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch rename to config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch index 30926494..622fac5a 100644 --- a/config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch +++ b/config/coreboot/haswell/patches/0010-haswell-NRI-Add-library-to-change-margins.patch @@ -1,24 +1,24 @@ -From 54cfbe4cf53d16f747bfcfadd20445a0f5f1e5db Mon Sep 17 00:00:00 2001 +From 8ad18cc335f60a78f47ab9e5a7994f6075b6a176 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 01:11:03 +0200 -Subject: [PATCH 20/26] haswell NRI: Add library to change margins +Subject: [PATCH 10/20] haswell NRI: Add library to change margins Implement a library to change Rx/Tx margins. It will be expanded later. Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/change_margin.c | 154 ++++++++++++++++++ .../haswell/native_raminit/raminit_native.h | 50 ++++++ .../intel/haswell/registers/mchbar.h | 9 + 4 files changed, 214 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 2da950771d..ebe9e9b762 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -28,13 +28,13 @@ index 2da950771d..ebe9e9b762 100644 romstage-y += jedec_reset.c diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c new file mode 100644 -index 0000000000..12da59580f +index 0000000000..055c666eee --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include ++#include +#include +#include +#include @@ -187,7 +187,7 @@ index 0000000000..12da59580f + mchbar_write32(reg, ddr_data_control_0.raw); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 56df36ca8d..7c1a786780 100644 +index 7f19fde4cc..906b3143b9 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -117,6 +117,30 @@ enum test_stop { @@ -221,7 +221,7 @@ index 56df36ca8d..7c1a786780 100644 struct wdb_pat { uint32_t start_ptr; /* Starting pointer in WDB */ uint32_t stop_ptr; /* Stopping pointer in WDB */ -@@ -452,6 +476,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas +@@ -450,6 +474,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas void run_mpr_io_test(bool clear_errors); uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors); diff --git a/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch b/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch deleted file mode 100644 index 4c2a2670..00000000 --- a/config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch +++ /dev/null @@ -1,344 +0,0 @@ -From 354969af4361bcc7dc240ef5871d169728f7f0cc Mon Sep 17 00:00:00 2001 -From: Angel Pons -Date: Sat, 7 May 2022 13:48:53 +0200 -Subject: [PATCH 10/26] haswell NRI: Collect SPD info - -Collect SPD data from DIMMs and memory-down, and find the common -supported settings. - -Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a -Signed-off-by: Angel Pons ---- - .../intel/haswell/native_raminit/Makefile.inc | 1 + - .../haswell/native_raminit/raminit_main.c | 1 + - .../haswell/native_raminit/raminit_native.h | 57 +++++ - .../haswell/native_raminit/spd_bitmunching.c | 206 ++++++++++++++++++ - 4 files changed, 265 insertions(+) - create mode 100644 src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c - -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -index 90af951c5a..ebf7abc6ec 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc -@@ -2,3 +2,4 @@ - - romstage-y += raminit_main.c - romstage-y += raminit_native.c -+romstage-y += spd_bitmunching.c -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -index 9b42c25b40..2d2cfa48bb 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c -@@ -20,6 +20,7 @@ struct task_entry { - }; - - static const struct task_entry cold_boot[] = { -+ { collect_spd_info, true, "PROCSPD", }, - }; - - /* Return a generic stepping value to make stepping checks simpler */ -diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 885f0184f4..1a0793947e 100644 ---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h -+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -3,6 +3,15 @@ - #ifndef HASWELL_RAMINIT_NATIVE_H - #define HASWELL_RAMINIT_NATIVE_H - -+#include -+#include -+ -+#define SPD_LEN 256 -+ -+/* 8 data lanes + 1 ECC lane */ -+#define NUM_LANES 9 -+#define NUM_LANES_NO_ECC 8 -+ - enum raminit_boot_mode { - BOOTMODE_COLD, - BOOTMODE_WARM, -@@ -12,6 +21,8 @@ enum raminit_boot_mode { - - enum raminit_status { - RAMINIT_STATUS_SUCCESS = 0, -+ RAMINIT_STATUS_NO_MEMORY_INSTALLED, -+ RAMINIT_STATUS_UNSUPPORTED_MEMORY, - RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ - }; - -@@ -21,14 +32,60 @@ enum generic_stepping { - STEPPING_C0 = 3, - }; - -+struct raminit_dimm_info { -+ spd_raw_data raw_spd; -+ struct dimm_attr_ddr3_st data; -+ uint8_t spd_addr; -+ bool valid; -+}; -+ - struct sysinfo { - enum raminit_boot_mode bootmode; - enum generic_stepping stepping; - uint32_t cpu; /* CPUID value */ - - bool dq_pins_interleaved; -+ -+ /** TODO: ECC support untested **/ -+ bool is_ecc; -+ -+ /** -+ * FIXME: LPDDR support is incomplete. The largest chunks are missing, -+ * but some LPDDR-specific variations in algorithms have been handled. -+ * LPDDR-specific functions have stubs which will halt upon execution. -+ */ -+ bool lpddr; -+ -+ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; -+ union dimm_flags_ddr3_st flags; -+ uint16_t cas_supported; -+ -+ /* Except for tCK, everything is eventually stored in DCLKs */ -+ uint32_t tCK; -+ uint32_t tAA; /* Also known as tCL */ -+ uint32_t tWR; -+ uint32_t tRCD; -+ uint32_t tRRD; -+ uint32_t tRP; -+ uint32_t tRAS; -+ uint32_t tRC; -+ uint32_t tRFC; -+ uint32_t tWTR; -+ uint32_t tRTP; -+ uint32_t tFAW; -+ uint32_t tCWL; -+ uint32_t tCMD; -+ -+ uint8_t lanes; /* 8 or 9 */ -+ uint8_t chanmap; -+ uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */ -+ uint8_t rankmap[NUM_CHANNELS]; -+ uint8_t rank_mirrored[NUM_CHANNELS]; -+ uint32_t channel_size_mb[NUM_CHANNELS]; - }; - - void raminit_main(enum raminit_boot_mode bootmode); - -+enum raminit_status collect_spd_info(struct sysinfo *ctrl); -+ - #endif -diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -new file mode 100644 -index 0000000000..dbe02c72d0 ---- /dev/null -+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c -@@ -0,0 +1,206 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "raminit_native.h" -+ -+static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi) -+{ -+ if (!CONFIG(HAVE_SPD_IN_CBFS)) -+ return NULL; -+ -+ printk(RAM_DEBUG, "SPD index %u\n", spdi->spd_index); -+ -+ size_t spd_file_len; -+ uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len); -+ -+ if (!spd_file) { -+ printk(BIOS_ERR, "SPD data not found in CBFS\n"); -+ return NULL; -+ } -+ -+ if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) { -+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); -+ spdi->spd_index = 0; -+ } -+ -+ if (spd_file_len < SPD_LEN) { -+ printk(BIOS_ERR, "Invalid SPD data in CBFS\n"); -+ return NULL; -+ } -+ -+ return spd_file + (spdi->spd_index * SPD_LEN); -+} -+ -+static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd) -+{ -+ if (dimm->spd_addr == SPD_MEMORY_DOWN) { -+ if (cbfs_spd) { -+ memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN); -+ dimm->valid = true; -+ printk(RAM_DEBUG, "memory-down\n"); -+ return; -+ } else { -+ printk(RAM_DEBUG, "memory-down but no CBFS SPD data, ignoring\n"); -+ return; -+ } -+ } -+ printk(RAM_DEBUG, "slotted "); -+ const uint8_t spd_mem_type = smbus_read_byte(dimm->spd_addr, SPD_MEMORY_TYPE); -+ if (spd_mem_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { -+ printk(RAM_DEBUG, "and not DDR3, ignoring\n"); -+ return; -+ } -+ printk(RAM_DEBUG, "and DDR3\n"); -+ if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) { -+ printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n"); -+ for (uint32_t i = 0; i < SPD_LEN; i++) -+ dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i); -+ } -+ dimm->valid = true; -+} -+ -+static void get_spd_data(struct sysinfo *ctrl) -+{ -+ struct spd_info spdi = {0}; -+ mb_get_spd_map(&spdi); -+ const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi); -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot]; -+ dimm->spd_addr = spdi.addresses[channel + channel + slot]; -+ if (!dimm->spd_addr) -+ continue; -+ -+ printk(RAM_DEBUG, "CH%uS%u is ", channel, slot); -+ get_spd_for_dimm(dimm, cbfs_spd); -+ } -+ } -+} -+ -+static void decode_spd(struct raminit_dimm_info *const dimm) -+{ -+ /** TODO: Hook up somewhere, and handle lack of XMP data **/ -+ const bool enable_xmp = false; -+ memset(&dimm->data, 0, sizeof(dimm->data)); -+ if (enable_xmp) -+ spd_xmp_decode_ddr3(&dimm->data, dimm->raw_spd, DDR3_XMP_PROFILE_1); -+ else -+ spd_decode_ddr3(&dimm->data, dimm->raw_spd); -+ -+ if (CONFIG(DEBUG_RAM_SETUP)) -+ dram_print_spd_ddr3(&dimm->data); -+} -+ -+static enum raminit_status find_common_spd_parameters(struct sysinfo *ctrl) -+{ -+ ctrl->cas_supported = 0xffff; -+ ctrl->flags.raw = 0xffffffff; -+ -+ ctrl->tCK = 0; -+ ctrl->tAA = 0; -+ ctrl->tWR = 0; -+ ctrl->tRCD = 0; -+ ctrl->tRRD = 0; -+ ctrl->tRP = 0; -+ ctrl->tRAS = 0; -+ ctrl->tRC = 0; -+ ctrl->tRFC = 0; -+ ctrl->tWTR = 0; -+ ctrl->tRTP = 0; -+ ctrl->tFAW = 0; -+ ctrl->tCWL = 0; -+ ctrl->tCMD = 0; -+ ctrl->chanmap = 0; -+ -+ bool yes_ecc = false; -+ bool not_ecc = false; -+ -+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { -+ ctrl->dpc[channel] = 0; -+ ctrl->rankmap[channel] = 0; -+ ctrl->rank_mirrored[channel] = 0; -+ ctrl->channel_size_mb[channel] = 0; -+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { -+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot]; -+ if (!dimm->valid) -+ continue; -+ -+ printk(RAM_DEBUG, "\nCH%uS%u SPD:\n", channel, slot); -+ decode_spd(dimm); -+ -+ ctrl->chanmap |= BIT(channel); -+ ctrl->dpc[channel]++; -+ ctrl->channel_size_mb[channel] += dimm->data.size_mb; -+ -+ /* The first rank of a populated slot is always present */ -+ const uint8_t rank = slot + slot; -+ assert(dimm->data.ranks); -+ ctrl->rankmap[channel] |= (BIT(dimm->data.ranks) - 1) << rank; -+ -+ if (dimm->data.flags.pins_mirrored) -+ ctrl->rank_mirrored[channel] |= BIT(rank + 1); -+ -+ /* Find common settings */ -+ ctrl->cas_supported &= dimm->data.cas_supported; -+ ctrl->flags.raw &= dimm->data.flags.raw; -+ ctrl->tCK = MAX(ctrl->tCK, dimm->data.tCK); -+ ctrl->tAA = MAX(ctrl->tAA, dimm->data.tAA); -+ ctrl->tWR = MAX(ctrl->tWR, dimm->data.tWR); -+ ctrl->tRCD = MAX(ctrl->tRCD, dimm->data.tRCD); -+ ctrl->tRRD = MAX(ctrl->tRRD, dimm->data.tRRD); -+ ctrl->tRP = MAX(ctrl->tRP, dimm->data.tRP); -+ ctrl->tRAS = MAX(ctrl->tRAS, dimm->data.tRAS); -+ ctrl->tRC = MAX(ctrl->tRC, dimm->data.tRC); -+ ctrl->tRFC = MAX(ctrl->tRFC, dimm->data.tRFC); -+ ctrl->tWTR = MAX(ctrl->tWTR, dimm->data.tWTR); -+ ctrl->tRTP = MAX(ctrl->tRTP, dimm->data.tRTP); -+ ctrl->tFAW = MAX(ctrl->tFAW, dimm->data.tFAW); -+ ctrl->tCWL = MAX(ctrl->tCWL, dimm->data.tCWL); -+ ctrl->tCMD = MAX(ctrl->tCMD, dimm->data.tCMD); -+ -+ yes_ecc |= dimm->data.flags.is_ecc; -+ not_ecc |= !dimm->data.flags.is_ecc; -+ } -+ } -+ -+ if (!ctrl->chanmap) { -+ printk(BIOS_ERR, "No DIMMs were found\n"); -+ return RAMINIT_STATUS_NO_MEMORY_INSTALLED; -+ } -+ if (!ctrl->cas_supported) { -+ printk(BIOS_ERR, "Could not resolve common CAS latency\n"); -+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY; -+ } -+ /** TODO: Properly handle ECC support and ECC forced **/ -+ if (yes_ecc && not_ecc) { -+ /** TODO: Test if the ECC DIMMs can be operated as non-ECC DIMMs **/ -+ printk(BIOS_ERR, "Both ECC and non-ECC DIMMs present, this is unsupported\n"); -+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY; -+ } -+ if (yes_ecc) -+ ctrl->lanes = NUM_LANES; -+ else -+ ctrl->lanes = NUM_LANES_NO_ECC; -+ -+ ctrl->is_ecc = yes_ecc; -+ -+ /** TODO: Complete LPDDR support **/ -+ ctrl->lpddr = false; -+ -+ return RAMINIT_STATUS_SUCCESS; -+} -+ -+enum raminit_status collect_spd_info(struct sysinfo *ctrl) -+{ -+ get_spd_data(ctrl); -+ return find_common_spd_parameters(ctrl); -+} --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch b/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch similarity index 98% rename from config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch rename to config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch index 9139a67e..4815be9a 100644 --- a/config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch +++ b/config/coreboot/haswell/patches/0011-haswell-NRI-Add-RcvEn-training.patch @@ -1,14 +1,14 @@ -From ac8843553af34855d0331554c03280e66c4ea582 Mon Sep 17 00:00:00 2001 +From 4254a9ff03658d7a6f1a4e32cfe4c65dbfc072f8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 00:05:41 +0200 -Subject: [PATCH 21/26] haswell NRI: Add RcvEn training +Subject: [PATCH 11/20] haswell NRI: Add RcvEn training Implement the RcvEn (Receive Enable) calibration procedure. Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 14 + .../haswell/native_raminit/reg_structs.h | 13 + @@ -17,10 +17,10 @@ Signed-off-by: Angel Pons 6 files changed, 593 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index ebe9e9b762..e2fbfb4211 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,3 +16,4 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -39,7 +39,7 @@ index 5e4674957d..7d444659c3 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 7c1a786780..a36ebfacd1 100644 +index 906b3143b9..b4e8c7de5a 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -42,6 +42,9 @@ @@ -83,7 +83,7 @@ index 7c1a786780..a36ebfacd1 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -401,6 +414,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); +@@ -399,6 +412,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch b/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch similarity index 96% rename from config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch rename to config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch index 2e6de17c..f4f5161e 100644 --- a/config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch +++ b/config/coreboot/haswell/patches/0012-haswell-NRI-Add-function-to-change-margins.patch @@ -1,7 +1,7 @@ -From 8c3874195c0fc1af9d0b84611496689da1c19d8c Mon Sep 17 00:00:00 2001 +From c24b26594bfab47a8709ed7fb5cb77307fb73a53 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 11:58:59 +0200 -Subject: [PATCH 22/26] haswell NRI: Add function to change margins +Subject: [PATCH 12/20] haswell NRI: Add function to change margins Implement a function to change margin parameters. Haswell provides a register to apply an offset to margin parameters during training, so @@ -19,14 +19,14 @@ Signed-off-by: Angel Pons 4 files changed, 188 insertions(+) diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c -index 12da59580f..4ba9cfa5c6 100644 +index 055c666eee..299c44a6b0 100644 --- a/src/northbridge/intel/haswell/native_raminit/change_margin.c +++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include - #include + #include #include #include @@ -152,3 +153,138 @@ void download_regfile( @@ -169,7 +169,7 @@ index 12da59580f..4ba9cfa5c6 100644 + change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile); +} diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index a36ebfacd1..500fc28909 100644 +index b4e8c7de5a..5242b16f28 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -35,6 +35,18 @@ @@ -206,7 +206,7 @@ index a36ebfacd1..500fc28909 100644 /* ZQ calibration types */ enum { ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */ -@@ -516,6 +536,25 @@ void download_regfile( +@@ -514,6 +534,25 @@ void download_regfile( bool read_rf_rd, bool read_rf_wr); diff --git a/config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch b/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch similarity index 93% rename from config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch rename to config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch index b13eb2db..5f154bcc 100644 --- a/config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch +++ b/config/coreboot/haswell/patches/0013-haswell-NRI-Add-read-MPR-training.patch @@ -1,25 +1,25 @@ -From 6781cec818501f7afd6ee26464fd4556ac3068cb Mon Sep 17 00:00:00 2001 +From e263f0d2e9d6d016d603342651da261bbcb6af1f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 11:35:49 +0200 -Subject: [PATCH 23/26] haswell NRI: Add read MPR training +Subject: [PATCH 13/20] haswell NRI: Add read MPR training Implement read training using DDR3 MPR (Multi-Purpose Register). Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 4 + - .../haswell/native_raminit/train_read_mpr.c | 240 ++++++++++++++++++ + .../haswell/native_raminit/train_read_mpr.c | 241 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 2 +- - 5 files changed, 247 insertions(+), 1 deletion(-) + 5 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index e2fbfb4211..c442be0728 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,4 +16,5 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -39,7 +39,7 @@ index 7d444659c3..264d1468f5 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 500fc28909..a7551ad63c 100644 +index 5242b16f28..49e9214656 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -27,6 +27,8 @@ @@ -59,7 +59,7 @@ index 500fc28909..a7551ad63c 100644 RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ }; -@@ -435,6 +438,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); +@@ -433,6 +436,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl); enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); @@ -69,13 +69,13 @@ index 500fc28909..a7551ad63c 100644 void configure_refresh(struct sysinfo *ctrl); diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c new file mode 100644 -index 0000000000..0225e1a384 +index 0000000000..ade1e36148 --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c -@@ -0,0 +1,240 @@ +@@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + -+#include ++#include +#include +#include +#include @@ -206,7 +206,8 @@ index 0000000000..0225e1a384 + for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) { + printk(RMPR_PLOT, "% 5d", dqs_delay); + const enum regfile_mode regfile = REG_FILE_USE_START; -+ change_1d_margin_multicast(ctrl, RdT, dqs_delay, 0, false, regfile); ++ /* Looks like MRC uses rank 0 here, but it feels wrong */ ++ change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile); + for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { + if (!rank_in_ch(ctrl, rank, channel)) + continue; diff --git a/config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch b/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch similarity index 96% rename from config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch rename to config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch index 59e9af9d..5a96cd1f 100644 --- a/config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch +++ b/config/coreboot/haswell/patches/0014-haswell-NRI-Add-write-leveling.patch @@ -1,7 +1,7 @@ -From 20fe4fa852d3e13851a01b51dc984ec5976c864e Mon Sep 17 00:00:00 2001 +From bebe0b74bede64b03aa1e3781310ef539465627b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 12:56:04 +0200 -Subject: [PATCH 24/26] haswell NRI: Add write leveling +Subject: [PATCH 14/20] haswell NRI: Add write leveling Implement JEDEC write leveling, which is done in two steps. The first step uses the JEDEC procedure to do "fine" write leveling, i.e. align @@ -11,18 +11,18 @@ read-write test to correct "coarse" cycle errors. Change-Id: I27678523fe22c38173a688e2a4751c259a20f009 Signed-off-by: Angel Pons --- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/raminit_main.c | 1 + .../haswell/native_raminit/raminit_native.h | 10 + - .../train_jedec_write_leveling.c | 580 ++++++++++++++++++ + .../train_jedec_write_leveling.c | 581 ++++++++++++++++++ .../intel/haswell/registers/mchbar.h | 2 + - 5 files changed, 594 insertions(+) + 5 files changed, 595 insertions(+) create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index c442be0728..40c2f5e014 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -16,5 +16,6 @@ romstage-y += setup_wdb.c romstage-y += spd_bitmunching.c romstage-y += testing_io.c @@ -43,7 +43,7 @@ index 264d1468f5..1ff23be615 100644 /* Return a generic stepping value to make stepping checks simpler */ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index a7551ad63c..666b233c45 100644 +index 49e9214656..86d89f2120 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -59,6 +59,9 @@ @@ -76,7 +76,7 @@ index a7551ad63c..666b233c45 100644 /* Number of ticks to wait in units of 69.841279 ns (citation needed) */ static inline void tick_delay(const uint32_t delay) { -@@ -439,6 +448,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); +@@ -437,6 +446,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl); enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); @@ -86,10 +86,10 @@ index a7551ad63c..666b233c45 100644 void configure_refresh(struct sysinfo *ctrl); diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c new file mode 100644 -index 0000000000..1ba28a3bd4 +index 0000000000..ef6483e2bd --- /dev/null +++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c -@@ -0,0 +1,580 @@ +@@ -0,0 +1,581 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include @@ -106,7 +106,8 @@ index 0000000000..1ba28a3bd4 + +static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank) +{ -+ reut_issue_mrs(ctrl, channel, BIT(rank), 0, ctrl->mr0[channel][rank] | MR0_DLL_RESET); ++ const uint16_t mr0reg = ctrl->mr0[channel][rank / 2]; ++ reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET); +} + +static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert) @@ -463,7 +464,7 @@ index 0000000000..1ba28a3bd4 + continue; + + /** TODO: Differs for LPDDR **/ -+ uint16_t mr1reg = ctrl->mr1[channel][rank]; ++ uint16_t mr1reg = ctrl->mr1[channel][rank / 2]; + mr1reg &= ~MR1_QOFF_ENABLE; + mr1reg |= MR1_WL_ENABLE; + if (is_hsw_ult()) { @@ -605,7 +606,7 @@ index 0000000000..1ba28a3bd4 + mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0); + + /** TODO: Differs for LPDDR **/ -+ const uint16_t mr1reg = ctrl->mr1[channel][rank] | MR1_QOFF_ENABLE; ++ const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE; + reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg); + + printk(BIOS_DEBUG, "\nC%u.R%u: LftEdge Width\n", channel, rank); diff --git a/config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch b/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch similarity index 96% rename from config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch rename to config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch index d15ea5d1..3626bf6d 100644 --- a/config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch +++ b/config/coreboot/haswell/patches/0015-haswell-NRI-Add-final-raminit-steps.patch @@ -1,7 +1,7 @@ -From d041b14f3af69db5f4598c84e3f53c9cd572ffb5 Mon Sep 17 00:00:00 2001 +From eba8680d618db95028e3f984f25881df0e67abf7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 8 May 2022 14:29:05 +0200 -Subject: [PATCH 25/26] haswell NRI: Add final raminit steps +Subject: [PATCH 15/20] haswell NRI: Add final raminit steps Implement the remaining raminit steps. Although many training steps are missing, this is enough to boot on the Asrock B85M Pro4. @@ -10,7 +10,7 @@ Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21 Signed-off-by: Angel Pons --- src/northbridge/intel/haswell/Kconfig | 4 +- - .../intel/haswell/native_raminit/Makefile.inc | 1 + + .../intel/haswell/native_raminit/Makefile.mk | 1 + .../haswell/native_raminit/activate_mc.c | 388 ++++++++++++++++++ .../haswell/native_raminit/raminit_main.c | 5 +- .../haswell/native_raminit/raminit_native.c | 5 +- @@ -21,10 +21,10 @@ Signed-off-by: Angel Pons create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig -index b659bf6d98..61f2a3c64c 100644 +index 4b83a25bc1..c6ab27184e 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig -@@ -10,12 +10,12 @@ config NORTHBRIDGE_INTEL_HASWELL +@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL if NORTHBRIDGE_INTEL_HASWELL config USE_NATIVE_RAMINIT @@ -39,10 +39,10 @@ index b659bf6d98..61f2a3c64c 100644 config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT -diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk index 40c2f5e014..d97da72890 100644 ---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc -+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later @@ -466,10 +466,10 @@ index 1ff23be615..3a65fb01fb 100644 - die("NATIVE RAMINIT: More Magic (tm) required.\n"); } diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -index bd9bc8e692..1ea729b23d 100644 +index 2fed93de5b..5f7ceec222 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c -@@ -200,8 +200,6 @@ void perform_raminit(const int s3resume) +@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume) else me_status = ME_INIT_STATUS_SUCCESS; @@ -478,7 +478,7 @@ index bd9bc8e692..1ea729b23d 100644 intel_early_me_init_done(me_status); } -@@ -217,7 +215,8 @@ void perform_raminit(const int s3resume) +@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume) } /* Save training data on non-S3 resumes */ @@ -489,10 +489,10 @@ index bd9bc8e692..1ea729b23d 100644 /** TODO: setup_sdram_meminfo **/ diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -index 666b233c45..98e39cb76e 100644 +index 86d89f2120..9bab57b518 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h -@@ -449,6 +449,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); +@@ -447,6 +447,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); enum raminit_status train_receive_enable(struct sysinfo *ctrl); enum raminit_status train_read_mpr(struct sysinfo *ctrl); enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); diff --git a/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch b/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch new file mode 100644 index 00000000..c2fd8b60 --- /dev/null +++ b/config/coreboot/haswell/patches/0016-Haswell-NRI-Implement-fast-boot-path.patch @@ -0,0 +1,722 @@ +From c7d6a901edf648f0f02dd2053337bcf3a319e49b Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Sat, 13 Apr 2024 01:16:30 +0200 +Subject: [PATCH 16/20] Haswell NRI: Implement fast boot path + +When the memory configuration hasn't changed, there is no need to do +full memory training. Instead, boot firmware can use saved training +data to reinitialise the memory controller and memory. + +Unlike native RAM init for other platforms, Haswell does not save the +main structure (the "mighty ctrl" struct) to flash. Instead, separate +structures define the data to be saved, which can be smaller than the +main structure. + +This makes S3 suspend and resume work: RAM contents MUST be preserved +for a S3 resume to succeed, but RAM training destroys RAM contents. + +Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6 +Signed-off-by: Angel Pons +--- + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/activate_mc.c | 17 + + .../intel/haswell/native_raminit/ddr3.c | 41 ++ + .../haswell/native_raminit/raminit_main.c | 34 +- + .../haswell/native_raminit/raminit_native.c | 30 +- + .../haswell/native_raminit/raminit_native.h | 18 + + .../haswell/native_raminit/save_restore.c | 387 ++++++++++++++++++ + 7 files changed, 504 insertions(+), 24 deletions(-) + create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c + +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +index d97da72890..8fdd17c542 100644 +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +@@ -13,6 +13,7 @@ romstage-y += raminit_main.c + romstage-y += raminit_native.c + romstage-y += ranges.c + romstage-y += reut.c ++romstage-y += save_restore.c + romstage-y += setup_wdb.c + romstage-y += spd_bitmunching.c + romstage-y += testing_io.c +diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c +index 78a7ad27ef..0b3eb917da 100644 +--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c ++++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c +@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl) + return RAMINIT_STATUS_SUCCESS; + } + ++enum raminit_status normal_state(struct sysinfo *ctrl) ++{ ++ /* Enable periodic COMP */ ++ mchbar_write32(M_COMP, (union pcu_comp_reg) { ++ .comp_interval = COMP_INT, ++ }.raw); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Set MC to normal mode and clean the ODT and CKE */ ++ mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12); ++ } ++ power_down_config(ctrl); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ + static void mc_lockdown(void) + { + /* Lock memory controller registers */ +diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c +index 6ddb11488b..9b6368edb1 100644 +--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c ++++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c +@@ -2,6 +2,7 @@ + + #include + #include ++#include + #include + #include + +@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl) + ddr3_program_mr0(ctrl, 1); + return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT); + } ++ ++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl) ++{ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Fields in ctrl aren't populated on a warm boot */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = mchbar_read32(DQ_CONTROL_0(channel, 0)), ++ }; ++ data_control_0.read_rf_rd = 1; ++ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) { ++ if (!rank_in_ch(ctrl, rank, channel)) ++ continue; ++ ++ data_control_0.read_rf_rank = rank; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ } ++ } ++ ++ /* Time needed to stabilize the DCLK (~6 us) */ ++ udelay(6); ++ ++ /* Pull the DIMMs out of self refresh by asserting CKE high */ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = { ++ .cke_on = ctrl->rankmap[channel], ++ }; ++ mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw); ++ } ++ mchbar_write32(REUT_MISC_ODT_CTRL, 0); ++ ++ const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG); ++ if (status) { ++ /* ZQCL errors don't seem to be a fatal problem here */ ++ printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n"); ++ } ++ return RAMINIT_STATUS_SUCCESS; ++} +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +index 3a65fb01fb..056dde1adc 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = { + { train_read_mpr, true, "RDMPRT", }, + { train_jedec_write_leveling, true, "JWRL", }, + { activate_mc, true, "ACTIVATE", }, ++ { save_training_values, true, "SAVE_TRAIN", }, ++ { save_non_training, true, "SAVE_NONT", }, ++ { raminit_done, true, "RAMINITEND", }, ++}; ++ ++static const struct task_entry fast_boot[] = { ++ { collect_spd_info, true, "PROCSPD", }, ++ { restore_non_training, true, "RST_NONT", }, ++ { initialise_mpll, true, "INITMPLL", }, ++ { configure_mc, true, "CONFMC", }, ++ { configure_memory_map, true, "MEMMAP", }, ++ { do_jedec_init, true, "JEDECINIT", }, ++ { pre_training, true, "PRETRAIN", }, ++ { restore_training_values, true, "RST_TRAIN", }, ++ { exit_selfrefresh, true, "EXIT_SR", }, ++ { normal_state, true, "NORMALMODE", }, + { raminit_done, true, "RAMINITEND", }, + }; + +@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl) + ctrl->bootmode = bootmode; + } + +-static enum raminit_status try_raminit(struct sysinfo *ctrl) ++static enum raminit_status try_raminit( ++ struct sysinfo *ctrl, ++ const struct task_entry *const schedule, ++ const size_t length) + { +- const struct task_entry *const schedule = cold_boot; +- const size_t length = ARRAY_SIZE(cold_boot); +- + enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; + + for (size_t i = 0; i < length; i++) { +@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode) + mighty_ctrl.bootmode = bootmode; + initialize_ctrl(&mighty_ctrl); + ++ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; ++ ++ if (bootmode != BOOTMODE_COLD) { ++ status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot)); ++ if (status == RAMINIT_STATUS_SUCCESS) ++ return; ++ } ++ + /** TODO: Try more than once **/ +- enum raminit_status status = try_raminit(&mighty_ctrl); ++ status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot)); + + if (status != RAMINIT_STATUS_SUCCESS) + die("Memory initialization was met with utmost failure and misery\n"); +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +index 5f7ceec222..3ad8ce29e7 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode) + return cpu_replaced; + } + +-#define MRC_CACHE_VERSION 1 +- +-struct mrc_data { +- const void *buffer; +- size_t buffer_len; +-}; +- +-static void save_mrc_data(struct mrc_data *md) ++static void save_mrc_data(void) + { +- mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len); ++ mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(), ++ reg_frame_ptr(), reg_frame_size()); + } + + static struct mrc_data prepare_mrc_cache(void) + { + struct mrc_data md = {0}; + md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, +- MRC_CACHE_VERSION, ++ reg_frame_rev(), + &md.buffer_len); + return md; + } +@@ -94,14 +88,15 @@ static void raminit_reset(void) + } + + static enum raminit_boot_mode do_actual_raminit( +- struct mrc_data *md, + const bool s3resume, + const bool cpu_replaced, + const enum raminit_boot_mode orig_bootmode) + { ++ struct mrc_data md = prepare_mrc_cache(); ++ + enum raminit_boot_mode bootmode = orig_bootmode; + +- bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/ ++ bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size(); + + if (s3resume) { + if (bootmode == BOOTMODE_COLD) { +@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit( + assert(save_data_valid != (bootmode == BOOTMODE_COLD)); + if (save_data_valid) { + printk(BIOS_INFO, "Using cached memory parameters\n"); +- die("RAMINIT: Fast boot is not yet implemented\n"); ++ memcpy(reg_frame_ptr(), md.buffer, reg_frame_size()); + } + printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]); + printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]); +@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume) + wait_txt_clear(); + wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0}); + +- struct mrc_data md = prepare_mrc_cache(); +- + const enum raminit_boot_mode bootmode = +- do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode); ++ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); + + /** TODO: report_memory_config **/ + +@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume) + } + + /* Save training data on non-S3 resumes */ +- /** TODO: Enable this once training data is populated **/ +- if (0 && !s3resume) +- save_mrc_data(&md); ++ if (!s3resume) ++ save_mrc_data(); + + /** TODO: setup_sdram_meminfo **/ + } +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index 9bab57b518..0750904aec 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -169,6 +169,8 @@ enum regfile_mode { + REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */ + }; + ++struct register_save_frame; ++ + struct wdb_pat { + uint32_t start_ptr; /* Starting pointer in WDB */ + uint32_t stop_ptr; /* Stopping pointer in WDB */ +@@ -219,6 +221,7 @@ enum raminit_status { + RAMINIT_STATUS_RCVEN_FAILURE, + RAMINIT_STATUS_RMPR_FAILURE, + RAMINIT_STATUS_JWRL_FAILURE, ++ RAMINIT_STATUS_INVALID_CACHE, + RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ + }; + +@@ -228,6 +231,11 @@ enum generic_stepping { + STEPPING_C0 = 3, + }; + ++struct mrc_data { ++ const void *buffer; ++ size_t buffer_len; ++}; ++ + struct raminit_dimm_info { + spd_raw_data raw_spd; + struct dimm_attr_ddr3_st data; +@@ -447,12 +455,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl); + enum raminit_status train_receive_enable(struct sysinfo *ctrl); + enum raminit_status train_read_mpr(struct sysinfo *ctrl); + enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); ++enum raminit_status save_training_values(struct sysinfo *ctrl); ++enum raminit_status restore_training_values(struct sysinfo *ctrl); ++enum raminit_status save_non_training(struct sysinfo *ctrl); ++enum raminit_status restore_non_training(struct sysinfo *ctrl); ++enum raminit_status exit_selfrefresh(struct sysinfo *ctrl); ++enum raminit_status normal_state(struct sysinfo *ctrl); + enum raminit_status activate_mc(struct sysinfo *ctrl); + enum raminit_status raminit_done(struct sysinfo *ctrl); + + void configure_timings(struct sysinfo *ctrl); + void configure_refresh(struct sysinfo *ctrl); + ++struct register_save_frame *reg_frame_ptr(void); ++size_t reg_frame_size(void); ++uint32_t reg_frame_rev(void); ++ + uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr); + uint32_t get_tXPDLL(uint32_t mem_clock_mhz); + uint32_t get_tAONPD(uint32_t mem_clock_mhz); +diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c +new file mode 100644 +index 0000000000..f1f50e3ff8 +--- /dev/null ++++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c +@@ -0,0 +1,387 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++#include ++#include ++#include ++ ++#include "raminit_native.h" ++ ++uint32_t reg_frame_rev(void) ++{ ++ /* ++ * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction. ++ * The structures that get saved to flash are contained within ++ * this translation unit, so changes outside this file shouldn't ++ * require invalidating the cache. ++ */ ++ return 1; ++} ++ ++struct register_save { ++ uint16_t lower; ++ uint16_t upper; ++}; ++ ++/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/ ++static const struct register_save ddrio_per_byte_list[] = { ++ {0x0000, 0x003c}, /* 16 registers */ ++// {0x0048, 0x0084}, /* 16 registers */ /** TODO: BDW support **/ ++ {0x0048, 0x004c}, /* 2 registers */ ++ {0x005c, 0x0078}, /* 8 registers */ ++}; ++#define DDRIO_PER_BYTE_REGISTER_COUNT (16 + 2 + 8) ++ ++static const struct register_save ddrio_per_ch_list[] = { ++ /* CKE */ ++ {0x1204, 0x1208}, /* 2 registers */ ++ {0x1214, 0x121c}, /* 3 registers */ ++ /* CMD North */ ++ {0x1404, 0x140c}, /* 3 registers */ ++ /* CLK */ ++ {0x1808, 0x1810}, /* 3 registers */ ++ /* CMD South */ ++ {0x1a04, 0x1a0c}, /* 3 registers */ ++ /* CTL */ ++ {0x1c14, 0x1c1c}, /* 3 registers */ ++}; ++#define DDRIO_PER_CH_REGISTER_COUNT (2 + 3 * 5) ++ ++static const struct register_save ddrio_common_list[] = { ++ {0x2000, 0x2008}, /* 3 registers */ ++ {0x3a14, 0x3a1c}, /* 3 registers */ ++ {0x3a24, 0x3a24}, /* 1 registers */ ++}; ++ ++#define DDRIO_COMMON_REGISTER_COUNT (3 + 3 + 1) ++ ++static const struct register_save mcmain_per_ch_list[] = { ++ {0x4000, 0x4014}, /* 6 registers */ ++ {0x4024, 0x4028}, /* 2 registers */ ++ {0x40d0, 0x40d0}, /* 1 registers */ ++ {0x4220, 0x4224}, /* 2 registers */ ++ {0x4294, 0x4294}, /* 1 registers */ ++ {0x429c, 0x42a0}, /* 2 registers */ ++ {0x42ec, 0x42fc}, /* 5 registers */ ++ {0x4328, 0x4328}, /* 1 registers */ ++ {0x438c, 0x4390}, /* 2 registers */ ++}; ++#define MCMAIN_PER_CH_REGISTER_COUNT (6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2) ++ ++static const struct register_save misc_common_list[] = { ++ {0x5884, 0x5888}, /* 2 registers */ ++ {0x5890, 0x589c}, /* 4 registers */ ++ {0x58a4, 0x58a4}, /* 1 registers */ ++ {0x58d0, 0x58e4}, /* 6 registers */ ++ {0x5880, 0x5880}, /* 1 registers */ ++ {0x5000, 0x50dc}, /* 56 registers */ ++ {0x59b8, 0x59b8} /* 1 registers */ ++}; ++#define MISC_COMMON_REGISTER_COUNT (2 + 4 + 1 + 6 + 1 + 56 + 1) ++ ++struct save_params { ++ bool is_initialised; ++ ++ /* Memory base frequency, either 100 or 133 MHz */ ++ uint8_t base_freq; ++ ++ /* Multiplier */ ++ uint32_t multiplier; ++ ++ /* Memory clock in MHz */ ++ uint32_t mem_clock_mhz; ++ ++ /* Memory clock in femtoseconds */ ++ uint32_t mem_clock_fs; ++ ++ /* Quadrature clock in picoseconds */ ++ uint16_t qclkps; ++ ++ /* Bitfield of supported CAS latencies */ ++ uint16_t cas_supported; ++ ++ /* CPUID value */ ++ uint32_t cpu; ++ ++ /* Cached CPU stepping value */ ++ uint8_t stepping; ++ ++ uint16_t vdd_mv; ++ ++ union dimm_flags_ddr3_st flags; ++ ++ /* Except for tCK, everything is stored in DCLKs */ ++ uint32_t tCK; ++ uint32_t tAA; ++ uint32_t tWR; ++ uint32_t tRCD; ++ uint32_t tRRD; ++ uint32_t tRP; ++ uint32_t tRAS; ++ uint32_t tRC; ++ uint32_t tRFC; ++ uint32_t tWTR; ++ uint32_t tRTP; ++ uint32_t tFAW; ++ uint32_t tCWL; ++ uint32_t tCMD; ++ ++ uint32_t tREFI; ++ uint32_t tXP; ++ ++ uint8_t lpddr_cke_rank_map[NUM_CHANNELS]; ++ ++ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; ++ ++ uint8_t chanmap; ++ ++ uint32_t channel_size_mb[NUM_CHANNELS]; ++ ++ /* DIMMs per channel */ ++ uint8_t dpc[NUM_CHANNELS]; ++ ++ uint8_t rankmap[NUM_CHANNELS]; ++ ++ /* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */ ++ uint8_t rank_mirrored[NUM_CHANNELS]; ++ ++ /* ++ * FIXME: LPDDR support is incomplete. The largest chunks are missing, ++ * but some LPDDR-specific variations in algorithms have been handled. ++ * LPDDR-specific functions have stubs which will halt upon execution. ++ */ ++ bool lpddr; ++ ++ uint8_t lanes; ++ ++ /* FIXME: ECC support missing */ ++ bool is_ecc; ++}; ++ ++struct register_save_frame { ++ uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT]; ++ uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT]; ++ uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT]; ++ uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT]; ++ uint32_t misc_common[MISC_COMMON_REGISTER_COUNT]; ++ struct save_params params; ++}; ++ ++struct register_save_frame *reg_frame_ptr(void) ++{ ++ /* The chonky register save frame struct, used for fast boot and S3 resume */ ++ static struct register_save_frame register_frame = { 0 }; ++ return ®ister_frame; ++} ++ ++size_t reg_frame_size(void) ++{ ++ return sizeof(struct register_save_frame); ++} ++ ++typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value); ++ ++static void save_value(const uint16_t offset, uint32_t *const value) ++{ ++ *value = mchbar_read32(offset); ++} ++ ++static void restore_value(const uint16_t offset, uint32_t *const value) ++{ ++ mchbar_write32(offset, *value); ++} ++ ++static void save_restore( ++ uint32_t *reg_frame, ++ const uint16_t g_offset, ++ const struct register_save *reg_save_list, ++ const size_t reg_save_length, ++ reg_func_t handle_reg) ++{ ++ for (size_t i = 0; i < reg_save_length; i++) { ++ const struct register_save *entry = ®_save_list[i]; ++ for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) { ++ handle_reg(offset + g_offset, reg_frame++); ++ } ++ } ++} ++ ++static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg) ++{ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t byte = 0; byte < NUM_LANES; byte++) { ++ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte); ++ save_restore( ++ reg_frame->ddrio_per_byte[channel][byte], ++ g_offset, ++ ddrio_per_byte_list, ++ ARRAY_SIZE(ddrio_per_byte_list), ++ handle_reg); ++ } ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0); ++ save_restore( ++ reg_frame->ddrio_per_ch[channel], ++ g_offset, ++ ddrio_per_ch_list, ++ ARRAY_SIZE(ddrio_per_ch_list), ++ handle_reg); ++ } ++ save_restore( ++ reg_frame->ddrio_common, ++ 0, ++ ddrio_common_list, ++ ARRAY_SIZE(ddrio_common_list), ++ handle_reg); ++ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ const uint16_t g_offset = _MCMAIN_C(0, channel); ++ save_restore( ++ reg_frame->mcmain_per_ch[channel], ++ g_offset, ++ mcmain_per_ch_list, ++ ARRAY_SIZE(mcmain_per_ch_list), ++ handle_reg); ++ } ++ save_restore( ++ reg_frame->misc_common, ++ 0, ++ misc_common_list, ++ ARRAY_SIZE(misc_common_list), ++ handle_reg); ++} ++ ++enum raminit_status save_training_values(struct sysinfo *ctrl) ++{ ++ save_restore_all(reg_frame_ptr(), save_value); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++enum raminit_status restore_training_values(struct sysinfo *ctrl) ++{ ++ save_restore_all(reg_frame_ptr(), restore_value); ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++enum raminit_status save_non_training(struct sysinfo *ctrl) ++{ ++ struct register_save_frame *reg_frame = reg_frame_ptr(); ++ struct save_params *params = ®_frame->params; ++ ++ params->is_initialised = true; ++ ++ params->base_freq = ctrl->base_freq; ++ params->multiplier = ctrl->multiplier; ++ params->mem_clock_mhz = ctrl->mem_clock_mhz; ++ params->mem_clock_fs = ctrl->mem_clock_fs; ++ params->qclkps = ctrl->qclkps; ++ params->cas_supported = ctrl->cas_supported; ++ params->cpu = ctrl->cpu; ++ params->stepping = ctrl->stepping; ++ params->vdd_mv = ctrl->vdd_mv; ++ params->flags = ctrl->flags; ++ ++ params->tCK = ctrl->tCK; ++ params->tAA = ctrl->tAA; ++ params->tWR = ctrl->tWR; ++ params->tRCD = ctrl->tRCD; ++ params->tRRD = ctrl->tRRD; ++ params->tRP = ctrl->tRP; ++ params->tRAS = ctrl->tRAS; ++ params->tRC = ctrl->tRC; ++ params->tRFC = ctrl->tRFC; ++ params->tWTR = ctrl->tWTR; ++ params->tRTP = ctrl->tRTP; ++ params->tFAW = ctrl->tFAW; ++ params->tCWL = ctrl->tCWL; ++ params->tCMD = ctrl->tCMD; ++ params->tREFI = ctrl->tREFI; ++ params->tXP = ctrl->tXP; ++ ++ params->chanmap = ctrl->chanmap; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel]; ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) ++ params->dimms[channel][slot] = ctrl->dimms[channel][slot]; ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ params->dpc[channel] = ctrl->dpc[channel]; ++ params->rankmap[channel] = ctrl->rankmap[channel]; ++ params->rank_mirrored[channel] = ctrl->rank_mirrored[channel]; ++ params->channel_size_mb[channel] = ctrl->channel_size_mb[channel]; ++ } ++ params->lpddr = ctrl->lpddr; ++ params->lanes = ctrl->lanes; ++ params->is_ecc = ctrl->is_ecc; ++ return RAMINIT_STATUS_SUCCESS; ++} ++ ++#define RAMINIT_COMPARE(_s1, _s2) \ ++ ((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1))) ++ ++enum raminit_status restore_non_training(struct sysinfo *ctrl) ++{ ++ struct register_save_frame *reg_frame = reg_frame_ptr(); ++ struct save_params *params = ®_frame->params; ++ ++ if (!params->is_initialised) { ++ printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) { ++ printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ if (ctrl->cpu != params->cpu) { ++ printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n"); ++ return RAMINIT_STATUS_INVALID_CACHE; ++ } ++ ++ ctrl->base_freq = params->base_freq; ++ ctrl->multiplier = params->multiplier; ++ ctrl->mem_clock_mhz = params->mem_clock_mhz; ++ ctrl->mem_clock_fs = params->mem_clock_fs; ++ ctrl->qclkps = params->qclkps; ++ ctrl->cas_supported = params->cas_supported; ++ ctrl->cpu = params->cpu; ++ ctrl->stepping = params->stepping; ++ ctrl->vdd_mv = params->vdd_mv; ++ ctrl->flags = params->flags; ++ ++ ctrl->tCK = params->tCK; ++ ctrl->tAA = params->tAA; ++ ctrl->tWR = params->tWR; ++ ctrl->tRCD = params->tRCD; ++ ctrl->tRRD = params->tRRD; ++ ctrl->tRP = params->tRP; ++ ctrl->tRAS = params->tRAS; ++ ctrl->tRC = params->tRC; ++ ctrl->tRFC = params->tRFC; ++ ctrl->tWTR = params->tWTR; ++ ctrl->tRTP = params->tRTP; ++ ctrl->tFAW = params->tFAW; ++ ctrl->tCWL = params->tCWL; ++ ctrl->tCMD = params->tCMD; ++ ctrl->tREFI = params->tREFI; ++ ctrl->tXP = params->tXP; ++ ++ ctrl->chanmap = params->chanmap; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel]; ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) ++ ctrl->dimms[channel][slot] = params->dimms[channel][slot]; ++ } ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ ctrl->dpc[channel] = params->dpc[channel]; ++ ctrl->rankmap[channel] = params->rankmap[channel]; ++ ctrl->rank_mirrored[channel] = params->rank_mirrored[channel]; ++ ctrl->channel_size_mb[channel] = params->channel_size_mb[channel]; ++ } ++ ctrl->lpddr = params->lpddr; ++ ctrl->lanes = params->lanes; ++ ctrl->is_ecc = params->is_ecc; ++ return RAMINIT_STATUS_SUCCESS; ++} +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch b/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch new file mode 100644 index 00000000..846fe9a3 --- /dev/null +++ b/config/coreboot/haswell/patches/0017-haswell-NRI-Do-sense-amplifier-offset-training.patch @@ -0,0 +1,476 @@ +From be58501141aa97aa544b670e566cd6cf6797c18e Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Wed, 17 Apr 2024 13:20:32 +0200 +Subject: [PATCH 17/20] haswell NRI: Do sense amplifier offset training + +Quoting Wikipedia: + + A sense amplifier is a circuit that is used to amplify and detect + small signals in electronic systems. It is commonly used in memory + circuits, such as dynamic random access memory (DRAM), to read and + amplify the weak signals stored in memory cells. + +In this case, we're calibrating the sense amplifiers in the memory +controller. This training procedure uses a magic "sense amp offset +cancel" mode of the DDRIO to observe the sampled logic levels, and +sweeps Vref to find the low-high transition for each bit lane. The +procedure consists of two stages: the first stage centers per-byte +Vref (to ensure per-bit Vref offsets are as small as possible) and +the second stage centers per-bit Vref. + +Because this procedure uses the "sense amp offset cancel" mode, it +does not rely on DRAM being trained. It is assumed that the memory +controller simply makes sense amp output levels observable via the +`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle +during this training step (so the lane voltage is Vdd / 2). + +Note: This procedure will need to be adapted for Broadwell because +it has per-rank per-bit RxVref registers, whereas Haswell only has +a single per-bit RxVref register for all ranks. + +Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07 +Signed-off-by: Angel Pons +--- + .../intel/haswell/native_raminit/Makefile.mk | 1 + + .../haswell/native_raminit/raminit_main.c | 1 + + .../haswell/native_raminit/raminit_native.h | 12 + + .../native_raminit/train_sense_amp_offset.c | 341 ++++++++++++++++++ + .../intel/haswell/registers/mchbar.h | 2 + + 5 files changed, 357 insertions(+) + create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c + +diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +index 8fdd17c542..4bd668a2d6 100644 +--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk ++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk +@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c + romstage-y += train_jedec_write_leveling.c + romstage-y += train_read_mpr.c + romstage-y += train_receive_enable.c ++romstage-y += train_sense_amp_offset.c +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +index 056dde1adc..ce637e2d03 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c +@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = { + { configure_memory_map, true, "MEMMAP", }, + { do_jedec_init, true, "JEDECINIT", }, + { pre_training, true, "PRETRAIN", }, ++ { train_sense_amp_offset, true, "SOT", }, + { train_receive_enable, true, "RCVET", }, + { train_read_mpr, true, "RDMPRT", }, + { train_jedec_write_leveling, true, "JWRL", }, +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index 0750904aec..95ccd0a8b3 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -22,6 +22,8 @@ + #define NUM_LANES 9 + #define NUM_LANES_NO_ECC 8 + ++#define NUM_BITS 8 ++ + #define COMP_INT 10 + + /* Always use 12 legs for emphasis (not trained) */ +@@ -218,6 +220,7 @@ enum raminit_status { + RAMINIT_STATUS_MPLL_INIT_FAILURE, + RAMINIT_STATUS_POLL_TIMEOUT, + RAMINIT_STATUS_REUT_ERROR, ++ RAMINIT_STATUS_SAMP_OFFSET_FAILURE, + RAMINIT_STATUS_RCVEN_FAILURE, + RAMINIT_STATUS_RMPR_FAILURE, + RAMINIT_STATUS_JWRL_FAILURE, +@@ -243,6 +246,12 @@ struct raminit_dimm_info { + bool valid; + }; + ++struct vref_margin { ++ uint8_t low; ++ uint8_t center; ++ uint8_t high; ++}; ++ + struct sysinfo { + enum raminit_boot_mode bootmode; + enum generic_stepping stepping; +@@ -330,6 +339,8 @@ struct sysinfo { + uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; + ++ struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS]; ++ + uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; + uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; + uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS]; +@@ -452,6 +463,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl); + enum raminit_status configure_mc(struct sysinfo *ctrl); + enum raminit_status configure_memory_map(struct sysinfo *ctrl); + enum raminit_status do_jedec_init(struct sysinfo *ctrl); ++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl); + enum raminit_status train_receive_enable(struct sysinfo *ctrl); + enum raminit_status train_read_mpr(struct sysinfo *ctrl); + enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl); +diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c +new file mode 100644 +index 0000000000..d4f199fefb +--- /dev/null ++++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c +@@ -0,0 +1,341 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "raminit_native.h" ++ ++#define VREF_OFFSET_PLOT RAM_DEBUG ++#define SAMP_OFFSET_PLOT RAM_DEBUG ++ ++struct vref_train_data { ++ int8_t best_sum; ++ int8_t best_vref; ++ int8_t sum_bits; ++ uint8_t high_mask; ++ uint8_t low_mask; ++}; ++ ++static enum raminit_status train_vref_offset(struct sysinfo *ctrl) ++{ ++ const int8_t vref_start = -15; ++ const int8_t vref_stop = 15; ++ const struct vref_train_data initial_vref_values = { ++ .best_sum = -NUM_LANES, ++ .best_vref = 0, ++ .high_mask = 0, ++ .low_mask = 0xff, ++ }; ++ struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES]; ++ ++ printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel"); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel); ++ } ++ ++ printk(VREF_OFFSET_PLOT, "\nByte"); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(VREF_OFFSET_PLOT, "\t"); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ printk(VREF_OFFSET_PLOT, "%u ", byte); ++ vref_data[channel][byte] = initial_vref_values; ++ union ddr_data_control_2_reg data_control_2 = { ++ .raw = ctrl->dq_control_2[channel][byte], ++ }; ++ data_control_2.force_bias_on = 1; ++ data_control_2.force_rx_on = 1; ++ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw); ++ } ++ } ++ ++ /* Sweep through Vref settings and find point SampOffset of +/- 7 passes */ ++ printk(VREF_OFFSET_PLOT, "\n1/2 Vref"); ++ for (int8_t vref = vref_start; vref <= vref_stop; vref++) { ++ printk(VREF_OFFSET_PLOT, "\n% 3d", vref); ++ ++ /* ++ * To perform this test, enable offset cancel mode and enable ODT. ++ * Check results and update variables. Ideal result is all zeroes. ++ * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ. ++ */ ++ change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK); ++ ++ /* Program settings for Vref and SampOffset = 7 (8 + 7) */ ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint8_t feedback = get_data_train_feedback(channel, byte); ++ struct vref_train_data *curr_data = &vref_data[channel][byte]; ++ curr_data->low_mask &= feedback; ++ curr_data->sum_bits = -popcnt(feedback); ++ } ++ } ++ ++ /* Program settings for Vref and SampOffset = -7 (8 - 7) */ ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ printk(VREF_OFFSET_PLOT, "\t"); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint8_t feedback = get_data_train_feedback(channel, byte); ++ struct vref_train_data *curr_data = &vref_data[channel][byte]; ++ curr_data->high_mask |= feedback; ++ curr_data->sum_bits += popcnt(feedback); ++ printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits); ++ if (curr_data->sum_bits > curr_data->best_sum) { ++ curr_data->best_sum = curr_data->sum_bits; ++ curr_data->best_vref = vref; ++ ctrl->rxvref[channel][0][byte] = vref; ++ } else if (curr_data->sum_bits == curr_data->best_sum) { ++ curr_data->best_vref = vref; ++ } ++ } ++ } ++ } ++ printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):"); ++ enum raminit_status status = RAMINIT_STATUS_SUCCESS; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "\n C%u:", channel); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ struct vref_train_data *const curr_data = &vref_data[channel][byte]; ++ const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask; ++ printk(BIOS_DEBUG, "\t0x%02x", bit_xor); ++ if (bit_xor == 0xff) ++ continue; ++ ++ /* Report an error if any bit did not change */ ++ status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE; ++ } ++ } ++ if (status) ++ printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n"); ++ ++ printk(BIOS_DEBUG, "\n\nRdVref:"); ++ change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "\n C%u:", channel); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ struct vref_train_data *const curr_data = &vref_data[channel][byte]; ++ const int8_t vref_width = ++ curr_data->best_vref - ctrl->rxvref[channel][0][byte]; ++ ++ /* ++ * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV ++ * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV ++ */ ++ int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2; ++ if (vref < 0) ++ vref--; ++ else ++ vref++; ++ ++ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) { ++ if (!rank_in_ch(ctrl, rank, channel)) ++ continue; ++ ++ ctrl->rxvref[channel][rank][byte] = vref / 2; ++ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0); ++ } ++ printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]); ++ } ++ } ++ printk(BIOS_DEBUG, "\n\n"); ++ return status; ++} ++ ++/** ++ * LPDDR has an additional bit for DQS per each byte. ++ * ++ * TODO: The DQS value must be written into Data Control 2. ++ */ ++#define NUM_OFFSET_TRAIN_BITS (NUM_BITS + 1) ++ ++#define PLOT_CH_SPACE " " ++ ++struct samp_train_data { ++ uint8_t first_zero; ++ uint8_t last_one; ++}; ++ ++static void train_samp_offset(struct sysinfo *ctrl) ++{ ++ const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS; ++ ++ struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0}; ++ ++ printk(BIOS_DEBUG, "Channel "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(BIOS_DEBUG, " %s ", ctrl->lpddr ? " " : ""); ++ } ++ printk(BIOS_DEBUG, "\nByte "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(BIOS_DEBUG, "%u %s ", byte, ctrl->lpddr ? " " : ""); ++ ++ printk(BIOS_DEBUG, PLOT_CH_SPACE); ++ } ++ printk(SAMP_OFFSET_PLOT, "\nBits "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : ""); ++ ++ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE); ++ } ++ printk(SAMP_OFFSET_PLOT, "\n SAmp\n"); ++ for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) { ++ printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset); ++ ++ uint32_t rx_offset_vdq = 0; ++ for (uint8_t bit = 0; bit < NUM_BITS; bit++) { ++ rx_offset_vdq += samp_offset << (4 * bit); ++ } ++ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ /* Propagate delay values (without a read command) */ ++ union ddr_data_control_0_reg data_control_0 = { ++ .raw = ctrl->dq_control_0[channel], ++ }; ++ data_control_0.read_rf_rd = 1; ++ data_control_0.read_rf_wr = 0; ++ data_control_0.read_rf_rank = 0; ++ data_control_0.force_odt_on = 1; ++ data_control_0.samp_train_mode = 1; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ udelay(1); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ const uint32_t feedback = ++ get_data_train_feedback(channel, byte); ++ ++ for (uint8_t bit = 0; bit < max_train_bits; bit++) { ++ struct samp_train_data *const curr_data = ++ &samp_data[channel][byte][bit]; ++ const bool result = feedback & BIT(bit); ++ if (result) { ++ curr_data->last_one = samp_offset; ++ } else if (curr_data->first_zero == 0) { ++ curr_data->first_zero = samp_offset; ++ } ++ printk(SAMP_OFFSET_PLOT, result ? "." : "#"); ++ } ++ printk(SAMP_OFFSET_PLOT, " "); ++ } ++ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE); ++ data_control_0.samp_train_mode = 0; ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw); ++ } ++ printk(SAMP_OFFSET_PLOT, "\n"); ++ } ++ printk(BIOS_DEBUG, "\nBitSAmp "); ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) { ++ uint32_t rx_offset_vdq = 0; ++ for (uint8_t bit = 0; bit < max_train_bits; bit++) { ++ struct samp_train_data *const curr_data = ++ &samp_data[channel][byte][bit]; ++ ++ uint8_t vref = curr_data->first_zero + curr_data->last_one; ++ vref = clamp_u8(0, vref / 2, 15); ++ /* ++ * Check for saturation conditions to make sure ++ * we are as close as possible to Vdd/2 (750 mV). ++ */ ++ if (curr_data->first_zero == 0) ++ vref = 15; ++ if (curr_data->last_one == 0) ++ vref = 0; ++ ++ ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref; ++ rx_offset_vdq += vref & 0xf << (4 * bit); ++ printk(BIOS_DEBUG, "%x", vref); ++ } ++ mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq); ++ printk(BIOS_DEBUG, " "); ++ download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0); ++ } ++ printk(BIOS_DEBUG, PLOT_CH_SPACE); ++ } ++ printk(BIOS_DEBUG, "\n"); ++} ++ ++enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl) ++{ ++ printk(BIOS_DEBUG, "Stage 1: Vref offset training\n"); ++ const enum raminit_status status = train_vref_offset(ctrl); ++ ++ printk(BIOS_DEBUG, "Stage 2: Samp offset training\n"); ++ train_samp_offset(ctrl); ++ ++ /* Clean up after test */ ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ if (!does_ch_exist(ctrl, channel)) ++ continue; ++ ++ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]); ++ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) ++ mchbar_write32(DQ_CONTROL_2(channel, byte), ++ ctrl->dq_control_2[channel][byte]); ++ } ++ io_reset(); ++ return status; ++} +diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h +index 49a215aa71..1a168a3fc8 100644 +--- a/src/northbridge/intel/haswell/registers/mchbar.h ++++ b/src/northbridge/intel/haswell/registers/mchbar.h +@@ -18,6 +18,8 @@ + #define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte) + #define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte) + ++#define RX_OFFSET_VDQ(ch, byte) _DDRIO_C_R_B(0x004c, ch, 0, byte) ++ + #define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte) + + #define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte) +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch similarity index 74% rename from config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch rename to config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch index 547c6392..34309242 100644 --- a/config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch +++ b/config/coreboot/haswell/patches/0018-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -1,26 +1,27 @@ -From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001 +From c25dcd8ac80598939edffd011df0fd9ba3d8a1a8 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 12 May 2023 19:55:15 -0600 -Subject: [PATCH] Remove warning for coreboot images built without a payload +Subject: [PATCH 18/20] Remove warning for coreboot images built without a + payload I added this in upstream to prevent people from accidentally flashing roms without a payload resulting in a no boot situation, but in libreboot lbmk handles the payload and thus this warning always comes up. This has caused confusion and concern so just patch it out. --- - payloads/Makefile.inc | 13 +------------ + payloads/Makefile.mk | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc -index e735443a76..4f1692a873 100644 ---- a/payloads/Makefile.inc -+++ b/payloads/Makefile.inc +diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk +index a2336aa876..4f1692a873 100644 +--- a/payloads/Makefile.mk ++++ b/payloads/Makefile.mk @@ -49,16 +49,5 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) -ifeq ($(CONFIG_PAYLOAD_NONE),y) --files_added:: warn_no_payload +-show_notices:: warn_no_payload -endif - -warn_no_payload: @@ -34,5 +35,5 @@ index e735443a76..4f1692a873 100644 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads -- -2.40.1 +2.39.2 diff --git a/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch new file mode 100644 index 00000000..e197b3f3 --- /dev/null +++ b/config/coreboot/haswell/patches/0019-use-mirrorservice.org-for-gcc-downloads.patch @@ -0,0 +1,36 @@ +From 081890bab8d454247b6f7e9cb209f46159c45c8b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 5 Nov 2023 23:19:42 +0000 +Subject: [PATCH 19/20] use mirrorservice.org for gcc downloads + +the gnu.org 302 redirect often fails + +Signed-off-by: Leah Rowe +--- + util/crossgcc/buildgcc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 0a0462e2f6..6ae201239d 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" + # to the jenkins build as well, or the builder won't download it. + + # GCC toolchain archive locations +-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" +-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" +-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" +-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" ++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" ++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" ++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" ++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" ++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" + IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch b/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch new file mode 100644 index 00000000..60490608 --- /dev/null +++ b/config/coreboot/haswell/patches/0020-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch @@ -0,0 +1,204 @@ +From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 19 Feb 2023 18:21:43 +0000 +Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region) + +When this option is used, the region's contents are overwritten +with all ones (0xFF). + +Example: + +./ifdtool --nuke gbe coreboot.rom +./ifdtool --nuke bios coreboot.com +./ifdtool --nuke me coreboot.com + +Rebased since the last revision update in lbmk. + +Signed-off-by: Leah Rowe +--- + util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++----------- + 1 file changed, 82 insertions(+), 31 deletions(-) + +diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c +index 516570e0a3..1638e1710e 100644 +--- a/util/ifdtool/ifdtool.c ++++ b/util/ifdtool/ifdtool.c +@@ -2143,6 +2143,7 @@ static void print_usage(const char *name) + " tgl - Tiger Lake\n" + " wbg - Wellsburg\n" + " -S | --setpchstrap Write a PCH strap\n" ++ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" + " -V | --newvalue The new value to write into PCH strap specified by -S\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" +@@ -2151,6 +2152,60 @@ static void print_usage(const char *name) + "\n"); + } + ++static int ++get_region_type_string(const char *region_type_string) ++{ ++ if (!strcasecmp("Descriptor", region_type_string)) ++ return 0; ++ else if (!strcasecmp("BIOS", region_type_string)) ++ return 1; ++ else if (!strcasecmp("ME", region_type_string)) ++ return 2; ++ else if (!strcasecmp("GbE", region_type_string)) ++ return 3; ++ else if (!strcasecmp("Platform Data", region_type_string)) ++ return 4; ++ else if (!strcasecmp("Device Exp1", region_type_string)) ++ return 5; ++ else if (!strcasecmp("Secondary BIOS", region_type_string)) ++ return 6; ++ else if (!strcasecmp("Reserved", region_type_string)) ++ return 7; ++ else if (!strcasecmp("EC", region_type_string)) ++ return 8; ++ else if (!strcasecmp("Device Exp2", region_type_string)) ++ return 9; ++ else if (!strcasecmp("IE", region_type_string)) ++ return 10; ++ else if (!strcasecmp("10GbE_0", region_type_string)) ++ return 11; ++ else if (!strcasecmp("10GbE_1", region_type_string)) ++ return 12; ++ else if (!strcasecmp("PTT", region_type_string)) ++ return 15; ++ return -1; ++} ++ ++static void ++nuke(const char *filename, char *image, int size, int region_type) ++{ ++ int i; ++ struct region region; ++ const struct frba *frba = find_frba(image, size); ++ if (!frba) ++ exit(EXIT_FAILURE); ++ ++ region = get_region(frba, region_type); ++ if (region.size > 0) { ++ for (i = region.base; i <= region.limit; i++) { ++ if ((i + 1) > (size)) ++ break; ++ image[i] = 0xFF; ++ } ++ write_image(filename, image, size); ++ } ++} ++ + int main(int argc, char *argv[]) + { + int opt, option_index = 0; +@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[]) + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; + int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0; ++ int mode_nuke = 0; + int mode_gpr0_disable = 0, mode_gpr0_enable = 0; + char *region_type_string = NULL, *region_fname = NULL; + const char *layout_fname = NULL; +@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[]) + {"validate", 0, NULL, 't'}, + {"setpchstrap", 1, NULL, 'S'}, + {"newvalue", 1, NULL, 'V'}, ++ {"nuke", 1, NULL, 'N'}, + {0, 0, 0, 0} + }; + +@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[]) + region_fname++; + // Descriptor, BIOS, ME, GbE, Platform + // valid type? +- if (!strcasecmp("Descriptor", region_type_string)) +- region_type = 0; +- else if (!strcasecmp("BIOS", region_type_string)) +- region_type = 1; +- else if (!strcasecmp("ME", region_type_string)) +- region_type = 2; +- else if (!strcasecmp("GbE", region_type_string)) +- region_type = 3; +- else if (!strcasecmp("Platform Data", region_type_string)) +- region_type = 4; +- else if (!strcasecmp("Device Exp1", region_type_string)) +- region_type = 5; +- else if (!strcasecmp("Secondary BIOS", region_type_string)) +- region_type = 6; +- else if (!strcasecmp("Reserved", region_type_string)) +- region_type = 7; +- else if (!strcasecmp("EC", region_type_string)) +- region_type = 8; +- else if (!strcasecmp("Device Exp2", region_type_string)) +- region_type = 9; +- else if (!strcasecmp("IE", region_type_string)) +- region_type = 10; +- else if (!strcasecmp("10GbE_0", region_type_string)) +- region_type = 11; +- else if (!strcasecmp("10GbE_1", region_type_string)) +- region_type = 12; +- else if (!strcasecmp("PTT", region_type_string)) +- region_type = 15; +- if (region_type == -1) { ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { + fprintf(stderr, "No such region type: '%s'\n\n", + region_type_string); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); +@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[]) + case 't': + mode_validate = 1; + break; ++ case 'N': ++ region_type_string = strdup(optarg); ++ if (!region_type_string) { ++ fprintf(stderr, "No region specified\n"); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ if ((region_type = ++ get_region_type_string(region_type_string)) == -1) { ++ fprintf(stderr, "No such region type: '%s'\n\n", ++ region_type_string); ++ print_usage(argv[0]); ++ exit(EXIT_FAILURE); ++ } ++ mode_nuke = 1; ++ break; + case 'v': + print_version(); + exit(EXIT_SUCCESS); +@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 | + mode_unlocked | mode_locked) + mode_altmedisable + mode_validate + +- (mode_gpr0_disable | mode_gpr0_enable)) > 1) { ++ (mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) { + fprintf(stderr, "You may not specify more than one mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[]) + if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject + + mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 + + mode_locked + mode_unlocked + mode_density + mode_altmedisable + +- mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) { ++ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + ++ mode_nuke) == 0) { + fprintf(stderr, "You need to specify a mode.\n\n"); + fprintf(stderr, "run '%s -h' for usage\n", argv[0]); + exit(EXIT_FAILURE); +@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[]) + write_image(new_filename, image, size); + } + ++ if (mode_nuke) { ++ nuke(new_filename, image, size, region_type); ++ } ++ + if (mode_altmedisable) { + struct fpsba *fpsba = find_fpsba(image, size); + struct fmsba *fmsba = find_fmsba(image, size); +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch b/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch deleted file mode 100644 index 9f22c06d..00000000 --- a/config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 29c1116ebd5879568010a8386e4838294a78b408 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 16 Jul 2023 03:48:23 +0100 -Subject: [PATCH 1/1] coreboot/haswell: fix acpica downloads - -the upstream link died. i now host the relevant acpica -tarball myself, on libreboot rsync. this patch makes -coreboot crossgcc use that - -Signed-off-by: Leah Rowe ---- - util/crossgcc/buildgcc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index 3c4b10cc92..0c4262b7b1 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -52,7 +52,7 @@ MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" - MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" - GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" - BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" --IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz" - # CLANG toolchain archive locations - LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" - CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz" --- -2.40.1 - diff --git a/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch b/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch deleted file mode 100644 index 0d0a66a1..00000000 --- a/config/coreboot/haswell/patches/0028-use-mirrorservice.org-for-gcc-downloads.patch +++ /dev/null @@ -1,36 +0,0 @@ -From ca1bd48a87ab46ebfb444b0e092442bf6270ec7a Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sun, 5 Nov 2023 23:19:42 +0000 -Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads - -the gnu.org 302 redirect often fails - -Signed-off-by: Leah Rowe ---- - util/crossgcc/buildgcc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc -index d4cc8b2a24..526940acfa 100755 ---- a/util/crossgcc/buildgcc -+++ b/util/crossgcc/buildgcc -@@ -47,11 +47,11 @@ NASM_VERSION=2.15.05 - # These are sanitized by the jenkins toolchain test builder, so if - # a completely new URL is added here, it probably needs to be added - # to the jenkins build as well, or the builder won't download it. --GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" --MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" --MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" --GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" --BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" -+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz" -+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz" -+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" -+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz" - IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz" - # CLANG toolchain archive locations - LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" --- -2.39.2 - diff --git a/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch b/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch deleted file mode 100644 index 18d6a21e..00000000 --- a/config/coreboot/haswell/patches/0029-ifdtool-nuke-option.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 6f94e9aa38a5d6589b1a64642dfcb5ccbf90b8d3 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Tue, 9 Jan 2024 01:53:54 +0000 -Subject: [PATCH 1/1] ifdtool nuke option - -Signed-off-by: Leah Rowe ---- - util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++----------- - 1 file changed, 83 insertions(+), 31 deletions(-) - -diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c -index e97efcc206..ee27e7f2e6 100644 ---- a/util/ifdtool/ifdtool.c -+++ b/util/ifdtool/ifdtool.c -@@ -1711,6 +1711,7 @@ static void print_usage(const char *name) - " tgl - Tiger Lake\n" - " -S | --setpchstrap Write a PCH strap\n" - " -V | --newvalue The new value to write into PCH strap specified by -S\n" -+ " -N | --nuke Overwrite the specified region with 0xFF (all ones)\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" - " is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " -@@ -1718,6 +1719,60 @@ static void print_usage(const char *name) - "\n"); - } - -+static int -+get_region_type_string(const char *region_type_string) -+{ -+ if (!strcasecmp("Descriptor", region_type_string)) -+ return 0; -+ else if (!strcasecmp("BIOS", region_type_string)) -+ return 1; -+ else if (!strcasecmp("ME", region_type_string)) -+ return 2; -+ else if (!strcasecmp("GbE", region_type_string)) -+ return 3; -+ else if (!strcasecmp("Platform Data", region_type_string)) -+ return 4; -+ else if (!strcasecmp("Device Exp1", region_type_string)) -+ return 5; -+ else if (!strcasecmp("Secondary BIOS", region_type_string)) -+ return 6; -+ else if (!strcasecmp("Reserved", region_type_string)) -+ return 7; -+ else if (!strcasecmp("EC", region_type_string)) -+ return 8; -+ else if (!strcasecmp("Device Exp2", region_type_string)) -+ return 9; -+ else if (!strcasecmp("IE", region_type_string)) -+ return 10; -+ else if (!strcasecmp("10GbE_0", region_type_string)) -+ return 11; -+ else if (!strcasecmp("10GbE_1", region_type_string)) -+ return 12; -+ else if (!strcasecmp("PTT", region_type_string)) -+ return 15; -+ return -1; -+} -+ -+static void -+nuke(const char *filename, char *image, int size, int region_type) -+{ -+ int i; -+ region_t region; -+ const frba_t *frba = find_frba(image, size); -+ if (!frba) -+ exit(EXIT_FAILURE); -+ -+ region = get_region(frba, region_type); -+ if (region.size > 0) { -+ for (i = region.base; i <= region.limit; i++) { -+ if ((i + 1) > (size)) -+ break; -+ image[i] = 0xFF; -+ } -+ write_image(filename, image, size); -+ } -+} -+ - int main(int argc, char *argv[]) - { - int opt, option_index = 0; -@@ -1725,6 +1780,7 @@ int main(int argc, char *argv[]) - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; - int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0; - int mode_read = 0, mode_altmedisable = 0, altmedisable = 0; -+ int mode_nuke = 0; - char *region_type_string = NULL, *region_fname = NULL; - const char *layout_fname = NULL; - char *new_filename = NULL; -@@ -1755,6 +1811,7 @@ int main(int argc, char *argv[]) - {"validate", 0, NULL, 't'}, - {"setpchstrap", 1, NULL, 'S'}, - {"newvalue", 1, NULL, 'V'}, -+ {"nuke", 1, NULL, 'N'}, - {0, 0, 0, 0} - }; - -@@ -1795,35 +1852,8 @@ int main(int argc, char *argv[]) - region_fname++; - // Descriptor, BIOS, ME, GbE, Platform - // valid type? -- if (!strcasecmp("Descriptor", region_type_string)) -- region_type = 0; -- else if (!strcasecmp("BIOS", region_type_string)) -- region_type = 1; -- else if (!strcasecmp("ME", region_type_string)) -- region_type = 2; -- else if (!strcasecmp("GbE", region_type_string)) -- region_type = 3; -- else if (!strcasecmp("Platform Data", region_type_string)) -- region_type = 4; -- else if (!strcasecmp("Device Exp1", region_type_string)) -- region_type = 5; -- else if (!strcasecmp("Secondary BIOS", region_type_string)) -- region_type = 6; -- else if (!strcasecmp("Reserved", region_type_string)) -- region_type = 7; -- else if (!strcasecmp("EC", region_type_string)) -- region_type = 8; -- else if (!strcasecmp("Device Exp2", region_type_string)) -- region_type = 9; -- else if (!strcasecmp("IE", region_type_string)) -- region_type = 10; -- else if (!strcasecmp("10GbE_0", region_type_string)) -- region_type = 11; -- else if (!strcasecmp("10GbE_1", region_type_string)) -- region_type = 12; -- else if (!strcasecmp("PTT", region_type_string)) -- region_type = 15; -- if (region_type == -1) { -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { - fprintf(stderr, "No such region type: '%s'\n\n", - region_type_string); - print_usage(argv[0]); -@@ -1988,6 +2018,22 @@ int main(int argc, char *argv[]) - case 't': - mode_validate = 1; - break; -+ case 'N': -+ region_type_string = strdup(optarg); -+ if (!region_type_string) { -+ fprintf(stderr, "No region specified\n"); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ if ((region_type = -+ get_region_type_string(region_type_string)) == -1) { -+ fprintf(stderr, "No such region type: '%s'\n\n", -+ region_type_string); -+ print_usage(argv[0]); -+ exit(EXIT_FAILURE); -+ } -+ mode_nuke = 1; -+ break; - case 'v': - print_version(); - exit(EXIT_SUCCESS); -@@ -2003,7 +2049,8 @@ int main(int argc, char *argv[]) - - if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap + - mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | -- mode_locked) + mode_altmedisable + mode_validate) > 1) { -+ mode_locked) + mode_altmedisable + mode_validate + -+ mode_nuke) > 1) { - fprintf(stderr, "You may not specify more than one mode.\n\n"); - print_usage(argv[0]); - exit(EXIT_FAILURE); -@@ -2011,7 +2058,8 @@ int main(int argc, char *argv[]) - - if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap + - mode_newlayout + mode_spifreq + mode_em100 + mode_locked + -- mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { -+ mode_unlocked + mode_density + mode_altmedisable + -+ mode_validate + mode_nuke) == 0) { - fprintf(stderr, "You need to specify a mode.\n\n"); - print_usage(argv[0]); - exit(EXIT_FAILURE); -@@ -2109,6 +2157,10 @@ int main(int argc, char *argv[]) - write_image(new_filename, image, size); - } - -+ if (mode_nuke) { -+ nuke(new_filename, image, size, region_type); -+ } -+ - if (mode_altmedisable) { - fpsba_t *fpsba = find_fpsba(image, size); - fmsba_t *fmsba = find_fmsba(image, size); --- -2.39.2 - diff --git a/config/coreboot/haswell/target.cfg b/config/coreboot/haswell/target.cfg index b3196341..a38399e4 100644 --- a/config/coreboot/haswell/target.cfg +++ b/config/coreboot/haswell/target.cfg @@ -1,3 +1,3 @@ tree="haswell" -rev="1411ecf6f0b2c7395bcb96b856dcfdddb1b0c81b" +rev="b7341da19133991efd29880849bdaab29a6e243d" xarch="i386-elf" diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..58daa6a1 --- /dev/null +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,668 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad T440p" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T440p" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0416" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_LENOVO_THINKPAD_T440P=y +# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN0036" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode index 967b3b2e..89a4925b 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -14,12 +13,15 @@ CONFIG_COMPILER_GCC=y CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set # CONFIG_OPTION_BACKEND_NONE is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -36,6 +38,12 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) # end of General setup # @@ -53,30 +61,28 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set @@ -91,7 +97,6 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_STARLABS is not set @@ -111,31 +116,30 @@ CONFIG_FMDFILE="" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0xBE0000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -# CONFIG_VBOOT is not set -CONFIG_VBOOT_VBNV_OFFSET=0x2a -CONFIG_VARIANT_DIR="t440p" CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="t440p" +CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_OVERRIDE_DEVICETREE="" CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xff7c0000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -148,15 +152,16 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T440p" CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_G505S is not set CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set # CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T500 is not set @@ -177,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_Z61T is not set # CONFIG_BOARD_LENOVO_R60 is not set # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set # CONFIG_BOARD_LENOVO_X131E is not set # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set @@ -188,6 +194,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y @@ -195,11 +202,16 @@ CONFIG_PS2K_EISAID="LEN0071" CONFIG_PS2M_EISAID="LEN0036" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="eDP" -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_HEAP_SIZE=0x4000 +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -212,6 +224,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set CONFIG_COREBOOT_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=12288 @@ -233,7 +246,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # -CONFIG_ARCH_ALL_STAGES_X86=y CONFIG_CHIPSET_DEVICETREE="" CONFIG_CBFS_MCACHE_SIZE=0x4000 CONFIG_ROMSTAGE_ADDR=0x2000000 @@ -241,34 +253,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_TSEG_SIZE=0x800000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d" +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 -CONFIG_UART_PCI_ADDR=0x0 -CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 # # CPU # CONFIG_CPU_INTEL_HASWELL=y -CONFIG_SSE2=y CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -277,7 +289,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y CONFIG_CPU_INTEL_COMMON_TIMEBASE=y CONFIG_CPU_INTEL_COMMON_VOLTAGE=y CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y CONFIG_PARALLEL_MP=y CONFIG_XAPIC_ONLY=y # CONFIG_X2APIC_ONLY is not set @@ -286,14 +297,13 @@ CONFIG_XAPIC_ONLY=y CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y -CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y -CONFIG_SMM_STUB_STACK_SIZE=0x400 -CONFIG_CPU_INFO_V2=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y -CONFIG_MMX=y CONFIG_SSE=y +CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y @@ -310,9 +320,7 @@ CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge # -CONFIG_SOUTH_BRIDGE_OPTIONS=y -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_PCIEXP_HOTPLUG=y +# CONFIG_PCIEXP_HOTPLUG is not set CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y CONFIG_FINALIZE_USB_ROUTE_XHCI=y @@ -328,12 +336,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 CONFIG_RCBA_LENGTH=0x4000 @@ -347,11 +355,13 @@ CONFIG_RCBA_LENGTH=0x4000 # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y CONFIG_EC_LENOVO_PMH7=y # @@ -374,8 +384,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_NUM_IPI_STARTS=2 +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -385,6 +397,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -396,6 +409,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y CONFIG_MAINBOARD_USE_LIBGFXINIT=y # CONFIG_VGA_ROM_RUN is not set # CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y # # Display @@ -407,17 +421,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -425,7 +436,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATOR_V4=y +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y # end of Devices # @@ -435,21 +447,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y # CONFIG_MRC_SETTINGS_PROTECT is not set -CONFIG_MRC_STASH_TO_CBMEM=y # CONFIG_SMMSTORE is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y CONFIG_TPM_INIT_RAMSTAGE=y # CONFIG_TPM_PPI is not set @@ -460,28 +470,35 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y # CONFIG_USBDEBUG is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set CONFIG_INTEL_DDI=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -CONFIG_INTEL_GMA_OPREGION_2_0=y CONFIG_GFX_GMA_DYN_CPU=y CONFIG_GFX_GMA_GENERATION="Haswell" CONFIG_GFX_GMA_PCH="Lynx_Point" CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_MEMORY_MAPPED_TPM=y CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -509,7 +526,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set # CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set -# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -531,6 +552,9 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y @@ -548,17 +572,18 @@ CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_CBMEM=y # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_EM100PRO_SPI_CONSOLE is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +591,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_NULL=y +CONFIG_HWBASE_DEBUG_CB=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -580,6 +605,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y # System tables # CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -587,32 +613,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # Payload # CONFIG_PAYLOAD_NONE=y -# CONFIG_PAYLOAD_ELF is not set -# CONFIG_PAYLOAD_BOOTBOOT is not set -# CONFIG_PAYLOAD_FILO is not set -# CONFIG_PAYLOAD_GRUB2 is not set -# CONFIG_PAYLOAD_SEAGRUB is not set -# CONFIG_PAYLOAD_LINUXBOOT is not set -# CONFIG_PAYLOAD_SEABIOS is not set -# CONFIG_PAYLOAD_UBOOT is not set -# CONFIG_PAYLOAD_YABITS is not set -# CONFIG_PAYLOAD_LINUX is not set -# CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_OPTIONS="" -# CONFIG_PXE is not set -CONFIG_COMPRESS_SECONDARY_PAYLOAD=y - -# -# Secondary Payloads -# -# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set -# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set -# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set -# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set -# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set -# CONFIG_TINT_SECONDARY_PAYLOAD is not set -# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set -# end of Secondary Payloads # end of Payload # @@ -624,6 +624,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # # CONFIG_DISPLAY_MTRRS is not set +# +# Vendorcode Debug Settings +# + # # BLOB Debug Settings # @@ -637,13 +641,14 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set CONFIG_HAVE_EM100_SUPPORT=y # CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_RAMSTAGE_ADA=y @@ -651,6 +656,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y CONFIG_HWBASE_DYNAMIC_MMIO=y CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y CONFIG_WARNINGS_ARE_ERRORS=y CONFIG_MAX_REBOOT_CNT=3 CONFIG_RELOCATABLE_MODULES=y diff --git a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..15e93305 --- /dev/null +++ b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,667 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_DELL is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_MAINBOARD_FAMILY="ThinkPad W541" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W541" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="lenovo/haswell" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 +CONFIG_MAX_CPUS=8 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/t440p/ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set +CONFIG_BOARD_LENOVO_THINKPAD_W541=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_R500 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T410 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_R60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X301 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X230T is not set +# CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_HASWELL_COMMON=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_PS2K_EISAID="LEN0071" +CONFIG_PS2M_EISAID="LEN004A" +CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" +CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set +CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y +CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y +CONFIG_EC_LENOVO_PMH7=y + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_INTEL_TXT is not set +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/w541_12mb/config/libgfxinit_txtmode b/config/coreboot/w541_12mb/config/libgfxinit_txtmode index b3e169d4..2c0dddb9 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541_12mb/config/libgfxinit_txtmode @@ -6,7 +6,6 @@ # # General setup # -CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -14,12 +13,15 @@ CONFIG_COMPILER_GCC=y CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set +# CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set # CONFIG_OPTION_BACKEND_NONE is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -31,11 +33,17 @@ CONFIG_USE_BLOBS=y CONFIG_HAVE_ASAN_IN_ROMSTAGE=y CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -CONFIG_NO_STAGE_CACHE=y -# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_TSEG_STAGE_CACHE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) # end of General setup # @@ -53,30 +61,28 @@ CONFIG_NO_STAGE_CACHE=y # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_EXAMPLE is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set @@ -91,7 +97,6 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_STARLABS is not set @@ -111,31 +116,30 @@ CONFIG_FMDFILE="" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0xBE0000 CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -# CONFIG_VBOOT is not set -CONFIG_VBOOT_VBNV_OFFSET=0x2a -CONFIG_VARIANT_DIR="w541" CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_VARIANT_DIR="w541" +CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt" +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_OVERRIDE_DEVICETREE="" CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set CONFIG_TPM_PIRQ=0x0 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xff7c0000 CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -148,12 +152,16 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/t440p/gbe" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_ENABLE_DDR_2X_REFRESH is not set CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad W541" CONFIG_HAVE_IFD_BIN=y -# CONFIG_BOARD_LENOVO_G505S is not set # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY is not set # CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T500 is not set @@ -174,6 +182,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_Z61T is not set # CONFIG_BOARD_LENOVO_R60 is not set # CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_M710S is not set # CONFIG_BOARD_LENOVO_X131E is not set # CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set @@ -185,6 +194,7 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set +# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y @@ -192,11 +202,16 @@ CONFIG_PS2K_EISAID="LEN0071" CONFIG_PS2M_EISAID="LEN004A" CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" CONFIG_GFX_GMA_PANEL_1_PORT="DP3" +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y # CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_HEAP_SIZE=0x4000 +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -209,6 +224,7 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set CONFIG_COREBOOT_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=12288 @@ -230,7 +246,6 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # -CONFIG_ARCH_ALL_STAGES_X86=y CONFIG_CHIPSET_DEVICETREE="" CONFIG_CBFS_MCACHE_SIZE=0x4000 CONFIG_ROMSTAGE_ADDR=0x2000000 @@ -238,34 +253,34 @@ CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_TSEG_SIZE=0x800000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d" +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_ASPM=y CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4 -CONFIG_UART_PCI_ADDR=0x0 -CONFIG_CBFS_CACHE_ALIGN=8 +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 # # CPU # CONFIG_CPU_INTEL_HASWELL=y -CONFIG_SSE2=y CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -274,7 +289,6 @@ CONFIG_SET_MSR_AESNI_LOCK_BIT=y CONFIG_CPU_INTEL_COMMON_TIMEBASE=y CONFIG_CPU_INTEL_COMMON_VOLTAGE=y CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y CONFIG_PARALLEL_MP=y CONFIG_XAPIC_ONLY=y # CONFIG_X2APIC_ONLY is not set @@ -283,14 +297,13 @@ CONFIG_XAPIC_ONLY=y CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y -CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y -CONFIG_SMM_STUB_STACK_SIZE=0x400 -CONFIG_CPU_INFO_V2=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y -CONFIG_MMX=y CONFIG_SSE=y +CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y @@ -307,8 +320,6 @@ CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge # -CONFIG_SOUTH_BRIDGE_OPTIONS=y -CONFIG_HPET_MIN_TICKS=0x80 # CONFIG_PCIEXP_HOTPLUG is not set CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y @@ -325,12 +336,12 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 CONFIG_RCBA_LENGTH=0x4000 @@ -347,8 +358,10 @@ CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +# CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y CONFIG_H8_HAS_PRIMARY_FN_KEYS=y +CONFIG_H8_HAS_LEDLOGO=y CONFIG_EC_LENOVO_PMH7=y # @@ -371,8 +384,10 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_NUM_IPI_STARTS=2 +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -382,6 +397,7 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -393,6 +409,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y CONFIG_MAINBOARD_USE_LIBGFXINIT=y # CONFIG_VGA_ROM_RUN is not set # CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y # # Display @@ -404,14 +421,14 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_AZALIA_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -419,7 +436,8 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATOR_V4=y +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y # end of Devices # @@ -429,21 +447,19 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 # CONFIG_ELOG is not set CONFIG_CACHE_MRC_SETTINGS=y # CONFIG_MRC_SETTINGS_PROTECT is not set -CONFIG_MRC_STASH_TO_CBMEM=y # CONFIG_SMMSTORE is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y CONFIG_TPM_INIT_RAMSTAGE=y # CONFIG_TPM_PPI is not set @@ -454,27 +470,34 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y # CONFIG_USBDEBUG is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set CONFIG_INTEL_DDI=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -CONFIG_INTEL_GMA_OPREGION_2_0=y CONFIG_GFX_GMA_DYN_CPU=y CONFIG_GFX_GMA_GENERATION="Haswell" CONFIG_GFX_GMA_PCH="Lynx_Point" CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_MEMORY_MAPPED_TPM=y CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y # end of Generic Drivers # @@ -502,7 +525,11 @@ CONFIG_MAINBOARD_HAS_TPM1=y # CONFIG_TPM_DEACTIVATE is not set # CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set -# CONFIG_TPM_MEASURED_BOOT is not set +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -524,6 +551,9 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y @@ -541,6 +571,7 @@ CONFIG_SQUELCH_EARLY_SMP=y CONFIG_CONSOLE_CBMEM=y # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_EM100PRO_SPI_CONSOLE is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y @@ -573,6 +604,7 @@ CONFIG_USE_WATCHDOG_ON_BOOT=y # System tables # CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -580,32 +612,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # Payload # CONFIG_PAYLOAD_NONE=y -# CONFIG_PAYLOAD_ELF is not set -# CONFIG_PAYLOAD_BOOTBOOT is not set -# CONFIG_PAYLOAD_FILO is not set -# CONFIG_PAYLOAD_GRUB2 is not set -# CONFIG_PAYLOAD_SEAGRUB is not set -# CONFIG_PAYLOAD_LINUXBOOT is not set -# CONFIG_PAYLOAD_SEABIOS is not set -# CONFIG_PAYLOAD_UBOOT is not set -# CONFIG_PAYLOAD_YABITS is not set -# CONFIG_PAYLOAD_LINUX is not set -# CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_OPTIONS="" -# CONFIG_PXE is not set -CONFIG_COMPRESS_SECONDARY_PAYLOAD=y - -# -# Secondary Payloads -# -# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set -# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set -# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set -# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set -# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set -# CONFIG_TINT_SECONDARY_PAYLOAD is not set -# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set -# end of Secondary Payloads # end of Payload # @@ -617,6 +623,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # # CONFIG_DISPLAY_MTRRS is not set +# +# Vendorcode Debug Settings +# + # # BLOB Debug Settings # @@ -630,7 +640,6 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set @@ -638,6 +647,7 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_ADA_CODE is not set CONFIG_HAVE_EM100_SUPPORT=y # CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_RAMSTAGE_ADA=y @@ -645,6 +655,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y CONFIG_HWBASE_DYNAMIC_MMIO=y CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y CONFIG_WARNINGS_ARE_ERRORS=y CONFIG_MAX_REBOOT_CNT=3 CONFIG_RELOCATABLE_MODULES=y From ac7ce93005ca7d8eccec5052d2e459514af70f39 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 20 Apr 2024 22:22:22 +0100 Subject: [PATCH 0017/1319] add 9020sff/mt configs using haswell NRI Signed-off-by: Leah Rowe --- .../config/libgfxinit_corebootfb | 627 ++++++++++++++++++ .../config/libgfxinit_txtmode | 624 +++++++++++++++++ .../coreboot/dell9020mt-nri_12mb/target.cfg | 7 + .../config/libgfxinit_corebootfb | 627 ++++++++++++++++++ .../config/libgfxinit_txtmode | 624 +++++++++++++++++ .../coreboot/dell9020sff-nri_12mb/target.cfg | 7 + ...-haswell-make-IOMMU-a-runtime-option.patch | 292 ++++++++ ...tiplex_9020-Disable-IOMMU-by-default.patch | 29 + ..._9020-Implement-late-HWM-initializat.patch | 594 +++++++++++++++++ ...Fully-disable-iGPU-when-dGPU-is-used.patch | 51 ++ config/vendor/sources | 2 +- 11 files changed, 3483 insertions(+), 1 deletion(-) create mode 100644 config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/dell9020mt-nri_12mb/target.cfg create mode 100644 config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb create mode 100644 config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode create mode 100644 config/coreboot/dell9020sff-nri_12mb/target.cfg create mode 100644 config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch create mode 100644 config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch create mode 100644 config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch create mode 100644 config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..d587473c --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,627 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +CONFIG_UTIL_GENPARSER=y +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..fb415885 --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode @@ -0,0 +1,624 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +CONFIG_UTIL_GENPARSER=y +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_E6400 is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020mt-nri_12mb/target.cfg b/config/coreboot/dell9020mt-nri_12mb/target.cfg new file mode 100644 index 00000000..37d8f553 --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="haswell" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb new file mode 100644 index 00000000..7bfe30a2 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb @@ -0,0 +1,627 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840 +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_BOOTSPLASH is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode new file mode 100644 index 00000000..c976b093 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode @@ -0,0 +1,624 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ARCH_SUPPORTS_CLANG=y +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_IWYU is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_OPTION_BACKEND_NONE is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE_LZMA=y +# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set +CONFIG_SEPARATE_ROMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_USE_AMD_BLOBS is not set +# CONFIG_USE_QC_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_HAVE_ASAN_IN_ROMSTAGE=y +CONFIG_HAVE_ASAN_IN_RAMSTAGE=y +# CONFIG_ASAN is not set +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_FW_CONFIG is not set + +# +# Software Bill Of Materials (SBOM) +# +# CONFIG_SBOM is not set +# end of Software Bill Of Materials (SBOM) +# end of General setup + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_51NB is not set +# CONFIG_VENDOR_ACER is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BOSTENTECH is not set +# CONFIG_VENDOR_BYTEDANCE is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_CLEVO is not set +# CONFIG_VENDOR_COMPULAB is not set +CONFIG_VENDOR_DELL=y +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_EXAMPLE is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_INVENTEC is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIBRETREND is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PINE64 is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PRODRIVE is not set +# CONFIG_VENDOR_PROTECTLI is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RAZER is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_STARLABS is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_SYSTEM76 is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_UP is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_DIR="dell/optiplex_9020" +CONFIG_VGA_BIOS_ID="8086,0166" +CONFIG_DIMM_MAX=4 +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_FMDFILE="" +# CONFIG_NO_POST is not set +CONFIG_MAINBOARD_VENDOR="Dell Inc." +CONFIG_CBFS_SIZE=0x800000 +CONFIG_CONSOLE_SERIAL=y +CONFIG_MAX_CPUS=8 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_IO=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_VBOOT is not set +CONFIG_OVERRIDE_DEVICETREE="" +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc." +CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +# CONFIG_CONSOLE_POST is not set +# CONFIG_BOARD_DELL_E6400 is not set +CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y +# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set +# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set +# CONFIG_BOARD_DELL_PRECISION_T1650 is not set +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 +CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" +CONFIG_DCACHE_RAM_BASE=0xff7c0000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 +CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd" +CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin" +CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_ENABLE_DDR_2X_REFRESH is not set +CONFIG_PCIEXP_AER=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_DEBUG_SMI is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +CONFIG_GFX_GMA_PANEL_1_PORT="eDP" +CONFIG_TTYS0_BAUD=115200 +CONFIG_D3COLD_SUPPORT=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_GFX_GMA_PANEL_1_ON_EDP=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +CONFIG_HEAP_SIZE=0x100000 +CONFIG_EC_GPE_SCI=0x50 +CONFIG_BOARD_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +CONFIG_COREBOOT_ROMSIZE_KB_12288=y +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=12288 +CONFIG_ROM_SIZE=0x00c00000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 +# end of Mainboard + +# +# Chipset +# + +# +# SoC +# +CONFIG_CHIPSET_DEVICETREE="" +CONFIG_CBFS_MCACHE_SIZE=0x4000 +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_SERIRQ_CONTINUOUS_MODE=y +CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000 +CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 +CONFIG_EHCI_BAR=0xe8000000 +CONFIG_ACPI_CPU_STRING="CP%02X" +CONFIG_STACK_SIZE=0x2000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 +CONFIG_INTEL_GMA_BCLV_WIDTH=16 +CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 +CONFIG_INTEL_GMA_BCLM_WIDTH=16 +CONFIG_BOOTBLOCK_IN_CBFS=y +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 +CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 +CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_DISABLE_ME_PCI=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6 +CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 +CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_CBFS_CACHE_ALIGN=8 + +# +# CPU +# +CONFIG_CPU_INTEL_HASWELL=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_SET_MSR_AESNI_LOCK_BIT=y +CONFIG_CPU_INTEL_COMMON_TIMEBASE=y +CONFIG_CPU_INTEL_COMMON_VOLTAGE=y +CONFIG_CPU_INTEL_COMMON_SMM=y +CONFIG_PARALLEL_MP=y +CONFIG_XAPIC_ONLY=y +# CONFIG_X2APIC_ONLY is not set +# CONFIG_X2APIC_RUNTIME is not set +# CONFIG_X2APIC_LATE_WORKAROUND is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_MONOTONIC_TIMER=y +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_HAVE_SMI_HANDLER=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 +CONFIG_AP_STACK_SIZE=0x800 +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SSE2=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_INTEL_HASWELL=y +CONFIG_USE_NATIVE_RAMINIT=y + +# +# Southbridge +# +# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y +CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y +CONFIG_FINALIZE_USB_ROUTE_XHCI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y +CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set +CONFIG_INTEL_CHIPSET_LOCKDOWN=y +CONFIG_TCO_SPACE_NOT_YET_SPLIT=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y +CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 +CONFIG_RCBA_LENGTH=0x4000 + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_SCH555x=y + +# +# Embedded Controllers +# + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_STITCH_ME_BIN is not set +# CONFIG_CHECK_ME is not set +# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set +# CONFIG_USE_ME_CLEANER is not set +CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y +CONFIG_HAVE_GBE_BIN=y +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_ARCH_ALL_STAGES_X86_32=y +CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y +CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_POSTCAR_STAGE=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +CONFIG_HAVE_CF9_RESET=y +CONFIG_DEBUG_HW_BREAKPOINTS=y +CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y +# CONFIG_DUMP_SMBIOS_TYPE17 is not set +# end of Chipset + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_LIBGFXINIT=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +CONFIG_NO_EARLY_GFX_INIT=y + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set +# end of Display + +CONFIG_PCI=y +CONFIG_ECAM_MMCONF_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_ECAM_MMCONF_LENGTH=0x04000000 +CONFIG_PCI_ALLOW_BUS_MASTER=y +CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y +CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y +# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set +# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_INTEL_GMA_HAVE_VBT=y +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +CONFIG_USE_DDR3=y +# end of Devices + +# +# Generic Drivers +# +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_ELOG is not set +CONFIG_CACHE_MRC_SETTINGS=y +# CONFIG_MRC_SETTINGS_PROTECT is not set +# CONFIG_SMMSTORE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_OXPCIE is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_USBDEBUG is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set +# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set +# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set +# CONFIG_DRIVERS_I2C_MAX98396 is not set +CONFIG_INTEL_DDI=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_VBT_CBFS_COMPRESSION_LZMA=y +# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set +# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set +CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_GFX_GMA=y +CONFIG_GFX_GMA_DYN_CPU=y +CONFIG_GFX_GMA_GENERATION="Haswell" +CONFIG_GFX_GMA_PCH="Lynx_Point" +CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" +CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" +# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_VGA=y +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_DRIVERS_WIFI_GENERIC=y +CONFIG_DRIVERS_MTK_WIFI=y +# end of Generic Drivers + +# +# Security +# + +# +# CBFS verification +# +# CONFIG_CBFS_VERIFICATION is not set +# end of CBFS verification + +# +# Verified Boot (vboot) +# +# end of Verified Boot (vboot) + +# +# Trusted Platform Module +# +CONFIG_NO_TPM=y +CONFIG_PCR_BOOT_MODE=1 +CONFIG_PCR_HWID=1 +CONFIG_PCR_SRTM=2 +CONFIG_PCR_FW_VER=10 +CONFIG_PCR_RUNTIME_DATA=3 +# end of Trusted Platform Module + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +# end of Memory initialization + +# CONFIG_STM is not set +# CONFIG_INTEL_CBNT_SUPPORT is not set +CONFIG_BOOTMEDIA_LOCK_NONE=y +# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set +# CONFIG_BOOTMEDIA_LOCK_CHIP is not set +# CONFIG_BOOTMEDIA_SMM_BWP is not set +# end of Security + +CONFIG_ACPI_HAVE_PCAT_8259=y +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +CONFIG_ACPI_SOC_NVS=y +CONFIG_ACPI_NO_CUSTOM_MADT=y +CONFIG_ACPI_COMMON_MADT_LAPIC=y +CONFIG_ACPI_COMMON_MADT_IOAPIC=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_CONSOLE_I2C_SMBUS is not set +# CONFIG_EM100PRO_SPI_CONSOLE is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y +CONFIG_CONSOLE_USE_ANSI_ESCAPES=y +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HWBASE_DEBUG_CB=y +# end of Console + +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_MONOTONIC_TIMER=y +CONFIG_HAVE_OPTION_TABLE=y +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y + +# +# System tables +# +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_BIOS_VENDOR="coreboot" +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +# end of System tables + +# +# Payload +# +CONFIG_PAYLOAD_NONE=y +# end of Payload + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DISPLAY_MTRRS is not set + +# +# Vendorcode Debug Settings +# + +# +# BLOB Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set +# end of Debugging + +CONFIG_RAMSTAGE_ADA=y +CONFIG_RAMSTAGE_LIBHWBASE=y +CONFIG_HWBASE_DYNAMIC_MMIO=y +CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 +CONFIG_HWBASE_DIRECT_PCIDEV=y +CONFIG_DECOMPRESS_OFAST=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_RELOCATABLE_MODULES=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/target.cfg b/config/coreboot/dell9020sff-nri_12mb/target.cfg new file mode 100644 index 00000000..37d8f553 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/target.cfg @@ -0,0 +1,7 @@ +tree="haswell" +xarch="i386-elf" +payload_seabios="y" +payload_seabios_withgrub="y" +payload_seabios_grubonly="y" +payload_memtest="y" +grub_scan_disk="ahci" diff --git a/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch b/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch new file mode 100644 index 00000000..81b8e839 --- /dev/null +++ b/config/coreboot/haswell/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch @@ -0,0 +1,292 @@ +From d97b865a2210e70583e8bf5ee3a73d3c131b29c1 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 22:51:09 +0000 +Subject: [PATCH 1/4] nb/intel/haswell: make IOMMU a runtime option + +When I tested graphics cards on a coreboot port for Dell +OptiPlex 9020 SFF, I could not use a graphics card unless +I set iommu=off on the Linux cmdline. + +Coreboot's current behaviour is to check whether the CPU +has vt-d support and, if it does, initialise the IOMMU. + +This patch maintains the current behaviour by default, but +allows the user to turn *off* the IOMMU, even if vt-d is +supported by the host CPU. + +If iommu=Disable is specified, the check will not be +performed, and the IOMMU will be left disabled. This option +has been added to all current Haswell boards, though it is +recommended to leave the IOMMU turned on in most setups. + +Signed-off-by: Leah Rowe +--- + src/mainboard/asrock/b85m_pro4/cmos.default | 1 + + src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++ + src/mainboard/asrock/h81m-hds/cmos.default | 1 + + src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++ + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++ + src/mainboard/google/beltino/cmos.layout | 5 +++++ + src/mainboard/google/slippy/cmos.layout | 5 +++++ + src/mainboard/intel/baskingridge/cmos.layout | 4 ++++ + src/mainboard/lenovo/haswell/cmos.default | 1 + + src/mainboard/lenovo/haswell/cmos.layout | 3 +++ + src/mainboard/supermicro/x10slm-f/cmos.default | 1 + + src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++ + src/northbridge/intel/haswell/early_init.c | 5 +++++ + 14 files changed, 48 insertions(+) + +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.default ++++ b/src/mainboard/asrock/b85m_pro4/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout +index efdc333fc2..c9883ea71d 100644 +--- a/src/mainboard/asrock/b85m_pro4/cmos.layout ++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout +@@ -11,6 +11,7 @@ + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail ++ 412 1 e 6 iommu + 984 16 h 0 check_sum + # ----------------------------------------------------------------- + +@@ -38,6 +39,8 @@ + 5 0 Disable + 5 1 Enable + 5 2 Keep ++ 6 0 Disable ++ 6 1 Enable + # ----------------------------------------------------------------- + + # ----------------------------------------------------------------- +diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default +index 01bf20ad16..dfc8b80fb0 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.default ++++ b/src/mainboard/asrock/h81m-hds/cmos.default +@@ -4,3 +4,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Enable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout +index c9ba76c78f..95ee3d36fb 100644 +--- a/src/mainboard/asrock/h81m-hds/cmos.layout ++++ b/src/mainboard/asrock/h81m-hds/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index cd4046f1ab..c974022472 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,3 +3,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable ++iommu=Enable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index c9ba76c78f..72ff9c4bee 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# turn iommu on or off ++412 1 e 6 iommu ++ + # coreboot config options: check sums + 984 16 h 0 check_sum + +@@ -52,6 +55,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/beltino/cmos.layout ++++ b/src/mainboard/google/beltino/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout +index 78d44c1415..c143979ae1 100644 +--- a/src/mainboard/google/slippy/cmos.layout ++++ b/src/mainboard/google/slippy/cmos.layout +@@ -19,6 +19,9 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++# enable or disable iommu ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +50,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout +index 78d44c1415..f2c602f541 100644 +--- a/src/mainboard/intel/baskingridge/cmos.layout ++++ b/src/mainboard/intel/baskingridge/cmos.layout +@@ -19,6 +19,8 @@ entries + 408 1 e 1 nmi + 409 2 e 7 power_on_after_fail + ++412 1 e 8 iommu ++ + # coreboot config options: bootloader + #Used by ChromeOS: + 416 128 r 0 vbnv +@@ -47,6 +49,8 @@ enumerations + 7 0 Disable + 7 1 Enable + 7 2 Keep ++8 0 Disable ++8 1 Enable + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default +index 08db97c5a9..cc6b363cd9 100644 +--- a/src/mainboard/lenovo/haswell/cmos.default ++++ b/src/mainboard/lenovo/haswell/cmos.default +@@ -14,3 +14,4 @@ trackpoint=Enable + backlight=Keyboard + enable_dual_graphics=Disable + usb_always_on=Disable ++iommu=Enable +diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout +index 27915d3ab7..59df76b64c 100644 +--- a/src/mainboard/lenovo/haswell/cmos.layout ++++ b/src/mainboard/lenovo/haswell/cmos.layout +@@ -23,6 +23,7 @@ entries + + # coreboot config options: EC + 411 1 e 8 first_battery ++413 1 e 14 iommu + 415 1 e 1 wlan + 416 1 e 1 trackpoint + 417 1 e 1 fn_ctrl_swap +@@ -72,6 +73,8 @@ enumerations + 13 0 Disable + 13 1 AC and battery + 13 2 AC only ++14 0 Disable ++14 1 Enable + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default +index 7ce38fb5d7..6049e7938a 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.default ++++ b/src/mainboard/supermicro/x10slm-f/cmos.default +@@ -5,3 +5,4 @@ debug_level=Debug + nmi=Enable + power_on_after_fail=Keep + hide_ast2400=Disable ++iommu=Enable +diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout +index 38ba87aa45..24d39e97ee 100644 +--- a/src/mainboard/supermicro/x10slm-f/cmos.layout ++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout +@@ -21,6 +21,9 @@ entries + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + ++# enable or disable iommu ++412 1 e 6 iommu ++ + # coreboot config options: mainboard + 416 1 e 1 hide_ast2400 + +@@ -55,6 +58,9 @@ enumerations + 5 1 Enable + 5 2 Keep + ++6 0 Disable ++6 1 Enable ++ + # ----------------------------------------------------------------- + checksums + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index e47deb5da6..1a7e0b1076 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -5,6 +5,7 @@ + #include + #include + #include ++#include + + #include "haswell.h" + +@@ -157,6 +158,10 @@ static void haswell_setup_misc(void) + static void haswell_setup_iommu(void) + { + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ u8 enable_iommu = get_uint_option("iommu", 1); ++ ++ if (!enable_iommu) ++ return; + + if (capid0_a & VTD_DISABLE) + return; +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch b/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch new file mode 100644 index 00000000..fbb40293 --- /dev/null +++ b/config/coreboot/haswell/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch @@ -0,0 +1,29 @@ +From 153ca1a43c2c978fa2b2b82d988b0f838953cfb9 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 2 Mar 2024 23:00:09 +0000 +Subject: [PATCH 2/4] dell/optiplex_9020: Disable IOMMU by default + +Needed to make graphics cards work. Turning it on is +recommended if only using iGPU, otherwise leave it off +by default. The IOMMU is extremely buggy when a graphics +card is used. Leaving it off by default will ensure that +the default ROM images in Libreboot will work on any setup. + +Signed-off-by: Leah Rowe +--- + src/mainboard/dell/optiplex_9020/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index c974022472..a0acd7b6bb 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -3,4 +3,4 @@ boot_option=Fallback + debug_level=Debug + nmi=Disable + power_on_after_fail=Disable +-iommu=Enable ++iommu=Disable +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch new file mode 100644 index 00000000..527c18d3 --- /dev/null +++ b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -0,0 +1,594 @@ +From 08bae51a77c2c92fefef79e9c9b6ff963b3812cc Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Sat, 6 Apr 2024 23:25:15 +0100 +Subject: [PATCH 3/4] mb/dell/optiplex_9020: Implement late HWM initialization + +There are 4 different chassis types specified by vendor firmware, each +with a slightly different HWM configuration. + +The chassis type to use is determined at runtime by reading a set of +4 PCH GPIOs: 70, 38, 17, and 0. + +Additionally vendor firmware also provides an option to run the fans at +full speed. This is substituted with a coreboot nvram option in this +implementation. + +This was tested to make fan control work on my OptiPlex 7020 SFF. + +NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 +however the OptiPlex 9020's SCH5555 does not use externally +programmed EC firmware. + +Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 +Signed-off-by: Mate Kukri +--- + src/mainboard/dell/optiplex_9020/Makefile.mk | 3 +- + src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- + src/mainboard/dell/optiplex_9020/cmos.default | 1 + + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- + src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 + + 7 files changed, 455 insertions(+), 22 deletions(-) + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c + create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h + +diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk +index 6ca2f2afaa..08e2e53577 100644 +--- a/src/mainboard/dell/optiplex_9020/Makefile.mk ++++ b/src/mainboard/dell/optiplex_9020/Makefile.mk +@@ -2,4 +2,5 @@ + + romstage-y += gpio.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +-bootblock-y += bootblock.c ++ramstage-y += sch5555_ec.c ++bootblock-y += bootblock.c sch5555_ec.c +diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c +index 2837cf9cf1..e5e759273e 100644 +--- a/src/mainboard/dell/optiplex_9020/bootblock.c ++++ b/src/mainboard/dell/optiplex_9020/bootblock.c +@@ -4,29 +4,14 @@ + #include + #include + #include +- +-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) +-{ +- // Clear EC-to-Host mailbox +- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); +- outb(tmp, SCH555x_EMI_IOBASE + 1); +- +- // Send address and value to the EC +- sch555x_emi_write16(0, (addr1 * 2) | 0x101); +- sch555x_emi_write32(4, val | (addr2 << 16)); +- +- // Wait for acknowledgement message from EC +- outb(1, SCH555x_EMI_IOBASE); +- size_t timeout = 0; +- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); +-} ++#include "sch5555_ec.h" + + struct ec_init_entry { + uint16_t addr; + uint8_t val; + }; + +-static void ec_init(void) ++static void bootblock_ec_init(void) + { + /* + * Tables from CORE_PEI +@@ -108,9 +93,9 @@ void mainboard_config_superio(void) + outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); + outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); + +- // Magic EC init +- ec_init(); ++ // Perform bootblock EC initialization ++ bootblock_ec_init(); + +- // Magic EC init is needed for UART1 initialization to work ++ // Bootblock EC initialization is required for UART1 to work + sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default +index a0acd7b6bb..9e02534c16 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.default ++++ b/src/mainboard/dell/optiplex_9020/cmos.default +@@ -4,3 +4,4 @@ debug_level=Debug + nmi=Disable + power_on_after_fail=Disable + iommu=Disable ++fan_full_speed=Disable +diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout +index 72ff9c4bee..4a1496a878 100644 +--- a/src/mainboard/dell/optiplex_9020/cmos.layout ++++ b/src/mainboard/dell/optiplex_9020/cmos.layout +@@ -22,7 +22,10 @@ entries + 409 2 e 5 power_on_after_fail + + # turn iommu on or off +-412 1 e 6 iommu ++411 1 e 6 iommu ++ ++# coreboot config options: EC ++412 1 e 1 fan_full_speed + + # coreboot config options: check sums + 984 16 h 0 check_sum +diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c +index c834fea5d3..10b8aaca0e 100644 +--- a/src/mainboard/dell/optiplex_9020/mainboard.c ++++ b/src/mainboard/dell/optiplex_9020/mainboard.c +@@ -1,7 +1,12 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include ++#include + #include + #include ++#include ++#include ++#include "sch5555_ec.h" + + static void mainboard_enable(struct device *dev) + { +@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev) + struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + }; ++ ++#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_PKG_POWER_ANY 0xffff ++ ++struct hwm_tab_entry { ++ uint16_t addr; ++ uint8_t val; ++ uint8_t flags; ++ uint16_t pkg_power; ++}; ++ ++struct hwm_tab_entry HWM_TAB3[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x8a, 0, 0x0010 }, ++ { 0x086, 0x4c, 0, 0x0010 }, ++ { 0x08a, 0x66, 0, 0x0010 }, ++ { 0x08b, 0x5b, 0, 0x0010 }, ++ { 0x090, 0x65, 0, 0xffff }, ++ { 0x091, 0x70, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x86, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x99, 0, 0xffff }, ++ { 0x280, 0xa0, 0, 0x0010 }, ++ { 0x281, 0x0f, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x68, 0, 0x0010 }, ++ { 0x289, 0x10, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB4[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x99, 0, 0x0020 }, ++ { 0x085, 0xad, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x8b, 0, 0x0010 }, ++ { 0x090, 0x5e, 0, 0xffff }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa4, 0, 0xffff }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0a, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x90, 0, 0xffff }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB5[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x66, 0, 0x0020 }, ++ { 0x085, 0x5d, 0, 0x0010 }, ++ { 0x086, 0x1c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x41, 0, 0x0010 }, ++ { 0x08b, 0x76, 0, 0x0020 }, ++ { 0x08b, 0x80, 0, 0x0010 }, ++ { 0x090, 0x5d, 0, 0x0020 }, ++ { 0x090, 0x5e, 0, 0x0010 }, ++ { 0x091, 0x5e, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0xa3, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x08, 0, 0xffff }, ++ { 0x0a1, 0x0a, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9a, 0, 0xffff }, ++ { 0x0b3, 0x7c, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x98, 0, 0x0020 }, ++ { 0x1be, 0x90, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x28, 0, 0x0020 }, ++ { 0x289, 0x0a, 0, 0x0020 }, ++ { 0x288, 0x28, 0, 0x0010 }, ++ { 0x289, 0x0a, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++struct hwm_tab_entry HWM_TAB6[] = { ++ { 0x005, 0x33, 0, 0xffff }, ++ { 0x018, 0x2f, 0, 0xffff }, ++ { 0x019, 0x2f, 0, 0xffff }, ++ { 0x01a, 0x2f, 0, 0xffff }, ++ { 0x080, 0x00, 0, 0xffff }, ++ { 0x081, 0x00, 0, 0xffff }, ++ { 0x083, 0xbb, 0, 0xffff }, ++ { 0x085, 0x98, 0, 0xffff }, ++ { 0x086, 0x3c, 0, 0xffff }, ++ { 0x08a, 0x39, 0, 0x0020 }, ++ { 0x08a, 0x3d, 0, 0x0010 }, ++ { 0x08b, 0x44, 0, 0x0020 }, ++ { 0x08b, 0x51, 0, 0x0010 }, ++ { 0x090, 0x61, 0, 0xffff }, ++ { 0x091, 0x6d, 0, 0xffff }, ++ { 0x092, 0x86, 0, 0xffff }, ++ { 0x096, 0xa4, 0, 0xffff }, ++ { 0x097, 0xa4, 0, 0xffff }, ++ { 0x098, 0x9f, 0, 0x0020 }, ++ { 0x098, 0xa4, 0, 0x0010 }, ++ { 0x09b, 0xa4, 0, 0xffff }, ++ { 0x0a0, 0x0e, 0, 0xffff }, ++ { 0x0a1, 0x0e, 0, 0xffff }, ++ { 0x0ae, 0x7c, 0, 0xffff }, ++ { 0x0af, 0x7c, 0, 0xffff }, ++ { 0x0b0, 0x9b, 0, 0x0020 }, ++ { 0x0b0, 0x98, 0, 0x0010 }, ++ { 0x0b3, 0x9a, 0, 0xffff }, ++ { 0x0b6, 0x08, 0, 0xffff }, ++ { 0x0b7, 0x08, 0, 0xffff }, ++ { 0x0ea, 0x64, 0, 0x0020 }, ++ { 0x0ea, 0x5c, 0, 0x0010 }, ++ { 0x0ef, 0xff, 0, 0xffff }, ++ { 0x0f8, 0x15, 0, 0xffff }, ++ { 0x0f9, 0x00, 0, 0xffff }, ++ { 0x0f0, 0x30, 0, 0xffff }, ++ { 0x0fd, 0x01, 0, 0xffff }, ++ { 0x1a1, 0x00, 0, 0xffff }, ++ { 0x1a2, 0x00, 0, 0xffff }, ++ { 0x1b1, 0x08, 0, 0xffff }, ++ { 0x1be, 0x9a, 0, 0x0020 }, ++ { 0x1be, 0x96, 0, 0x0010 }, ++ { 0x280, 0x94, 0, 0x0020 }, ++ { 0x281, 0x11, 0, 0x0020 }, ++ { 0x280, 0x94, 0, 0x0010 }, ++ { 0x281, 0x11, 0, 0x0010 }, ++ { 0x282, 0x03, 0, 0xffff }, ++ { 0x283, 0x0a, 0, 0xffff }, ++ { 0x284, 0x80, 0, 0xffff }, ++ { 0x285, 0x03, 0, 0xffff }, ++ { 0x288, 0x94, 0, 0x0020 }, ++ { 0x289, 0x11, 0, 0x0020 }, ++ { 0x288, 0x94, 0, 0x0010 }, ++ { 0x289, 0x11, 0, 0x0010 }, ++ { 0x28a, 0x03, 0, 0xffff }, ++ { 0x28b, 0x0a, 0, 0xffff }, ++ { 0x28c, 0x80, 0, 0xffff }, ++ { 0x28d, 0x03, 0, 0xffff }, ++}; ++ ++static uint8_t get_chassis_type(void) ++{ ++ uint8_t gpio_chassis_type; ++ ++ // Read chassis type from GPIO ++ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | ++ get_gpio(17) << 1 | get_gpio(0); ++ ++ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); ++ ++ // Turn it into internal chassis index ++ switch (gpio_chassis_type) { ++ case 0x08: ++ case 0x0a: ++ return 4; ++ case 0x0b: ++ return 3; ++ case 0x0c: ++ return 5; ++ case 0x0d: // SFF ++ case 0x0e: ++ case 0x0f: ++ return 6; ++ default: ++ die("Unknown GPIO chassis type\n"); ++ } ++ ++} ++ ++static uint8_t get_temp_target(void) ++{ ++ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; ++ if (!val) ++ val = 20; ++ return 0x95 - val; ++} ++ ++static uint16_t get_pkg_power(void) ++{ ++ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; ++ if (rapl_power_unit) ++ rapl_power_unit = 2 << (rapl_power_unit - 1); ++ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; ++ if (pkg_power_info / rapl_power_unit > 0x41) ++ return 32; ++ else ++ return 16; ++} ++ ++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) ++{ ++ uint8_t temp_target = get_temp_target(); ++ uint16_t pkg_power = get_pkg_power(); ++ ++ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); ++ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); ++ ++ for (size_t i = 0; i < size; ++i) { ++ // Skip entry if it doesn't apply for this package power ++ if (arr[i].pkg_power != pkg_power && ++ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) ++ continue; ++ ++ uint8_t val = arr[i].val; ++ ++ // Add temp target to value if requested (current tables never do) ++ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) ++ val += temp_target; ++ ++ // Perform write ++ ec_write(1, arr[i].addr, val); ++ ++ } ++} ++ ++static void sch5555_ec_hwm_init(void *arg) ++{ ++ uint8_t chassis_type, saved_2fc; ++ ++ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); ++ ++ saved_2fc = ec_read(1, 0x2fc); ++ ec_write(1, 0x2fc, 0xa0); ++ ec_write(1, 0x2fd, 0x32); ++ ++ // Apply HWM table based on chassis type ++ chassis_type = get_chassis_type(); ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ switch (chassis_type) { ++ case 3: ++ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); ++ break; ++ case 4: ++ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); ++ break; ++ case 5: ++ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); ++ break; ++ case 6: ++ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); ++ break; ++ default: ++ die("Unknown chassis type\n"); ++ } ++ ++ if (CONFIG_MAX_CPUS > 2) { ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); ++ } ++ ++ ec_write(1, 0x2fc, saved_2fc); ++ ++ // Apply full speed fan config if requested ++ if (get_uint_option("fan_full_speed", 0)) { ++ printk(BIOS_DEBUG, "Setting full fan speed\n"); ++ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); ++ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); ++ } ++ ++ ec_read(1, 0xb8); ++ ++ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) { ++ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb); ++ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb); ++ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb); ++ ec_write(1, 0x8a, 0x99); ++ ec_write(1, 0x8b, 0x47); ++ ec_write(1, 0x8c, 0x91); ++ } ++} ++ ++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +new file mode 100644 +index 0000000000..92244da9ab +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "sch5555_ec.h" ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++ ++ // read result ++ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); ++ return inb(SCH555x_EMI_IOBASE + 4); ++} ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) ++{ ++ // clear ec-to-host mailbox ++ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); ++ outb(tmp, SCH555x_EMI_IOBASE + 1); ++ ++ // send address and value ++ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); ++ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); ++ ++ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); ++ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); ++ ++ // send message to ec ++ outb(1, SCH555x_EMI_IOBASE); ++ ++ // wait for ack ++ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ if (inb(SCH555x_EMI_IOBASE + 1) & 1) ++ break; ++} +diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +new file mode 100644 +index 0000000000..6e703ff865 +--- /dev/null ++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h +@@ -0,0 +1,7 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#pragma once ++ ++uint8_t ec_read(uint8_t addr1, uint16_t addr2); ++ ++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch b/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch new file mode 100644 index 00000000..fb112f8c --- /dev/null +++ b/config/coreboot/haswell/patches/0024-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch @@ -0,0 +1,51 @@ +From ae494dc1b1dde92ec42390b85ced0ffe816f5110 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 6 Apr 2024 01:22:47 +0100 +Subject: [PATCH 4/4] nb/haswell: Fully disable iGPU when dGPU is used + +My earlier patch disabled decode *and* disabled the iGPU itself, but +a subsequent revision disabled only VGA decode. Upon revisiting, I +found that, actually, yes, you also need to disable the iGPU entirely. + +Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU. +With this patch, the iGPU is completely disabled when you install a +graphics card, but the iGPU is available to use when no graphics card +is present. + +For more context, see: + +Author: Leah Rowe +Date: Fri Feb 23 13:33:31 2024 +0000 + + nb/haswell: Disable iGPU when dGPU is used + +And look at the Gerrit comments: + +https://review.coreboot.org/c/coreboot/+/80717/ + +So, my original submission on change 80717 was actually correct. +This patch fixes the issue. I tested on iGPU and dGPU, with both +broadwell and haswell mrc.bin. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/gma.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c +index 9e9f9804f5..526a51aff0 100644 +--- a/src/northbridge/intel/haswell/gma.c ++++ b/src/northbridge/intel/haswell/gma.c +@@ -464,6 +464,9 @@ static void gma_func0_disable(struct device *dev) + { + /* Disable VGA decode */ + pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1); ++ ++ /* Required or else the graphics card doesn't work */ ++ dev->enabled = 0; + } + + static struct device_operations gma_func0_ops = { +-- +2.39.2 + diff --git a/config/vendor/sources b/config/vendor/sources index 2d54bd44..2653c877 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -35,7 +35,7 @@ # NOTE: google's manifest for archives containing mrc.bin, used here: # https://web.archive.org/web/20210211071412/https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf -{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff}{ +{t440pmrc w541mrc t440plibremrc w541 dell9020mt dell9020sff dell9020sff-nri dell9020mt-nri}{ DL_hash f3d79aec805c8b0094a4081be76b3a22d329c479ad18210449b7acc3236ccfc4a2103eaa7c5b79a4872bfd699eede047efd46dfb06dc8f47e3216fc254612998 DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe From c557e9e0e10c7661f40c5fd47c8e3b514e1f6562 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 21 Apr 2024 01:52:29 +0100 Subject: [PATCH 0018/1319] haswell nri: set 8MB CBFS on thinkpads (fix S3) hell added a patch fixing S3 on haswell NRI, but it seems you still need to set 8MB CBFS size as with the MRC tested on a t440p. S3 now works on haswell NRI. Signed-off-by: Leah Rowe --- config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb | 2 +- config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode | 2 +- config/coreboot/w541_12mb/config/libgfxinit_corebootfb | 2 +- config/coreboot/w541_12mb/config/libgfxinit_txtmode | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb index 58daa6a1..dd614202 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_corebootfb @@ -114,7 +114,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode index 89a4925b..a0dce901 100644 --- a/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440plibremrc_12mb/config/libgfxinit_txtmode @@ -114,7 +114,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y diff --git a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb index 15e93305..c9a45666 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb @@ -114,7 +114,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot/w541_12mb/config/libgfxinit_txtmode b/config/coreboot/w541_12mb/config/libgfxinit_txtmode index 2c0dddb9..e5b2e1f8 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541_12mb/config/libgfxinit_txtmode @@ -114,7 +114,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 +CONFIG_CBFS_SIZE=0x800000 CONFIG_MAX_CPUS=8 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_POST_DEVICE=y From 523f1df9bf0fbb13ca8124bf0cf692700bbb94da Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 21 Apr 2024 03:16:43 +0100 Subject: [PATCH 0019/1319] w541 libremrc: disable tseg stage cache a hangover from earlier days, but i still disable it. i forgot to do so on this config, when updating the nri code. do it now. Signed-off-by: Leah Rowe --- config/coreboot/w541_12mb/config/libgfxinit_corebootfb | 4 ++-- config/coreboot/w541_12mb/config/libgfxinit_txtmode | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb index c9a45666..ae155585 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541_12mb/config/libgfxinit_corebootfb @@ -33,8 +33,8 @@ CONFIG_USE_BLOBS=y CONFIG_HAVE_ASAN_IN_ROMSTAGE=y CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set diff --git a/config/coreboot/w541_12mb/config/libgfxinit_txtmode b/config/coreboot/w541_12mb/config/libgfxinit_txtmode index e5b2e1f8..9a891434 100644 --- a/config/coreboot/w541_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541_12mb/config/libgfxinit_txtmode @@ -33,8 +33,8 @@ CONFIG_USE_BLOBS=y CONFIG_HAVE_ASAN_IN_ROMSTAGE=y CONFIG_HAVE_ASAN_IN_RAMSTAGE=y # CONFIG_ASAN is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_TSEG_STAGE_CACHE=y +CONFIG_NO_STAGE_CACHE=y +# CONFIG_TSEG_STAGE_CACHE is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_FW_CONFIG is not set From f5035e327a3a2b7ac1550dd0882b66c8834fe1d8 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 21 Apr 2024 21:55:57 +0100 Subject: [PATCH 0020/1319] 9020 sff/mt: fix bad gpio read on hwm patch sff happened to work, but mt would not boot with the patch, because it called die() on unknown chassis type, and the gpio happened to have a bad value in the old patch, because it wasn't reading the right gpio. i tested the fix on the old patch, but then decided to use mate's new patch because instead of calling die(), it simply boots with fan control disabled (max fan speed in that case), if this happens again. mt and sff have both been tested with this new version of the patch. both of them boot, and they both have proper fan control. Signed-off-by: Leah Rowe --- ..._9020-Implement-late-HWM-initializat.patch | 64 ++++++++++-------- ..._9020-Implement-late-HWM-initializat.patch | 66 +++++++++++-------- 2 files changed, 73 insertions(+), 57 deletions(-) diff --git a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch index f6bd1940..37353e20 100644 --- a/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch +++ b/config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -1,13 +1,13 @@ -From f6340f3fe21e948ba94d0429467882c2fb90b77e Mon Sep 17 00:00:00 2001 +From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001 From: Mate Kukri -Date: Sat, 6 Apr 2024 23:25:15 +0100 +Date: Thu, 18 Apr 2024 20:28:45 +0100 Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization There are 4 different chassis types specified by vendor firmware, each with a slightly different HWM configuration. The chassis type to use is determined at runtime by reading a set of -4 PCH GPIOs: 70, 38, 17, and 0. +4 PCH GPIOs: 70, 38, 17, and 1. Additionally vendor firmware also provides an option to run the fans at full speed. This is substituted with a coreboot nvram option in this @@ -26,10 +26,10 @@ Signed-off-by: Mate Kukri src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- src/mainboard/dell/optiplex_9020/cmos.default | 1 + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- - src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ - src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 + - 7 files changed, 455 insertions(+), 22 deletions(-) + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + + 7 files changed, 463 insertions(+), 22 deletions(-) create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h @@ -119,7 +119,7 @@ index 72ff9c4bee..4a1496a878 100644 # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c -index c834fea5d3..10b8aaca0e 100644 +index c834fea5d3..0b7829c736 100644 --- a/src/mainboard/dell/optiplex_9020/mainboard.c +++ b/src/mainboard/dell/optiplex_9020/mainboard.c @@ -1,7 +1,12 @@ @@ -130,18 +130,19 @@ index c834fea5d3..10b8aaca0e 100644 #include #include +#include -+#include ++#include +#include "sch5555_ec.h" static void mainboard_enable(struct device *dev) { -@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev) +@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + -+#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_ADD_TEMP_TARGET 1 +#define HWM_TAB_PKG_POWER_ANY 0xffff ++#define CHASSIS_TYPE_UNKNOWN 0xff + +struct hwm_tab_entry { + uint16_t addr; @@ -390,7 +391,7 @@ index c834fea5d3..10b8aaca0e 100644 + + // Read chassis type from GPIO + gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | -+ get_gpio(17) << 1 | get_gpio(0); ++ get_gpio(17) << 1 | get_gpio(1); + + printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); + @@ -408,7 +409,7 @@ index c834fea5d3..10b8aaca0e 100644 + case 0x0f: + return 6; + default: -+ die("Unknown GPIO chassis type\n"); ++ return CHASSIS_TYPE_UNKNOWN; + } + +} @@ -469,9 +470,15 @@ index c834fea5d3..10b8aaca0e 100644 + ec_write(1, 0x2fc, 0xa0); + ec_write(1, 0x2fd, 0x32); + -+ // Apply HWM table based on chassis type + chassis_type = get_chassis_type(); -+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ ++ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ } else { ++ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); ++ } ++ ++ // Apply HWM table based on chassis type + switch (chassis_type) { + case 3: + apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); @@ -485,19 +492,17 @@ index c834fea5d3..10b8aaca0e 100644 + case 6: + apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); + break; -+ default: -+ die("Unknown chassis type\n"); + } + -+ if (CONFIG_MAX_CPUS > 2) { -+ ec_write(1, 0x9e, 0x30); -+ ec_write(1, 0xeb, ec_read(1, 0xea)); -+ } ++ // NOTE: vendor firmware applies these when "max core address" > 2 ++ // i think this is always the case ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); + + ec_write(1, 0x2fc, saved_2fc); + -+ // Apply full speed fan config if requested -+ if (get_uint_option("fan_full_speed", 0)) { ++ // Apply full speed fan config if requested or if the chassis type is unknown ++ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { + printk(BIOS_DEBUG, "Setting full fan speed\n"); + ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); + ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); @@ -518,7 +523,7 @@ index c834fea5d3..10b8aaca0e 100644 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c new file mode 100644 -index 0000000000..92244da9ab +index 0000000000..a1067ac063 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c @@ -0,0 +1,54 @@ @@ -546,7 +551,7 @@ index 0000000000..92244da9ab + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack -+ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; + @@ -572,23 +577,26 @@ index 0000000000..92244da9ab + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack -+ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; +} diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h new file mode 100644 -index 0000000000..6e703ff865 +index 0000000000..7e399e8e74 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -@@ -0,0 +1,7 @@ +@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + -+#pragma once ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ + +uint8_t ec_read(uint8_t addr1, uint16_t addr2); + +void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif -- 2.39.2 diff --git a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch index 527c18d3..e2db6a17 100644 --- a/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch +++ b/config/coreboot/haswell/patches/0023-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch @@ -1,13 +1,13 @@ -From 08bae51a77c2c92fefef79e9c9b6ff963b3812cc Mon Sep 17 00:00:00 2001 +From 05cc767d1398f91533e87db5ceaa0aabb7918425 Mon Sep 17 00:00:00 2001 From: Mate Kukri -Date: Sat, 6 Apr 2024 23:25:15 +0100 -Subject: [PATCH 3/4] mb/dell/optiplex_9020: Implement late HWM initialization +Date: Thu, 18 Apr 2024 20:28:45 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization There are 4 different chassis types specified by vendor firmware, each with a slightly different HWM configuration. The chassis type to use is determined at runtime by reading a set of -4 PCH GPIOs: 70, 38, 17, and 0. +4 PCH GPIOs: 70, 38, 17, and 1. Additionally vendor firmware also provides an option to run the fans at full speed. This is substituted with a coreboot nvram option in this @@ -26,10 +26,10 @@ Signed-off-by: Mate Kukri src/mainboard/dell/optiplex_9020/bootblock.c | 25 +- src/mainboard/dell/optiplex_9020/cmos.default | 1 + src/mainboard/dell/optiplex_9020/cmos.layout | 5 +- - src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++ + src/mainboard/dell/optiplex_9020/mainboard.c | 387 ++++++++++++++++++ src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++ - src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 + - 7 files changed, 455 insertions(+), 22 deletions(-) + src/mainboard/dell/optiplex_9020/sch5555_ec.h | 10 + + 7 files changed, 463 insertions(+), 22 deletions(-) create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h @@ -119,7 +119,7 @@ index 72ff9c4bee..4a1496a878 100644 # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c -index c834fea5d3..10b8aaca0e 100644 +index c834fea5d3..0b7829c736 100644 --- a/src/mainboard/dell/optiplex_9020/mainboard.c +++ b/src/mainboard/dell/optiplex_9020/mainboard.c @@ -1,7 +1,12 @@ @@ -130,18 +130,19 @@ index c834fea5d3..10b8aaca0e 100644 #include #include +#include -+#include ++#include +#include "sch5555_ec.h" static void mainboard_enable(struct device *dev) { -@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev) +@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + -+#define HWM_TAB_ADD_TEMP_TARGET 1 ++#define HWM_TAB_ADD_TEMP_TARGET 1 +#define HWM_TAB_PKG_POWER_ANY 0xffff ++#define CHASSIS_TYPE_UNKNOWN 0xff + +struct hwm_tab_entry { + uint16_t addr; @@ -390,7 +391,7 @@ index c834fea5d3..10b8aaca0e 100644 + + // Read chassis type from GPIO + gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | -+ get_gpio(17) << 1 | get_gpio(0); ++ get_gpio(17) << 1 | get_gpio(1); + + printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); + @@ -408,7 +409,7 @@ index c834fea5d3..10b8aaca0e 100644 + case 0x0f: + return 6; + default: -+ die("Unknown GPIO chassis type\n"); ++ return CHASSIS_TYPE_UNKNOWN; + } + +} @@ -469,9 +470,15 @@ index c834fea5d3..10b8aaca0e 100644 + ec_write(1, 0x2fc, 0xa0); + ec_write(1, 0x2fd, 0x32); + -+ // Apply HWM table based on chassis type + chassis_type = get_chassis_type(); -+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ ++ if (chassis_type != CHASSIS_TYPE_UNKNOWN) { ++ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); ++ } else { ++ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); ++ } ++ ++ // Apply HWM table based on chassis type + switch (chassis_type) { + case 3: + apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); @@ -485,19 +492,17 @@ index c834fea5d3..10b8aaca0e 100644 + case 6: + apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); + break; -+ default: -+ die("Unknown chassis type\n"); + } + -+ if (CONFIG_MAX_CPUS > 2) { -+ ec_write(1, 0x9e, 0x30); -+ ec_write(1, 0xeb, ec_read(1, 0xea)); -+ } ++ // NOTE: vendor firmware applies these when "max core address" > 2 ++ // i think this is always the case ++ ec_write(1, 0x9e, 0x30); ++ ec_write(1, 0xeb, ec_read(1, 0xea)); + + ec_write(1, 0x2fc, saved_2fc); + -+ // Apply full speed fan config if requested -+ if (get_uint_option("fan_full_speed", 0)) { ++ // Apply full speed fan config if requested or if the chassis type is unknown ++ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { + printk(BIOS_DEBUG, "Setting full fan speed\n"); + ec_write(1, 0x80, 0x60 | ec_read(1, 0x80)); + ec_write(1, 0x81, 0x60 | ec_read(1, 0x81)); @@ -518,7 +523,7 @@ index c834fea5d3..10b8aaca0e 100644 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c new file mode 100644 -index 0000000000..92244da9ab +index 0000000000..a1067ac063 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c @@ -0,0 +1,54 @@ @@ -546,7 +551,7 @@ index 0000000000..92244da9ab + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack -+ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; + @@ -572,23 +577,26 @@ index 0000000000..92244da9ab + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack -+ for (size_t timeout = 0; timeout < 0xfff; ++timeout) ++ for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; +} diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h new file mode 100644 -index 0000000000..6e703ff865 +index 0000000000..7e399e8e74 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h -@@ -0,0 +1,7 @@ +@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + -+#pragma once ++#ifndef __SCH5555_EC_H__ ++#define __SCH5555_EC_H__ + +uint8_t ec_read(uint8_t addr1, uint16_t addr2); + +void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val); ++ ++#endif -- 2.39.2 From ed0678ae2e9b58b3eb9a7606816e21ad8798192e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 24 Apr 2024 05:27:27 +0100 Subject: [PATCH 0021/1319] haswell: only provide NRI-based ROMs in releases release="n" is set in target.cfg on haswell build targets that use mrc.bin script/update/release exports LBMK_RELEASE="y" script/build/roms skips building a given target if release="n" in target.cfg *and* LBMK_RELEASE="y" you could also do the export yourself before running ./build roms, for example: export LBMK_RELEASE="y" ./build roms all This would skip these ROM images. The native haswell raminit is now stable enough in my testing, that I wish to delete the MRC-based targets. This is in line with Libreboot's Binary Blob Reduction Policy, which states: if a blob can be avoided, it should be avoided. The problem is that users often run the inject script in *lbmk* from Git, instead of from the src release archive. I forsee some users running this on modern lbmk with older release images. If the mrc-based target isn't there, the user may use an NRI-based target name, and think it works; they will insert without MRC. I foresaw this ages ago, which is why Caleb and I ensured that the script checks hashes, and hashes are included in releases. Therefore: for the time being, keep the MRC-based configs in lbmk but do not include images for them in releases. This can be done indefinitely, but I'll probably remove those configs entirely at some point. On the following boards, Libreboot now will *only* provide NRI-based ROM images for the following machines: * Dell OptiPlex 9020 SFF * Dell OptiPlex 9020 MT * Lenovo ThinkPad T440p * Lenovo ThinkPad W541/W540 I now recommend exclusive use of NRI-based images, on Haswell hardware. It's stable enough in my testing, and now supports S3. Signed-off-by: Leah Rowe --- build | 2 ++ config/coreboot/dell9020mt_12mb/target.cfg | 1 + config/coreboot/dell9020mtbmrc_12mb/target.cfg | 1 + config/coreboot/dell9020sff_12mb/target.cfg | 1 + config/coreboot/dell9020sffbmrc_12mb/target.cfg | 1 + config/coreboot/t440pbmrc_12mb/target.cfg | 1 + config/coreboot/t440pmrc_12mb/target.cfg | 1 + config/coreboot/w541bmrc_12mb/target.cfg | 1 + config/coreboot/w541mrc_12mb/target.cfg | 1 + include/err.sh | 7 +++++++ script/build/roms | 9 ++++++++- script/update/release | 2 ++ 12 files changed, 27 insertions(+), 1 deletion(-) diff --git a/build b/build index 38d1694c..14353245 100755 --- a/build +++ b/build @@ -13,6 +13,8 @@ export LC_ALL=C . "include/err.sh" . "include/option.sh" +export LBMK_RELEASE="$lbmk_release" + eval "$(setvars "" option aur_notice tmpdir)" err="fail" diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index e6d3bec6..0da057a9 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg index e6d3bec6..0da057a9 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index e6d3bec6..0da057a9 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg index e6d3bec6..0da057a9 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/t440pbmrc_12mb/target.cfg b/config/coreboot/t440pbmrc_12mb/target.cfg index 8688df3f..06f3025c 100644 --- a/config/coreboot/t440pbmrc_12mb/target.cfg +++ b/config/coreboot/t440pbmrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/t440pmrc_12mb/target.cfg b/config/coreboot/t440pmrc_12mb/target.cfg index 8688df3f..06f3025c 100644 --- a/config/coreboot/t440pmrc_12mb/target.cfg +++ b/config/coreboot/t440pmrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/w541bmrc_12mb/target.cfg b/config/coreboot/w541bmrc_12mb/target.cfg index 8688df3f..06f3025c 100644 --- a/config/coreboot/w541bmrc_12mb/target.cfg +++ b/config/coreboot/w541bmrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/config/coreboot/w541mrc_12mb/target.cfg b/config/coreboot/w541mrc_12mb/target.cfg index 8688df3f..06f3025c 100644 --- a/config/coreboot/w541mrc_12mb/target.cfg +++ b/config/coreboot/w541mrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" diff --git a/include/err.sh b/include/err.sh index 5b66c999..3cadf042 100755 --- a/include/err.sh +++ b/include/err.sh @@ -4,6 +4,13 @@ version=""; versiondate=""; projectname=""; _nogit="" err="err_" +# if "y": a coreboot target won't be built if target.cfg says release="n" +# (this is used to exclude certain build targets from releases) +lbmk_release= +set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : +[ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE" +[ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" + x_() { [ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0 } diff --git a/script/build/roms b/script/build/roms index a90e1daa..2510b1fd 100755 --- a/script/build/roms +++ b/script/build/roms @@ -20,7 +20,7 @@ cfgsdir="config/coreboot" # target.cfg files have to specifically enable [a] payload(s) pv="payload_grub payload_grub_withseabios payload_seabios payload_memtest t" pv="${pv} payload_seabios_withgrub payload_seabios_grubonly payload_uboot memtest_bin" -v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps" +v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps release" v="${v} grub_timeout ubdir board grub_scan_disk uboot_config" eval "$(setvars "n" ${pv})" eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets)" @@ -56,6 +56,13 @@ main() grub_background="background1280x800.png" board="${x}" configure_target + + # exclude certain targets from the release + if [ "$release" = "n" ] && [ "$lbmk_release" = "y" ]; then + printf "Skipping target: %s\n" "$x" + continue + fi + build_payloads build_target_mainboard [ -d "bin/${board}" ] || continue diff --git a/script/update/release b/script/update/release index 25ada9da..e8eff300 100755 --- a/script/update/release +++ b/script/update/release @@ -9,6 +9,8 @@ set -u -e eval "$(setvars "" vdir relname src_dirname srcdir _xm target romdir mode)" +export LBMK_RELEASE="y" + main() { vdir="release" From 02e4c0b28e348face651b273fd39b32618ebf17f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 25 Apr 2024 12:45:28 +0100 Subject: [PATCH 0022/1319] hp820g2: allow building, but don't do release ROMs at present, the inject scripts compress refcode in a way that is not reproducible, so there's no way to verify that the firmware is correct, via checksum verification, when injecting vendor code on release images the lack of reproducibility in recompression will have to be addressed, but the issue is that lbmk does not provide its own sources for compression utilities, instead opting to use the system's own compression utility so the solution might be for lbmk not to use the host's utility, and compile its own, or insert the refcode uncompressed. for now, simply disable the hp 820 g2 target in libreboot releases this uses the same logic recently implemented for excluding mrc-based haswell images in libreboot releases Signed-off-by: Leah Rowe --- config/coreboot/hp820g2_12mb/target.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/config/coreboot/hp820g2_12mb/target.cfg b/config/coreboot/hp820g2_12mb/target.cfg index 8688df3f..06f3025c 100644 --- a/config/coreboot/hp820g2_12mb/target.cfg +++ b/config/coreboot/hp820g2_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +release="n" From f5f2c58a0e06d629b28e2dfb14c5dcf169626568 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 25 Apr 2024 19:03:43 +0100 Subject: [PATCH 0023/1319] build/roms: add missing deletion of tmp file the temporary rom per build was not being deleted after finishing the current target. this adds up in /tmp during large builds, when building for many targets. fix this! Signed-off-by: Leah Rowe --- script/build/roms | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/script/build/roms b/script/build/roms index 2510b1fd..5fdc05c9 100755 --- a/script/build/roms +++ b/script/build/roms @@ -201,7 +201,8 @@ build_target_mainboard() [ "$displaymode" != "txtmode" ] && continue cbcfg="${targetdir}/config/${initmode}_${displaymode}" [ "${initmode}" = "normal" ] && cbcfg="${cbcfg%_*}" - build_roms "${cbcfg}" + build_roms "${cbcfg}" + x_ rm -f "$cbrom" done done } From 08859bb4a56b282cb566c262bd591d7271308ef3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 25 Apr 2024 19:08:53 +0100 Subject: [PATCH 0024/1319] lbmk: export TMPDIR from err.sh, not build lbmk sets TMPDIR to /tmp, and then creates a tmpdir, then exports *that* as the value of TMPDIR. this unified TMPDIR location then contains all subsequent files and directories, when any script or program makes use of /tmp, via mktemp. at least, that's the theory! in practise, because it was only being properly exported from the main build scripts, subscripts that are then called were not exporting it, at least that is my assumption because in some cases, i found that the coreboot build system was leaving errant files behind outside of our own TMPDIR, and that build system did not seem to be setting TMPDIR itself; more debugging is needed. anyway: use the exact same logic, but do it from err.sh. since err.sh is included from every lbmk script, that means it will always be exported when running every single part of lbmk. this should reduce the chance that mktemp creates files and directories outside of our custom TMPDIR location. this is because in lbmk, we mitigate unhandled tmpdirs/files by unifying it in the manner described, then deleting the entire TMPDIR on exit from the main lbmk parent process (the main script that the user called from, which is always the "build" file). in lbmk, effort is made to clean up temporary files properly, without relying on this catch-all, but we can't rely on that. the catch-all should also be as robust as possible. Signed-off-by: Leah Rowe --- build | 16 +--------------- include/err.sh | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/build b/build index 14353245..dbcd6939 100755 --- a/build +++ b/build @@ -15,23 +15,9 @@ export LC_ALL=C export LBMK_RELEASE="$lbmk_release" -eval "$(setvars "" option aur_notice tmpdir)" +eval "$(setvars "" option aur_notice)" err="fail" -tmpdir_was_set="y" -set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" -if [ "${tmpdir_was_set}" = "y" ]; then - [ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n" -fi -if [ "${tmpdir_was_set}" = "n" ]; then - export TMPDIR="/tmp" - tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)" - export TMPDIR="${tmpdir}" -else - export TMPDIR="${TMPDIR}" - tmpdir="${TMPDIR}" -fi - linkpath="${0}" linkname="${linkpath##*/}" buildpath="./script/${linkname}" diff --git a/include/err.sh b/include/err.sh index 3cadf042..7a6d3fe5 100755 --- a/include/err.sh +++ b/include/err.sh @@ -2,7 +2,7 @@ # SPDX-FileCopyrightText: 2022, 2023 Leah Rowe version=""; versiondate=""; projectname=""; _nogit="" -err="err_" +err="err_"; tmpdir="" # if "y": a coreboot target won't be built if target.cfg says release="n" # (this is used to exclude certain build targets from releases) @@ -11,6 +11,20 @@ set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : [ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE" [ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" +tmpdir_was_set="y" +set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" +if [ "${tmpdir_was_set}" = "y" ]; then + [ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n" +fi +if [ "${tmpdir_was_set}" = "n" ]; then + export TMPDIR="/tmp" + tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)" + export TMPDIR="${tmpdir}" +else + export TMPDIR="${TMPDIR}" + tmpdir="${TMPDIR}" +fi + x_() { [ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0 } From 2d7debd33c2f42bfe6296d4b72a0710e3039bbd4 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 25 Apr 2024 20:18:01 +0100 Subject: [PATCH 0025/1319] 9020 sff/mt: add tpm enable patch from mate kukri Signed-off-by: Leah Rowe --- ...x_9020-Add-support-for-TPM1.2-device.patch | 49 +++++++++++++++++++ .../config/libgfxinit_corebootfb | 6 +++ .../config/libgfxinit_txtmode | 6 +++ .../config/libgfxinit_corebootfb | 6 +++ .../dell9020mt_12mb/config/libgfxinit_txtmode | 6 +++ .../config/libgfxinit_corebootfb | 6 +++ .../config/libgfxinit_txtmode | 6 +++ .../config/libgfxinit_corebootfb | 6 +++ .../config/libgfxinit_txtmode | 6 +++ .../config/libgfxinit_corebootfb | 6 +++ .../config/libgfxinit_txtmode | 6 +++ .../config/libgfxinit_corebootfb | 6 +++ .../config/libgfxinit_txtmode | 6 +++ ...x_9020-Add-support-for-TPM1.2-device.patch | 49 +++++++++++++++++++ 14 files changed, 170 insertions(+) create mode 100644 config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch create mode 100644 config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch diff --git a/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch new file mode 100644 index 00000000..556e8e07 --- /dev/null +++ b/config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch @@ -0,0 +1,49 @@ +From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Wed, 10 Apr 2024 20:31:35 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device + +These machines come with a TPM1.2 device by default. It is somewhat +obsolete these days, but there is no harm in enabling it. + +Change-Id: Iec05321862aed58695c256b00494e5953219786d +Signed-off-by: Mate Kukri +Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 +Reviewed-by: Angel Pons +Tested-by: build bot (Jenkins) +--- + src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ + src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ + 2 files changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig +index 774a72f161..296938aa8d 100644 +--- a/src/mainboard/dell/optiplex_9020/Kconfig ++++ b/src/mainboard/dell/optiplex_9020/Kconfig +@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index 7bfa6736a6..e5cbd64127 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -70,6 +70,9 @@ chip northbridge/intel/haswell + device pnp 2e.b off end # Floppy Controller + device pnp 2e.11 off end # Parallel Port + end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus +-- +2.39.2 + diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb index d587473c..afbe83aa 100644 --- a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y @@ -447,6 +448,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y CONFIG_DRIVERS_MTK_WIFI=y @@ -471,6 +474,9 @@ CONFIG_DRIVERS_MTK_WIFI=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode index fb415885..b649afff 100644 --- a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set # CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y @@ -443,6 +444,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -468,6 +471,9 @@ CONFIG_DRIVERS_MTK_WIFI=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb index ea4cfb53..d3b7d221 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode index c52eae4c..cf9eec5f 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb index 953901cd..85952b07 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode index 682c9e99..adb1ba55 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb index 7bfe30a2..22b153fa 100644 --- a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb @@ -134,6 +134,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set @@ -447,6 +448,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y CONFIG_DRIVERS_MTK_WIFI=y @@ -471,6 +474,9 @@ CONFIG_DRIVERS_MTK_WIFI=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode index c976b093..935c29bf 100644 --- a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode @@ -132,6 +132,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_E6400 is not set CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y # CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set @@ -443,6 +444,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -468,6 +471,9 @@ CONFIG_DRIVERS_MTK_WIFI=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb index 26202d3a..9909153c 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode index 0cceca51..5d7b424b 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb index c4995430..df48538d 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb @@ -135,6 +135,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -458,6 +459,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers @@ -481,6 +484,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode index dc3d337d..297aa07b 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode @@ -133,6 +133,7 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set +CONFIG_TPM_PIRQ=0x0 # CONFIG_BOARD_DELL_LATITUDE_E5420 is not set # CONFIG_BOARD_DELL_LATITUDE_E5520 is not set # CONFIG_BOARD_DELL_LATITUDE_E5530 is not set @@ -454,6 +455,8 @@ CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_MEMORY_MAPPED_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_DRIVERS_WIFI_GENERIC=y @@ -478,6 +481,9 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y +# CONFIG_TPM1 is not set +CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 CONFIG_PCR_SRTM=2 diff --git a/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch b/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch new file mode 100644 index 00000000..52147426 --- /dev/null +++ b/config/coreboot/haswell/patches/0025-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch @@ -0,0 +1,49 @@ +From 355536155898e649fa50277136ccd2df53a52bb1 Mon Sep 17 00:00:00 2001 +From: Mate Kukri +Date: Wed, 10 Apr 2024 20:31:35 +0100 +Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device + +These machines come with a TPM1.2 device by default. It is somewhat +obsolete these days, but there is no harm in enabling it. + +Change-Id: Iec05321862aed58695c256b00494e5953219786d +Signed-off-by: Mate Kukri +Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827 +Reviewed-by: Angel Pons +Tested-by: build bot (Jenkins) +--- + src/mainboard/dell/optiplex_9020/Kconfig | 2 ++ + src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++ + 2 files changed, 5 insertions(+) + +diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig +index 2de4a9abd6..38c3281e70 100644 +--- a/src/mainboard/dell/optiplex_9020/Kconfig ++++ b/src/mainboard/dell/optiplex_9020/Kconfig +@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT ++ select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION ++ select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT +diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb +index dce5869478..841285bb9c 100644 +--- a/src/mainboard/dell/optiplex_9020/devicetree.cb ++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb +@@ -70,6 +70,9 @@ chip northbridge/intel/haswell + device pnp 2e.b off end # Floppy Controller + device pnp 2e.11 off end # Parallel Port + end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus +-- +2.39.2 + From ddfe71a366469f090d859d1e97b57ee184f6ba25 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 05:10:12 +0100 Subject: [PATCH 0026/1319] 9020 sff/mt: actually enable the TPM (by default) i added mkukri's patch but didn't enable it. this was intentional. this patch enables tpm by default, on all 9020 sff/mt targets. most users probably won't need it, but enabling it won't hurt. Signed-off-by: Leah Rowe --- .../dell9020mt-nri_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020mt-nri_12mb/config/libgfxinit_txtmode | 11 +++++++++-- .../dell9020mt_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020mt_12mb/config/libgfxinit_txtmode | 11 +++++++++-- .../dell9020mtbmrc_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020mtbmrc_12mb/config/libgfxinit_txtmode | 11 +++++++++-- .../dell9020sff-nri_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020sff-nri_12mb/config/libgfxinit_txtmode | 11 +++++++++-- .../dell9020sff_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020sff_12mb/config/libgfxinit_txtmode | 11 +++++++++-- .../dell9020sffbmrc_12mb/config/libgfxinit_corebootfb | 11 +++++++++-- .../dell9020sffbmrc_12mb/config/libgfxinit_txtmode | 11 +++++++++-- 12 files changed, 108 insertions(+), 24 deletions(-) diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb index afbe83aa..509e784e 100644 --- a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_corebootfb @@ -178,6 +178,7 @@ CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -418,6 +419,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -473,9 +476,12 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -491,6 +497,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode index b649afff..428bed87 100644 --- a/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt-nri_12mb/config/libgfxinit_txtmode @@ -176,6 +176,7 @@ CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -414,6 +415,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -470,9 +473,12 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -488,6 +494,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb index d3b7d221..2fbd5982 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_corebootfb @@ -185,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -429,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -483,9 +486,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -501,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode index cf9eec5f..c92a7c7c 100644 --- a/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mt_12mb/config/libgfxinit_txtmode @@ -183,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -425,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -480,9 +483,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -498,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb index 85952b07..2878f894 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_corebootfb @@ -185,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -429,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -483,9 +486,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -501,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode index adb1ba55..35bbcf5b 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020mtbmrc_12mb/config/libgfxinit_txtmode @@ -183,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -425,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -480,9 +483,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -498,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb index 22b153fa..ac1d9f16 100644 --- a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_corebootfb @@ -178,6 +178,7 @@ CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -418,6 +419,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -473,9 +476,12 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -491,6 +497,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode index 935c29bf..179af9cc 100644 --- a/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff-nri_12mb/config/libgfxinit_txtmode @@ -176,6 +176,7 @@ CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_HEAP_SIZE=0x100000 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -414,6 +415,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -470,9 +473,12 @@ CONFIG_DRIVERS_MTK_WIFI=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -488,6 +494,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb index 9909153c..65d9ddf2 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_corebootfb @@ -185,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -429,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -483,9 +486,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -501,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode index 5d7b424b..127c034d 100644 --- a/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sff_12mb/config/libgfxinit_txtmode @@ -183,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -425,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -480,9 +483,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -498,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb index df48538d..f544407a 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_corebootfb @@ -185,6 +185,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -429,6 +430,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -483,9 +486,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -501,6 +507,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y diff --git a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode index 297aa07b..0586764c 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/dell9020sffbmrc_12mb/config/libgfxinit_txtmode @@ -183,6 +183,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y CONFIG_DRIVERS_UART_8250IO=y CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 CONFIG_EC_GPE_SCI=0x50 +# CONFIG_TPM_MEASURED_BOOT is not set CONFIG_BOARD_ROMSIZE_KB_12288=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set @@ -425,6 +426,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_ISSI=y CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y +CONFIG_TPM_INIT_RAMSTAGE=y +# CONFIG_TPM_PPI is not set CONFIG_DRIVERS_UART=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y @@ -480,9 +483,12 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # # Trusted Platform Module # -CONFIG_NO_TPM=y -# CONFIG_TPM1 is not set +# CONFIG_NO_TPM is not set +CONFIG_TPM1=y +CONFIG_TPM=y CONFIG_MAINBOARD_HAS_TPM1=y +# CONFIG_TPM_DEACTIVATE is not set +# CONFIG_DEBUG_TPM is not set # CONFIG_TPM_RDRESP_NEED_DELAY is not set CONFIG_PCR_BOOT_MODE=1 CONFIG_PCR_HWID=1 @@ -498,6 +504,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y # end of Memory initialization +# CONFIG_INTEL_TXT is not set # CONFIG_STM is not set # CONFIG_INTEL_CBNT_SUPPORT is not set CONFIG_BOOTMEDIA_LOCK_NONE=y From a5082de43cd7fd86491722a7637cf4eec838d6e3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 05:12:04 +0100 Subject: [PATCH 0027/1319] GRUB: bump to today's latest revision GRUB has not pushed many patches to master since the recent 2.12 release, but there are a number of interesting fixes. libreboot is doing a release soon. bump to latest grub revision. Some of the new patches in GRUB are interesting: XFS fixes: "fs/xfs: Handle non-continuous data blocks in directory extents" 68dd65cfdaad08b1f8ec01b84949b0bf88bc0d8c Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2254370 Apparently, XFS could not boot in some reports, though this was likely with BIOS or UEFI GRUB; no such reports were made to libreboot "gfxmenu/view: Resolve false grub_errno disrupting boot process" 39c927df66c7ca62d97905d1385054ac9ce67209 "util/grub-fstest: Add a new command zfs-bootfs" 28c4405208cfb6e2cea737f6cbaf17e631bac6cd The gnulib revision does not need to be updated at this time. Signed-off-by: Leah Rowe --- config/git/grub | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/git/grub b/config/git/grub index 3abec3e4..b52fa0fb 100644 --- a/config/git/grub +++ b/config/git/grub @@ -1,5 +1,5 @@ {grub}{ - rev: b835601c7639ed1890f2d3db91900a8506011a8e + rev: 8719cc2040368d43ab2de0b6e1b850b2c9cfc5b7 loc: grub url: git://git.savannah.gnu.org/grub.git bkup_url: https://codeberg.org/libreboot/grub From 64177dbb8e7ff9ca9c7ad847c137398f6a67cfcf Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 08:20:19 +0100 Subject: [PATCH 0028/1319] exports variables from err.sh, not build LC_COLLATE and LBMK_RELEASE are important variables. we want to make sure that these are seen by everything. since err.sh is included from all scripts, doing it there will accomplish just that. Signed-off-by: Leah Rowe --- build | 5 ----- include/err.sh | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/build b/build index dbcd6939..277390fd 100755 --- a/build +++ b/build @@ -7,14 +7,9 @@ set -u -e -export LC_COLLATE=C -export LC_ALL=C - . "include/err.sh" . "include/option.sh" -export LBMK_RELEASE="$lbmk_release" - eval "$(setvars "" option aur_notice)" err="fail" diff --git a/include/err.sh b/include/err.sh index 7a6d3fe5..d4f8700b 100755 --- a/include/err.sh +++ b/include/err.sh @@ -1,6 +1,9 @@ # SPDX-License-Identifier: MIT # SPDX-FileCopyrightText: 2022, 2023 Leah Rowe +export LC_COLLATE=C +export LC_ALL=C + version=""; versiondate=""; projectname=""; _nogit="" err="err_"; tmpdir="" @@ -10,6 +13,7 @@ lbmk_release= set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : [ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE" [ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" +export LBMK_RELEASE="$lbmk_release" tmpdir_was_set="y" set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" From a2f423535840382d72bfa1ae1e1cb5c06e4f8604 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 09:37:01 +0100 Subject: [PATCH 0029/1319] i945: switch boards to 20230625 coreboot revision On T60 with Libreboot 20231106 and the GRUB payload, a user reported this error in GRUB when a battery was connected: "alloc magic is broken at 0x7b1aedf0: 0" This error disappears when a battery is not connected, or when using Libreboot 20230625. The issue has persisted through to LIbreboot 20240225 and after, and I believe the issue will be somewhere in coreboot, not in GRUB itself. For now, switch i945 laptops (X60, T60, Macbook2,1) back to the February 2023 coreboot revision used in Libreboot 20230625. A bisect can be done before the next Libreboot release, ETA May 2024, if time permits. Otherwise, this revert should solve the problem for now, at least so far as Libreboot is concerned. The following coreboot patches have been backported: commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94 Author: Bill Xie Date: Sat Oct 7 01:32:51 2023 +0800 drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume Further patches from upstream: commit 432e92688eca0e85cbaebca3232f65936b305a98 Author: Bill Xie Date: Fri Nov 3 12:34:01 2023 +0800 drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum These patches fixed S3 on GM45 machines, though it will be useful on the i945 machines aswell. The reason I'm doing it this way it is because I don't have a battery for my X60 or T60, and my T60 isn't in a very good state either, so I can't reproduce the error myself yet. Signed-off-by: Leah Rowe --- ...Set-default-VRAM-to-64MiB-instead-of.patch | 23 ++++ ...d-c3-and-clockgen-to-apple-macbook21.patch | 68 +++++++++ ...-Video-RAM-changed-to-default-previo.patch | 23 ++++ ...64MiB-VRAM-the-default-in-cmos.defau.patch | 22 +++ ...use-mirrorservice-for-gnu-toolchains.patch | 34 +++++ ...-option.c-Stop-resetting-CMOS-during.patch | 56 ++++++++ ...-option.c-Reset-only-CMOS-range-cove.patch | 51 +++++++ ...or-coreboot-images-built-without-a-p.patch | 38 ++++++ config/coreboot/i945/target.cfg | 2 + .../macbook11/config/libgfxinit_corebootfb | 116 ++++++---------- .../macbook11/config/libgfxinit_txtmode | 116 ++++++---------- config/coreboot/macbook11/target.cfg | 2 +- .../config/libgfxinit_corebootfb | 114 ++++++---------- .../macbook11_16mb/config/libgfxinit_txtmode | 114 ++++++---------- config/coreboot/macbook11_16mb/target.cfg | 2 +- .../macbook21/config/libgfxinit_corebootfb | 116 ++++++---------- .../macbook21/config/libgfxinit_txtmode | 116 ++++++---------- config/coreboot/macbook21/target.cfg | 2 +- .../config/libgfxinit_corebootfb | 114 ++++++---------- .../macbook21_16mb/config/libgfxinit_txtmode | 114 ++++++---------- config/coreboot/macbook21_16mb/target.cfg | 2 +- .../config/libgfxinit_corebootfb | 128 ++++++----------- .../config/libgfxinit_txtmode | 128 ++++++----------- config/coreboot/t60_16mb_intelgpu/target.cfg | 2 +- .../t60_intelgpu/config/libgfxinit_corebootfb | 128 ++++++----------- .../t60_intelgpu/config/libgfxinit_txtmode | 128 ++++++----------- config/coreboot/t60_intelgpu/target.cfg | 2 +- .../coreboot/x60/config/libgfxinit_corebootfb | 129 ++++++------------ config/coreboot/x60/config/libgfxinit_txtmode | 129 ++++++------------ config/coreboot/x60/target.cfg | 2 +- .../x60_16mb/config/libgfxinit_corebootfb | 129 ++++++------------ .../x60_16mb/config/libgfxinit_txtmode | 129 ++++++------------ config/coreboot/x60_16mb/target.cfg | 2 +- 33 files changed, 973 insertions(+), 1308 deletions(-) create mode 100644 config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch create mode 100644 config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch create mode 100644 config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch create mode 100644 config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch create mode 100644 config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch create mode 100644 config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch create mode 100644 config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch create mode 100644 config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch create mode 100644 config/coreboot/i945/target.cfg diff --git a/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch new file mode 100644 index 00000000..a06a5058 --- /dev/null +++ b/config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch @@ -0,0 +1,23 @@ +From 4c5971a6fcf7e948f7df4d0ce2ab0751060cb2ca Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 19 Mar 2021 05:54:58 +0000 +Subject: [PATCH 01/18] apple/macbook21: Set default VRAM to 64MiB instead of + 8MiB + +--- + src/mainboard/apple/macbook21/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default +index cf1bc4566e..dc0df3b6d6 100644 +--- a/src/mainboard/apple/macbook21/cmos.default ++++ b/src/mainboard/apple/macbook21/cmos.default +@@ -5,4 +5,4 @@ boot_devices='' + boot_default=0x40 + cmos_defaults_loaded=Yes + lpt=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch new file mode 100644 index 00000000..57c32ec7 --- /dev/null +++ b/config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch @@ -0,0 +1,68 @@ +From ff523fd40649b72512b0f1253701509d83ca4a8d Mon Sep 17 00:00:00 2001 +From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com> +Date: Wed, 27 Oct 2021 13:36:01 +0200 +Subject: [PATCH 02/18] add c3 and clockgen to apple/macbook21 + +--- + src/mainboard/apple/macbook21/Kconfig | 1 + + src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++ + src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++ + 3 files changed, 20 insertions(+) + +diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig +index 5f5ffde588..27377b737c 100644 +--- a/src/mainboard/apple/macbook21/Kconfig ++++ b/src/mainboard/apple/macbook21/Kconfig +@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select I945_LVDS ++ select DRIVERS_I2C_CK505 + + config MAINBOARD_DIR + default "apple/macbook21" +diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c +index 13d06f0839..88b8669c61 100644 +--- a/src/mainboard/apple/macbook21/cstates.c ++++ b/src/mainboard/apple/macbook21/cstates.c +@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = { + .addrh = 0, + } + }, ++ { ++ .ctype = 3, ++ .latency = 17, ++ .power = 250, ++ .resource = { ++ .space_id = ACPI_ADDRESS_SPACE_FIXED, ++ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, ++ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, ++ .access_size = ACPI_ACCESS_SIZE_UNDEFINED, ++ .addrl = 0x20, ++ .addrh = 0, ++ } ++ }, + }; + + int get_cst_entries(const acpi_cstate_t **entries) +diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb +index dd701da7ed..5587c48d1f 100644 +--- a/src/mainboard/apple/macbook21/devicetree.cb ++++ b/src/mainboard/apple/macbook21/devicetree.cb +@@ -100,7 +100,13 @@ chip northbridge/intel/i945 + end + device pci 1f.3 on # SMBUS + subsystemid 0x8086 0x7270 ++ chip drivers/i2c/ck505 ++ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" ++ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }" ++ device i2c 69 on end ++ end + end ++ + end + end + end +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch new file mode 100644 index 00000000..d8ca5b1f --- /dev/null +++ b/config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch @@ -0,0 +1,23 @@ +From fe79712702002bf2044227d6c3cef7ae022e3539 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 3 Jan 2021 03:34:01 +0000 +Subject: [PATCH 03/18] lenovo/x60: 64MiB Video RAM changed to default + (previously it was 8MiB) + +--- + src/mainboard/lenovo/x60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default +index 5c3576d1f3..88170a1aab 100644 +--- a/src/mainboard/lenovo/x60/cmos.default ++++ b/src/mainboard/lenovo/x60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch new file mode 100644 index 00000000..630e68a6 --- /dev/null +++ b/config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch @@ -0,0 +1,22 @@ +From 79440902866bdafeec651476a5a0e51d42b43b21 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Mon, 22 Feb 2021 22:16:59 +0000 +Subject: [PATCH 04/18] lenovo/t60: make 64MiB VRAM the default in cmos.default + +--- + src/mainboard/lenovo/t60/cmos.default | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default +index af865f16da..7f03157df7 100644 +--- a/src/mainboard/lenovo/t60/cmos.default ++++ b/src/mainboard/lenovo/t60/cmos.default +@@ -15,4 +15,4 @@ trackpoint=Enable + sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable +-gfx_uma_size=8M ++gfx_uma_size=64M +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch new file mode 100644 index 00000000..dcb28780 --- /dev/null +++ b/config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch @@ -0,0 +1,34 @@ +From 5d8fc92948782e9837b26ee8cdfaa88f41fce174 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 26 Apr 2024 09:16:57 +0100 +Subject: [PATCH 1/1] buildgcc: use mirrorservice for gnu toolchains + +Signed-off-by: Leah Rowe +--- + util/crossgcc/buildgcc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 0de27ed6e8..0faea86894 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -66,11 +66,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" + # to the jenkins build as well, or the builder won't download it. + + # GCC toolchain archive locations +-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" +-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" +-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" +-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" ++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp" ++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" ++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" ++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" ++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" + IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch new file mode 100644 index 00000000..e11e33da --- /dev/null +++ b/config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch @@ -0,0 +1,56 @@ +From 412f1d68c610f69384b156f09f0b326af984b7cc Mon Sep 17 00:00:00 2001 +From: Bill XIE +Date: Sat, 7 Oct 2023 01:32:51 +0800 +Subject: [PATCH 1/2] drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 + resume + +After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS +defaults to extend to bank 1"), Thinkpad X200 with +CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via +bisect). + +Further inspection shows that DRAM training result of GM45 is stored +in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume +to restore, but it will be erased by sanitize_cmos(), which now clears +both bank 0 and bank 1, leaving only "untrained" result restored, so s3 +resume will fail. + +However, resetting CMOS seems unnecessary during s3 resume. Now, +cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. + +Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from + s3 again with these changes. + +Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b +Signed-off-by: Bill XIE +Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288 +Reviewed-by: Jonathon Hall +Tested-by: build bot (Jenkins) +--- + src/drivers/pc80/rtc/option.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c +index e8e2345133..e6cfa175ad 100644 +--- a/src/drivers/pc80/rtc/option.c ++++ b/src/drivers/pc80/rtc/option.c +@@ -1,5 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include + #include + #include + #include +@@ -200,7 +201,8 @@ void sanitize_cmos(void) + { + const unsigned char *cmos_default; + const bool cmos_need_reset = +- CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid(); ++ (CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid()) ++ && !acpi_is_wakeup_s3(); + size_t length = 128; + size_t i; + +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch new file mode 100644 index 00000000..1a614db7 --- /dev/null +++ b/config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch @@ -0,0 +1,51 @@ +From 0bc5a67f926e193a429cce4028fb382c49fa08f8 Mon Sep 17 00:00:00 2001 +From: Bill XIE +Date: Fri, 3 Nov 2023 12:34:01 +0800 +Subject: [PATCH 2/2] drivers/pc80/rtc/option.c: Reset only CMOS range covered + by checksum + +Proposed in the comment of commit 29030d0f3dad +("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), +during sanitize_cmos(), only reset CMOS range covered by checksum and +the checksum itself from the file cmos.default in CBFS, in order to +prevent other runtime data in CMOS (e.g. the DRAM training data on +GM45 platforms for s3 resume) being erased. + +Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: + Bring HEAP_SIZE to a common, large value"), which is already + before my commit 29030d0f3dad , Thinkpad X200 with + CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, + indicating that DRAM training data are no longer erased. + +Signed-off-by: Bill XIE +Co-authored-by: Jonathon Hall +Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a +Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 +Tested-by: build bot (Jenkins) +Reviewed-by: Nico Huber +Reviewed-by: Jonathon Hall +--- + src/drivers/pc80/rtc/option.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c +index e6cfa175ad..cb18e14ae9 100644 +--- a/src/drivers/pc80/rtc/option.c ++++ b/src/drivers/pc80/rtc/option.c +@@ -213,8 +213,12 @@ void sanitize_cmos(void) + return; + + u8 control_state = cmos_disable_rtc(); +- for (i = 14; i < MIN(128, length); i++) ++ /* Copy checked range and the checksum from the default */ ++ for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++) + cmos_write_inner(cmos_default[i], i); ++ /* CMOS checksum takes 2 bytes */ ++ cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC); ++ cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1); + cmos_restore_rtc(control_state); + } + } +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch new file mode 100644 index 00000000..547c6392 --- /dev/null +++ b/config/coreboot/i945/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch @@ -0,0 +1,38 @@ +From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 12 May 2023 19:55:15 -0600 +Subject: [PATCH] Remove warning for coreboot images built without a payload + +I added this in upstream to prevent people from accidentally flashing +roms without a payload resulting in a no boot situation, but in +libreboot lbmk handles the payload and thus this warning always comes +up. This has caused confusion and concern so just patch it out. +--- + payloads/Makefile.inc | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc +index e735443a76..4f1692a873 100644 +--- a/payloads/Makefile.inc ++++ b/payloads/Makefile.inc +@@ -49,16 +49,5 @@ distclean-payloads: + print-repo-info-payloads: + -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) + +-ifeq ($(CONFIG_PAYLOAD_NONE),y) +-files_added:: warn_no_payload +-endif +- +-warn_no_payload: +- printf "\n\t** WARNING **\n" +- printf "coreboot has been built without a payload. Writing\n" +- printf "a coreboot image without a payload to your board's\n" +- printf "flash chip will result in a non-booting system. You\n" +- printf "can use cbfstool to add a payload to the image.\n\n" +- + .PHONY: force-payload coreinfo nvramcui +-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload ++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +-- +2.40.1 + diff --git a/config/coreboot/i945/target.cfg b/config/coreboot/i945/target.cfg new file mode 100644 index 00000000..16a4de7d --- /dev/null +++ b/config/coreboot/i945/target.cfg @@ -0,0 +1,2 @@ +tree="i945" +rev="e70bc423f9a2e1d13827f2703efe1f9c72549f20" diff --git a/config/coreboot/macbook11/config/libgfxinit_corebootfb b/config/coreboot/macbook11/config/libgfxinit_corebootfb index 17efec62..1fe47062 100644 --- a/config/coreboot/macbook11/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +337,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +346,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +379,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +399,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +427,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +446,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,39 +457,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -510,7 +480,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -526,7 +496,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -545,10 +514,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -556,19 +521,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11/config/libgfxinit_txtmode b/config/coreboot/macbook11/config/libgfxinit_txtmode index da70f85a..5779bb7f 100644 --- a/config/coreboot/macbook11/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +335,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +344,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +377,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +397,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +425,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +444,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,39 +455,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -508,7 +478,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -524,7 +494,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -543,10 +512,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -554,19 +519,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11/target.cfg b/config/coreboot/macbook11/target.cfg index cc83f2c3..dcf5d1de 100644 --- a/config/coreboot/macbook11/target.cfg +++ b/config/coreboot/macbook11/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb index 8dc8524d..634f287c 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_corebootfb @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +336,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +345,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +378,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +398,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +426,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +445,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,27 +456,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -526,7 +495,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -545,10 +513,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -556,7 +520,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -568,7 +531,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode index 2dee7106..6549df1b 100644 --- a/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook11_16mb/config/libgfxinit_txtmode @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Macbook1,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +334,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +343,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +376,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +396,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +424,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +443,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,27 +454,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -524,7 +493,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -543,10 +511,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -554,7 +518,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -566,7 +529,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook11_16mb/target.cfg b/config/coreboot/macbook11_16mb/target.cfg index cc83f2c3..dcf5d1de 100644 --- a/config/coreboot/macbook11_16mb/target.cfg +++ b/config/coreboot/macbook11_16mb/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/macbook21/config/libgfxinit_corebootfb b/config/coreboot/macbook21/config/libgfxinit_corebootfb index ca8b079b..900e1b32 100644 --- a/config/coreboot/macbook21/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +337,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +346,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +379,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +399,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +427,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +446,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,39 +457,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -510,7 +480,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -526,7 +496,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -545,10 +514,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -556,19 +521,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21/config/libgfxinit_txtmode b/config/coreboot/macbook21/config/libgfxinit_txtmode index db019922..49cde773 100644 --- a/config/coreboot/macbook21/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +111,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +129,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +166,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -203,23 +193,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +219,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +237,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +263,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +301,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +312,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +335,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +344,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +377,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +397,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +425,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +444,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,39 +455,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -508,7 +478,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -524,7 +494,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -543,10 +512,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -554,19 +519,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21/target.cfg b/config/coreboot/macbook21/target.cfg index 8688df3f..bb56ec25 100644 --- a/config/coreboot/macbook21/target.cfg +++ b/config/coreboot/macbook21/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb index 06889a94..70287afc 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_corebootfb @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -350,7 +336,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -358,13 +345,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -382,11 +378,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -402,14 +398,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -431,11 +426,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -455,14 +445,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -470,27 +456,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -526,7 +495,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -545,10 +513,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -556,7 +520,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -568,7 +531,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode index 9e9ec4f9..e9712d24 100644 --- a/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/macbook21_16mb/config/libgfxinit_txtmode @@ -17,12 +17,10 @@ CONFIG_ARCH_SUPPORTS_CLANG=y # CONFIG_IWYU is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y +CONFIG_OPTION_BACKEND_NONE=y +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +61,6 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +74,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIBRETREND is not set @@ -115,12 +110,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" @@ -135,33 +128,30 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="PNP0F13" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="PNP0F13" +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -175,7 +165,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -203,23 +192,22 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set @@ -230,6 +218,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -247,12 +236,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -272,7 +262,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y @@ -310,11 +300,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -324,7 +311,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -348,7 +334,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -356,13 +343,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -380,11 +376,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -400,14 +396,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 +CONFIG_USE_PC_CMOS_ALTCENTURY=y CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -429,11 +424,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -453,14 +443,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -468,27 +454,10 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set @@ -524,7 +493,6 @@ CONFIG_HAVE_MP_TABLE=y # CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -543,10 +511,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -554,7 +518,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -566,7 +529,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/macbook21_16mb/target.cfg b/config/coreboot/macbook21_16mb/target.cfg index 8688df3f..bb56ec25 100644 --- a/config/coreboot/macbook21_16mb/target.cfg +++ b/config/coreboot/macbook21_16mb/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb index 64ef081d..7867f6dd 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +382,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +391,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +403,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -430,11 +425,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -450,18 +445,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -483,11 +473,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -507,14 +492,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -522,39 +503,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -562,7 +526,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -579,7 +543,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -598,10 +561,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -609,19 +568,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode index a04bafeb..aee059ba 100644 --- a/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_16mb_intelgpu/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -395,7 +380,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -403,6 +389,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -410,7 +401,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -428,11 +423,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -448,18 +443,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -481,11 +471,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -505,14 +490,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -520,39 +501,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -560,7 +524,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -577,7 +541,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -596,10 +559,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -607,19 +566,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_16mb_intelgpu/target.cfg b/config/coreboot/t60_16mb_intelgpu/target.cfg index 5316aa6f..2daf00f7 100644 --- a/config/coreboot/t60_16mb_intelgpu/target.cfg +++ b/config/coreboot/t60_16mb_intelgpu/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb index 0916331f..b42d92e7 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +382,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +391,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +403,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -430,11 +425,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -450,18 +445,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -483,11 +473,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -507,14 +492,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -522,39 +503,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -562,7 +526,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -579,7 +543,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -598,10 +561,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -609,19 +568,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode index b41b4286..1fc2ab3c 100644 --- a/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode +++ b/config/coreboot/t60_intelgpu/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,12 +112,10 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set CONFIG_VARIANT_DIR="t60" @@ -134,25 +128,22 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM0057" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad T60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -184,22 +175,20 @@ CONFIG_BOARD_LENOVO_T60=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM0057" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -213,7 +202,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -241,26 +229,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -268,6 +255,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -285,12 +273,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -310,7 +299,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -345,8 +334,8 @@ CONFIG_SUPERIO_NSC_PC87384=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -357,11 +346,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -371,7 +357,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -395,7 +380,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -403,6 +389,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -410,7 +401,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -428,11 +423,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -448,18 +443,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -481,11 +471,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -505,14 +490,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -520,39 +501,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -560,7 +524,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -577,7 +541,6 @@ CONFIG_HAVE_MP_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -596,10 +559,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -607,19 +566,16 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/t60_intelgpu/target.cfg b/config/coreboot/t60_intelgpu/target.cfg index 5316aa6f..2daf00f7 100644 --- a/config/coreboot/t60_intelgpu/target.cfg +++ b/config/coreboot/t60_intelgpu/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/x60/config/libgfxinit_corebootfb b/config/coreboot/x60/config/libgfxinit_corebootfb index da9884e7..8197735b 100644 --- a/config/coreboot/x60/config/libgfxinit_corebootfb +++ b/config/coreboot/x60/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -399,7 +385,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -407,6 +394,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -414,7 +406,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -436,11 +432,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -456,18 +452,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -489,11 +480,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -513,14 +499,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -528,39 +510,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -568,7 +533,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -587,7 +552,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -606,10 +570,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -617,7 +577,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -625,12 +584,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60/config/libgfxinit_txtmode b/config/coreboot/x60/config/libgfxinit_txtmode index 218e23f4..9ac40a02 100644 --- a/config/coreboot/x60/config/libgfxinit_txtmode +++ b/config/coreboot/x60/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x00200000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +383,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +392,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +404,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -434,11 +430,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -454,18 +450,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -487,11 +478,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -511,14 +497,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -526,39 +508,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +531,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -585,7 +550,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -604,10 +568,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -615,7 +575,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -623,12 +582,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60/target.cfg b/config/coreboot/x60/target.cfg index 5316aa6f..2daf00f7 100644 --- a/config/coreboot/x60/target.cfg +++ b/config/coreboot/x60/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" diff --git a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb index 68b98d98..fc3a4402 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x60_16mb/config/libgfxinit_corebootfb @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -399,7 +385,8 @@ CONFIG_LINEAR_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -407,6 +394,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -414,7 +406,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -436,11 +432,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -456,18 +452,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -489,11 +480,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -513,14 +499,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -528,39 +510,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -568,7 +533,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -587,7 +552,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -606,10 +570,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -617,7 +577,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -625,12 +584,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60_16mb/config/libgfxinit_txtmode b/config/coreboot/x60_16mb/config/libgfxinit_txtmode index f6883deb..c4049565 100644 --- a/config/coreboot/x60_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x60_16mb/config/libgfxinit_txtmode @@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y CONFIG_COMPRESS_RAMSTAGE_LZMA=y # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set @@ -63,7 +62,6 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_CLEVO is not set # CONFIG_VENDOR_COMPULAB is not set @@ -77,9 +75,7 @@ CONFIG_TSEG_STAGE_CACHE=y # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set # CONFIG_VENDOR_KONTRON is not set CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LIBRETREND is not set @@ -116,14 +112,13 @@ CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_CBFS_SIZE=0x01000000 -CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=2 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_POST_DEVICE=y CONFIG_POST_IO=y -CONFIG_UART_FOR_CONSOLE=0 CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VBOOT is not set +CONFIG_VBOOT_VBNV_OFFSET=0x76 CONFIG_IRQ_SLOT_COUNT=18 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set @@ -134,26 +129,23 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_CONSOLE_POST is not set -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="IBM3780" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" CONFIG_VBOOT_SLOTS_RW_A=y CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ECAM_MMCONF_BUS_NUMBER=64 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" +CONFIG_PCIEXP_HOTPLUG_BUSES=8 +CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set # CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set # CONFIG_BOARD_LENOVO_L520 is not set @@ -185,22 +177,20 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60" # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set CONFIG_BOARD_LENOVO_X60=y CONFIG_DRIVER_LENOVO_SERIALS=y +CONFIG_PS2K_EISAID="PNP0303" +CONFIG_PS2M_EISAID="IBM3780" CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_TTYS0_BAUD=115200 -CONFIG_D3COLD_SUPPORT=y -# CONFIG_PCIEXP_ASPM is not set +# CONFIG_DEBUG_SMI is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_PCIEXP_CLK_PM is not set -CONFIG_DRIVERS_UART_8250IO=y -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 +# CONFIG_DRIVERS_UART_8250IO is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_HEAP_SIZE=0x4000 CONFIG_EC_GPE_SCI=0x50 CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -214,7 +204,6 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 @@ -242,26 +231,25 @@ CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_SMM_RESERVED_SIZE=0x100000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 +CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X" CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" CONFIG_STACK_SIZE=0x2000 +CONFIG_VBT_DATA_SIZE_KB=8 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254 CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 +# CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 CONFIG_FIXED_SMBUS_IO_BASE=0x400 +CONFIG_HPET_MIN_TICKS=0x80 CONFIG_CBFS_CACHE_ALIGN=8 CONFIG_INTEL_HAS_TOP_SWAP=y -CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK=y +# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # @@ -269,6 +257,7 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000 # CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SOCKET_SPECIFIC_OPTIONS=y CONFIG_CPU_INTEL_SOCKET_M=y CONFIG_CPU_INTEL_COMMON=y CONFIG_ENABLE_VMX=y @@ -286,12 +275,13 @@ CONFIG_UDELAY_TSC=y CONFIG_TSC_MONOTONIC_TIMER=y CONFIG_TSC_SYNC_MFENCE=y CONFIG_SETUP_XIP_CACHE=y +CONFIG_LOGICAL_CPUS=y CONFIG_HAVE_SMI_HANDLER=y CONFIG_SMM_TSEG=y CONFIG_SMM_LAPIC_REMAP_MITIGATION=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 CONFIG_AP_STACK_SIZE=0x800 CONFIG_SMP=y +CONFIG_MMX=y CONFIG_SSE=y CONFIG_SSE2=y CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y @@ -311,7 +301,7 @@ CONFIG_I945_LVDS=y # # Southbridge # -# CONFIG_PCIEXP_HOTPLUG is not set +CONFIG_PCIEXP_HOTPLUG=y CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y @@ -347,8 +337,8 @@ CONFIG_SUPERIO_NSC_PC87392=y # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y -CONFIG_H8_BEEP_ON_DEATH=y -CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_BEEP_ON_DEATH is not set +# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set # CONFIG_H8_FN_CTRL_SWAP is not set CONFIG_EC_LENOVO_PMH7=y @@ -359,11 +349,8 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 CONFIG_PC80_SYSTEM=y CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_POSTCAR_STAGE=y @@ -373,7 +360,6 @@ CONFIG_COLLECT_TIMESTAMPS_TSC=y CONFIG_HAVE_CF9_RESET=y CONFIG_DEBUG_HW_BREAKPOINTS=y CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set # end of Chipset # @@ -397,7 +383,8 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y CONFIG_PCI=y CONFIG_ECAM_MMCONF_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +CONFIG_AZALIA_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_ECAM_MMCONF_LENGTH=0x04000000 CONFIG_PCI_ALLOW_BUS_MASTER=y @@ -405,6 +392,11 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y +# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_FIRMWARE_CONNECTION_MANAGER=y +# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 @@ -412,7 +404,11 @@ CONFIG_INTEL_GMA_HAVE_VBT=y CONFIG_INTEL_GMA_ADD_VBT=y # CONFIG_SOFTWARE_I2C is not set CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_NO_DDR5=y +CONFIG_NO_LPDDR4=y +CONFIG_NO_DDR4=y +CONFIG_NO_DDR3=y CONFIG_USE_DDR2=y # end of Devices @@ -434,11 +430,11 @@ CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_DRIVERS_UART=y +CONFIG_SPI_FLASH_STMICRO=y # CONFIG_DRIVERS_UART_OXPCIE is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_USBDEBUG is not set @@ -454,18 +450,13 @@ CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" +CONFIG_INTEL_GMA_OPREGION_2_0=y # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_DRIVERS_MC146818=y # CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 CONFIG_VGA=y # CONFIG_DRIVERS_SIL_3114 is not set -CONFIG_DRIVERS_WIFI_GENERIC=y # end of Generic Drivers # @@ -487,11 +478,6 @@ CONFIG_DRIVERS_WIFI_GENERIC=y # Trusted Platform Module # CONFIG_NO_TPM=y -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 # end of Trusted Platform Module # @@ -511,14 +497,10 @@ CONFIG_BOOTMEDIA_LOCK_NONE=y CONFIG_ACPI_HAVE_PCAT_8259=y CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y CONFIG_HAVE_ACPI_TABLES=y CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_HEAP_SIZE=0x100000 # # Console @@ -526,39 +508,22 @@ CONFIG_HEAP_SIZE=0x100000 CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y - -# -# I/O mapped, 8250-compatible -# -CONFIG_TTYS0_BASE=0x3f8 - -# -# Serial port base address = 0x3f8 -# -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -CONFIG_CONSOLE_SERIAL_115200=y -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_LCS=3 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM=y +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_CONSOLE_I2C_SMBUS is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y CONFIG_CONSOLE_USE_ANSI_ESCAPES=y # CONFIG_CMOS_POST is not set @@ -566,7 +531,7 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HWBASE_DEBUG_NULL=y # end of Console CONFIG_HAVE_ACPI_RESUME=y @@ -585,7 +550,6 @@ CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" # end of System tables @@ -604,10 +568,6 @@ CONFIG_PAYLOAD_NONE=y # # CONFIG_DISPLAY_MTRRS is not set -# -# Vendorcode Debug Settings -# - # # BLOB Debug Settings # @@ -615,7 +575,6 @@ CONFIG_PAYLOAD_NONE=y # # General Debug Settings # -# CONFIG_GDB_STUB is not set # CONFIG_FATAL_ASSERTS is not set # CONFIG_DEBUG_CBFS is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y @@ -623,12 +582,10 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_PIRQ is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_CONSOLE_INIT is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set # end of Debugging CONFIG_DECOMPRESS_OFAST=y diff --git a/config/coreboot/x60_16mb/target.cfg b/config/coreboot/x60_16mb/target.cfg index 5316aa6f..2daf00f7 100644 --- a/config/coreboot/x60_16mb/target.cfg +++ b/config/coreboot/x60_16mb/target.cfg @@ -1,4 +1,4 @@ -tree="default" +tree="i945" xarch="i386-elf" payload_grub="y" payload_grub_withseabios="y" From ce7fd754a3d831c563a8589f1cc35e55ce027814 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 19:41:00 +0100 Subject: [PATCH 0030/1319] build/roms: report status when building images export LBMK_VERSION_TYPE=x x can be: stable, unstable in target.cfg files, specify: status=x x can be: stable, unstable, broken, untested if unset, lbmk defaults to "unknown" if LBMK_VERSION_TYPE is set, no confirmation is asked if the given target matches what's set (but what's set in that environmental variable can only be stable or unstable) if LBMK_RELEASE="y", no confirmation is asked, unless the target is something other than stable/unstable "unstable" means it works, but has a few non-breaking bugs, e.g. broken s3 on dell e6400 whereas, if raminit regularly fails or it is so absolutely unreliable as to be unusable, then the board should be declared "broken" untested means: it has not been tested With this change, it should now be easier to track whether a given board is tested, in preparation for releases. When working on trees/boards, status can be set for targets. Also: in the board directory, you can add a "warn.txt" file which will display a message. For example, if a board has a particular quirk to watch out for, write that there. The message will be printed during the build process, to stdout. If status is anything *other* than stable, or it is unstable but LBMK_VERSION_TYPE is not set to "unstable", and not building a release, a confirmation is passed. If the board is not specified as stable or unstable, during a release build, the build is skipped and the ROM is not provided in that release; this is in *addition* to release="n" or release="y" that can be set in target.cfg, which will skip the release build for that target if "n" Signed-off-by: Leah Rowe --- config/coreboot/d510mo/target.cfg | 1 + config/coreboot/d510mo_16mb/target.cfg | 1 + config/coreboot/d945gclf_512kb/target.cfg | 1 + config/coreboot/d945gclf_8mb/target.cfg | 1 + .../coreboot/dell9020mt-nri_12mb/target.cfg | 1 + config/coreboot/dell9020mt_12mb/target.cfg | 1 + .../coreboot/dell9020mtbmrc_12mb/target.cfg | 1 + .../coreboot/dell9020sff-nri_12mb/target.cfg | 1 + config/coreboot/dell9020sff_12mb/target.cfg | 1 + .../coreboot/dell9020sffbmrc_12mb/target.cfg | 1 + config/coreboot/e5420_6mb/target.cfg | 1 + config/coreboot/e5520_6mb/target.cfg | 1 + config/coreboot/e5530_12mb/target.cfg | 1 + config/coreboot/e6400_4mb/target.cfg | 1 + config/coreboot/e6400_4mb/warn.txt | 1 + config/coreboot/e6400nvidia_4mb/target.cfg | 1 + config/coreboot/e6400nvidia_4mb/warn.txt | 2 + config/coreboot/e6420_10mb/target.cfg | 1 + config/coreboot/e6430_12mb/target.cfg | 1 + config/coreboot/e6520_10mb/target.cfg | 1 + config/coreboot/e6530_12mb/target.cfg | 1 + config/coreboot/g43t-am3/target.cfg | 1 + config/coreboot/g43t-am3_16mb/target.cfg | 1 + config/coreboot/ga-g41m-es2l/target.cfg | 1 + config/coreboot/gru_bob/target.cfg | 1 + config/coreboot/gru_kevin/target.cfg | 1 + config/coreboot/hp2170p_16mb/target.cfg | 1 + config/coreboot/hp2560p_8mb/target.cfg | 1 + config/coreboot/hp2570p_16mb/target.cfg | 1 + config/coreboot/hp8200sff_4mb/target.cfg | 1 + config/coreboot/hp8200sff_8mb/target.cfg | 1 + config/coreboot/hp820g2_12mb/target.cfg | 1 + config/coreboot/hp8300cmt_16mb/target.cfg | 1 + config/coreboot/hp8300usdt_16mb/target.cfg | 1 + config/coreboot/hp8460pintel_8mb/target.cfg | 1 + config/coreboot/hp8470pintel_16mb/target.cfg | 1 + config/coreboot/hp8560w_8mb/target.cfg | 1 + config/coreboot/hp9470m_16mb/target.cfg | 1 + config/coreboot/kcma-d8-rdimm_16mb/target.cfg | 1 + config/coreboot/kcma-d8-rdimm_2mb/target.cfg | 1 + config/coreboot/kcma-d8-udimm_16mb/target.cfg | 1 + config/coreboot/kcma-d8-udimm_2mb/target.cfg | 1 + config/coreboot/kfsn4-dre_1mb/target.cfg | 1 + config/coreboot/kfsn4-dre_2mb/target.cfg | 1 + .../coreboot/kgpe-d16-rdimm_16mb/target.cfg | 1 + config/coreboot/kgpe-d16-rdimm_2mb/target.cfg | 1 + .../coreboot/kgpe-d16-udimm_16mb/target.cfg | 1 + config/coreboot/kgpe-d16-udimm_2mb/target.cfg | 1 + config/coreboot/macbook11/target.cfg | 1 + config/coreboot/macbook11_16mb/target.cfg | 1 + config/coreboot/macbook21/target.cfg | 1 + config/coreboot/macbook21_16mb/target.cfg | 1 + config/coreboot/qemu_arm64_12mb/target.cfg | 1 + config/coreboot/qemu_x86_12mb/target.cfg | 1 + config/coreboot/r400_16mb/target.cfg | 1 + config/coreboot/r400_4mb/target.cfg | 1 + config/coreboot/r400_8mb/target.cfg | 1 + config/coreboot/r500_4mb/target.cfg | 1 + config/coreboot/t1650_12mb/target.cfg | 1 + config/coreboot/t400_16mb/target.cfg | 1 + config/coreboot/t400_4mb/target.cfg | 1 + config/coreboot/t400_8mb/target.cfg | 1 + config/coreboot/t420_8mb/target.cfg | 1 + config/coreboot/t420s_8mb/target.cfg | 1 + config/coreboot/t430_12mb/target.cfg | 1 + config/coreboot/t440pbmrc_12mb/target.cfg | 1 + config/coreboot/t440plibremrc_12mb/target.cfg | 1 + config/coreboot/t440pmrc_12mb/target.cfg | 1 + config/coreboot/t500_16mb/target.cfg | 1 + config/coreboot/t500_4mb/target.cfg | 1 + config/coreboot/t500_8mb/target.cfg | 1 + config/coreboot/t520_8mb/target.cfg | 1 + config/coreboot/t530_12mb/target.cfg | 1 + config/coreboot/t60_16mb_intelgpu/target.cfg | 1 + config/coreboot/t60_intelgpu/target.cfg | 1 + config/coreboot/w500_16mb/target.cfg | 1 + config/coreboot/w500_4mb/target.cfg | 1 + config/coreboot/w500_8mb/target.cfg | 1 + config/coreboot/w530_12mb/target.cfg | 1 + config/coreboot/w541_12mb/target.cfg | 1 + config/coreboot/w541bmrc_12mb/target.cfg | 1 + config/coreboot/w541mrc_12mb/target.cfg | 1 + config/coreboot/x200_16mb/target.cfg | 1 + config/coreboot/x200_4mb/target.cfg | 1 + config/coreboot/x200_8mb/target.cfg | 1 + config/coreboot/x220_8mb/target.cfg | 1 + config/coreboot/x220edp_8mb/target.cfg | 1 + config/coreboot/x220edp_8mb/warn.txt | 1 + config/coreboot/x230_12mb/target.cfg | 1 + config/coreboot/x230_12mb/warn.txt | 1 + config/coreboot/x230_16mb/target.cfg | 1 + config/coreboot/x230edp_12mb/target.cfg | 1 + config/coreboot/x230t_12mb/target.cfg | 1 + config/coreboot/x230t_16mb/target.cfg | 1 + config/coreboot/x301_16mb/target.cfg | 1 + config/coreboot/x301_4mb/target.cfg | 1 + config/coreboot/x301_8mb/target.cfg | 1 + config/coreboot/x60/target.cfg | 1 + config/coreboot/x60_16mb/target.cfg | 1 + include/err.sh | 13 +++- script/build/roms | 66 +++++++++++++++++-- 101 files changed, 172 insertions(+), 7 deletions(-) create mode 100644 config/coreboot/e6400_4mb/warn.txt create mode 100644 config/coreboot/e6400nvidia_4mb/warn.txt create mode 100644 config/coreboot/x220edp_8mb/warn.txt create mode 100644 config/coreboot/x230_12mb/warn.txt diff --git a/config/coreboot/d510mo/target.cfg b/config/coreboot/d510mo/target.cfg index 69c1db41..f07fee9a 100644 --- a/config/coreboot/d510mo/target.cfg +++ b/config/coreboot/d510mo/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="y" +status="untested" diff --git a/config/coreboot/d510mo_16mb/target.cfg b/config/coreboot/d510mo_16mb/target.cfg index 1e7b56ca..a99b11f0 100644 --- a/config/coreboot/d510mo_16mb/target.cfg +++ b/config/coreboot/d510mo_16mb/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_seabios_withgrub="y" payload_memtest="y" +status="untested" diff --git a/config/coreboot/d945gclf_512kb/target.cfg b/config/coreboot/d945gclf_512kb/target.cfg index cfae0b2c..5899fae2 100644 --- a/config/coreboot/d945gclf_512kb/target.cfg +++ b/config/coreboot/d945gclf_512kb/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" +status="untested" diff --git a/config/coreboot/d945gclf_8mb/target.cfg b/config/coreboot/d945gclf_8mb/target.cfg index cfae0b2c..5899fae2 100644 --- a/config/coreboot/d945gclf_8mb/target.cfg +++ b/config/coreboot/d945gclf_8mb/target.cfg @@ -4,3 +4,4 @@ payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" +status="untested" diff --git a/config/coreboot/dell9020mt-nri_12mb/target.cfg b/config/coreboot/dell9020mt-nri_12mb/target.cfg index 37d8f553..bc4053d4 100644 --- a/config/coreboot/dell9020mt-nri_12mb/target.cfg +++ b/config/coreboot/dell9020mt-nri_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index 0da057a9..a3acd5fb 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg index 0da057a9..a3acd5fb 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/dell9020sff-nri_12mb/target.cfg b/config/coreboot/dell9020sff-nri_12mb/target.cfg index 37d8f553..bc4053d4 100644 --- a/config/coreboot/dell9020sff-nri_12mb/target.cfg +++ b/config/coreboot/dell9020sff-nri_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index 0da057a9..a3acd5fb 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg index 0da057a9..a3acd5fb 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index 3a458ee4..d1ea26ad 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="unstable" # broken s3 diff --git a/config/coreboot/e6400_4mb/warn.txt b/config/coreboot/e6400_4mb/warn.txt new file mode 100644 index 00000000..95b8ebbf --- /dev/null +++ b/config/coreboot/e6400_4mb/warn.txt @@ -0,0 +1 @@ +broken s3 resume/suspend, no battery indicator/status diff --git a/config/coreboot/e6400nvidia_4mb/target.cfg b/config/coreboot/e6400nvidia_4mb/target.cfg index 3a458ee4..d1026eed 100644 --- a/config/coreboot/e6400nvidia_4mb/target.cfg +++ b/config/coreboot/e6400nvidia_4mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="unstable" # s3, nvidia+nouveau diff --git a/config/coreboot/e6400nvidia_4mb/warn.txt b/config/coreboot/e6400nvidia_4mb/warn.txt new file mode 100644 index 00000000..a604fc87 --- /dev/null +++ b/config/coreboot/e6400nvidia_4mb/warn.txt @@ -0,0 +1,2 @@ +broken s3 resume/suspend, no battery indicator/status. +nouveau crashes xorg under linux (can use nomodeset) diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index 1cf0792e..70be0ab9 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -9,3 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" +status="untested" diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index 03fd230b..e2375ad4 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,3 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/g43t-am3/target.cfg b/config/coreboot/g43t-am3/target.cfg index 13f2a260..af80482f 100644 --- a/config/coreboot/g43t-am3/target.cfg +++ b/config/coreboot/g43t-am3/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 +status="untested" diff --git a/config/coreboot/g43t-am3_16mb/target.cfg b/config/coreboot/g43t-am3_16mb/target.cfg index 13f2a260..af80482f 100644 --- a/config/coreboot/g43t-am3_16mb/target.cfg +++ b/config/coreboot/g43t-am3_16mb/target.cfg @@ -3,3 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 +status="untested" diff --git a/config/coreboot/ga-g41m-es2l/target.cfg b/config/coreboot/ga-g41m-es2l/target.cfg index ef85da4b..9fc566d8 100644 --- a/config/coreboot/ga-g41m-es2l/target.cfg +++ b/config/coreboot/ga-g41m-es2l/target.cfg @@ -4,3 +4,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ata" grub_timeout=10 +status="untested" diff --git a/config/coreboot/gru_bob/target.cfg b/config/coreboot/gru_bob/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/gru_bob/target.cfg +++ b/config/coreboot/gru_bob/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/gru_kevin/target.cfg b/config/coreboot/gru_kevin/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/gru_kevin/target.cfg +++ b/config/coreboot/gru_kevin/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/hp2170p_16mb/target.cfg b/config/coreboot/hp2170p_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2170p_16mb/target.cfg +++ b/config/coreboot/hp2170p_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp2560p_8mb/target.cfg b/config/coreboot/hp2560p_8mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2560p_8mb/target.cfg +++ b/config/coreboot/hp2560p_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp2570p_16mb/target.cfg b/config/coreboot/hp2570p_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp2570p_16mb/target.cfg +++ b/config/coreboot/hp2570p_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8200sff_4mb/target.cfg b/config/coreboot/hp8200sff_4mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8200sff_4mb/target.cfg +++ b/config/coreboot/hp8200sff_4mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8200sff_8mb/target.cfg b/config/coreboot/hp8200sff_8mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8200sff_8mb/target.cfg +++ b/config/coreboot/hp8200sff_8mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp820g2_12mb/target.cfg b/config/coreboot/hp820g2_12mb/target.cfg index 06f3025c..e19a0d14 100644 --- a/config/coreboot/hp820g2_12mb/target.cfg +++ b/config/coreboot/hp820g2_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/hp8300cmt_16mb/target.cfg b/config/coreboot/hp8300cmt_16mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8300cmt_16mb/target.cfg +++ b/config/coreboot/hp8300cmt_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8300usdt_16mb/target.cfg b/config/coreboot/hp8300usdt_16mb/target.cfg index 0badb4fb..12afcd76 100644 --- a/config/coreboot/hp8300usdt_16mb/target.cfg +++ b/config/coreboot/hp8300usdt_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8460pintel_8mb/target.cfg b/config/coreboot/hp8460pintel_8mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp8460pintel_8mb/target.cfg +++ b/config/coreboot/hp8460pintel_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8470pintel_16mb/target.cfg b/config/coreboot/hp8470pintel_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp8470pintel_16mb/target.cfg +++ b/config/coreboot/hp8470pintel_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/hp8560w_8mb/target.cfg b/config/coreboot/hp8560w_8mb/target.cfg index ae56c735..a352b46d 100644 --- a/config/coreboot/hp8560w_8mb/target.cfg +++ b/config/coreboot/hp8560w_8mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="unstable" diff --git a/config/coreboot/hp9470m_16mb/target.cfg b/config/coreboot/hp9470m_16mb/target.cfg index fee132f4..1b9e33f0 100644 --- a/config/coreboot/hp9470m_16mb/target.cfg +++ b/config/coreboot/hp9470m_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg index d5d37291..c618cc13 100644 --- a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg index d5d37291..c618cc13 100644 --- a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-udimm_16mb/target.cfg b/config/coreboot/kcma-d8-udimm_16mb/target.cfg index 35354c26..37d16a2a 100644 --- a/config/coreboot/kcma-d8-udimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_16mb/target.cfg @@ -6,3 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kcma-d8-udimm_2mb/target.cfg b/config/coreboot/kcma-d8-udimm_2mb/target.cfg index 35354c26..37d16a2a 100644 --- a/config/coreboot/kcma-d8-udimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_2mb/target.cfg @@ -6,3 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" +status="untested" diff --git a/config/coreboot/kfsn4-dre_1mb/target.cfg b/config/coreboot/kfsn4-dre_1mb/target.cfg index 19c57b8d..15f35ccd 100644 --- a/config/coreboot/kfsn4-dre_1mb/target.cfg +++ b/config/coreboot/kfsn4-dre_1mb/target.cfg @@ -4,3 +4,4 @@ payload_seabios="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kfsn4-dre_2mb/target.cfg b/config/coreboot/kfsn4-dre_2mb/target.cfg index 9bd20d45..e65a5e9c 100644 --- a/config/coreboot/kfsn4-dre_2mb/target.cfg +++ b/config/coreboot/kfsn4-dre_2mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg index 2867a730..e074689c 100644 --- a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg index 2867a730..e074689c 100644 --- a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg index 5b4010d8..1e128ae9 100644 --- a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg index 5b4010d8..1e128ae9 100644 --- a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 +status="untested" diff --git a/config/coreboot/macbook11/target.cfg b/config/coreboot/macbook11/target.cfg index dcf5d1de..404e0129 100644 --- a/config/coreboot/macbook11/target.cfg +++ b/config/coreboot/macbook11/target.cfg @@ -4,3 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook11_16mb/target.cfg b/config/coreboot/macbook11_16mb/target.cfg index dcf5d1de..404e0129 100644 --- a/config/coreboot/macbook11_16mb/target.cfg +++ b/config/coreboot/macbook11_16mb/target.cfg @@ -4,3 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook21/target.cfg b/config/coreboot/macbook21/target.cfg index bb56ec25..e9eab4e9 100644 --- a/config/coreboot/macbook21/target.cfg +++ b/config/coreboot/macbook21/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/macbook21_16mb/target.cfg b/config/coreboot/macbook21_16mb/target.cfg index bb56ec25..e9eab4e9 100644 --- a/config/coreboot/macbook21_16mb/target.cfg +++ b/config/coreboot/macbook21_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/qemu_arm64_12mb/target.cfg b/config/coreboot/qemu_arm64_12mb/target.cfg index a7c36159..3ff37611 100644 --- a/config/coreboot/qemu_arm64_12mb/target.cfg +++ b/config/coreboot/qemu_arm64_12mb/target.cfg @@ -1,3 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" +status="untested" diff --git a/config/coreboot/qemu_x86_12mb/target.cfg b/config/coreboot/qemu_x86_12mb/target.cfg index 4d03eb4a..d92fda66 100644 --- a/config/coreboot/qemu_x86_12mb/target.cfg +++ b/config/coreboot/qemu_x86_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="both" +status="untested" diff --git a/config/coreboot/r400_16mb/target.cfg b/config/coreboot/r400_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_16mb/target.cfg +++ b/config/coreboot/r400_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r400_4mb/target.cfg b/config/coreboot/r400_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_4mb/target.cfg +++ b/config/coreboot/r400_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r400_8mb/target.cfg b/config/coreboot/r400_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r400_8mb/target.cfg +++ b/config/coreboot/r400_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/r500_4mb/target.cfg b/config/coreboot/r500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/r500_4mb/target.cfg +++ b/config/coreboot/r500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t1650_12mb/target.cfg b/config/coreboot/t1650_12mb/target.cfg index e6d3bec6..6333672b 100644 --- a/config/coreboot/t1650_12mb/target.cfg +++ b/config/coreboot/t1650_12mb/target.cfg @@ -5,3 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_16mb/target.cfg b/config/coreboot/t400_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_16mb/target.cfg +++ b/config/coreboot/t400_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_4mb/target.cfg b/config/coreboot/t400_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_4mb/target.cfg +++ b/config/coreboot/t400_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t400_8mb/target.cfg b/config/coreboot/t400_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t400_8mb/target.cfg +++ b/config/coreboot/t400_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t420_8mb/target.cfg b/config/coreboot/t420_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t420_8mb/target.cfg +++ b/config/coreboot/t420_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t420s_8mb/target.cfg b/config/coreboot/t420s_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t420s_8mb/target.cfg +++ b/config/coreboot/t420s_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t430_12mb/target.cfg b/config/coreboot/t430_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t430_12mb/target.cfg +++ b/config/coreboot/t430_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t440pbmrc_12mb/target.cfg b/config/coreboot/t440pbmrc_12mb/target.cfg index 06f3025c..e19a0d14 100644 --- a/config/coreboot/t440pbmrc_12mb/target.cfg +++ b/config/coreboot/t440pbmrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/t440plibremrc_12mb/target.cfg b/config/coreboot/t440plibremrc_12mb/target.cfg index 8bb575a9..0efb19ed 100644 --- a/config/coreboot/t440plibremrc_12mb/target.cfg +++ b/config/coreboot/t440plibremrc_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/t440pmrc_12mb/target.cfg b/config/coreboot/t440pmrc_12mb/target.cfg index 06f3025c..e19a0d14 100644 --- a/config/coreboot/t440pmrc_12mb/target.cfg +++ b/config/coreboot/t440pmrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/t500_16mb/target.cfg b/config/coreboot/t500_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_16mb/target.cfg +++ b/config/coreboot/t500_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t500_4mb/target.cfg b/config/coreboot/t500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_4mb/target.cfg +++ b/config/coreboot/t500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t500_8mb/target.cfg b/config/coreboot/t500_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t500_8mb/target.cfg +++ b/config/coreboot/t500_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t520_8mb/target.cfg b/config/coreboot/t520_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t520_8mb/target.cfg +++ b/config/coreboot/t520_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t530_12mb/target.cfg b/config/coreboot/t530_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/t530_12mb/target.cfg +++ b/config/coreboot/t530_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/t60_16mb_intelgpu/target.cfg b/config/coreboot/t60_16mb_intelgpu/target.cfg index 2daf00f7..6a6d833a 100644 --- a/config/coreboot/t60_16mb_intelgpu/target.cfg +++ b/config/coreboot/t60_16mb_intelgpu/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/t60_intelgpu/target.cfg b/config/coreboot/t60_intelgpu/target.cfg index 2daf00f7..6a6d833a 100644 --- a/config/coreboot/t60_intelgpu/target.cfg +++ b/config/coreboot/t60_intelgpu/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/w500_16mb/target.cfg b/config/coreboot/w500_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_16mb/target.cfg +++ b/config/coreboot/w500_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w500_4mb/target.cfg b/config/coreboot/w500_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_4mb/target.cfg +++ b/config/coreboot/w500_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w500_8mb/target.cfg b/config/coreboot/w500_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w500_8mb/target.cfg +++ b/config/coreboot/w500_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w530_12mb/target.cfg b/config/coreboot/w530_12mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/w530_12mb/target.cfg +++ b/config/coreboot/w530_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/w541_12mb/target.cfg b/config/coreboot/w541_12mb/target.cfg index 8bb575a9..0efb19ed 100644 --- a/config/coreboot/w541_12mb/target.cfg +++ b/config/coreboot/w541_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/w541bmrc_12mb/target.cfg b/config/coreboot/w541bmrc_12mb/target.cfg index 06f3025c..e19a0d14 100644 --- a/config/coreboot/w541bmrc_12mb/target.cfg +++ b/config/coreboot/w541bmrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/w541mrc_12mb/target.cfg b/config/coreboot/w541mrc_12mb/target.cfg index 06f3025c..e19a0d14 100644 --- a/config/coreboot/w541mrc_12mb/target.cfg +++ b/config/coreboot/w541mrc_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" release="n" +status="stable" diff --git a/config/coreboot/x200_16mb/target.cfg b/config/coreboot/x200_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_16mb/target.cfg +++ b/config/coreboot/x200_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x200_4mb/target.cfg b/config/coreboot/x200_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_4mb/target.cfg +++ b/config/coreboot/x200_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x200_8mb/target.cfg b/config/coreboot/x200_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x200_8mb/target.cfg +++ b/config/coreboot/x200_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x220_8mb/target.cfg b/config/coreboot/x220_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x220_8mb/target.cfg +++ b/config/coreboot/x220_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x220edp_8mb/target.cfg b/config/coreboot/x220edp_8mb/target.cfg index 8688df3f..529581bd 100644 --- a/config/coreboot/x220edp_8mb/target.cfg +++ b/config/coreboot/x220edp_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="broken" # TODO: VCC3P patch diff --git a/config/coreboot/x220edp_8mb/warn.txt b/config/coreboot/x220edp_8mb/warn.txt new file mode 100644 index 00000000..a153edeb --- /dev/null +++ b/config/coreboot/x220edp_8mb/warn.txt @@ -0,0 +1 @@ +TODO: VCC3P patch diff --git a/config/coreboot/x230_12mb/target.cfg b/config/coreboot/x230_12mb/target.cfg index 8688df3f..f16a94a4 100644 --- a/config/coreboot/x230_12mb/target.cfg +++ b/config/coreboot/x230_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/x230_12mb/warn.txt b/config/coreboot/x230_12mb/warn.txt new file mode 100644 index 00000000..a153edeb --- /dev/null +++ b/config/coreboot/x230_12mb/warn.txt @@ -0,0 +1 @@ +TODO: VCC3P patch diff --git a/config/coreboot/x230_16mb/target.cfg b/config/coreboot/x230_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x230_16mb/target.cfg +++ b/config/coreboot/x230_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x230edp_12mb/target.cfg b/config/coreboot/x230edp_12mb/target.cfg index 8688df3f..529581bd 100644 --- a/config/coreboot/x230edp_12mb/target.cfg +++ b/config/coreboot/x230edp_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="broken" # TODO: VCC3P patch diff --git a/config/coreboot/x230t_12mb/target.cfg b/config/coreboot/x230t_12mb/target.cfg index 8688df3f..f16a94a4 100644 --- a/config/coreboot/x230t_12mb/target.cfg +++ b/config/coreboot/x230t_12mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="stable" diff --git a/config/coreboot/x230t_16mb/target.cfg b/config/coreboot/x230t_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x230t_16mb/target.cfg +++ b/config/coreboot/x230t_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_16mb/target.cfg b/config/coreboot/x301_16mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_16mb/target.cfg +++ b/config/coreboot/x301_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_4mb/target.cfg b/config/coreboot/x301_4mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_4mb/target.cfg +++ b/config/coreboot/x301_4mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x301_8mb/target.cfg b/config/coreboot/x301_8mb/target.cfg index 8688df3f..6c267eca 100644 --- a/config/coreboot/x301_8mb/target.cfg +++ b/config/coreboot/x301_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" +status="untested" diff --git a/config/coreboot/x60/target.cfg b/config/coreboot/x60/target.cfg index 2daf00f7..6a6d833a 100644 --- a/config/coreboot/x60/target.cfg +++ b/config/coreboot/x60/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/config/coreboot/x60_16mb/target.cfg b/config/coreboot/x60_16mb/target.cfg index 2daf00f7..6a6d833a 100644 --- a/config/coreboot/x60_16mb/target.cfg +++ b/config/coreboot/x60_16mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" +status="untested" diff --git a/include/err.sh b/include/err.sh index d4f8700b..097d4230 100755 --- a/include/err.sh +++ b/include/err.sh @@ -5,7 +5,7 @@ export LC_COLLATE=C export LC_ALL=C version=""; versiondate=""; projectname=""; _nogit="" -err="err_"; tmpdir="" +err="err_"; tmpdir=""; release_type="" # if "y": a coreboot target won't be built if target.cfg says release="n" # (this is used to exclude certain build targets from releases) @@ -15,6 +15,17 @@ set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : [ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" export LBMK_RELEASE="$lbmk_release" +# valid values: +# empty / not set +# value: stable +# value: unstable +# e.g. export LBMK_VERSION_TYPE=stable +set | grep LBMK_VERSION_TYPE 1>/dev/null 2>/dev/null && \ + release_type="$LBMK_VERSION_TYPE" +[ -z "$release_type" ] || [ "$release_type" = "stable" ] || \ + [ "$release_type" = "unstable" ] || release_type="" +export LBMK_VERSION_TYPE="$release_type" + tmpdir_was_set="y" set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" if [ "${tmpdir_was_set}" = "y" ]; then diff --git a/script/build/roms b/script/build/roms index 5fdc05c9..2269e714 100755 --- a/script/build/roms +++ b/script/build/roms @@ -21,9 +21,10 @@ cfgsdir="config/coreboot" pv="payload_grub payload_grub_withseabios payload_seabios payload_memtest t" pv="${pv} payload_seabios_withgrub payload_seabios_grubonly payload_uboot memtest_bin" v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps release" -v="${v} grub_timeout ubdir board grub_scan_disk uboot_config" +v="${v} grub_timeout ubdir board grub_scan_disk uboot_config status" eval "$(setvars "n" ${pv})" -eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets)" +eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets \ + skipped)" main() { @@ -55,20 +56,31 @@ main() eval "$(setvars "n" ${pv}) $(setvars "" ${v})" grub_background="background1280x800.png" board="${x}" + configure_target + [ "$board" = "$tree" ] && \ + return 1 + + handle_status # exclude certain targets from the release - if [ "$release" = "n" ] && [ "$lbmk_release" = "y" ]; then - printf "Skipping target: %s\n" "$x" - continue - fi + skip_board && \ + printf "Skip target %s(%s)\n" "$board" "$status" && \ + skipped="* $board($status)\n$skipped" && continue build_payloads build_target_mainboard + [ -d "bin/${board}" ] || continue targets="* bin/${board}\n${targets}" done + if [ -n "$skipped" ]; then + printf "\nThese targets were skipped:\n" + eval "printf \"${skipped}\"" + printf "^^ These targets were skipped.\n\n" + fi + [ -z "${targets}" ] && $err "No ROM images were compiled" printf "\nROM images available in these directories:\n" eval "printf \"${targets}\"" @@ -125,6 +137,48 @@ configure_target() eval "payload_${_payload}=y" } +handle_status() +{ + [ "$status" = "stable" ] || [ "$status" = "unstable" ] || \ + [ "$status" = "broken" ] || [ "$status" = "untested" ] || \ + status="unknown" + + printf "Handling target: %s (status=%s)\n" "$board" "$status" + + [ "$status" = "broken" ] && release="n" + [ "$status" = "unknown" ] && release="n" + [ "$status" = "untested" ] && release="n" + + [ "$status" != "stable" ] && [ "$status" != "$release_type" ] && \ + printf "WARNING: %s not marked stable (status=%s):\n\n" \ + "$board" "$status"; return 0 +} + +skip_board() +{ + [ "$release" = "n" ] && [ "$lbmk_release" = "y" ] && \ + return 0 + [ -n "$release_type" ] && [ "$status" = "$release_type" ] && \ + return 1 + + if [ "$lbmk_release" != "y" ] && [ "$status" != "stable" ] && \ + [ "$status" != "$release_type" ]; then + if [ -f "$targetdir/warn.txt" ]; then + printf "Regarding board '%s' (status '%s'):\n" \ + "$board" "$status" + cat -u "$targetdir/warn.txt" || \ + $err "!cat $targetdir/warn.txt" + fi + while true; do + printf "Board %s has status '%s'. Skip? [y/n]" \ + "$board" "$status" + read -r skip + [ "$skip" = "y" ] && return 0 + [ "$skip" = "n" ] && return 1; continue + done + fi; return 1 +} + build_payloads() { romdir="bin/${board}" From b6014a65acc786bee37590214c6af46d554d19a0 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 21:10:06 +0100 Subject: [PATCH 0031/1319] erroneous return Signed-off-by: Leah Rowe --- script/build/roms | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/build/roms b/script/build/roms index 2269e714..1d36ad8a 100755 --- a/script/build/roms +++ b/script/build/roms @@ -59,7 +59,7 @@ main() configure_target [ "$board" = "$tree" ] && \ - return 1 + continue handle_status From d88783b7341656c26186e967425cf33341841dee Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 21:23:09 +0100 Subject: [PATCH 0032/1319] build/roms: let "list" specify status types for example: ./build roms list this will list every now, still. same behaviour. now see: ./build roms list stable this will list all stable roms ./build roms list untested this lists untested roms. but wait! ./build roms list untested broken unstable ./build roms list broken unstable yes. it works this way. now you can use lbmk to easily see what rom status are, during maintenance. Signed-off-by: Leah Rowe --- script/build/roms | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/script/build/roms b/script/build/roms index 1d36ad8a..03310315 100755 --- a/script/build/roms +++ b/script/build/roms @@ -24,20 +24,33 @@ v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps release" v="${v} grub_timeout ubdir board grub_scan_disk uboot_config status" eval "$(setvars "n" ${pv})" eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets \ - skipped)" + skipped listboards list_type)" main() { check_project while [ $# -gt 0 ]; do + + if [ "$listboards" = "y" ]; then + [ "$1" = "stable" ] || [ "$1" = "unstable" ] || \ + [ "$1" = "broken" ] || [ "$1" = "untested" ] || \ + [ "$1" = "unknown" ] || \ + $err "invalid list type '$1'" + list_type="$list_type $1" + list_type="${list_type# }" + shift 1; continue + fi + case ${1} in help) usage exit 0 ;; list) - items config/coreboot || : - exit 0 ;; + boards=$(items config/coreboot) || \ + $err "Cannot generate list of boards for list" + listboards="y" + shift 1; continue ;; -d) _displaymode="${2}" ;; -p) _payload="${2}" ;; -k) _keyboard="${2}" ;; @@ -49,6 +62,9 @@ main() shift 2 done + [ "$listboards" = "y" ] && [ -z "$list_type" ] && \ + list_type="stable unstable broken untested unknown" + [ "${all}" != "y" ] || boards=$(items config/coreboot) || \ $err "Cannot generate list of boards for building" @@ -63,6 +79,14 @@ main() handle_status + if [ "$listboards" = "y" ]; then + for _list_type in $list_type; do + [ "$status" != "$_list_type" ] && continue + printf "%s\n" "$board" + done + continue + fi + # exclude certain targets from the release skip_board && \ printf "Skip target %s(%s)\n" "$board" "$status" && \ @@ -75,6 +99,8 @@ main() targets="* bin/${board}\n${targets}" done + [ "$listboards" = "y" ] && return 0 + if [ -n "$skipped" ]; then printf "\nThese targets were skipped:\n" eval "printf \"${skipped}\"" @@ -143,13 +169,15 @@ handle_status() [ "$status" = "broken" ] || [ "$status" = "untested" ] || \ status="unknown" - printf "Handling target: %s (status=%s)\n" "$board" "$status" + [ "$listboards" != "y" ] && \ + printf "Handling target: %s (status=%s)\n" "$board" "$status" [ "$status" = "broken" ] && release="n" [ "$status" = "unknown" ] && release="n" [ "$status" = "untested" ] && release="n" - [ "$status" != "stable" ] && [ "$status" != "$release_type" ] && \ + [ "$listboards" != "y" ] && \ + [ "$status" != "stable" ] && [ "$status" != "$release_type" ] && \ printf "WARNING: %s not marked stable (status=%s):\n\n" \ "$board" "$status"; return 0 } From c0b4ba2eeadc5bdc6c7b10251561ecf1a9c72a7b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 26 Apr 2024 23:32:10 +0100 Subject: [PATCH 0033/1319] build/roms: update help, pertaining to status Signed-off-by: Leah Rowe --- script/build/roms | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/script/build/roms b/script/build/roms index 03310315..ea7ef62c 100755 --- a/script/build/roms +++ b/script/build/roms @@ -497,8 +497,23 @@ usage() ./build roms x200_8mb x60 ./build roms x60 -p grub -d corebootfb -k usqwerty - possible values for 'target': - $(items "config/coreboot") + to see possible values for 'target': + + ./build roms list + + to see targets of only a given status (stable, unstable, + broken, untested and unknown), try e.g. + + ./build roms list stable + ./build roms list unstable untested + ./build roms list unknown + ./build roms list broken + ./build roms list broken stable + + the value is set in target.cfg for each board. if status + is unitialised, it defaults to "unknown". only stable/unstable + targets are permitted in releases; broken, untested and + unknown are not allowed, but are accessible via normal building Refer to the ${projectname} documentation for more information. EOF From b99ebe05514609ba8ee7cf33d128ee3efb7fd803 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 06:08:07 +0100 Subject: [PATCH 0034/1319] kcma-d8/kgpe-d16: mark as tested(unstable) raminit has never been fully reliable on this board, and so this board has never been stable. so, now that lbmk specifies such status per board, mark these boards as such. Signed-off-by: Leah Rowe --- config/coreboot/kcma-d8-rdimm_16mb/target.cfg | 2 +- config/coreboot/kcma-d8-rdimm_16mb/warn.txt | 1 + config/coreboot/kcma-d8-rdimm_2mb/target.cfg | 2 +- config/coreboot/kcma-d8-rdimm_2mb/warn.txt | 1 + config/coreboot/kcma-d8-udimm_16mb/target.cfg | 2 +- config/coreboot/kcma-d8-udimm_16mb/warn.txt | 1 + config/coreboot/kcma-d8-udimm_2mb/target.cfg | 2 +- config/coreboot/kcma-d8-udimm_2mb/warn.txt | 1 + config/coreboot/kgpe-d16-rdimm_16mb/target.cfg | 2 +- config/coreboot/kgpe-d16-rdimm_16mb/warn.txt | 1 + config/coreboot/kgpe-d16-rdimm_2mb/target.cfg | 2 +- config/coreboot/kgpe-d16-rdimm_2mb/warn.txt | 1 + config/coreboot/kgpe-d16-udimm_16mb/target.cfg | 2 +- config/coreboot/kgpe-d16-udimm_16mb/warn.txt | 1 + config/coreboot/kgpe-d16-udimm_2mb/target.cfg | 2 +- config/coreboot/kgpe-d16-udimm_2mb/warn.txt | 1 + 16 files changed, 16 insertions(+), 8 deletions(-) create mode 100644 config/coreboot/kcma-d8-rdimm_16mb/warn.txt create mode 100644 config/coreboot/kcma-d8-rdimm_2mb/warn.txt create mode 100644 config/coreboot/kcma-d8-udimm_16mb/warn.txt create mode 100644 config/coreboot/kcma-d8-udimm_2mb/warn.txt create mode 100644 config/coreboot/kgpe-d16-rdimm_16mb/warn.txt create mode 100644 config/coreboot/kgpe-d16-rdimm_2mb/warn.txt create mode 100644 config/coreboot/kgpe-d16-udimm_16mb/warn.txt create mode 100644 config/coreboot/kgpe-d16-udimm_2mb/warn.txt diff --git a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg index c618cc13..3d0185e9 100644 --- a/config/coreboot/kcma-d8-rdimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" -status="untested" +status="unstable" diff --git a/config/coreboot/kcma-d8-rdimm_16mb/warn.txt b/config/coreboot/kcma-d8-rdimm_16mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kcma-d8-rdimm_16mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg index c618cc13..3d0185e9 100644 --- a/config/coreboot/kcma-d8-rdimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-rdimm_2mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" -status="untested" +status="unstable" diff --git a/config/coreboot/kcma-d8-rdimm_2mb/warn.txt b/config/coreboot/kcma-d8-rdimm_2mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kcma-d8-rdimm_2mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kcma-d8-udimm_16mb/target.cfg b/config/coreboot/kcma-d8-udimm_16mb/target.cfg index 37d16a2a..2c3bc306 100644 --- a/config/coreboot/kcma-d8-udimm_16mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_16mb/target.cfg @@ -6,4 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" -status="untested" +status="unstable" diff --git a/config/coreboot/kcma-d8-udimm_16mb/warn.txt b/config/coreboot/kcma-d8-udimm_16mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kcma-d8-udimm_16mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kcma-d8-udimm_2mb/target.cfg b/config/coreboot/kcma-d8-udimm_2mb/target.cfg index 37d16a2a..2c3bc306 100644 --- a/config/coreboot/kcma-d8-udimm_2mb/target.cfg +++ b/config/coreboot/kcma-d8-udimm_2mb/target.cfg @@ -6,4 +6,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" xlang="c" -status="untested" +status="unstable" diff --git a/config/coreboot/kcma-d8-udimm_2mb/warn.txt b/config/coreboot/kcma-d8-udimm_2mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kcma-d8-udimm_2mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg index e074689c..f469e6fe 100644 --- a/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_16mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/kgpe-d16-rdimm_16mb/warn.txt b/config/coreboot/kgpe-d16-rdimm_16mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kgpe-d16-rdimm_16mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg index e074689c..f469e6fe 100644 --- a/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-rdimm_2mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/kgpe-d16-rdimm_2mb/warn.txt b/config/coreboot/kgpe-d16-rdimm_2mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kgpe-d16-rdimm_2mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg index 1e128ae9..298d1f20 100644 --- a/config/coreboot/kgpe-d16-udimm_16mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/kgpe-d16-udimm_16mb/warn.txt b/config/coreboot/kgpe-d16-udimm_16mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kgpe-d16-udimm_16mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv diff --git a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg index 1e128ae9..298d1f20 100644 --- a/config/coreboot/kgpe-d16-udimm_2mb/target.cfg +++ b/config/coreboot/kgpe-d16-udimm_2mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/kgpe-d16-udimm_2mb/warn.txt b/config/coreboot/kgpe-d16-udimm_2mb/warn.txt new file mode 100644 index 00000000..639ecd41 --- /dev/null +++ b/config/coreboot/kgpe-d16-udimm_2mb/warn.txt @@ -0,0 +1 @@ +raminit has always been unreliable on this board; ymmv From 5218bfb0c81e9b9b6fd7fff69c8816cb69abbf78 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 14:49:14 +0100 Subject: [PATCH 0035/1319] declare gm45 thinkpads stable for release Signed-off-by: Leah Rowe --- config/coreboot/r400_16mb/target.cfg | 2 +- config/coreboot/r400_4mb/target.cfg | 2 +- config/coreboot/r400_8mb/target.cfg | 2 +- config/coreboot/r500_4mb/target.cfg | 2 +- config/coreboot/t400_16mb/target.cfg | 2 +- config/coreboot/t400_4mb/target.cfg | 2 +- config/coreboot/t400_8mb/target.cfg | 2 +- config/coreboot/t500_16mb/target.cfg | 2 +- config/coreboot/t500_4mb/target.cfg | 2 +- config/coreboot/t500_8mb/target.cfg | 2 +- config/coreboot/w500_16mb/target.cfg | 2 +- config/coreboot/w500_4mb/target.cfg | 2 +- config/coreboot/w500_8mb/target.cfg | 2 +- config/coreboot/x200_16mb/target.cfg | 2 +- config/coreboot/x200_4mb/target.cfg | 2 +- config/coreboot/x200_8mb/target.cfg | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/config/coreboot/r400_16mb/target.cfg b/config/coreboot/r400_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/r400_16mb/target.cfg +++ b/config/coreboot/r400_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/r400_4mb/target.cfg b/config/coreboot/r400_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/r400_4mb/target.cfg +++ b/config/coreboot/r400_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/r400_8mb/target.cfg b/config/coreboot/r400_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/r400_8mb/target.cfg +++ b/config/coreboot/r400_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/r500_4mb/target.cfg b/config/coreboot/r500_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/r500_4mb/target.cfg +++ b/config/coreboot/r500_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t400_16mb/target.cfg b/config/coreboot/t400_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t400_16mb/target.cfg +++ b/config/coreboot/t400_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t400_4mb/target.cfg b/config/coreboot/t400_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t400_4mb/target.cfg +++ b/config/coreboot/t400_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t400_8mb/target.cfg b/config/coreboot/t400_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t400_8mb/target.cfg +++ b/config/coreboot/t400_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t500_16mb/target.cfg b/config/coreboot/t500_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t500_16mb/target.cfg +++ b/config/coreboot/t500_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t500_4mb/target.cfg b/config/coreboot/t500_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t500_4mb/target.cfg +++ b/config/coreboot/t500_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t500_8mb/target.cfg b/config/coreboot/t500_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t500_8mb/target.cfg +++ b/config/coreboot/t500_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/w500_16mb/target.cfg b/config/coreboot/w500_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/w500_16mb/target.cfg +++ b/config/coreboot/w500_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/w500_4mb/target.cfg b/config/coreboot/w500_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/w500_4mb/target.cfg +++ b/config/coreboot/w500_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/w500_8mb/target.cfg b/config/coreboot/w500_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/w500_8mb/target.cfg +++ b/config/coreboot/w500_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x200_16mb/target.cfg b/config/coreboot/x200_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x200_16mb/target.cfg +++ b/config/coreboot/x200_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x200_4mb/target.cfg b/config/coreboot/x200_4mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x200_4mb/target.cfg +++ b/config/coreboot/x200_4mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x200_8mb/target.cfg b/config/coreboot/x200_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x200_8mb/target.cfg +++ b/config/coreboot/x200_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" From 1fd9ba9ae0fe50a57c8bada531850af9ad22dc1c Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 14:51:59 +0100 Subject: [PATCH 0036/1319] declare ivy/sandy thinkpads stable for release Signed-off-by: Leah Rowe --- config/coreboot/t420_8mb/target.cfg | 2 +- config/coreboot/t420s_8mb/target.cfg | 2 +- config/coreboot/t430_12mb/target.cfg | 2 +- config/coreboot/t520_8mb/target.cfg | 2 +- config/coreboot/t530_12mb/target.cfg | 2 +- config/coreboot/w530_12mb/target.cfg | 2 +- config/coreboot/x220_8mb/target.cfg | 2 +- config/coreboot/x230_16mb/target.cfg | 2 +- config/coreboot/x230t_16mb/target.cfg | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/config/coreboot/t420_8mb/target.cfg b/config/coreboot/t420_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t420_8mb/target.cfg +++ b/config/coreboot/t420_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t420s_8mb/target.cfg b/config/coreboot/t420s_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t420s_8mb/target.cfg +++ b/config/coreboot/t420s_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t430_12mb/target.cfg b/config/coreboot/t430_12mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t430_12mb/target.cfg +++ b/config/coreboot/t430_12mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t520_8mb/target.cfg b/config/coreboot/t520_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t520_8mb/target.cfg +++ b/config/coreboot/t520_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/t530_12mb/target.cfg b/config/coreboot/t530_12mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/t530_12mb/target.cfg +++ b/config/coreboot/t530_12mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/w530_12mb/target.cfg b/config/coreboot/w530_12mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/w530_12mb/target.cfg +++ b/config/coreboot/w530_12mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x220_8mb/target.cfg b/config/coreboot/x220_8mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x220_8mb/target.cfg +++ b/config/coreboot/x220_8mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x230_16mb/target.cfg b/config/coreboot/x230_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x230_16mb/target.cfg +++ b/config/coreboot/x230_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" diff --git a/config/coreboot/x230t_16mb/target.cfg b/config/coreboot/x230t_16mb/target.cfg index 6c267eca..f16a94a4 100644 --- a/config/coreboot/x230t_16mb/target.cfg +++ b/config/coreboot/x230t_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" From e761922542264629d7035735ea7b3e31f7a9ee74 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 15:01:31 +0100 Subject: [PATCH 0037/1319] Set status=unstable on dell latitudes also warn about issues, in a warn.txt file for each. Signed-off-by: Leah Rowe --- config/coreboot/e5420_6mb/target.cfg | 2 +- config/coreboot/e5420_6mb/warn.txt | 1 + config/coreboot/e5520_6mb/target.cfg | 2 +- config/coreboot/e5520_6mb/warn.txt | 1 + config/coreboot/e5530_12mb/target.cfg | 2 +- config/coreboot/e5530_12mb/warn.txt | 1 + config/coreboot/e6400_4mb/warn.txt | 4 +++- config/coreboot/e6400nvidia_4mb/warn.txt | 5 +++-- config/coreboot/e6420_10mb/target.cfg | 2 +- config/coreboot/e6420_10mb/warn.txt | 1 + config/coreboot/e6430_12mb/target.cfg | 2 +- config/coreboot/e6430_12mb/warn.txt | 1 + config/coreboot/e6520_10mb/target.cfg | 2 +- config/coreboot/e6520_10mb/warn.txt | 1 + config/coreboot/e6530_12mb/target.cfg | 2 +- config/coreboot/e6530_12mb/warn.txt | 1 + 16 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 config/coreboot/e5420_6mb/warn.txt create mode 100644 config/coreboot/e5520_6mb/warn.txt create mode 100644 config/coreboot/e5530_12mb/warn.txt create mode 100644 config/coreboot/e6420_10mb/warn.txt create mode 100644 config/coreboot/e6430_12mb/warn.txt create mode 100644 config/coreboot/e6520_10mb/warn.txt create mode 100644 config/coreboot/e6530_12mb/warn.txt diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index 70be0ab9..153d4d2d 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -9,4 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" -status="untested" +status="unstable" diff --git a/config/coreboot/e5420_6mb/warn.txt b/config/coreboot/e5420_6mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e5420_6mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index 70be0ab9..153d4d2d 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -9,4 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" -status="untested" +status="unstable" diff --git a/config/coreboot/e5520_6mb/warn.txt b/config/coreboot/e5520_6mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e5520_6mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index e2375ad4..e48db5e5 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/e5530_12mb/warn.txt b/config/coreboot/e5530_12mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e5530_12mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6400_4mb/warn.txt b/config/coreboot/e6400_4mb/warn.txt index 95b8ebbf..30e61da5 100644 --- a/config/coreboot/e6400_4mb/warn.txt +++ b/config/coreboot/e6400_4mb/warn.txt @@ -1 +1,3 @@ -broken s3 resume/suspend, no battery indicator/status +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. + +If you have the nvidia gpu variant, please use e6400nvidia_4mb instead. diff --git a/config/coreboot/e6400nvidia_4mb/warn.txt b/config/coreboot/e6400nvidia_4mb/warn.txt index a604fc87..5b2e4a00 100644 --- a/config/coreboot/e6400nvidia_4mb/warn.txt +++ b/config/coreboot/e6400nvidia_4mb/warn.txt @@ -1,2 +1,3 @@ -broken s3 resume/suspend, no battery indicator/status. -nouveau crashes xorg under linux (can use nomodeset) +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. + +Nvidia GPU on this model doesn't work when you try xorg; xorg will hang. Use "nomodeset" under Linux, when booting. On BSD, the nv driver works ok but can get very slow-slideshow-y when dragging windows, yet rendered video will usually run smooth; use a tiling window manager on BSD systems, or again use software rendering. diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index 70be0ab9..153d4d2d 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -9,4 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" -status="untested" +status="unstable" diff --git a/config/coreboot/e6420_10mb/warn.txt b/config/coreboot/e6420_10mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e6420_10mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index e2375ad4..e48db5e5 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/e6430_12mb/warn.txt b/config/coreboot/e6430_12mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e6430_12mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index 70be0ab9..153d4d2d 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -9,4 +9,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" microcode_required="n" -status="untested" +status="unstable" diff --git a/config/coreboot/e6520_10mb/warn.txt b/config/coreboot/e6520_10mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e6520_10mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index e2375ad4..e48db5e5 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/e6530_12mb/warn.txt b/config/coreboot/e6530_12mb/warn.txt new file mode 100644 index 00000000..57d05e6a --- /dev/null +++ b/config/coreboot/e6530_12mb/warn.txt @@ -0,0 +1 @@ +Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. From 3ace925e916a1277f6f4ade03282d34d7968d6f1 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 15:25:43 +0100 Subject: [PATCH 0038/1319] update more board statuses before release what's left to properly test are pineview/x4x/i945 and some of the ivy/sandy elitebooks/hp workstations Signed-off-by: Leah Rowe --- config/coreboot/gru_bob/target.cfg | 2 +- config/coreboot/gru_bob/warn.txt | 1 + config/coreboot/gru_kevin/target.cfg | 2 +- config/coreboot/gru_kevin/warn.txt | 1 + config/coreboot/kfsn4-dre_1mb/target.cfg | 2 +- config/coreboot/kfsn4-dre_2mb/target.cfg | 2 +- config/coreboot/qemu_arm64_12mb/target.cfg | 2 +- config/coreboot/qemu_x86_12mb/target.cfg | 2 +- config/coreboot/t1650_12mb/target.cfg | 2 +- 9 files changed, 9 insertions(+), 7 deletions(-) create mode 100644 config/coreboot/gru_bob/warn.txt create mode 100644 config/coreboot/gru_kevin/warn.txt diff --git a/config/coreboot/gru_bob/target.cfg b/config/coreboot/gru_bob/target.cfg index 3ff37611..c6ad9102 100644 --- a/config/coreboot/gru_bob/target.cfg +++ b/config/coreboot/gru_bob/target.cfg @@ -1,4 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" -status="untested" +status="unstable" diff --git a/config/coreboot/gru_bob/warn.txt b/config/coreboot/gru_bob/warn.txt new file mode 100644 index 00000000..1dcc4e7d --- /dev/null +++ b/config/coreboot/gru_bob/warn.txt @@ -0,0 +1 @@ +Incomplete UEFI implementation but should boot most distros fine. Debian Bookworm installed and the first 1GB or so of the partition got corrupted. Leave the first 2GB or so unpartitioned, when installing any distro. diff --git a/config/coreboot/gru_kevin/target.cfg b/config/coreboot/gru_kevin/target.cfg index 3ff37611..c6ad9102 100644 --- a/config/coreboot/gru_kevin/target.cfg +++ b/config/coreboot/gru_kevin/target.cfg @@ -1,4 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" -status="untested" +status="unstable" diff --git a/config/coreboot/gru_kevin/warn.txt b/config/coreboot/gru_kevin/warn.txt new file mode 100644 index 00000000..1dcc4e7d --- /dev/null +++ b/config/coreboot/gru_kevin/warn.txt @@ -0,0 +1 @@ +Incomplete UEFI implementation but should boot most distros fine. Debian Bookworm installed and the first 1GB or so of the partition got corrupted. Leave the first 2GB or so unpartitioned, when installing any distro. diff --git a/config/coreboot/kfsn4-dre_1mb/target.cfg b/config/coreboot/kfsn4-dre_1mb/target.cfg index 15f35ccd..e5b66b38 100644 --- a/config/coreboot/kfsn4-dre_1mb/target.cfg +++ b/config/coreboot/kfsn4-dre_1mb/target.cfg @@ -4,4 +4,4 @@ payload_seabios="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="stable" diff --git a/config/coreboot/kfsn4-dre_2mb/target.cfg b/config/coreboot/kfsn4-dre_2mb/target.cfg index e65a5e9c..8f4e6a81 100644 --- a/config/coreboot/kfsn4-dre_2mb/target.cfg +++ b/config/coreboot/kfsn4-dre_2mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" xlang="c" grub_timeout=10 -status="untested" +status="stable" diff --git a/config/coreboot/qemu_arm64_12mb/target.cfg b/config/coreboot/qemu_arm64_12mb/target.cfg index 3ff37611..86283f7a 100644 --- a/config/coreboot/qemu_arm64_12mb/target.cfg +++ b/config/coreboot/qemu_arm64_12mb/target.cfg @@ -1,4 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" -status="untested" +status="stable" diff --git a/config/coreboot/qemu_x86_12mb/target.cfg b/config/coreboot/qemu_x86_12mb/target.cfg index d92fda66..dba2c61e 100644 --- a/config/coreboot/qemu_x86_12mb/target.cfg +++ b/config/coreboot/qemu_x86_12mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="both" -status="untested" +status="stable" diff --git a/config/coreboot/t1650_12mb/target.cfg b/config/coreboot/t1650_12mb/target.cfg index 6333672b..b0abee49 100644 --- a/config/coreboot/t1650_12mb/target.cfg +++ b/config/coreboot/t1650_12mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="stable" From ad7e3966b9884dc3a5cff116d33cc27b0d775d27 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 15:45:49 +0100 Subject: [PATCH 0039/1319] update 9020 sff/mt release status Signed-off-by: Leah Rowe --- config/coreboot/dell9020mt-nri_12mb/target.cfg | 2 +- config/coreboot/dell9020mt-nri_12mb/warn.txt | 1 + config/coreboot/dell9020mt_12mb/target.cfg | 2 +- config/coreboot/dell9020mt_12mb/warn.txt | 1 + config/coreboot/dell9020mtbmrc_12mb/target.cfg | 2 +- config/coreboot/dell9020mtbmrc_12mb/warn.txt | 1 + config/coreboot/dell9020sff-nri_12mb/target.cfg | 2 +- config/coreboot/dell9020sff-nri_12mb/warn.txt | 1 + config/coreboot/dell9020sff_12mb/target.cfg | 2 +- config/coreboot/dell9020sff_12mb/warn.txt | 1 + config/coreboot/dell9020sffbmrc_12mb/target.cfg | 2 +- config/coreboot/dell9020sffbmrc_12mb/warn.txt | 1 + 12 files changed, 12 insertions(+), 6 deletions(-) create mode 100644 config/coreboot/dell9020mt-nri_12mb/warn.txt create mode 100644 config/coreboot/dell9020mt_12mb/warn.txt create mode 100644 config/coreboot/dell9020mtbmrc_12mb/warn.txt create mode 100644 config/coreboot/dell9020sff-nri_12mb/warn.txt create mode 100644 config/coreboot/dell9020sff_12mb/warn.txt create mode 100644 config/coreboot/dell9020sffbmrc_12mb/warn.txt diff --git a/config/coreboot/dell9020mt-nri_12mb/target.cfg b/config/coreboot/dell9020mt-nri_12mb/target.cfg index bc4053d4..bb76392a 100644 --- a/config/coreboot/dell9020mt-nri_12mb/target.cfg +++ b/config/coreboot/dell9020mt-nri_12mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020mt-nri_12mb/warn.txt b/config/coreboot/dell9020mt-nri_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020mt-nri_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index a3acd5fb..ac0b1792 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020mt_12mb/warn.txt b/config/coreboot/dell9020mt_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020mt_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg index a3acd5fb..ac0b1792 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020mtbmrc_12mb/warn.txt b/config/coreboot/dell9020mtbmrc_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020mtbmrc_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable diff --git a/config/coreboot/dell9020sff-nri_12mb/target.cfg b/config/coreboot/dell9020sff-nri_12mb/target.cfg index bc4053d4..bb76392a 100644 --- a/config/coreboot/dell9020sff-nri_12mb/target.cfg +++ b/config/coreboot/dell9020sff-nri_12mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020sff-nri_12mb/warn.txt b/config/coreboot/dell9020sff-nri_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020sff-nri_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index a3acd5fb..ac0b1792 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020sff_12mb/warn.txt b/config/coreboot/dell9020sff_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020sff_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg index a3acd5fb..ac0b1792 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="unstable" diff --git a/config/coreboot/dell9020sffbmrc_12mb/warn.txt b/config/coreboot/dell9020sffbmrc_12mb/warn.txt new file mode 100644 index 00000000..fe1aa7f9 --- /dev/null +++ b/config/coreboot/dell9020sffbmrc_12mb/warn.txt @@ -0,0 +1 @@ +Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable From 6c4f07b35071923b4b7cf66f9064108a67d28855 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 16:46:31 +0100 Subject: [PATCH 0040/1319] allow disabling status checks during builds export LBMK_STATUS=n if not set, the status checks and confirmation dialogs persist. if set to y they persist. if you set it to n, all checks are disabled, so e.g.: ./build roms all this would once again build all targets, regardless of status. this is if you want the old behaviour. Signed-off-by: Leah Rowe --- include/err.sh | 9 ++++++++- script/build/roms | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/err.sh b/include/err.sh index 097d4230..0b1c3e70 100755 --- a/include/err.sh +++ b/include/err.sh @@ -5,7 +5,7 @@ export LC_COLLATE=C export LC_ALL=C version=""; versiondate=""; projectname=""; _nogit="" -err="err_"; tmpdir=""; release_type="" +err="err_"; tmpdir=""; release_type=""; lbmk_status="" # if "y": a coreboot target won't be built if target.cfg says release="n" # (this is used to exclude certain build targets from releases) @@ -26,6 +26,13 @@ set | grep LBMK_VERSION_TYPE 1>/dev/null 2>/dev/null && \ [ "$release_type" = "unstable" ] || release_type="" export LBMK_VERSION_TYPE="$release_type" +# if set to n via export, status checks will be skipped during +# all builds, and all targets will be built regardless of status. +# this replicates the old behaviour of lbmk, prior to the checks. +set | grep LBMK_STATUS 1>/dev/null 2>/dev/null && lbmk_status="$LBMK_STATUS" +[ "$lbmk_status" = "y" ] || [ "$lbmk_status" = "n" ] || lbmk_status="y" +export LBMK_STATUS="$lbmk_status" + tmpdir_was_set="y" set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" if [ "${tmpdir_was_set}" = "y" ]; then diff --git a/script/build/roms b/script/build/roms index ea7ef62c..08b9c92a 100755 --- a/script/build/roms +++ b/script/build/roms @@ -190,7 +190,7 @@ skip_board() return 1 if [ "$lbmk_release" != "y" ] && [ "$status" != "stable" ] && \ - [ "$status" != "$release_type" ]; then + [ "$status" != "$release_type" ] && [ "$lbmk_status" = "y" ]; then if [ -f "$targetdir/warn.txt" ]; then printf "Regarding board '%s' (status '%s'):\n" \ "$board" "$status" From f22305fbf585a4d16109ad44b24739228ae5b503 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 17:01:38 +0100 Subject: [PATCH 0041/1319] update macbook21/x60/t60 status Signed-off-by: Leah Rowe --- config/coreboot/macbook11/target.cfg | 2 +- config/coreboot/macbook11/warn.txt | 1 + config/coreboot/macbook11_16mb/target.cfg | 2 +- config/coreboot/macbook11_16mb/warn.txt | 1 + config/coreboot/macbook21/target.cfg | 2 +- config/coreboot/macbook21/warn.txt | 1 + config/coreboot/macbook21_16mb/target.cfg | 2 +- config/coreboot/macbook21_16mb/warn.txt | 1 + config/coreboot/t60_16mb_intelgpu/target.cfg | 2 +- config/coreboot/t60_16mb_intelgpu/warn.txt | 1 + config/coreboot/t60_intelgpu/target.cfg | 2 +- config/coreboot/t60_intelgpu/warn.txt | 1 + config/coreboot/x60/target.cfg | 2 +- config/coreboot/x60/warn.txt | 1 + config/coreboot/x60_16mb/target.cfg | 2 +- config/coreboot/x60_16mb/warn.txt | 1 + 16 files changed, 16 insertions(+), 8 deletions(-) create mode 100644 config/coreboot/macbook11/warn.txt create mode 100644 config/coreboot/macbook11_16mb/warn.txt create mode 100644 config/coreboot/macbook21/warn.txt create mode 100644 config/coreboot/macbook21_16mb/warn.txt create mode 100644 config/coreboot/t60_16mb_intelgpu/warn.txt create mode 100644 config/coreboot/t60_intelgpu/warn.txt create mode 100644 config/coreboot/x60/warn.txt create mode 100644 config/coreboot/x60_16mb/warn.txt diff --git a/config/coreboot/macbook11/target.cfg b/config/coreboot/macbook11/target.cfg index 404e0129..3c06a458 100644 --- a/config/coreboot/macbook11/target.cfg +++ b/config/coreboot/macbook11/target.cfg @@ -4,4 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/macbook11/warn.txt b/config/coreboot/macbook11/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/macbook11/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook11_16mb/target.cfg b/config/coreboot/macbook11_16mb/target.cfg index 404e0129..3c06a458 100644 --- a/config/coreboot/macbook11_16mb/target.cfg +++ b/config/coreboot/macbook11_16mb/target.cfg @@ -4,4 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/macbook11_16mb/warn.txt b/config/coreboot/macbook11_16mb/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/macbook11_16mb/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook21/target.cfg b/config/coreboot/macbook21/target.cfg index e9eab4e9..b4feb4de 100644 --- a/config/coreboot/macbook21/target.cfg +++ b/config/coreboot/macbook21/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/macbook21/warn.txt b/config/coreboot/macbook21/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/macbook21/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook21_16mb/target.cfg b/config/coreboot/macbook21_16mb/target.cfg index e9eab4e9..b4feb4de 100644 --- a/config/coreboot/macbook21_16mb/target.cfg +++ b/config/coreboot/macbook21_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" +status="unstable" diff --git a/config/coreboot/macbook21_16mb/warn.txt b/config/coreboot/macbook21_16mb/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/macbook21_16mb/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/t60_16mb_intelgpu/target.cfg b/config/coreboot/t60_16mb_intelgpu/target.cfg index 6a6d833a..004ba1b0 100644 --- a/config/coreboot/t60_16mb_intelgpu/target.cfg +++ b/config/coreboot/t60_16mb_intelgpu/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="untested" +status="unstable" diff --git a/config/coreboot/t60_16mb_intelgpu/warn.txt b/config/coreboot/t60_16mb_intelgpu/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/t60_16mb_intelgpu/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/t60_intelgpu/target.cfg b/config/coreboot/t60_intelgpu/target.cfg index 6a6d833a..004ba1b0 100644 --- a/config/coreboot/t60_intelgpu/target.cfg +++ b/config/coreboot/t60_intelgpu/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="untested" +status="unstable" diff --git a/config/coreboot/t60_intelgpu/warn.txt b/config/coreboot/t60_intelgpu/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/t60_intelgpu/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/x60/target.cfg b/config/coreboot/x60/target.cfg index 6a6d833a..004ba1b0 100644 --- a/config/coreboot/x60/target.cfg +++ b/config/coreboot/x60/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="untested" +status="unstable" diff --git a/config/coreboot/x60/warn.txt b/config/coreboot/x60/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/x60/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/x60_16mb/target.cfg b/config/coreboot/x60_16mb/target.cfg index 6a6d833a..004ba1b0 100644 --- a/config/coreboot/x60_16mb/target.cfg +++ b/config/coreboot/x60_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="untested" +status="unstable" diff --git a/config/coreboot/x60_16mb/warn.txt b/config/coreboot/x60_16mb/warn.txt new file mode 100644 index 00000000..5bffd9da --- /dev/null +++ b/config/coreboot/x60_16mb/warn.txt @@ -0,0 +1 @@ +Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. From e614f90638ffda7dd9cd2634d856aa40e96d2010 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 18:50:49 +0100 Subject: [PATCH 0042/1319] build/roms: tell the user how to ignore status Signed-off-by: Leah Rowe --- script/build/roms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/script/build/roms b/script/build/roms index 08b9c92a..b14213b9 100755 --- a/script/build/roms +++ b/script/build/roms @@ -197,6 +197,8 @@ skip_board() cat -u "$targetdir/warn.txt" || \ $err "!cat $targetdir/warn.txt" fi + printf "\nTo disable this dialog when building, do:\n" + printf "export LBMK_STATUS=n\n\n" while true; do printf "Board %s has status '%s'. Skip? [y/n]" \ "$board" "$status" From 714d4b3ed3aba68421128f4558f6a493c96a014a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 27 Apr 2024 22:42:12 +0100 Subject: [PATCH 0043/1319] update/release: disable status checking just to ensure that nothing goes wrong. we don't rely on the status variable for releases, because there is another variable, release, that target.cfg files declare, e.g. release="n" release="y" you can just omit the variable, because it defaults to y, so you only need declare it when it needs to be "n" Signed-off-by: Leah Rowe --- script/update/release | 1 + 1 file changed, 1 insertion(+) diff --git a/script/update/release b/script/update/release index e8eff300..d7b7d108 100755 --- a/script/update/release +++ b/script/update/release @@ -10,6 +10,7 @@ set -u -e eval "$(setvars "" vdir relname src_dirname srcdir _xm target romdir mode)" export LBMK_RELEASE="y" +export LBMK_STATUS="n" main() { From d923d31451673651ba39eb634e733d38976f20a8 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 02:02:15 +0100 Subject: [PATCH 0044/1319] use mirrorservice.org for iasl downloads github is unreliable. i host these files myself. coreboot uses intel.com again now in the latest revisions, and intel broke it before. i'm going to start backing up the acpica releases onto my rsync server from now on, and keep patching coreboot to use my files. Signed-off-by: Leah Rowe --- ...mirrorservice.org-for-iasl-downloads.patch | 28 +++++++++++++++++++ ...mirrorservice.org-for-iasl-downloads.patch | 28 +++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch create mode 100644 config/coreboot/i945/patches/0023-use-mirrorservice.org-for-iasl-downloads.patch diff --git a/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch b/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch new file mode 100644 index 00000000..f9981abd --- /dev/null +++ b/config/coreboot/haswell/patches/0026-use-mirrorservice.org-for-iasl-downloads.patch @@ -0,0 +1,28 @@ +From ed30cca924fa576dd5b69ce4a348b5a1466a8db1 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 28 Apr 2024 01:57:46 +0100 +Subject: [PATCH 1/1] use mirrorservice.org for iasl downloads + +github is unreliable. i mirror these files myself. + +Signed-off-by: Leah Rowe +--- + util/crossgcc/buildgcc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 6ae201239d..a8433a25e5 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" + MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" + GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" + BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" +-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" ++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" + CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + diff --git a/config/coreboot/i945/patches/0023-use-mirrorservice.org-for-iasl-downloads.patch b/config/coreboot/i945/patches/0023-use-mirrorservice.org-for-iasl-downloads.patch new file mode 100644 index 00000000..012d8dab --- /dev/null +++ b/config/coreboot/i945/patches/0023-use-mirrorservice.org-for-iasl-downloads.patch @@ -0,0 +1,28 @@ +From 781ab8407d08a5fdb7fbc2c239e684def7380b15 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sun, 28 Apr 2024 01:59:30 +0100 +Subject: [PATCH 1/1] use mirrorservice.org for iasl downloads + +github is unreliable. i mirror these files myself. + +Signed-off-by: Leah Rowe +--- + util/crossgcc/buildgcc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 0faea86894..6779a20425 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -71,7 +71,7 @@ MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr" + MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc" + GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}" + BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils" +-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags" ++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica" + # CLANG toolchain archive locations + LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" + CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}" +-- +2.39.2 + From a5c7cc1a0be949077d3e68fc2228ca9e1e02c5b4 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 03:27:54 +0100 Subject: [PATCH 0045/1319] fix target.cfg files on dell latitudes some latitudes still used the old style for variables in target.cfg, specifically arch="x86_64" - lbmk used to then check that on a big if/else and translate it to the correct target name for crossgcc, e.g. i386-elf, arm-eabi now it just puts the arch directly, in a new variable: xarch change arch="x86_64" to xarch="i386-elf" in these files. also remove a few obsolete variables. should build now. Signed-off-by: Leah Rowe --- config/coreboot/e5420_6mb/target.cfg | 4 +--- config/coreboot/e5520_6mb/target.cfg | 4 +--- config/coreboot/e6420_10mb/target.cfg | 4 +--- config/coreboot/e6520_10mb/target.cfg | 4 +--- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index 153d4d2d..e48db5e5 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -1,6 +1,5 @@ tree="default" -romtype="normal" -arch="x86_64" +xarch="i386-elf" payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" @@ -8,5 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -microcode_required="n" status="unstable" diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index 153d4d2d..e48db5e5 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -1,6 +1,5 @@ tree="default" -romtype="normal" -arch="x86_64" +xarch="i386-elf" payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" @@ -8,5 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -microcode_required="n" status="unstable" diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index 153d4d2d..e48db5e5 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -1,6 +1,5 @@ tree="default" -romtype="normal" -arch="x86_64" +xarch="i386-elf" payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" @@ -8,5 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -microcode_required="n" status="unstable" diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index 153d4d2d..e48db5e5 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -1,6 +1,5 @@ tree="default" -romtype="normal" -arch="x86_64" +xarch="i386-elf" payload_grub="n" payload_grub_withseabios="n" payload_seabios="y" @@ -8,5 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -microcode_required="n" status="unstable" From 71f8e6530a9c33748a26a2c4f68f84a3ec6badbd Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 17:24:41 +0100 Subject: [PATCH 0046/1319] eDP configs (x230/x220): don't release set to release="n" for now until the eDP targets are fixed. the regular non-eDP targets are stable, and will be released. Signed-off-by: Leah Rowe --- config/coreboot/x220edp_8mb/target.cfg | 1 + config/coreboot/x230edp_12mb/target.cfg | 1 + 2 files changed, 2 insertions(+) diff --git a/config/coreboot/x220edp_8mb/target.cfg b/config/coreboot/x220edp_8mb/target.cfg index 529581bd..cd477e6f 100644 --- a/config/coreboot/x220edp_8mb/target.cfg +++ b/config/coreboot/x220edp_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" status="broken" # TODO: VCC3P patch +release="n" diff --git a/config/coreboot/x230edp_12mb/target.cfg b/config/coreboot/x230edp_12mb/target.cfg index 529581bd..cd477e6f 100644 --- a/config/coreboot/x230edp_12mb/target.cfg +++ b/config/coreboot/x230edp_12mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" status="broken" # TODO: VCC3P patch +release="n" From 55204dc4449456c6a11ed19f530b7673143450a5 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 17:31:16 +0100 Subject: [PATCH 0047/1319] option.sh: don't use nproc (not portable) export LBMK_THREADS=x where x is an integer. this is already supported for setting the number of build threads, but if not set it uses nproc. openbsd doesn't have nproc. default to 1 thread. now you MUST set threads. e.g. in linux do: export LBMK_THREADS=$(nproc) preliminary work is being done to make lbmk run on openbsd! Signed-off-by: Leah Rowe --- include/option.sh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/option.sh b/include/option.sh index 8fc80aaa..eb792775 100755 --- a/include/option.sh +++ b/include/option.sh @@ -23,13 +23,14 @@ eval "$(setvars "" CONFIG_BOARD_DELL_E6400 CONFIG_HAVE_MRC CONFIG_HAVE_ME_BIN \ CONFIG_HAVE_REFCODE_BLOB CONFIG_REFCODE_BLOB_FILE)" threads= -set | grep LBMK_THREADS 1>/dev/null 2>/dev/null || threads=$(nproc) || : -[ -z "$threads" ] && threads=$LBMK_THREADS -[ -z "$threads" ] && threads=1 # LBMK_THREADS not set, and nproc failed +set | grep LBMK_THREADS 1>/dev/null 2>/dev/null && threads="$LBMK_THREADS" +[ -z "$threads" ] && threads=1 expr "X$threads" : "X-\{0,1\}[0123456789][0123456789]*$" \ 1>/dev/null 2>/dev/null || threads=1 # user specified a non-integer +export LBMK_THREADS="$threads" + items() { rval=1 From a88a8281df1d3688bb772578a3dd7d7cc1af1091 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 19:28:02 +0100 Subject: [PATCH 0048/1319] update/trees: simplified defconfig copying Signed-off-by: Leah Rowe --- script/update/trees | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/script/update/trees b/script/update/trees index ac5743be..af80d99a 100755 --- a/script/update/trees +++ b/script/update/trees @@ -199,15 +199,13 @@ handle_makefile() run_make_command || $err "handle_makefile $codedir: no makefile!" - if [ -e "${codedir}/.git" ] && [ "$project" = "u-boot" ] && \ - [ "$mode" = "distclean" ]; then - x_ git -C "$codedir" clean -fdx - elif [ "$mode" = "oldconfig" ] || [ "$mode" = "olddefconfig" ] || \ - [ "$mode" = "menuconfig" ] || [ "$mode" = "nconfig" ]; then - x_ cp "${codedir}/.config" "$config" - elif [ "$mode" = "savedefconfig" ]; then - x_ cp "${codedir}/defconfig" "$config" - fi + _copy=".config" + [ "$mode" = "savedefconfig" ] && _copy="defconfig" + [ "${mode%config}" = "$mode" ] || x_ cp "$codedir/$_copy" "$config" + + [ -e "${codedir}/.git" ] && [ "$project" = "u-boot" ] && \ + [ "$mode" = "distclean" ] && \ + x_ git -C "$codedir" clean -fdx; return 0 } run_make_command() From 515185a7f5f4ec75392c33737ddb9160fa28070e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 19:56:25 +0100 Subject: [PATCH 0049/1319] build/roms: support SeaGRUB *with menu enabled* This is useful on desktops, where you want GRUB to automatically start, but you still want access to the GRUB menu, in the case where you rely on SeaBIOS to execute the VGA ROM inside your graphics card. Signed-off-by: Leah Rowe --- script/build/roms | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/script/build/roms b/script/build/roms index b14213b9..853bbea6 100755 --- a/script/build/roms +++ b/script/build/roms @@ -398,8 +398,10 @@ build_grub_roms() newrom="${romdir}/${payload1}_${board}_" && \ newrom="${newrom}${initmode}_${keymap}.rom" x_ moverom "${tmpgrubrom}" "${newrom}" - [ "${payload_seabios_grubonly}" = "y" ] && \ + if [ "${payload_seabios_grubonly}" = "y" ]; then + mkSeagrubRom "${tmpgrubrom}" "${newrom}" mkSeabiosGrubonlyRom "${tmpgrubrom}" "${newrom}" + fi x_ rm -f "${tmpgrubrom}" done } @@ -428,7 +430,7 @@ mkSeabiosRom() { } # SeaGRUB configuration -mkSeabiosGrubonlyRom() +mkSeagrubRom() { _grubrom="${1}" _newrom="${2}" @@ -441,7 +443,17 @@ mkSeabiosGrubonlyRom() add -f "${tmpbootorder}" -n bootorder -t raw x_ rm -f "${tmpbootorder}" + x_ moverom "${_grubrom}" "${_newrom%.rom}_grubfirst.rom" +} + +# SeaGRUB, and disable the SeaBIOS menu (grub only) +mkSeabiosGrubonlyRom() +{ + _grubrom="${1}" + _newrom="${2}" + x_ "${cbfstool}" "${_grubrom}" add-int -i 0 -n etc/show-boot-menu + x_ moverom "${_grubrom}" "${_newrom%.rom}_grubonly.rom" } From 230f68fd8f9c4178051635f52df9ccf9700cd30d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 20:21:35 +0100 Subject: [PATCH 0050/1319] build/roms: simplified seagrub handling Signed-off-by: Leah Rowe --- config/grub/bootorder | 1 + script/build/roms | 36 ++++++------------------------------ 2 files changed, 7 insertions(+), 30 deletions(-) create mode 100644 config/grub/bootorder diff --git a/config/grub/bootorder b/config/grub/bootorder new file mode 100644 index 00000000..b33e1295 --- /dev/null +++ b/config/grub/bootorder @@ -0,0 +1 @@ +/rom@img/grub2 diff --git a/script/build/roms b/script/build/roms index 853bbea6..1c427b69 100755 --- a/script/build/roms +++ b/script/build/roms @@ -399,8 +399,12 @@ build_grub_roms() newrom="${newrom}${initmode}_${keymap}.rom" x_ moverom "${tmpgrubrom}" "${newrom}" if [ "${payload_seabios_grubonly}" = "y" ]; then - mkSeagrubRom "${tmpgrubrom}" "${newrom}" - mkSeabiosGrubonlyRom "${tmpgrubrom}" "${newrom}" + x_ "$cbfstool" "$tmpgrubrom" add \ + -f "config/grub/bootorder" -n bootorder -t raw + x_ moverom "$tmpgrubrom" "${newrom%.rom}_grubfirst.rom" + x_ "$cbfstool" "$tmpgrubrom" add-int -i 0 \ + -n etc/show-boot-menu + x_ moverom "$tmpgrubrom" "${newrom%.rom}_grubonly.rom" fi x_ rm -f "${tmpgrubrom}" done @@ -429,34 +433,6 @@ mkSeabiosRom() { printf "%s\n" "${tmprom}" } -# SeaGRUB configuration -mkSeagrubRom() -{ - _grubrom="${1}" - _newrom="${2}" - - tmpbootorder=$(mktemp -t coreboot_rom.XXXXXXXXXX) - - # only load grub, by inserting a custom bootorder file - printf "/rom@img/grub2\n" > "$tmpbootorder" || $err "printf bootorder" - x_ "${cbfstool}" "${_grubrom}" \ - add -f "${tmpbootorder}" -n bootorder -t raw - x_ rm -f "${tmpbootorder}" - - x_ moverom "${_grubrom}" "${_newrom%.rom}_grubfirst.rom" -} - -# SeaGRUB, and disable the SeaBIOS menu (grub only) -mkSeabiosGrubonlyRom() -{ - _grubrom="${1}" - _newrom="${2}" - - x_ "${cbfstool}" "${_grubrom}" add-int -i 0 -n etc/show-boot-menu - - x_ moverom "${_grubrom}" "${_newrom%.rom}_grubonly.rom" -} - build_uboot_roms() { tmprom=$(mkUbootRom "${cbrom}" "fallback/payload") || \ From 91927760db296596af3946327319625c17c1afa5 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 20:33:38 +0100 Subject: [PATCH 0051/1319] build/roms: simplified status handling Signed-off-by: Leah Rowe --- include/err.sh | 13 +------------ script/build/roms | 30 ++++++------------------------ 2 files changed, 7 insertions(+), 36 deletions(-) diff --git a/include/err.sh b/include/err.sh index 0b1c3e70..a94275f3 100755 --- a/include/err.sh +++ b/include/err.sh @@ -5,7 +5,7 @@ export LC_COLLATE=C export LC_ALL=C version=""; versiondate=""; projectname=""; _nogit="" -err="err_"; tmpdir=""; release_type=""; lbmk_status="" +err="err_"; tmpdir=""; lbmk_status="" # if "y": a coreboot target won't be built if target.cfg says release="n" # (this is used to exclude certain build targets from releases) @@ -15,17 +15,6 @@ set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : [ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" export LBMK_RELEASE="$lbmk_release" -# valid values: -# empty / not set -# value: stable -# value: unstable -# e.g. export LBMK_VERSION_TYPE=stable -set | grep LBMK_VERSION_TYPE 1>/dev/null 2>/dev/null && \ - release_type="$LBMK_VERSION_TYPE" -[ -z "$release_type" ] || [ "$release_type" = "stable" ] || \ - [ "$release_type" = "unstable" ] || release_type="" -export LBMK_VERSION_TYPE="$release_type" - # if set to n via export, status checks will be skipped during # all builds, and all targets will be built regardless of status. # this replicates the old behaviour of lbmk, prior to the checks. diff --git a/script/build/roms b/script/build/roms index 1c427b69..b84fd3b1 100755 --- a/script/build/roms +++ b/script/build/roms @@ -72,13 +72,12 @@ main() eval "$(setvars "n" ${pv}) $(setvars "" ${v})" grub_background="background1280x800.png" board="${x}" + status="unknown" configure_target [ "$board" = "$tree" ] && \ continue - handle_status - if [ "$listboards" = "y" ]; then for _list_type in $list_type; do [ "$status" != "$_list_type" ] && continue @@ -163,34 +162,17 @@ configure_target() eval "payload_${_payload}=y" } -handle_status() -{ - [ "$status" = "stable" ] || [ "$status" = "unstable" ] || \ - [ "$status" = "broken" ] || [ "$status" = "untested" ] || \ - status="unknown" - - [ "$listboards" != "y" ] && \ - printf "Handling target: %s (status=%s)\n" "$board" "$status" - - [ "$status" = "broken" ] && release="n" - [ "$status" = "unknown" ] && release="n" - [ "$status" = "untested" ] && release="n" - - [ "$listboards" != "y" ] && \ - [ "$status" != "stable" ] && [ "$status" != "$release_type" ] && \ - printf "WARNING: %s not marked stable (status=%s):\n\n" \ - "$board" "$status"; return 0 -} - skip_board() { + [ "$listboards" != "y" ] && [ "$status" != "stable" ] && \ + printf "WARNING: %s not stable (status=%s):\n\n" \ + "$board" "$status" + [ "$release" = "n" ] && [ "$lbmk_release" = "y" ] && \ return 0 - [ -n "$release_type" ] && [ "$status" = "$release_type" ] && \ - return 1 if [ "$lbmk_release" != "y" ] && [ "$status" != "stable" ] && \ - [ "$status" != "$release_type" ] && [ "$lbmk_status" = "y" ]; then + [ "$lbmk_status" = "y" ]; then if [ -f "$targetdir/warn.txt" ]; then printf "Regarding board '%s' (status '%s'):\n" \ "$board" "$status" From 0e2c56be4133eb4be62ad3eaa7490573a24ab2fd Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 20:40:41 +0100 Subject: [PATCH 0052/1319] build/roms: reduce indentation in skip_board() Signed-off-by: Leah Rowe --- script/build/roms | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/script/build/roms b/script/build/roms index b84fd3b1..f41f812b 100755 --- a/script/build/roms +++ b/script/build/roms @@ -168,27 +168,27 @@ skip_board() printf "WARNING: %s not stable (status=%s):\n\n" \ "$board" "$status" - [ "$release" = "n" ] && [ "$lbmk_release" = "y" ] && \ - return 0 + [ "$lbmk_release" = "y" ] && [ "$release" = "n" ] && return 0 + [ "$lbmk_release" = "y" ] && [ "$status" = "broken" ] && return 0 - if [ "$lbmk_release" != "y" ] && [ "$status" != "stable" ] && \ - [ "$lbmk_status" = "y" ]; then - if [ -f "$targetdir/warn.txt" ]; then - printf "Regarding board '%s' (status '%s'):\n" \ - "$board" "$status" - cat -u "$targetdir/warn.txt" || \ - $err "!cat $targetdir/warn.txt" - fi - printf "\nTo disable this dialog when building, do:\n" - printf "export LBMK_STATUS=n\n\n" - while true; do - printf "Board %s has status '%s'. Skip? [y/n]" \ - "$board" "$status" - read -r skip - [ "$skip" = "y" ] && return 0 - [ "$skip" = "n" ] && return 1; continue - done - fi; return 1 + [ "$lbmk_status" = "y" ] || return 1 + [ "$status" = "stable" ] && return 1 + + if [ -f "$targetdir/warn.txt" ]; then + printf "Regarding board '%s' (status '%s'):\n" \ + "$board" "$status" + cat -u "$targetdir/warn.txt" || \ + $err "!cat $targetdir/warn.txt" + fi + printf "\nTo disable this dialog when building, do:\n" + printf "export LBMK_STATUS=n\n\n" + while true; do + printf "Board %s has status '%s'. Skip? [y/n]" \ + "$board" "$status" + read -r skip + [ "$skip" = "y" ] && return 0 + [ "$skip" = "n" ] && return 1; continue + done } build_payloads() From dbe259ef6568a423354c37b7c2264bc9dcfd8d3d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 20:42:37 +0100 Subject: [PATCH 0053/1319] build/roms: always display warnings (even if status=stable) Signed-off-by: Leah Rowe --- script/build/roms | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/script/build/roms b/script/build/roms index f41f812b..1353ca18 100755 --- a/script/build/roms +++ b/script/build/roms @@ -168,18 +168,18 @@ skip_board() printf "WARNING: %s not stable (status=%s):\n\n" \ "$board" "$status" - [ "$lbmk_release" = "y" ] && [ "$release" = "n" ] && return 0 - [ "$lbmk_release" = "y" ] && [ "$status" = "broken" ] && return 0 - - [ "$lbmk_status" = "y" ] || return 1 - [ "$status" = "stable" ] && return 1 - - if [ -f "$targetdir/warn.txt" ]; then + if [ -f "$targetdir/warn.txt" ] && [ "$listboards" != "y" ]; then printf "Regarding board '%s' (status '%s'):\n" \ "$board" "$status" cat -u "$targetdir/warn.txt" || \ $err "!cat $targetdir/warn.txt" fi + + [ "$lbmk_release" = "y" ] && [ "$release" = "n" ] && return 0 + [ "$lbmk_release" = "y" ] && [ "$status" = "broken" ] && return 0 + [ "$lbmk_status" = "y" ] || return 1 + [ "$status" = "stable" ] && return 1 + printf "\nTo disable this dialog when building, do:\n" printf "export LBMK_STATUS=n\n\n" while true; do From 5003e02bb2cd7cededa85d13abbc7c6e720d7b56 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 28 Apr 2024 20:47:59 +0100 Subject: [PATCH 0054/1319] build/roms: if release, allow all non-broken roms this includes untested roms Signed-off-by: Leah Rowe --- script/build/roms | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/build/roms b/script/build/roms index 1353ca18..b8aab271 100755 --- a/script/build/roms +++ b/script/build/roms @@ -176,7 +176,7 @@ skip_board() fi [ "$lbmk_release" = "y" ] && [ "$release" = "n" ] && return 0 - [ "$lbmk_release" = "y" ] && [ "$status" = "broken" ] && return 0 + [ "$lbmk_release" = "y" ] && [ "$status" != "broken" ] && return 1 [ "$lbmk_status" = "y" ] || return 1 [ "$status" = "stable" ] && return 1 From b737a24c903ff75475fc7ac8a2f80901fb0acfcb Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sun, 28 Apr 2024 14:55:47 -0600 Subject: [PATCH 0055/1319] dell-flash-unlock: Remove memory clobber from inline assembly The x86 port IO instructions do not access memory so it is not needed in the clobber list. Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/accessors.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/dell-flash-unlock/accessors.c b/util/dell-flash-unlock/accessors.c index a35f8139..a5f936c8 100644 --- a/util/dell-flash-unlock/accessors.c +++ b/util/dell-flash-unlock/accessors.c @@ -43,7 +43,7 @@ sys_outb(unsigned int port, uint8_t data) outb(port, data); #endif #if defined(__NetBSD__) - __asm__ volatile ( "outb %b0, %w1" : : "a"(data), "d"(port) : "memory"); + __asm__ volatile ("outb %b0, %w1" : : "a"(data), "d"(port)); #endif } @@ -57,7 +57,7 @@ sys_outl(unsigned int port, uint32_t data) outl(port, data); #endif #if defined(__NetBSD__) - __asm__ volatile ( "outl %0, %w1" : : "a"(data), "d"(port) : "memory"); + __asm__ volatile ("outl %0, %w1" : : "a"(data), "d"(port)); #endif } @@ -70,7 +70,7 @@ sys_inb(unsigned int port) #if defined(__NetBSD__) uint8_t retval; - __asm__ volatile("inb %w1, %b0" : "=a" (retval) : "d" (port) : "memory"); + __asm__ volatile ("inb %w1, %b0" : "=a" (retval) : "d" (port)); return retval; #endif return 0; @@ -84,7 +84,7 @@ sys_inl(unsigned int port) #endif #if defined(__NetBSD__) int retval; - __asm__ volatile("inl %w1, %0" : "=a" (retval) : "d" (port) : "memory"); + __asm__ volatile ("inl %w1, %0" : "=a" (retval) : "d" (port)); return retval; #endif return 0; From 6fe2482fdf035abf4bfb076801aef314fe70776c Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sun, 28 Apr 2024 15:16:19 -0600 Subject: [PATCH 0056/1319] dell-flash-unlock: Remove unnecessary includes for NetBSD The pio.h header, although present on NetBSD, is not necessary, as it only declares x86 port IO inx()/outx() functions which are not actually implemented. Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/accessors.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/dell-flash-unlock/accessors.c b/util/dell-flash-unlock/accessors.c index a5f936c8..a8541e28 100644 --- a/util/dell-flash-unlock/accessors.c +++ b/util/dell-flash-unlock/accessors.c @@ -8,12 +8,15 @@ #if defined(__OpenBSD__) || defined(__NetBSD__) #include #include +#endif /* __OpenBSD__ || __NetBSD__ */ + +#if defined(__OpenBSD__) #if defined(__amd64__) #include #elif defined(__i386__) #include #endif /* __i386__ */ -#endif /* __OpenBSD__ || __NetBSD__ */ +#endif /* __OpenBSD__ */ #include From 310378c9e584aa8ad37266a1d7a0f07640574a49 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 29 Apr 2024 00:25:39 +0100 Subject: [PATCH 0057/1319] build/roms: simplified list handling Signed-off-by: Leah Rowe --- script/build/roms | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/script/build/roms b/script/build/roms index b8aab271..1ed64004 100755 --- a/script/build/roms +++ b/script/build/roms @@ -33,10 +33,6 @@ main() while [ $# -gt 0 ]; do if [ "$listboards" = "y" ]; then - [ "$1" = "stable" ] || [ "$1" = "unstable" ] || \ - [ "$1" = "broken" ] || [ "$1" = "untested" ] || \ - [ "$1" = "unknown" ] || \ - $err "invalid list type '$1'" list_type="$list_type $1" list_type="${list_type# }" shift 1; continue @@ -62,9 +58,6 @@ main() shift 2 done - [ "$listboards" = "y" ] && [ -z "$list_type" ] && \ - list_type="stable unstable broken untested unknown" - [ "${all}" != "y" ] || boards=$(items config/coreboot) || \ $err "Cannot generate list of boards for building" @@ -79,11 +72,11 @@ main() continue if [ "$listboards" = "y" ]; then + [ -z "$list_type" ] && printf "%s\n" "$board" for _list_type in $list_type; do [ "$status" != "$_list_type" ] && continue printf "%s\n" "$board" - done - continue + done; continue fi # exclude certain targets from the release From 3e86b3ab731fdf086c653d791f92ff7094bbb798 Mon Sep 17 00:00:00 2001 From: livio Date: Mon, 29 Apr 2024 14:39:47 +0200 Subject: [PATCH 0058/1319] Implemented failsafe options at boot and inside menus for enabling/disabling serial, spkmodem and gfxterm --- config/grub/config/grub.cfg | 65 ++++++++++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 8 deletions(-) diff --git a/config/grub/config/grub.cfg b/config/grub/config/grub.cfg index 17576b5f..a433000e 100644 --- a/config/grub/config/grub.cfg +++ b/config/grub/config/grub.cfg @@ -14,17 +14,36 @@ terminal_input --append at_keyboard terminal_input --append usb_keyboard terminal_output --append cbmemc -gfxpayload=keep -terminal_output --append gfxterm +# User interface overrides wherever "keystatus" is supported +# Keep SHIFT key pressed before powering on to disable graphics +if keystatus --shift; then + terminal_output --append vga_text +else + gfxpayload=keep + terminal_output --append gfxterm -if [ -f (cbfsdisk)/background.png ]; then - insmod png - background_image (cbfsdisk)/background.png -elif [ -f (cbfsdisk)/background.jpg ]; then - insmod jpeg - background_image (cbfsdisk)/background.jpg + if [ -f (cbfsdisk)/background.png ]; then + insmod png + background_image (cbfsdisk)/background.png + elif [ -f (cbfsdisk)/background.jpg ]; then + insmod jpeg + background_image (cbfsdisk)/background.jpg + fi fi +# Keep CTRL pressed to enable default serial terminal (COM1 or the like) +if keystatus --ctrl; then + serial + terminal_input --append serial + terminal_output --append serial +fi + +# Keep ALT pressed to enable spkmodem +if keystatus --alt; then + terminal_output --append spkmodem +fi + + set default="0" if [ -f (cbfsdisk)/timeout.cfg ]; then source (cbfsdisk)/timeout.cfg @@ -198,3 +217,33 @@ menuentry 'Load MemTest86+ [m]' --hotkey='m' { chainloader /img/memtest } fi + +submenu 'Other [z]' --hotkey='z' { + menuentry 'Enable default serial terminal [s]' --hotkey='s' { + serial + terminal_input --append serial + terminal_output --append serial + } + + menuentry 'Disable default serial terminal' { + terminal_input --remove serial + terminal_output --remove serial + } + + menuentry 'Enable gfxterm' { + terminal_output --append gfxterm + terminal_output --remove vga_text + } + menuentry 'Disable gfxterm [g]' --hotkey='g' { + terminal_output --remove gfxterm + terminal_output --append vga_text + } + + menuentry 'Enable spkmodem [a]' --hotkey='a' { + terminal_output --append spkmodem + } + + menuentry 'Disable spkmodem [z]' --hotkey='z' { + terminal_output --remove spkmodem + } +} \ No newline at end of file From 7e7c3c235deabf058f75ec6c8b0a5e81335ec71a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 May 2024 00:36:28 +0100 Subject: [PATCH 0059/1319] mark i945 machines as stable for release the previous issue was tested, and can no longer be reproduced Signed-off-by: Leah Rowe --- config/coreboot/macbook11/target.cfg | 2 +- config/coreboot/macbook11/warn.txt | 1 - config/coreboot/macbook11_16mb/target.cfg | 2 +- config/coreboot/macbook11_16mb/warn.txt | 1 - config/coreboot/macbook21/target.cfg | 2 +- config/coreboot/macbook21/warn.txt | 1 - config/coreboot/macbook21_16mb/target.cfg | 2 +- config/coreboot/macbook21_16mb/warn.txt | 1 - config/coreboot/t60_16mb_intelgpu/target.cfg | 2 +- config/coreboot/t60_16mb_intelgpu/warn.txt | 1 - config/coreboot/t60_intelgpu/target.cfg | 2 +- config/coreboot/t60_intelgpu/warn.txt | 1 - config/coreboot/x60/target.cfg | 2 +- config/coreboot/x60/warn.txt | 1 - config/coreboot/x60_16mb/target.cfg | 2 +- config/coreboot/x60_16mb/warn.txt | 1 - 16 files changed, 8 insertions(+), 16 deletions(-) delete mode 100644 config/coreboot/macbook11/warn.txt delete mode 100644 config/coreboot/macbook11_16mb/warn.txt delete mode 100644 config/coreboot/macbook21/warn.txt delete mode 100644 config/coreboot/macbook21_16mb/warn.txt delete mode 100644 config/coreboot/t60_16mb_intelgpu/warn.txt delete mode 100644 config/coreboot/t60_intelgpu/warn.txt delete mode 100644 config/coreboot/x60/warn.txt delete mode 100644 config/coreboot/x60_16mb/warn.txt diff --git a/config/coreboot/macbook11/target.cfg b/config/coreboot/macbook11/target.cfg index 3c06a458..38046653 100644 --- a/config/coreboot/macbook11/target.cfg +++ b/config/coreboot/macbook11/target.cfg @@ -4,4 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/macbook11/warn.txt b/config/coreboot/macbook11/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/macbook11/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook11_16mb/target.cfg b/config/coreboot/macbook11_16mb/target.cfg index 3c06a458..38046653 100644 --- a/config/coreboot/macbook11_16mb/target.cfg +++ b/config/coreboot/macbook11_16mb/target.cfg @@ -4,4 +4,4 @@ payload_grub="y" payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/macbook11_16mb/warn.txt b/config/coreboot/macbook11_16mb/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/macbook11_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook21/target.cfg b/config/coreboot/macbook21/target.cfg index b4feb4de..27d71b5a 100644 --- a/config/coreboot/macbook21/target.cfg +++ b/config/coreboot/macbook21/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/macbook21/warn.txt b/config/coreboot/macbook21/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/macbook21/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/macbook21_16mb/target.cfg b/config/coreboot/macbook21_16mb/target.cfg index b4feb4de..27d71b5a 100644 --- a/config/coreboot/macbook21_16mb/target.cfg +++ b/config/coreboot/macbook21_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/macbook21_16mb/warn.txt b/config/coreboot/macbook21_16mb/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/macbook21_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/t60_16mb_intelgpu/target.cfg b/config/coreboot/t60_16mb_intelgpu/target.cfg index 004ba1b0..bb3decba 100644 --- a/config/coreboot/t60_16mb_intelgpu/target.cfg +++ b/config/coreboot/t60_16mb_intelgpu/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="unstable" +status="stable" diff --git a/config/coreboot/t60_16mb_intelgpu/warn.txt b/config/coreboot/t60_16mb_intelgpu/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/t60_16mb_intelgpu/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/t60_intelgpu/target.cfg b/config/coreboot/t60_intelgpu/target.cfg index 004ba1b0..bb3decba 100644 --- a/config/coreboot/t60_intelgpu/target.cfg +++ b/config/coreboot/t60_intelgpu/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="unstable" +status="stable" diff --git a/config/coreboot/t60_intelgpu/warn.txt b/config/coreboot/t60_intelgpu/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/t60_intelgpu/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/x60/target.cfg b/config/coreboot/x60/target.cfg index 004ba1b0..bb3decba 100644 --- a/config/coreboot/x60/target.cfg +++ b/config/coreboot/x60/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="unstable" +status="stable" diff --git a/config/coreboot/x60/warn.txt b/config/coreboot/x60/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/x60/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. diff --git a/config/coreboot/x60_16mb/target.cfg b/config/coreboot/x60_16mb/target.cfg index 004ba1b0..bb3decba 100644 --- a/config/coreboot/x60_16mb/target.cfg +++ b/config/coreboot/x60_16mb/target.cfg @@ -5,4 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" grub_scan_disk="ahci" grub_background="background1024x768.png" -status="unstable" +status="stable" diff --git a/config/coreboot/x60_16mb/warn.txt b/config/coreboot/x60_16mb/warn.txt deleted file mode 100644 index 5bffd9da..00000000 --- a/config/coreboot/x60_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -Presumably fully stable, but see lbmk issue 179: https://codeberg.org/libreboot/lbmk/issues/179 - T60 on just battery power had the error in GRUB: alloc magic is broken at 0x7b1aedf0: 0 ----- the rev for Libreboot 2024050x is set to the LB 202306235 rev (February 2023) for now. I still think the users with that issue, and there weren't that many, just had bad RAM. GRUB shows that error on bad RAM, and I've seen it in that case on other machines too. So this machine is most likely fully stable, but I'm marking it unstable until we know fully what we're dealing with. From df5e321648f53ffa3c7d8ec2428deddb3e58a8d3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 May 2024 05:56:42 +0100 Subject: [PATCH 0060/1319] set dell latitudes stable for release Signed-off-by: Leah Rowe --- config/coreboot/e5420_6mb/target.cfg | 2 +- config/coreboot/e5520_6mb/target.cfg | 2 +- config/coreboot/e5530_12mb/target.cfg | 2 +- config/coreboot/e6400_4mb/target.cfg | 2 +- config/coreboot/e6420_10mb/target.cfg | 2 +- config/coreboot/e6430_12mb/target.cfg | 2 +- config/coreboot/e6520_10mb/target.cfg | 2 +- config/coreboot/e6530_12mb/target.cfg | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index d1ea26ad..fb7c7bfb 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" # broken s3 +status="stable" # broken s3 diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" From 50f6943ccd71c0249915c17e993bcb5c3341d5d3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 May 2024 05:59:31 +0100 Subject: [PATCH 0061/1319] set gru bob/kevin stable for release Signed-off-by: Leah Rowe --- config/coreboot/gru_bob/target.cfg | 2 +- config/coreboot/gru_kevin/target.cfg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/config/coreboot/gru_bob/target.cfg b/config/coreboot/gru_bob/target.cfg index c6ad9102..86283f7a 100644 --- a/config/coreboot/gru_bob/target.cfg +++ b/config/coreboot/gru_bob/target.cfg @@ -1,4 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" -status="unstable" +status="stable" diff --git a/config/coreboot/gru_kevin/target.cfg b/config/coreboot/gru_kevin/target.cfg index c6ad9102..86283f7a 100644 --- a/config/coreboot/gru_kevin/target.cfg +++ b/config/coreboot/gru_kevin/target.cfg @@ -1,4 +1,4 @@ tree="default" xarch="aarch64-elf arm-eabi" payload_uboot="y" -status="unstable" +status="stable" From 6dfd8c707052dfcd90d87342e4793ccde7084450 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 May 2024 06:12:50 +0100 Subject: [PATCH 0062/1319] update release status for HP machines Signed-off-by: Leah Rowe --- config/coreboot/hp2170p_16mb/target.cfg | 2 +- config/coreboot/hp2170p_16mb/warn.txt | 1 + config/coreboot/hp2560p_8mb/target.cfg | 2 +- config/coreboot/hp2560p_8mb/warn.txt | 1 + config/coreboot/hp2570p_16mb/target.cfg | 2 +- config/coreboot/hp2570p_16mb/warn.txt | 1 + config/coreboot/hp8200sff_4mb/target.cfg | 2 +- config/coreboot/hp8200sff_4mb/warn.txt | 1 + config/coreboot/hp8200sff_8mb/target.cfg | 2 +- config/coreboot/hp8200sff_8mb/warn.txt | 1 + config/coreboot/hp820g2_12mb/warn.txt | 1 + config/coreboot/hp8300cmt_16mb/target.cfg | 2 +- config/coreboot/hp8300cmt_16mb/warn.txt | 1 + config/coreboot/hp8300usdt_16mb/target.cfg | 2 +- config/coreboot/hp8300usdt_16mb/warn.txt | 1 + config/coreboot/hp8460pintel_8mb/target.cfg | 2 +- config/coreboot/hp8460pintel_8mb/warn.txt | 1 + config/coreboot/hp8470pintel_16mb/target.cfg | 2 +- config/coreboot/hp8470pintel_16mb/warn.txt | 1 + config/coreboot/hp8560w_8mb/warn.txt | 1 + config/coreboot/hp9470m_16mb/target.cfg | 2 +- config/coreboot/hp9470m_16mb/warn.txt | 1 + 22 files changed, 22 insertions(+), 10 deletions(-) create mode 100644 config/coreboot/hp2170p_16mb/warn.txt create mode 100644 config/coreboot/hp2560p_8mb/warn.txt create mode 100644 config/coreboot/hp2570p_16mb/warn.txt create mode 100644 config/coreboot/hp8200sff_4mb/warn.txt create mode 100644 config/coreboot/hp8200sff_8mb/warn.txt create mode 100644 config/coreboot/hp820g2_12mb/warn.txt create mode 100644 config/coreboot/hp8300cmt_16mb/warn.txt create mode 100644 config/coreboot/hp8300usdt_16mb/warn.txt create mode 100644 config/coreboot/hp8460pintel_8mb/warn.txt create mode 100644 config/coreboot/hp8470pintel_16mb/warn.txt create mode 100644 config/coreboot/hp8560w_8mb/warn.txt create mode 100644 config/coreboot/hp9470m_16mb/warn.txt diff --git a/config/coreboot/hp2170p_16mb/target.cfg b/config/coreboot/hp2170p_16mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp2170p_16mb/target.cfg +++ b/config/coreboot/hp2170p_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp2170p_16mb/warn.txt b/config/coreboot/hp2170p_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp2170p_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp2560p_8mb/target.cfg b/config/coreboot/hp2560p_8mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp2560p_8mb/target.cfg +++ b/config/coreboot/hp2560p_8mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp2560p_8mb/warn.txt b/config/coreboot/hp2560p_8mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp2560p_8mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp2570p_16mb/target.cfg b/config/coreboot/hp2570p_16mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp2570p_16mb/target.cfg +++ b/config/coreboot/hp2570p_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp2570p_16mb/warn.txt b/config/coreboot/hp2570p_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp2570p_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8200sff_4mb/target.cfg b/config/coreboot/hp8200sff_4mb/target.cfg index 12afcd76..01583d37 100644 --- a/config/coreboot/hp8200sff_4mb/target.cfg +++ b/config/coreboot/hp8200sff_4mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8200sff_4mb/warn.txt b/config/coreboot/hp8200sff_4mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8200sff_4mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8200sff_8mb/target.cfg b/config/coreboot/hp8200sff_8mb/target.cfg index 12afcd76..01583d37 100644 --- a/config/coreboot/hp8200sff_8mb/target.cfg +++ b/config/coreboot/hp8200sff_8mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8200sff_8mb/warn.txt b/config/coreboot/hp8200sff_8mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8200sff_8mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp820g2_12mb/warn.txt b/config/coreboot/hp820g2_12mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp820g2_12mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8300cmt_16mb/target.cfg b/config/coreboot/hp8300cmt_16mb/target.cfg index 12afcd76..01583d37 100644 --- a/config/coreboot/hp8300cmt_16mb/target.cfg +++ b/config/coreboot/hp8300cmt_16mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8300cmt_16mb/warn.txt b/config/coreboot/hp8300cmt_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8300cmt_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8300usdt_16mb/target.cfg b/config/coreboot/hp8300usdt_16mb/target.cfg index 12afcd76..01583d37 100644 --- a/config/coreboot/hp8300usdt_16mb/target.cfg +++ b/config/coreboot/hp8300usdt_16mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8300usdt_16mb/warn.txt b/config/coreboot/hp8300usdt_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8300usdt_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8460pintel_8mb/target.cfg b/config/coreboot/hp8460pintel_8mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp8460pintel_8mb/target.cfg +++ b/config/coreboot/hp8460pintel_8mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8460pintel_8mb/warn.txt b/config/coreboot/hp8460pintel_8mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8460pintel_8mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8470pintel_16mb/target.cfg b/config/coreboot/hp8470pintel_16mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp8470pintel_16mb/target.cfg +++ b/config/coreboot/hp8470pintel_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp8470pintel_16mb/warn.txt b/config/coreboot/hp8470pintel_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8470pintel_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8560w_8mb/warn.txt b/config/coreboot/hp8560w_8mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp8560w_8mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp9470m_16mb/target.cfg b/config/coreboot/hp9470m_16mb/target.cfg index 1b9e33f0..e6f295cf 100644 --- a/config/coreboot/hp9470m_16mb/target.cfg +++ b/config/coreboot/hp9470m_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="untested" +status="unstable" diff --git a/config/coreboot/hp9470m_16mb/warn.txt b/config/coreboot/hp9470m_16mb/warn.txt new file mode 100644 index 00000000..68f0b1fe --- /dev/null +++ b/config/coreboot/hp9470m_16mb/warn.txt @@ -0,0 +1 @@ +HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. From 5c3d81fff9f90b19f09c95fae43eacff10ab932e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 1 May 2024 06:29:09 +0100 Subject: [PATCH 0063/1319] correct dell latitude status for release it should be marked unstable, though these machines are basically reliable; they have certain missing features and quirky behaviour so it's important not to over-sell it mark it as unstable, on all of the dell latitudes Signed-off-by: Leah Rowe --- config/coreboot/e5420_6mb/target.cfg | 2 +- config/coreboot/e5520_6mb/target.cfg | 2 +- config/coreboot/e5530_12mb/target.cfg | 2 +- config/coreboot/e6400_4mb/target.cfg | 2 +- config/coreboot/e6420_10mb/target.cfg | 2 +- config/coreboot/e6430_12mb/target.cfg | 2 +- config/coreboot/e6520_10mb/target.cfg | 2 +- config/coreboot/e6530_12mb/target.cfg | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index fb7c7bfb..d1ea26ad 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" # broken s3 +status="unstable" # broken s3 diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index a0cfb47e..e48db5e5 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="stable" +status="unstable" From b4d27d0cc6e212ec05fe05a8f2b233138ec5b9de Mon Sep 17 00:00:00 2001 From: livio Date: Wed, 1 May 2024 11:06:27 +0200 Subject: [PATCH 0064/1319] Fixed boot selection menu --- config/grub/config/grub.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/grub/config/grub.cfg b/config/grub/config/grub.cfg index 17576b5f..d8ad7d02 100644 --- a/config/grub/config/grub.cfg +++ b/config/grub/config/grub.cfg @@ -164,7 +164,7 @@ menuentry 'Search for GRUB/SYSLINUX/EXTLINUX/ISOLINUX on AHCI [a]' --hotkey='a' search_bootcfg ahci } menuentry 'Search for GRUB/SYSLINUX/EXTLINUX/ISOLINUX on ATA/IDE [d]' --hotkey='d' { - search_bootcfg ahci + search_bootcfg ata } if [ -f (cbfsdisk)/grubtest.cfg ]; then menuentry 'Load test configuration (grubtest.cfg) inside of CBFS [t]' --hotkey='t' { From d654a3e5edf8c8bf63a72f2ca68428f19f28ef1b Mon Sep 17 00:00:00 2001 From: livio Date: Wed, 1 May 2024 11:17:59 +0200 Subject: [PATCH 0065/1319] Fixed QEMU x86 target's SMBIOS informations --- config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb b/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb index 81e94a21..6aa7a4b8 100644 --- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_corebootfb @@ -113,7 +113,7 @@ CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAINBOARD_VENDOR="QEMU" CONFIG_CBFS_SIZE=0xBE0000 CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=4 @@ -127,7 +127,7 @@ CONFIG_VBOOT_VBNV_OFFSET=0x2c CONFIG_IRQ_SLOT_COUNT=6 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="QEMU" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" @@ -152,7 +152,7 @@ CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X230" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86" CONFIG_PCIEXP_HOTPLUG_BUSES=8 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 From 707d7ce7d094ea40555119f045efee84f1d9cbad Mon Sep 17 00:00:00 2001 From: livio Date: Wed, 1 May 2024 11:20:46 +0200 Subject: [PATCH 0066/1319] Fixed QEMU x86 target's SMBIOS informations --- config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode b/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode index c5a77eb2..91435206 100644 --- a/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/qemu_x86_12mb/config/libgfxinit_txtmode @@ -113,7 +113,7 @@ CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAINBOARD_VENDOR="QEMU" CONFIG_CBFS_SIZE=0xBE0000 CONFIG_CONSOLE_SERIAL=y CONFIG_MAX_CPUS=4 @@ -127,7 +127,7 @@ CONFIG_VBOOT_VBNV_OFFSET=0x2c CONFIG_IRQ_SLOT_COUNT=6 CONFIG_OVERRIDE_DEVICETREE="" # CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="QEMU" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" @@ -152,7 +152,7 @@ CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X230" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86" CONFIG_PCIEXP_HOTPLUG_BUSES=8 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 From 355dffb7089707efd8ebe75b1652cec44a06f317 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 1 May 2024 20:09:50 -0600 Subject: [PATCH 0067/1319] dell_flash_unlock: Fix ec_set_fdo() signature Set argument list as void. Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/dell_flash_unlock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/dell-flash-unlock/dell_flash_unlock.c b/util/dell-flash-unlock/dell_flash_unlock.c index 174a1c92..6118b0d4 100644 --- a/util/dell-flash-unlock/dell_flash_unlock.c +++ b/util/dell-flash-unlock/dell_flash_unlock.c @@ -15,7 +15,7 @@ int get_fdo_status(void); int check_lpc_decode(void); -void ec_set_fdo(); +void ec_set_fdo(void); void write_ec_reg(uint8_t index, uint8_t data); void send_ec_cmd(uint8_t cmd); int wait_ec(void); @@ -141,7 +141,7 @@ check_lpc_decode(void) } void -ec_set_fdo() +ec_set_fdo(void) { /* EC FDO command arguments for reference: * 0 = Query EC FDO status From 61dbaf9463034fb893ca8f5131681bdd54ec5472 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 1 May 2024 20:10:43 -0600 Subject: [PATCH 0068/1319] dell_flash_unlock: Set iopl level back to 0 when done Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/dell_flash_unlock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/dell-flash-unlock/dell_flash_unlock.c b/util/dell-flash-unlock/dell_flash_unlock.c index 6118b0d4..d59f5d5b 100644 --- a/util/dell-flash-unlock/dell_flash_unlock.c +++ b/util/dell-flash-unlock/dell_flash_unlock.c @@ -96,6 +96,7 @@ main(int argc, char *argv[]) "You can now shutdown the system.\n"); } } + sys_iopl(0); return errno; } From 5e2e761142085f60c85f19895d985a58a6f5ee0f Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 1 May 2024 20:11:14 -0600 Subject: [PATCH 0069/1319] dell_flash_unlock: Add support for FreeBSD Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/accessors.c | 39 +++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/util/dell-flash-unlock/accessors.c b/util/dell-flash-unlock/accessors.c index a8541e28..0a5df760 100644 --- a/util/dell-flash-unlock/accessors.c +++ b/util/dell-flash-unlock/accessors.c @@ -18,6 +18,13 @@ #endif /* __i386__ */ #endif /* __OpenBSD__ */ +#if defined(__FreeBSD__) +#include +#include +#include +#include +#endif /* __FreeBSD__ */ + #include #include "accessors.h" @@ -42,7 +49,7 @@ sys_outb(unsigned int port, uint8_t data) #if defined(__linux__) outb(data, port); #endif - #if defined(__OpenBSD__) + #if defined(__OpenBSD__) || defined(__FreeBSD__) outb(port, data); #endif #if defined(__NetBSD__) @@ -56,7 +63,7 @@ sys_outl(unsigned int port, uint32_t data) #if defined(__linux__) outl(data, port); #endif - #if defined(__OpenBSD__) + #if defined(__OpenBSD__) || defined(__FreeBSD__) outl(port, data); #endif #if defined(__NetBSD__) @@ -67,7 +74,8 @@ sys_outl(unsigned int port, uint32_t data) uint8_t sys_inb(unsigned int port) { - #if defined(__linux__) || defined (__OpenBSD__) + #if defined(__linux__) || defined (__OpenBSD__) \ + || defined(__FreeBSD__) return inb(port); #endif @@ -82,7 +90,8 @@ sys_inb(unsigned int port) uint32_t sys_inl(unsigned int port) { - #if defined(__linux__) || defined (__OpenBSD__) + #if defined(__linux__) || defined (__OpenBSD__) \ + || defined(__FreeBSD__) return inl(port); #endif #if defined(__NetBSD__) @@ -115,6 +124,28 @@ sys_iopl(int level) #endif /* __amd64__ */ #endif /* __NetBSD__ */ +#if defined(__FreeBSD__) + /* Refer to io(4) manual page. This assumes the legacy behavior + * where opening /dev/io raises the IOPL of the process */ + static int io_fd = -1; + + /* Requesting privileged access */ + if (level > 0) { + if (io_fd == -1) { + io_fd = open("/dev/io", O_RDONLY); + return (io_fd == -1) ? -1 : 0; + } + /* Lowering access to lowest level */ + } else if (level == 0 && io_fd != -1) { + if (close(io_fd) == -1) { + return -1; + } else { + io_fd = -1; + } + } + return 0; +#endif /* __FreeBSD__ */ + errno = ENOSYS; return -1; } From 61f66a46eab2480d45b14a14889e082678daaa80 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 1 May 2024 20:20:24 -0600 Subject: [PATCH 0070/1319] dell-flash-unlock: Update README for BSD Add FreeBSD to the README as it is now supported. Make a note about using gmake instead of make as the makefile currently uses GNU extensions to determine build flags based on the OS. Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/README.md | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/util/dell-flash-unlock/README.md b/util/dell-flash-unlock/README.md index aca01743..e179e77c 100644 --- a/util/dell-flash-unlock/README.md +++ b/util/dell-flash-unlock/README.md @@ -20,14 +20,17 @@ around 2008 (E6400 era). If it says it is not set, then you will need to install or compile a kernel with that option set. -### OpenBSD/NetBSD -- On OpenBSD/NetBSD, ensure you are booting with securelevel set to -1. +### OpenBSD/NetBSD/FreeBSD +- The makefile is not currently compatible with POSIX make; install and use GNU + Make (gmake) to build dell-flash-unlock instead of make +- On OpenBSD/NetBSD/FreeBSD, ensure you are booting with securelevel set to -1. ### General Make sure an AC adapter is plugged into your system -Run `make` to compile the utility, and then run `./dell_flash_unlock` with -root/superuser permissions and follow the directions it outputs. +Run `make` (or `gmake` on BSD) to compile the utility, and then run +`./dell_flash_unlock` with root/superuser permissions and follow the directions +it outputs. ## Confirmed supported devices - Latitude E6400, E6500 From a5cb63764b9984f8e99275b00bd9d5d974a88d1e Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Wed, 1 May 2024 21:39:13 -0600 Subject: [PATCH 0071/1319] dell-flash-unlock: Remove dependency on GNU Make Use shell scripting in the recipe instead of GNU make's conditional syntax. This allows the Makefile to work with the default implementations of make on the BSDs. Signed-off-by: Nicholas Chin --- util/dell-flash-unlock/Makefile | 12 +++++------- util/dell-flash-unlock/README.md | 7 ++----- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/util/dell-flash-unlock/Makefile b/util/dell-flash-unlock/Makefile index aee07167..8528c10e 100644 --- a/util/dell-flash-unlock/Makefile +++ b/util/dell-flash-unlock/Makefile @@ -3,16 +3,14 @@ CC=cc CFLAGS=-Wall -Wextra -Werror -O2 -pedantic -ifeq ($(shell uname), OpenBSD) - CFLAGS += -l$(shell uname -p) -endif -ifeq ($(shell uname), NetBSD) - CFLAGS += -l$(shell uname -p) -endif SRCS=dell_flash_unlock.c accessors.c all: $(SRCS) accessors.h - $(CC) $(CFLAGS) $(SRCS) -o dell_flash_unlock + CFLAGS="$(CFLAGS)"; \ + if [ $$(uname) = OpenBSD ] || [ $$(uname) = NetBSD ]; then \ + CFLAGS="$$CFLAGS -l$$(uname -p)"; \ + fi; \ + $(CC) $$CFLAGS $(SRCS) -o dell_flash_unlock clean: rm -f dell_flash_unlock diff --git a/util/dell-flash-unlock/README.md b/util/dell-flash-unlock/README.md index e179e77c..7333f63e 100644 --- a/util/dell-flash-unlock/README.md +++ b/util/dell-flash-unlock/README.md @@ -21,16 +21,13 @@ around 2008 (E6400 era). with that option set. ### OpenBSD/NetBSD/FreeBSD -- The makefile is not currently compatible with POSIX make; install and use GNU - Make (gmake) to build dell-flash-unlock instead of make - On OpenBSD/NetBSD/FreeBSD, ensure you are booting with securelevel set to -1. ### General Make sure an AC adapter is plugged into your system -Run `make` (or `gmake` on BSD) to compile the utility, and then run -`./dell_flash_unlock` with root/superuser permissions and follow the directions -it outputs. +Run `make` to compile the utility, and then run `./dell_flash_unlock` with +root/superuser permissions and follow the directions it outputs. ## Confirmed supported devices - Latitude E6400, E6500 From 7db2ae0bd2064db5398e3c47cdfe2b399664ef17 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 07:11:43 +0100 Subject: [PATCH 0072/1319] update/release: say when an archive is being made without this change, the user might think lbmk crashed Signed-off-by: Leah Rowe --- script/update/release | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/script/update/release b/script/update/release index d7b7d108..bdada97a 100755 --- a/script/update/release +++ b/script/update/release @@ -1,6 +1,6 @@ #!/usr/bin/env sh # SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: 2020-2023 Leah Rowe +# SPDX-FileCopyrightText: 2020-2024 Leah Rowe set -u -e @@ -216,6 +216,7 @@ mktarball() [ "${2%/*}" = "${2}" ] || \ mkdir -p "${2%/*}" || $err "mk, !mkdir -p \"${2%/*}\"" + printf "\nCreating archive: %s\n\n" "$2" if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then tar --sort=name --owner=root:0 --group=root:0 \ --mtime="UTC 2024-02-25" -c "$1" | xz -T$threads -9e \ From 9caff26332ae2c0c5c49ebb4d9946237c1419561 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 07:13:54 +0100 Subject: [PATCH 0073/1319] err.sh: update copyright info i added a few changes during this year so far, 2024 update the copyright years Signed-off-by: Leah Rowe --- include/err.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/err.sh b/include/err.sh index a94275f3..a25effe6 100755 --- a/include/err.sh +++ b/include/err.sh @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: 2022, 2023 Leah Rowe +# SPDX-FileCopyrightText: 2022, 2024 Leah Rowe export LC_COLLATE=C export LC_ALL=C From 748b20721587793ec296875e41eb8cd02904a693 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 13:57:35 +0100 Subject: [PATCH 0074/1319] mark x4x boards ready for release Signed-off-by: Leah Rowe --- config/coreboot/g43t-am3/target.cfg | 2 +- config/coreboot/g43t-am3_16mb/target.cfg | 3 ++- config/coreboot/ga-g41m-es2l/target.cfg | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/config/coreboot/g43t-am3/target.cfg b/config/coreboot/g43t-am3/target.cfg index af80482f..21b6872f 100644 --- a/config/coreboot/g43t-am3/target.cfg +++ b/config/coreboot/g43t-am3/target.cfg @@ -3,4 +3,4 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 -status="untested" +status="stable" diff --git a/config/coreboot/g43t-am3_16mb/target.cfg b/config/coreboot/g43t-am3_16mb/target.cfg index af80482f..01cd4d07 100644 --- a/config/coreboot/g43t-am3_16mb/target.cfg +++ b/config/coreboot/g43t-am3_16mb/target.cfg @@ -3,4 +3,5 @@ xarch="i386-elf" payload_seabios="y" payload_memtest="y" grub_timeout=10 -status="untested" +status="stable" +release="n" diff --git a/config/coreboot/ga-g41m-es2l/target.cfg b/config/coreboot/ga-g41m-es2l/target.cfg index 9fc566d8..dc53b74a 100644 --- a/config/coreboot/ga-g41m-es2l/target.cfg +++ b/config/coreboot/ga-g41m-es2l/target.cfg @@ -4,4 +4,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ata" grub_timeout=10 -status="untested" +status="stable" From 64ae2ddd331528fb1231ced3d641f5c0a4a780c9 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 14:02:02 +0100 Subject: [PATCH 0075/1319] update/release: purge test/lib/strlcat.c in u-boot Signed-off-by: Leah Rowe --- script/update/release | 1 + 1 file changed, 1 insertion(+) diff --git a/script/update/release b/script/update/release index bdada97a..fcee49e7 100755 --- a/script/update/release +++ b/script/update/release @@ -185,6 +185,7 @@ insert_copying_files() cp -R "src/u-boot/default/Licenses" "${l}/COPYING.u-boot" || return 1 printf "Multiple licenses. Check corresponding %s source archive\n" \ "${projectname}" > "${1}/COPYING" || return 1 + rm -f src/u-boot/*/test/lib/strlcat.c || return 1 } mkrom_tarball() From 2d207c547cdfba50d9c376197f95ad892432a697 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 14:27:50 +0100 Subject: [PATCH 0076/1319] coreboot/x301: set release=n (will re-test) was reported broken on canoeboot 0.1, which uses 2021 coreboot. we use much newer coreboot now in libreboot, but still, better be cautious. set to release=n. i'll set status and remove release=n if it works on testing Signed-off-by: Leah Rowe --- config/coreboot/x301_16mb/target.cfg | 1 + config/coreboot/x301_4mb/target.cfg | 1 + config/coreboot/x301_8mb/target.cfg | 1 + 3 files changed, 3 insertions(+) diff --git a/config/coreboot/x301_16mb/target.cfg b/config/coreboot/x301_16mb/target.cfg index 6c267eca..0867e005 100644 --- a/config/coreboot/x301_16mb/target.cfg +++ b/config/coreboot/x301_16mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" status="untested" +release="n" diff --git a/config/coreboot/x301_4mb/target.cfg b/config/coreboot/x301_4mb/target.cfg index 6c267eca..0867e005 100644 --- a/config/coreboot/x301_4mb/target.cfg +++ b/config/coreboot/x301_4mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" status="untested" +release="n" diff --git a/config/coreboot/x301_8mb/target.cfg b/config/coreboot/x301_8mb/target.cfg index 6c267eca..0867e005 100644 --- a/config/coreboot/x301_8mb/target.cfg +++ b/config/coreboot/x301_8mb/target.cfg @@ -6,3 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" status="untested" +release="n" From 6e7b5c0b2422ce1852d402122403270f04d7cef1 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 18:24:04 +0100 Subject: [PATCH 0077/1319] Enable WiFi on HP EliteBook 8560w (GPIO config) angel pons said how to fix it. more info in the patch. works perfectly. i still see that scancode in dmesg and i guess i have to assign it to some function that sets software rfkill hw rfkill is no longer set. it's unblocked, and i can use wifi. just in time for the libreboot release. Signed-off-by: Leah Rowe --- .../patches/0044-hp-8560w-turn-on-wifi.patch | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch diff --git a/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch b/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch new file mode 100644 index 00000000..bb4a7b47 --- /dev/null +++ b/config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch @@ -0,0 +1,47 @@ +From 4ccef4fffd98071c339cb4135e2d8c805e554378 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 3 May 2024 17:45:52 +0100 +Subject: [PATCH 1/1] hp/8560w: turn on wifi + +according to angel pons, this gpio is WLAN_TRN_OFF# +and setting it high will make wifi work. testing with +this change as suggested by angel. see: + +https://review.coreboot.org/c/coreboot/+/39398/4/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c#158 + +if it makes it into a libreboot release, you can assume +the fix works. right now we have this problem: + +https://codeberg.org/libreboot/lbmk/issues/201 + +Riku reported: + +[ 333.890080] atkbd serio0: Unknown key pressed (translated set 2, code 0xf8 on isa0060/serio0). +[ 333.890102] atkbd serio0: Use 'setkeycodes e078 ' to make it known. +[ 334.104069] atkbd serio0: Unknown key released (translated set 2, code 0xf8 on isa0060/serio0). +[ 334.104090] atkbd serio0: Use 'setkeycodes e078 ' to make it known. + +The wifi stays to hardblocked in rfkill. When the wireless button +is pressed, nothing changes except for these lines in dmesg. + +Signed-off-by: Leah Rowe +--- + src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c +index 560d668d6f..10cd11ce48 100644 +--- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c ++++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c +@@ -155,7 +155,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, +- .gpio57 = GPIO_LEVEL_LOW, ++ .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + }; +-- +2.39.2 + From b379186a5c56b842161e4a08dfe5a65e5a912755 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 19:38:06 +0100 Subject: [PATCH 0078/1319] update hp machines to status=stable for release Signed-off-by: Leah Rowe --- config/coreboot/hp2170p_16mb/target.cfg | 2 +- config/coreboot/hp2170p_16mb/warn.txt | 1 - config/coreboot/hp2560p_8mb/target.cfg | 2 +- config/coreboot/hp2560p_8mb/warn.txt | 1 - config/coreboot/hp2570p_16mb/target.cfg | 2 +- config/coreboot/hp2570p_16mb/warn.txt | 1 - config/coreboot/hp8200sff_4mb/target.cfg | 2 +- config/coreboot/hp8200sff_4mb/warn.txt | 1 - config/coreboot/hp8200sff_8mb/target.cfg | 2 +- config/coreboot/hp8200sff_8mb/warn.txt | 1 - config/coreboot/hp820g2_12mb/warn.txt | 1 - config/coreboot/hp8300cmt_16mb/target.cfg | 2 +- config/coreboot/hp8300cmt_16mb/warn.txt | 1 - config/coreboot/hp8300usdt_16mb/target.cfg | 2 +- config/coreboot/hp8300usdt_16mb/warn.txt | 1 - config/coreboot/hp8460pintel_8mb/target.cfg | 2 +- config/coreboot/hp8460pintel_8mb/warn.txt | 1 - config/coreboot/hp8470pintel_16mb/target.cfg | 2 +- config/coreboot/hp8470pintel_16mb/warn.txt | 1 - config/coreboot/hp8560w_8mb/target.cfg | 2 +- config/coreboot/hp8560w_8mb/warn.txt | 1 - config/coreboot/hp9470m_16mb/target.cfg | 2 +- config/coreboot/hp9470m_16mb/warn.txt | 1 - 23 files changed, 11 insertions(+), 23 deletions(-) delete mode 100644 config/coreboot/hp2170p_16mb/warn.txt delete mode 100644 config/coreboot/hp2560p_8mb/warn.txt delete mode 100644 config/coreboot/hp2570p_16mb/warn.txt delete mode 100644 config/coreboot/hp8200sff_4mb/warn.txt delete mode 100644 config/coreboot/hp8200sff_8mb/warn.txt delete mode 100644 config/coreboot/hp820g2_12mb/warn.txt delete mode 100644 config/coreboot/hp8300cmt_16mb/warn.txt delete mode 100644 config/coreboot/hp8300usdt_16mb/warn.txt delete mode 100644 config/coreboot/hp8460pintel_8mb/warn.txt delete mode 100644 config/coreboot/hp8470pintel_16mb/warn.txt delete mode 100644 config/coreboot/hp8560w_8mb/warn.txt delete mode 100644 config/coreboot/hp9470m_16mb/warn.txt diff --git a/config/coreboot/hp2170p_16mb/target.cfg b/config/coreboot/hp2170p_16mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp2170p_16mb/target.cfg +++ b/config/coreboot/hp2170p_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp2170p_16mb/warn.txt b/config/coreboot/hp2170p_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp2170p_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp2560p_8mb/target.cfg b/config/coreboot/hp2560p_8mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp2560p_8mb/target.cfg +++ b/config/coreboot/hp2560p_8mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp2560p_8mb/warn.txt b/config/coreboot/hp2560p_8mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp2560p_8mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp2570p_16mb/target.cfg b/config/coreboot/hp2570p_16mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp2570p_16mb/target.cfg +++ b/config/coreboot/hp2570p_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp2570p_16mb/warn.txt b/config/coreboot/hp2570p_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp2570p_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8200sff_4mb/target.cfg b/config/coreboot/hp8200sff_4mb/target.cfg index 01583d37..04510c57 100644 --- a/config/coreboot/hp8200sff_4mb/target.cfg +++ b/config/coreboot/hp8200sff_4mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8200sff_4mb/warn.txt b/config/coreboot/hp8200sff_4mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8200sff_4mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8200sff_8mb/target.cfg b/config/coreboot/hp8200sff_8mb/target.cfg index 01583d37..04510c57 100644 --- a/config/coreboot/hp8200sff_8mb/target.cfg +++ b/config/coreboot/hp8200sff_8mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8200sff_8mb/warn.txt b/config/coreboot/hp8200sff_8mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8200sff_8mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp820g2_12mb/warn.txt b/config/coreboot/hp820g2_12mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp820g2_12mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8300cmt_16mb/target.cfg b/config/coreboot/hp8300cmt_16mb/target.cfg index 01583d37..04510c57 100644 --- a/config/coreboot/hp8300cmt_16mb/target.cfg +++ b/config/coreboot/hp8300cmt_16mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8300cmt_16mb/warn.txt b/config/coreboot/hp8300cmt_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8300cmt_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8300usdt_16mb/target.cfg b/config/coreboot/hp8300usdt_16mb/target.cfg index 01583d37..04510c57 100644 --- a/config/coreboot/hp8300usdt_16mb/target.cfg +++ b/config/coreboot/hp8300usdt_16mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8300usdt_16mb/warn.txt b/config/coreboot/hp8300usdt_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8300usdt_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8460pintel_8mb/target.cfg b/config/coreboot/hp8460pintel_8mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp8460pintel_8mb/target.cfg +++ b/config/coreboot/hp8460pintel_8mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8460pintel_8mb/warn.txt b/config/coreboot/hp8460pintel_8mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8460pintel_8mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8470pintel_16mb/target.cfg b/config/coreboot/hp8470pintel_16mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp8470pintel_16mb/target.cfg +++ b/config/coreboot/hp8470pintel_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8470pintel_16mb/warn.txt b/config/coreboot/hp8470pintel_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8470pintel_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp8560w_8mb/target.cfg b/config/coreboot/hp8560w_8mb/target.cfg index a352b46d..ea96b084 100644 --- a/config/coreboot/hp8560w_8mb/target.cfg +++ b/config/coreboot/hp8560w_8mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp8560w_8mb/warn.txt b/config/coreboot/hp8560w_8mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp8560w_8mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. diff --git a/config/coreboot/hp9470m_16mb/target.cfg b/config/coreboot/hp9470m_16mb/target.cfg index e6f295cf..5cdb7116 100644 --- a/config/coreboot/hp9470m_16mb/target.cfg +++ b/config/coreboot/hp9470m_16mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" grub_timeout=10 -status="unstable" +status="stable" diff --git a/config/coreboot/hp9470m_16mb/warn.txt b/config/coreboot/hp9470m_16mb/warn.txt deleted file mode 100644 index 68f0b1fe..00000000 --- a/config/coreboot/hp9470m_16mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -HP EliteBook 8560w has broken wifi. See issue https://codeberg.org/libreboot/lbmk/issues/201 - may affect other HP machines so setting them as unstable. The machines should otherwise boot reliably and you can use them - if wifi doesn't work, you can use a usb wifi dongle or, on HP desktops, use an add-on wifi card. From 780e03fe1e6222d353f56d14b003efc70dc4e975 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 3 May 2024 23:00:27 +0100 Subject: [PATCH 0079/1319] remove x220edp/x230edp (keep regular x220/x230) nitrocaster boards are hard to find nowadays and i'm not comfortable supporting the knockoff chinese gear; quality varies greatly, and i can't know how reliable they are. nitrocaster has been out of business so it's just not viable to support this mod anymore. in fact, keeping the eDP-based targets is a liability to libreboot. regular x220/x230 (non-eDP-modded) are retained. the eDP modkit from nitrocaster let you use eDP screens instead of lvds, on thinkpad x220 and x230, letting you use higher resolution screens. older lbmk revs can still be used, if you happen to come across one of these boards. i only recommend using the official nitrocaster board, if youcan find one unused. ymmv with the chinese gear. better just use an unmodded x230 or get a different machine. Signed-off-by: Leah Rowe --- ...13-lenovo-x230-introduce-FHD-variant.patch | 198 ----- ...the-data.vbt-path-for-the-EDP-varian.patch | 25 - ...ation-introduced-similar-to-x230_edp.patch | 164 ----- .../r400_16mb/config/libgfxinit_corebootfb | 2 - .../r400_16mb/config/libgfxinit_txtmode | 2 - .../r400_4mb/config/libgfxinit_corebootfb | 2 - .../r400_4mb/config/libgfxinit_txtmode | 2 - .../r400_8mb/config/libgfxinit_corebootfb | 2 - .../r400_8mb/config/libgfxinit_txtmode | 2 - .../r500_4mb/config/libgfxinit_corebootfb | 2 - .../r500_4mb/config/libgfxinit_txtmode | 2 - .../t400_16mb/config/libgfxinit_corebootfb | 2 - .../t400_16mb/config/libgfxinit_txtmode | 2 - .../t400_4mb/config/libgfxinit_corebootfb | 2 - .../t400_4mb/config/libgfxinit_txtmode | 2 - .../t400_8mb/config/libgfxinit_corebootfb | 2 - .../t400_8mb/config/libgfxinit_txtmode | 2 - .../t420_8mb/config/libgfxinit_corebootfb | 2 - .../t420s_8mb/config/libgfxinit_corebootfb | 2 - .../t420s_8mb/config/libgfxinit_txtmode | 2 - .../t430_12mb/config/libgfxinit_corebootfb | 2 - .../t430_12mb/config/libgfxinit_txtmode | 2 - .../config/libgfxinit_corebootfb | 2 - .../t440pbmrc_12mb/config/libgfxinit_txtmode | 2 - .../config/libgfxinit_corebootfb | 2 - .../t440pmrc_12mb/config/libgfxinit_txtmode | 2 - .../t500_16mb/config/libgfxinit_corebootfb | 2 - .../t500_16mb/config/libgfxinit_txtmode | 2 - .../t500_4mb/config/libgfxinit_corebootfb | 2 - .../t500_4mb/config/libgfxinit_txtmode | 2 - .../t500_8mb/config/libgfxinit_corebootfb | 2 - .../t500_8mb/config/libgfxinit_txtmode | 2 - .../t520_8mb/config/libgfxinit_corebootfb | 2 - .../t520_8mb/config/libgfxinit_txtmode | 2 - .../t530_12mb/config/libgfxinit_corebootfb | 2 - .../t530_12mb/config/libgfxinit_txtmode | 2 - .../w500_16mb/config/libgfxinit_corebootfb | 2 - .../w500_16mb/config/libgfxinit_txtmode | 2 - .../w500_4mb/config/libgfxinit_corebootfb | 2 - .../w500_4mb/config/libgfxinit_txtmode | 2 - .../w500_8mb/config/libgfxinit_corebootfb | 2 - .../w500_8mb/config/libgfxinit_txtmode | 2 - .../w530_12mb/config/libgfxinit_corebootfb | 2 - .../w530_12mb/config/libgfxinit_txtmode | 2 - .../config/libgfxinit_corebootfb | 2 - .../w541bmrc_12mb/config/libgfxinit_txtmode | 2 - .../w541mrc_12mb/config/libgfxinit_corebootfb | 2 - .../w541mrc_12mb/config/libgfxinit_txtmode | 2 - .../x200_16mb/config/libgfxinit_corebootfb | 2 - .../x200_16mb/config/libgfxinit_txtmode | 2 - .../x200_4mb/config/libgfxinit_corebootfb | 2 - .../x200_4mb/config/libgfxinit_txtmode | 2 - .../x200_8mb/config/libgfxinit_corebootfb | 2 - .../x200_8mb/config/libgfxinit_txtmode | 2 - .../x220_8mb/config/libgfxinit_corebootfb | 2 - .../x220_8mb/config/libgfxinit_txtmode | 2 - .../x220edp_8mb/config/libgfxinit_corebootfb | 674 ------------------ .../x220edp_8mb/config/libgfxinit_txtmode | 671 ----------------- config/coreboot/x220edp_8mb/target.cfg | 9 - config/coreboot/x220edp_8mb/warn.txt | 1 - .../x230_12mb/config/libgfxinit_corebootfb | 2 - .../x230_12mb/config/libgfxinit_txtmode | 2 - .../x230_16mb/config/libgfxinit_corebootfb | 2 - .../x230_16mb/config/libgfxinit_txtmode | 2 - .../x230edp_12mb/config/libgfxinit_corebootfb | 673 ----------------- .../x230edp_12mb/config/libgfxinit_txtmode | 670 ----------------- config/coreboot/x230edp_12mb/target.cfg | 9 - .../x230t_12mb/config/libgfxinit_corebootfb | 2 - .../x230t_12mb/config/libgfxinit_txtmode | 2 - .../x230t_16mb/config/libgfxinit_corebootfb | 2 - .../x230t_16mb/config/libgfxinit_txtmode | 2 - .../x301_16mb/config/libgfxinit_corebootfb | 2 - .../x301_16mb/config/libgfxinit_txtmode | 2 - .../x301_4mb/config/libgfxinit_corebootfb | 2 - .../x301_4mb/config/libgfxinit_txtmode | 2 - .../x301_8mb/config/libgfxinit_corebootfb | 2 - .../x301_8mb/config/libgfxinit_txtmode | 2 - config/vendor/sources | 4 +- 78 files changed, 2 insertions(+), 3230 deletions(-) delete mode 100644 config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch delete mode 100644 config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch delete mode 100644 config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch delete mode 100644 config/coreboot/x220edp_8mb/config/libgfxinit_corebootfb delete mode 100644 config/coreboot/x220edp_8mb/config/libgfxinit_txtmode delete mode 100644 config/coreboot/x220edp_8mb/target.cfg delete mode 100644 config/coreboot/x220edp_8mb/warn.txt delete mode 100644 config/coreboot/x230edp_12mb/config/libgfxinit_corebootfb delete mode 100644 config/coreboot/x230edp_12mb/config/libgfxinit_txtmode delete mode 100644 config/coreboot/x230edp_12mb/target.cfg diff --git a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch b/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch deleted file mode 100644 index a3810417..00000000 --- a/config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch +++ /dev/null @@ -1,198 +0,0 @@ -From 7b9003f98c7c685b2fe56781f3b0916018037b72 Mon Sep 17 00:00:00 2001 -From: Alexander Couzens -Date: Sat, 19 Mar 2022 13:42:33 +0000 -Subject: [PATCH 13/30] lenovo/x230: introduce FHD variant - -There is a modification for the x230 which uses the 2nd DP from the dock -as the integrated panel's connection, which allows using a custom eDP -panel instead of the stock LVDS display. - -There are several adapter boards present on the market and all of them -uses the same method of enabling the custom eDP panel. - -To make this work with coreboot, the internal LVDS connector should be -disabled in libgfxinit. The VBT has been modified as well, which allows -brightness controls to work out of the box. - -The modifications done to the VBT are: -- Remove the LVDS port entry. -- Move the DP-3 (which is the 2nd DP on the dock) entry to the first - position on the list. -- Set the DP-3 as internally connected. - -This has been reported to work with the following panels: -- LP125WF2-SPB4 (1920*1080, 12.5") -- LQ125T1JW02 (2560*1440, 12.5") -- LQ133M1JW21 (1920*1080, 13.3") -- LTN133HL10-201 (1920*1080, 13.3") -- B133HAN04.6 (1920*1080, 13.3") -- B133QAN02.0 (2560*1600, 13.3") - -Other eDP panels not on this list should work as well. - -Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 -Signed-off-by: Alexander Couzens -Signed-off-by: Felix Singer ---- - src/mainboard/lenovo/x230/Kconfig | 15 ++++++++----- - src/mainboard/lenovo/x230/Kconfig.name | 3 +++ - src/mainboard/lenovo/x230/Makefile.mk | 5 +++++ - .../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes - .../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++ - 5 files changed, 38 insertions(+), 6 deletions(-) - create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt - create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads - -diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig -index 279095629b..acfd0ed561 100644 ---- a/src/mainboard/lenovo/x230/Kconfig -+++ b/src/mainboard/lenovo/x230/Kconfig -@@ -1,4 +1,4 @@ --if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S -+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP - - config BOARD_SPECIFIC_OPTIONS - def_bool y -@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS - select H8_HAS_BAT_THRESHOLDS_IMPL - select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S - select NO_UART_ON_SUPERIO -- select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T -+ select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP - select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE -@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS - select INTEL_INT15 - select DRIVERS_RICOH_RCE822 - select MEMORY_MAPPED_TPM -- select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T -+ select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T - select INTEL_GMA_HAVE_VBT -@@ -47,17 +47,20 @@ config MAINBOARD_DIR - default "lenovo/x230" - - config VARIANT_DIR -- default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T -+ default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP - default "x230s" if BOARD_LENOVO_X230S - - config MAINBOARD_PART_NUMBER -- default "ThinkPad X230" if BOARD_LENOVO_X230 -+ default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP - default "ThinkPad X230t" if BOARD_LENOVO_X230T - default "ThinkPad X230s" if BOARD_LENOVO_X230S - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - -+config INTEL_GMA_VBT_FILE -+ default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP -+ - config USBDEBUG_HCD_INDEX - int - default 2 -@@ -79,4 +82,4 @@ config PS2M_EISAID - config THINKPADEC_HKEY_EISAID - default "LEN0068" - --endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S -+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP -diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name -index 1a01436879..e7290a12dd 100644 ---- a/src/mainboard/lenovo/x230/Kconfig.name -+++ b/src/mainboard/lenovo/x230/Kconfig.name -@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T - - config BOARD_LENOVO_X230S - bool "ThinkPad X230s" -+ -+config BOARD_LENOVO_X230_EDP -+ bool "ThinkPad X230 eDP Mod (2K/FHD)" -diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk -index 8e801f145d..6e6f9f90b9 100644 ---- a/src/mainboard/lenovo/x230/Makefile.mk -+++ b/src/mainboard/lenovo/x230/Makefile.mk -@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c - romstage-y += variants/$(VARIANT_DIR)/early_init.c - romstage-y += variants/$(VARIANT_DIR)/gpio.c - ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -+ -+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y) -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads -+else - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -+endif -diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186 -GIT binary patch -literal 4281 -zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK! -zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc -zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi -z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx} -z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD -z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@ -zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT -zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}( -z?1954MnX?xAuk79(< -zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2NpCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L -zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo8vk&YfS^jD1^rM=s>0ytuB(VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I_cUj9w4&M7&s8K0k@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H- -zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P -z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8 -zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(Uvj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH -z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H -zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?## Disabled); -+ -+end GMA.Mainboard; --- -2.39.2 - diff --git a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch b/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch deleted file mode 100644 index f439f2e7..00000000 --- a/config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9959fe252cceca7005b63e3313f7f95114f1f93c Mon Sep 17 00:00:00 2001 -From: Alexei Sorokin -Date: Sun, 27 Nov 2022 18:36:26 +0300 -Subject: [PATCH 14/30] lenovo/x230: fix the data.vbt path for the EDP variant - ---- - src/mainboard/lenovo/x230/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig -index acfd0ed561..34108c3c04 100644 ---- a/src/mainboard/lenovo/x230/Kconfig -+++ b/src/mainboard/lenovo/x230/Kconfig -@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - - config INTEL_GMA_VBT_FILE -- default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP -+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP - - config USBDEBUG_HCD_INDEX - int --- -2.39.2 - diff --git a/config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch b/config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch deleted file mode 100644 index e0d39892..00000000 --- a/config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch +++ /dev/null @@ -1,164 +0,0 @@ -From f07ed32c36978327709a113967ec40e5ba8d828e Mon Sep 17 00:00:00 2001 -From: risapav -Date: Sun, 17 Dec 2023 16:54:07 +0100 -Subject: [PATCH 29/30] x220_edp modification introduced, similar to x230_edp - ---- - src/mainboard/lenovo/x220/Kconfig | 13 ++++++----- - src/mainboard/lenovo/x220/Kconfig.name | 3 +++ - src/mainboard/lenovo/x220/Makefile.mk | 6 +++++ - .../lenovo/x220/variants/x220_edp/data.vbt | Bin 0 -> 4281 bytes - .../x220/variants/x220_edp/gma-mainboard.ads | 21 ++++++++++++++++++ - 5 files changed, 38 insertions(+), 5 deletions(-) - create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/data.vbt - create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads - -diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig -index eeb55b4393..bc73a47df9 100644 ---- a/src/mainboard/lenovo/x220/Kconfig -+++ b/src/mainboard/lenovo/x220/Kconfig -@@ -1,4 +1,4 @@ --if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 -+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP - - config BOARD_SPECIFIC_OPTIONS - def_bool y -@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS - select DRIVERS_RICOH_RCE822 - select EC_LENOVO_H8 - select EC_LENOVO_PMH7 -- select GFX_GMA_PANEL_1_ON_LVDS -+ select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 - select H8_HAS_BAT_THRESHOLDS_IMPL - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES -@@ -41,19 +41,22 @@ config MAINBOARD_DIR - default "lenovo/x220" - - config VARIANT_DIR -- default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I -+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X220_EDP - default "x1" if BOARD_LENOVO_X1 - - config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - - config MAINBOARD_PART_NUMBER -- default "ThinkPad X220" if BOARD_LENOVO_X220 -+ default "ThinkPad X220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220_EDP - default "ThinkPad X220i" if BOARD_LENOVO_X220I - default "ThinkPad X1" if BOARD_LENOVO_X1 - - config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -+ -+config INTEL_GMA_VBT_FILE -+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x220_edp/data.vbt" if BOARD_LENOVO_X220_EDP - - config USBDEBUG_HCD_INDEX - int -@@ -75,4 +78,4 @@ config PS2K_EISAID - config PS2M_EISAID - default "LEN0020" - --endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 -+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP -diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name -index 988ac4fb55..cd501954e0 100644 ---- a/src/mainboard/lenovo/x220/Kconfig.name -+++ b/src/mainboard/lenovo/x220/Kconfig.name -@@ -6,3 +6,6 @@ config BOARD_LENOVO_X220I - - config BOARD_LENOVO_X1 - bool "ThinkPad X1" -+ -+config BOARD_LENOVO_X220_EDP -+ bool "ThinkPad X220 eDP Mod (2K/FHD)" -diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk -index b104bb52a9..052bf17a22 100644 ---- a/src/mainboard/lenovo/x220/Makefile.mk -+++ b/src/mainboard/lenovo/x220/Makefile.mk -@@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c - romstage-y += variants/$(VARIANT_DIR)/gpio.c - romstage-y += variants/$(VARIANT_DIR)/romstage.c - -+ -+ifeq ($(CONFIG_BOARD_LENOVO_X220_EDP),y) -+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x220_edp/gma-mainboard.ads -+else - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -+endif -+ - bootblock-y += early_init.c - romstage-y += early_init.c -diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt b/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt -new file mode 100644 -index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186 -GIT binary patch -literal 4281 -zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK! -zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc -zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi -z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx} -z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD -z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@ -zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT -zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}( -z?1954MnX?xAuk79(< -zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2NpCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L -zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo8vk&YfS^jD1^rM=s>0ytuB(VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I_cUj9w4&M7&s8K0k@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H- -zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P -z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8 -zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(Uvj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH -z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H -zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?## Disabled); -+ -+end GMA.Mainboard; --- -2.39.2 - diff --git a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb index d0b3833f..3215ca68 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_16mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r400_16mb/config/libgfxinit_txtmode b/config/coreboot/r400_16mb/config/libgfxinit_txtmode index 06ae932d..4b6b5e6f 100644 --- a/config/coreboot/r400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_16mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb index dfe2b496..cd0beb97 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_4mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r400_4mb/config/libgfxinit_txtmode b/config/coreboot/r400_4mb/config/libgfxinit_txtmode index 6ec26a81..37c7462d 100644 --- a/config/coreboot/r400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_4mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb index c18a4e8c..665468d9 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r400_8mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r400_8mb/config/libgfxinit_txtmode b/config/coreboot/r400_8mb/config/libgfxinit_txtmode index ac0b262b..5b6f8870 100644 --- a/config/coreboot/r400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/r400_8mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_R400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb index aa31b675..1b500abb 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/r500_4mb/config/libgfxinit_corebootfb @@ -194,11 +194,9 @@ CONFIG_BOARD_LENOVO_R500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/r500_4mb/config/libgfxinit_txtmode b/config/coreboot/r500_4mb/config/libgfxinit_txtmode index fa51741a..5ec9de19 100644 --- a/config/coreboot/r500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/r500_4mb/config/libgfxinit_txtmode @@ -192,11 +192,9 @@ CONFIG_BOARD_LENOVO_R500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb index 25668253..4c3fe7d9 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_16mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_16mb/config/libgfxinit_txtmode b/config/coreboot/t400_16mb/config/libgfxinit_txtmode index 921bda4c..e5ef8b70 100644 --- a/config/coreboot/t400_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_16mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb index 29cb073c..598ee337 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_4mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_4mb/config/libgfxinit_txtmode b/config/coreboot/t400_4mb/config/libgfxinit_txtmode index 551265f7..30f21fc1 100644 --- a/config/coreboot/t400_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_4mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb index b1a2f829..5e198ab7 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t400_8mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t400_8mb/config/libgfxinit_txtmode b/config/coreboot/t400_8mb/config/libgfxinit_txtmode index 52a322dd..1aa474d7 100644 --- a/config/coreboot/t400_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t400_8mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb index 8cbabbf6..2a5b9aca 100644 --- a/config/coreboot/t420_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420_8mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_BOARD_LENOVO_T420=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb index 9ada1ffe..bfe34d36 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t420s_8mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_BOARD_LENOVO_T420S=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode index ba2f64a0..b1cfe169 100644 --- a/config/coreboot/t420s_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t420s_8mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_BOARD_LENOVO_T420S=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb index af6b1569..a293e1dd 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t430_12mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T430=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/t430_12mb/config/libgfxinit_txtmode b/config/coreboot/t430_12mb/config/libgfxinit_txtmode index 1277a19b..bbd70386 100644 --- a/config/coreboot/t430_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t430_12mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T430=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb index 5026c68e..0074fb6c 100644 --- a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_corebootfb @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode index a6b1bf70..0c7e6141 100644 --- a/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440pbmrc_12mb/config/libgfxinit_txtmode @@ -189,11 +189,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb index d7124b0f..6bf1dca1 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_corebootfb @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode index fc7db117..861a5d5e 100644 --- a/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t440pmrc_12mb/config/libgfxinit_txtmode @@ -189,11 +189,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_T440P=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb index 98052d20..4b1d2147 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_16mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t500_16mb/config/libgfxinit_txtmode b/config/coreboot/t500_16mb/config/libgfxinit_txtmode index b545fe6f..243d6bf0 100644 --- a/config/coreboot/t500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_16mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb index 3a0a094b..7704b0e0 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_4mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t500_4mb/config/libgfxinit_txtmode b/config/coreboot/t500_4mb/config/libgfxinit_txtmode index e6b4b8d7..5b5b323c 100644 --- a/config/coreboot/t500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_4mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb index d7e09d36..dcac539e 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t500_8mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t500_8mb/config/libgfxinit_txtmode b/config/coreboot/t500_8mb/config/libgfxinit_txtmode index 387e103e..081b6a0a 100644 --- a/config/coreboot/t500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t500_8mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb index 886a7ee6..bc3ef394 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t520_8mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_BOARD_LENOVO_T520=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" diff --git a/config/coreboot/t520_8mb/config/libgfxinit_txtmode b/config/coreboot/t520_8mb/config/libgfxinit_txtmode index df7b0b68..8c8a6145 100644 --- a/config/coreboot/t520_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/t520_8mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_BOARD_LENOVO_T520=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" diff --git a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb index 6b3e4eee..0d3a372a 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/t530_12mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_T530=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/t530_12mb/config/libgfxinit_txtmode b/config/coreboot/t530_12mb/config/libgfxinit_txtmode index 14b0bc33..fc8c903f 100644 --- a/config/coreboot/t530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/t530_12mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_T530=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb index f7e6b528..cc011456 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_16mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w500_16mb/config/libgfxinit_txtmode b/config/coreboot/w500_16mb/config/libgfxinit_txtmode index c9d9ca70..d63b87ea 100644 --- a/config/coreboot/w500_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_16mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb index 4aab04bf..7b1a2903 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_4mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w500_4mb/config/libgfxinit_txtmode b/config/coreboot/w500_4mb/config/libgfxinit_txtmode index 2cbbd0f4..53e1a547 100644 --- a/config/coreboot/w500_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_4mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb index b23b693b..1e44e5c2 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w500_8mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w500_8mb/config/libgfxinit_txtmode b/config/coreboot/w500_8mb/config/libgfxinit_txtmode index 5214b715..d7066e43 100644 --- a/config/coreboot/w500_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/w500_8mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_W500=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb index 1d42dd5d..16127d90 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w530_12mb/config/libgfxinit_corebootfb @@ -195,11 +195,9 @@ CONFIG_BOARD_LENOVO_W530=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/w530_12mb/config/libgfxinit_txtmode b/config/coreboot/w530_12mb/config/libgfxinit_txtmode index 632d8dfc..13cfb5d9 100644 --- a/config/coreboot/w530_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w530_12mb/config/libgfxinit_txtmode @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_W530=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb index a5342fbb..05de6472 100644 --- a/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_corebootfb @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode index 60686a0f..88f676c2 100644 --- a/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541bmrc_12mb/config/libgfxinit_txtmode @@ -189,11 +189,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb index 3f0cf31a..119ad89f 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_corebootfb @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode index e0d0c538..f04da340 100644 --- a/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/w541mrc_12mb/config/libgfxinit_txtmode @@ -189,11 +189,9 @@ CONFIG_BOARD_LENOVO_THINKPAD_W541=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_BOARD_LENOVO_HASWELL_COMMON=y CONFIG_VBOOT_SLOTS_RW_AB=y diff --git a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb index 8dc3aca4..6dcc4bca 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_16mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x200_16mb/config/libgfxinit_txtmode b/config/coreboot/x200_16mb/config/libgfxinit_txtmode index 49d18531..a7c23af7 100644 --- a/config/coreboot/x200_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_16mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb index f8a6f3fd..b522fff3 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_4mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x200_4mb/config/libgfxinit_txtmode b/config/coreboot/x200_4mb/config/libgfxinit_txtmode index fd808241..e7d4a538 100644 --- a/config/coreboot/x200_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_4mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb index 7640b94c..12e8cb6e 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x200_8mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x200_8mb/config/libgfxinit_txtmode b/config/coreboot/x200_8mb/config/libgfxinit_txtmode index 394ba67d..ca608667 100644 --- a/config/coreboot/x200_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x200_8mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb index c7eb54fc..3aaac0c4 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x220_8mb/config/libgfxinit_corebootfb @@ -197,11 +197,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 CONFIG_BOARD_LENOVO_X220=y # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x220_8mb/config/libgfxinit_txtmode b/config/coreboot/x220_8mb/config/libgfxinit_txtmode index 7d29db4c..0e679481 100644 --- a/config/coreboot/x220_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x220_8mb/config/libgfxinit_txtmode @@ -195,11 +195,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 CONFIG_BOARD_LENOVO_X220=y # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x220edp_8mb/config/libgfxinit_corebootfb b/config/coreboot/x220edp_8mb/config/libgfxinit_corebootfb deleted file mode 100644 index b9567e49..00000000 --- a/config/coreboot/x220edp_8mb/config/libgfxinit_corebootfb +++ /dev/null @@ -1,674 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# coreboot configuration -# - -# -# General setup -# -CONFIG_COREBOOT_BUILD=y -CONFIG_LOCALVERSION="" -CONFIG_CBFS_PREFIX="fallback" -CONFIG_COMPILER_GCC=y -# CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y -# CONFIG_ANY_TOOLCHAIN is not set -# CONFIG_CCACHE is not set -# CONFIG_IWYU is not set -# CONFIG_FMD_GENPARSER is not set -# CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE_LZMA=y -# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y -CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_COLLECT_TIMESTAMPS=y -# CONFIG_TIMESTAMPS_ON_CONSOLE is not set -CONFIG_USE_BLOBS=y -# CONFIG_USE_AMD_BLOBS is not set -# CONFIG_USE_QC_BLOBS is not set -# CONFIG_COVERAGE is not set -# CONFIG_UBSAN is not set -CONFIG_HAVE_ASAN_IN_RAMSTAGE=y -# CONFIG_ASAN is not set -CONFIG_NO_STAGE_CACHE=y -# CONFIG_TSEG_STAGE_CACHE is not set -# CONFIG_UPDATE_IMAGE is not set -# CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set - -# -# Software Bill Of Materials (SBOM) -# -# CONFIG_SBOM is not set -# end of Software Bill Of Materials (SBOM) -# end of General setup - -# -# Mainboard -# - -# -# Important: Run 'make distclean' before switching boards -# -# CONFIG_VENDOR_51NB is not set -# CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set -# CONFIG_VENDOR_AMD is not set -# CONFIG_VENDOR_AOPEN is not set -# CONFIG_VENDOR_APPLE is not set -# CONFIG_VENDOR_ASROCK is not set -# CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BIOSTAR is not set -# CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set -# CONFIG_VENDOR_CAVIUM is not set -# CONFIG_VENDOR_CLEVO is not set -# CONFIG_VENDOR_COMPULAB is not set -# CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_EMULATION is not set -# CONFIG_VENDOR_EXAMPLE is not set -# CONFIG_VENDOR_FACEBOOK is not set -# CONFIG_VENDOR_FOXCONN is not set -# CONFIG_VENDOR_GETAC is not set -# CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GOOGLE is not set -# CONFIG_VENDOR_HP is not set -# CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set -# CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set -# CONFIG_VENDOR_KONTRON is not set -CONFIG_VENDOR_LENOVO=y -# CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_MSI is not set -# CONFIG_VENDOR_OCP is not set -# CONFIG_VENDOR_OPENCELLULAR is not set -# CONFIG_VENDOR_PACKARDBELL is not set -# CONFIG_VENDOR_PCENGINES is not set -# CONFIG_VENDOR_PINE64 is not set -# CONFIG_VENDOR_PORTWELL is not set -# CONFIG_VENDOR_PRODRIVE is not set -# CONFIG_VENDOR_PROTECTLI is not set -# CONFIG_VENDOR_PURISM is not set -# CONFIG_VENDOR_RAZER is not set -# CONFIG_VENDOR_RODA is not set -# CONFIG_VENDOR_SAMSUNG is not set -# CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SIEMENS is not set -# CONFIG_VENDOR_SIFIVE is not set -# CONFIG_VENDOR_STARLABS is not set -# CONFIG_VENDOR_SUPERMICRO is not set -# CONFIG_VENDOR_SYSTEM76 is not set -# CONFIG_VENDOR_TI is not set -# CONFIG_VENDOR_UP is not set -CONFIG_BOARD_SPECIFIC_OPTIONS=y -CONFIG_MAINBOARD_FAMILY="ThinkPad X220" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X220" -CONFIG_MAINBOARD_VERSION="1.0" -CONFIG_MAINBOARD_DIR="lenovo/x220" -CONFIG_VGA_BIOS_ID="8086,0126" -CONFIG_DIMM_MAX=4 -CONFIG_DIMM_SPD_SIZE=256 -CONFIG_FMDFILE="" -# CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0x7E0000 -CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 -CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 -CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set -CONFIG_POST_DEVICE=y -CONFIG_POST_IO=y -CONFIG_DEVICETREE="devicetree.cb" -# CONFIG_VBOOT is not set -CONFIG_VARIANT_DIR="x220" -CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" -# CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_DRAM_RESET_GATE_GPIO=10 -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/x220_edp/data.vbt" -CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" -CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 -CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 -# CONFIG_CONSOLE_POST is not set -CONFIG_TPM_PIRQ=0x0 -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="LEN0020" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" -CONFIG_VBOOT_SLOTS_RW_A=y -CONFIG_DCACHE_RAM_BASE=0xfefe0000 -CONFIG_DCACHE_RAM_SIZE=0x20000 -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 -CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 -CONFIG_HAVE_INTEL_FIRMWARE=y -CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 -CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_DRIVERS_INTEL_WIFI is not set -CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd" -CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin" -CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe" -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X220" -CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set -# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set -# CONFIG_BOARD_LENOVO_L520 is not set -# CONFIG_BOARD_LENOVO_S230U is not set -# CONFIG_BOARD_LENOVO_T400 is not set -# CONFIG_BOARD_LENOVO_T500 is not set -# CONFIG_BOARD_LENOVO_R400 is not set -# CONFIG_BOARD_LENOVO_R500 is not set -# CONFIG_BOARD_LENOVO_W500 is not set -# CONFIG_BOARD_LENOVO_T410 is not set -# CONFIG_BOARD_LENOVO_T420 is not set -# CONFIG_BOARD_LENOVO_T420S is not set -# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set -# CONFIG_BOARD_LENOVO_T430S is not set -# CONFIG_BOARD_LENOVO_T431S is not set -# CONFIG_BOARD_LENOVO_T520 is not set -# CONFIG_BOARD_LENOVO_W520 is not set -# CONFIG_BOARD_LENOVO_T530 is not set -# CONFIG_BOARD_LENOVO_W530 is not set -# CONFIG_BOARD_LENOVO_T60 is not set -# CONFIG_BOARD_LENOVO_Z61T is not set -# CONFIG_BOARD_LENOVO_R60 is not set -# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set -# CONFIG_BOARD_LENOVO_X131E is not set -# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set -# CONFIG_BOARD_LENOVO_X200 is not set -# CONFIG_BOARD_LENOVO_X301 is not set -# CONFIG_BOARD_LENOVO_X201 is not set -# CONFIG_BOARD_LENOVO_X220 is not set -# CONFIG_BOARD_LENOVO_X220I is not set -# CONFIG_BOARD_LENOVO_X1 is not set -CONFIG_BOARD_LENOVO_X220_EDP=y -# CONFIG_BOARD_LENOVO_X230 is not set -# CONFIG_BOARD_LENOVO_X230T is not set -# CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set -# CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_DRIVER_LENOVO_SERIALS=y -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_GFX_GMA_PANEL_1_PORT="eDP" -CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 -CONFIG_EC_GPE_SCI=0x50 -# CONFIG_TPM_MEASURED_BOOT is not set -CONFIG_BOARD_ROMSIZE_KB_8192=y -# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set -CONFIG_COREBOOT_ROMSIZE_KB_8192=y -# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set -CONFIG_COREBOOT_ROMSIZE_KB=8192 -CONFIG_ROM_SIZE=0x00800000 -CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y -CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y -CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set -# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set -CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 -# end of Mainboard - -CONFIG_SYSTEM_TYPE_LAPTOP=y - -# -# Chipset -# - -# -# SoC -# -CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" -CONFIG_CBFS_MCACHE_SIZE=0x4000 -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_SMM_RESERVED_SIZE=0x100000 -CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set -CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" -CONFIG_STACK_SIZE=0x2000 -CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 -CONFIG_INTEL_GMA_BCLV_WIDTH=16 -CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 -CONFIG_INTEL_GMA_BCLM_WIDTH=16 -CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 -CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 -CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 -CONFIG_FIXED_SMBUS_IO_BASE=0x400 -CONFIG_CBFS_CACHE_ALIGN=8 - -# -# CPU -# -CONFIG_CPU_INTEL_MODEL_206AX=y -CONFIG_CPU_INTEL_COMMON=y -CONFIG_ENABLE_VMX=y -CONFIG_SET_IA32_FC_LOCK_BIT=y -CONFIG_SET_MSR_AESNI_LOCK_BIT=y -CONFIG_CPU_INTEL_COMMON_TIMEBASE=y -CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y -CONFIG_PARALLEL_MP=y -CONFIG_XAPIC_ONLY=y -# CONFIG_X2APIC_ONLY is not set -# CONFIG_X2APIC_RUNTIME is not set -# CONFIG_X2APIC_LATE_WORKAROUND is not set -CONFIG_UDELAY_TSC=y -CONFIG_TSC_MONOTONIC_TIMER=y -CONFIG_TSC_SYNC_MFENCE=y -CONFIG_HAVE_SMI_HANDLER=y -CONFIG_SMM_TSEG=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 -CONFIG_AP_STACK_SIZE=0x800 -CONFIG_SMP=y -CONFIG_SSE=y -CONFIG_SSE2=y -CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y -CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y -CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set -# CONFIG_CPU_MICROCODE_CBFS_NONE is not set - -# -# Northbridge -# -CONFIG_USE_NATIVE_RAMINIT=y -CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y -# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set -# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set -CONFIG_RAMINIT_ENABLE_ECC=y - -# -# Southbridge -# -CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y -CONFIG_SOUTHBRIDGE_INTEL_C216=y -CONFIG_HIDE_MEI_ON_ERROR=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y -CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y -# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set -CONFIG_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_TCO_SPACE_NOT_YET_SPLIT=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y -CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 -CONFIG_RCBA_LENGTH=0x4000 - -# -# Super I/O -# - -# -# Embedded Controllers -# -CONFIG_EC_ACPI=y -CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set -# CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_EC_LENOVO_PMH7=y - -# -# Intel Firmware -# -CONFIG_HAVE_ME_BIN=y -# CONFIG_STITCH_ME_BIN is not set -# CONFIG_CHECK_ME is not set -# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set -# CONFIG_USE_ME_CLEANER is not set -CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y -CONFIG_HAVE_GBE_BIN=y -# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set -# CONFIG_LOCK_MANAGEMENT_ENGINE is not set -CONFIG_UNLOCK_FLASH_REGIONS=y -CONFIG_ARCH_X86=y -CONFIG_ARCH_BOOTBLOCK_X86_32=y -CONFIG_ARCH_VERSTAGE_X86_32=y -CONFIG_ARCH_ROMSTAGE_X86_32=y -CONFIG_ARCH_POSTCAR_X86_32=y -CONFIG_ARCH_RAMSTAGE_X86_32=y -CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 -CONFIG_PC80_SYSTEM=y -CONFIG_HAVE_CMOS_DEFAULT=y -CONFIG_POSTCAR_STAGE=y -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_COLLECT_TIMESTAMPS_TSC=y -CONFIG_HAVE_CF9_RESET=y -CONFIG_DEBUG_HW_BREAKPOINTS=y -CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set -# end of Chipset - -# -# Devices -# -CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y -CONFIG_HAVE_LINEAR_FRAMEBUFFER=y -CONFIG_MAINBOARD_HAS_LIBGFXINIT=y -CONFIG_MAINBOARD_USE_LIBGFXINIT=y -# CONFIG_VGA_ROM_RUN is not set -# CONFIG_NO_GFX_INIT is not set -CONFIG_NO_EARLY_GFX_INIT=y - -# -# Display -# -# CONFIG_VGA_TEXT_FRAMEBUFFER is not set -CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y -CONFIG_LINEAR_FRAMEBUFFER=y -# CONFIG_BOOTSPLASH is not set -# end of Display - -CONFIG_PCI=y -CONFIG_ECAM_MMCONF_SUPPORT=y -CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y -CONFIG_ECAM_MMCONF_LENGTH=0x04000000 -CONFIG_PCI_ALLOW_BUS_MASTER=y -CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y -CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y -# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 -# CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -CONFIG_INTEL_GMA_HAVE_VBT=y -CONFIG_INTEL_GMA_ADD_VBT=y -# CONFIG_SOFTWARE_I2C is not set -CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set -CONFIG_USE_DDR3=y -# end of Devices - -# -# Generic Drivers -# -CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 -# CONFIG_ELOG is not set -CONFIG_CACHE_MRC_SETTINGS=y -# CONFIG_MRC_SETTINGS_PROTECT is not set -# CONFIG_SMMSTORE is not set -CONFIG_SPI_FLASH=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y -# CONFIG_SPI_FLASH_NO_FAST_READ is not set -CONFIG_SPI_FLASH_ADESTO=y -CONFIG_SPI_FLASH_AMIC=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_TPM_INIT_RAMSTAGE=y -# CONFIG_TPM_PPI is not set -CONFIG_NO_UART_ON_SUPERIO=y -# CONFIG_DRIVERS_UART_OXPCIE is not set -CONFIG_HAVE_USBDEBUG=y -CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_USBDEBUG is not set -# CONFIG_VPD is not set -# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set -# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set -# CONFIG_DRIVERS_I2C_MAX98396 is not set -CONFIG_INTEL_INT15=y -CONFIG_INTEL_GMA_ACPI=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" -CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_DYN_CPU=y -CONFIG_GFX_GMA_GENERATION="Ironlake" -CONFIG_GFX_GMA_PCH="Cougar_Point" -CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" -CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" -# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set -# CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 -CONFIG_MEMORY_MAPPED_TPM=y -CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 -CONFIG_DRIVERS_RICOH_RCE822=y -# CONFIG_DRIVERS_SIL_3114 is not set -# end of Generic Drivers - -# -# Security -# - -# -# CBFS verification -# -# CONFIG_CBFS_VERIFICATION is not set -# end of CBFS verification - -# -# Verified Boot (vboot) -# -# end of Verified Boot (vboot) - -# -# Trusted Platform Module -# -# CONFIG_NO_TPM is not set -CONFIG_TPM1=y -CONFIG_TPM=y -CONFIG_MAINBOARD_HAS_TPM1=y -# CONFIG_TPM_DEACTIVATE is not set -# CONFIG_DEBUG_TPM is not set -# CONFIG_TPM_RDRESP_NEED_DELAY is not set -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 -# end of Trusted Platform Module - -# -# Memory initialization -# -CONFIG_PLATFORM_HAS_DRAM_CLEAR=y -CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y -# end of Memory initialization - -# CONFIG_INTEL_TXT is not set -# CONFIG_STM is not set -CONFIG_BOOTMEDIA_LOCK_NONE=y -# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set -# CONFIG_BOOTMEDIA_LOCK_CHIP is not set -# CONFIG_BOOTMEDIA_SMM_BWP is not set -# end of Security - -CONFIG_ACPI_HAVE_PCAT_8259=y -CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y -CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y -CONFIG_HAVE_ACPI_TABLES=y -CONFIG_BOOT_DEVICE_SPI_FLASH=y -CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 - -# -# Console -# -CONFIG_BOOTBLOCK_CONSOLE=y -CONFIG_POSTCAR_CONSOLE=y -CONFIG_SQUELCH_EARLY_SMP=y -# CONFIG_SPKMODEM is not set -# CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set -# CONFIG_CONSOLE_SPI_FLASH is not set -# CONFIG_CONSOLE_I2C_SMBUS is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 -CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y -CONFIG_CONSOLE_USE_ANSI_ESCAPES=y -# CONFIG_CMOS_POST is not set -CONFIG_POST_DEVICE_NONE=y -# CONFIG_POST_DEVICE_LPC is not set -# CONFIG_POST_DEVICE_PCI_PCIE is not set -CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y -# end of Console - -CONFIG_HAVE_ACPI_RESUME=y -CONFIG_RESUME_PATH_SAME_AS_BOOT=y -CONFIG_HAVE_MONOTONIC_TIMER=y -CONFIG_HAVE_OPTION_TABLE=y -CONFIG_IOAPIC=y -CONFIG_USE_WATCHDOG_ON_BOOT=y - -# -# System tables -# -CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" -CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -# end of System tables - -# -# Payload -# -CONFIG_PAYLOAD_NONE=y -# end of Payload - -# -# Debugging -# - -# -# CPU Debug Settings -# -# CONFIG_DISPLAY_MTRRS is not set - -# -# Vendorcode Debug Settings -# - -# -# BLOB Debug Settings -# - -# -# General Debug Settings -# -# CONFIG_FATAL_ASSERTS is not set -# CONFIG_DEBUG_CBFS is not set -CONFIG_HAVE_DEBUG_RAM_SETUP=y -# CONFIG_DEBUG_RAM_SETUP is not set -CONFIG_HAVE_DEBUG_SMBUS=y -# CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set -# CONFIG_DEBUG_CONSOLE_INIT is not set -# CONFIG_DEBUG_SPI_FLASH is not set -# CONFIG_DEBUG_BOOT_STATE is not set -# CONFIG_DEBUG_ADA_CODE is not set -CONFIG_HAVE_EM100_SUPPORT=y -# CONFIG_EM100 is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set -# end of Debugging - -CONFIG_RAMSTAGE_ADA=y -CONFIG_RAMSTAGE_LIBHWBASE=y -CONFIG_HWBASE_DYNAMIC_MMIO=y -CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 -CONFIG_HWBASE_DIRECT_PCIDEV=y -CONFIG_DECOMPRESS_OFAST=y -CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_MAX_REBOOT_CNT=3 -CONFIG_RELOCATABLE_MODULES=y -CONFIG_HAVE_BOOTBLOCK=y -CONFIG_HAVE_ROMSTAGE=y -CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/x220edp_8mb/config/libgfxinit_txtmode b/config/coreboot/x220edp_8mb/config/libgfxinit_txtmode deleted file mode 100644 index b373ffa3..00000000 --- a/config/coreboot/x220edp_8mb/config/libgfxinit_txtmode +++ /dev/null @@ -1,671 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# coreboot configuration -# - -# -# General setup -# -CONFIG_COREBOOT_BUILD=y -CONFIG_LOCALVERSION="" -CONFIG_CBFS_PREFIX="fallback" -CONFIG_COMPILER_GCC=y -# CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y -# CONFIG_ANY_TOOLCHAIN is not set -# CONFIG_CCACHE is not set -# CONFIG_IWYU is not set -# CONFIG_FMD_GENPARSER is not set -# CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE_LZMA=y -# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y -CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_COLLECT_TIMESTAMPS=y -# CONFIG_TIMESTAMPS_ON_CONSOLE is not set -CONFIG_USE_BLOBS=y -# CONFIG_USE_AMD_BLOBS is not set -# CONFIG_USE_QC_BLOBS is not set -# CONFIG_COVERAGE is not set -# CONFIG_UBSAN is not set -CONFIG_HAVE_ASAN_IN_RAMSTAGE=y -# CONFIG_ASAN is not set -CONFIG_NO_STAGE_CACHE=y -# CONFIG_TSEG_STAGE_CACHE is not set -# CONFIG_UPDATE_IMAGE is not set -# CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set - -# -# Software Bill Of Materials (SBOM) -# -# CONFIG_SBOM is not set -# end of Software Bill Of Materials (SBOM) -# end of General setup - -# -# Mainboard -# - -# -# Important: Run 'make distclean' before switching boards -# -# CONFIG_VENDOR_51NB is not set -# CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set -# CONFIG_VENDOR_AMD is not set -# CONFIG_VENDOR_AOPEN is not set -# CONFIG_VENDOR_APPLE is not set -# CONFIG_VENDOR_ASROCK is not set -# CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BIOSTAR is not set -# CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set -# CONFIG_VENDOR_CAVIUM is not set -# CONFIG_VENDOR_CLEVO is not set -# CONFIG_VENDOR_COMPULAB is not set -# CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_EMULATION is not set -# CONFIG_VENDOR_EXAMPLE is not set -# CONFIG_VENDOR_FACEBOOK is not set -# CONFIG_VENDOR_FOXCONN is not set -# CONFIG_VENDOR_GETAC is not set -# CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GOOGLE is not set -# CONFIG_VENDOR_HP is not set -# CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set -# CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set -# CONFIG_VENDOR_KONTRON is not set -CONFIG_VENDOR_LENOVO=y -# CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_MSI is not set -# CONFIG_VENDOR_OCP is not set -# CONFIG_VENDOR_OPENCELLULAR is not set -# CONFIG_VENDOR_PACKARDBELL is not set -# CONFIG_VENDOR_PCENGINES is not set -# CONFIG_VENDOR_PINE64 is not set -# CONFIG_VENDOR_PORTWELL is not set -# CONFIG_VENDOR_PRODRIVE is not set -# CONFIG_VENDOR_PROTECTLI is not set -# CONFIG_VENDOR_PURISM is not set -# CONFIG_VENDOR_RAZER is not set -# CONFIG_VENDOR_RODA is not set -# CONFIG_VENDOR_SAMSUNG is not set -# CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SIEMENS is not set -# CONFIG_VENDOR_SIFIVE is not set -# CONFIG_VENDOR_STARLABS is not set -# CONFIG_VENDOR_SUPERMICRO is not set -# CONFIG_VENDOR_SYSTEM76 is not set -# CONFIG_VENDOR_TI is not set -# CONFIG_VENDOR_UP is not set -CONFIG_BOARD_SPECIFIC_OPTIONS=y -CONFIG_MAINBOARD_FAMILY="ThinkPad X220" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X220" -CONFIG_MAINBOARD_VERSION="1.0" -CONFIG_MAINBOARD_DIR="lenovo/x220" -CONFIG_VGA_BIOS_ID="8086,0126" -CONFIG_DIMM_MAX=4 -CONFIG_DIMM_SPD_SIZE=256 -CONFIG_FMDFILE="" -# CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0x7E0000 -CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set -CONFIG_POST_DEVICE=y -CONFIG_POST_IO=y -CONFIG_DEVICETREE="devicetree.cb" -# CONFIG_VBOOT is not set -CONFIG_VARIANT_DIR="x220" -CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" -# CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_DRAM_RESET_GATE_GPIO=10 -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/x220_edp/data.vbt" -CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" -CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 -CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 -# CONFIG_CONSOLE_POST is not set -CONFIG_TPM_PIRQ=0x0 -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="LEN0020" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" -CONFIG_VBOOT_SLOTS_RW_A=y -CONFIG_DCACHE_RAM_BASE=0xfefe0000 -CONFIG_DCACHE_RAM_SIZE=0x20000 -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 -CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 -CONFIG_HAVE_INTEL_FIRMWARE=y -CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 -CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_DRIVERS_INTEL_WIFI is not set -CONFIG_IFD_BIN_PATH="../../../config/ifd/xx20/ifd" -CONFIG_ME_BIN_PATH="../../../vendorfiles/xx20/me.bin" -CONFIG_GBE_BIN_PATH="../../../config/ifd/xx20/gbe" -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X220" -CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set -# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set -# CONFIG_BOARD_LENOVO_L520 is not set -# CONFIG_BOARD_LENOVO_S230U is not set -# CONFIG_BOARD_LENOVO_T400 is not set -# CONFIG_BOARD_LENOVO_T500 is not set -# CONFIG_BOARD_LENOVO_R400 is not set -# CONFIG_BOARD_LENOVO_R500 is not set -# CONFIG_BOARD_LENOVO_W500 is not set -# CONFIG_BOARD_LENOVO_T410 is not set -# CONFIG_BOARD_LENOVO_T420 is not set -# CONFIG_BOARD_LENOVO_T420S is not set -# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set -# CONFIG_BOARD_LENOVO_T430S is not set -# CONFIG_BOARD_LENOVO_T431S is not set -# CONFIG_BOARD_LENOVO_T520 is not set -# CONFIG_BOARD_LENOVO_W520 is not set -# CONFIG_BOARD_LENOVO_T530 is not set -# CONFIG_BOARD_LENOVO_W530 is not set -# CONFIG_BOARD_LENOVO_T60 is not set -# CONFIG_BOARD_LENOVO_Z61T is not set -# CONFIG_BOARD_LENOVO_R60 is not set -# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set -# CONFIG_BOARD_LENOVO_X131E is not set -# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set -# CONFIG_BOARD_LENOVO_X200 is not set -# CONFIG_BOARD_LENOVO_X301 is not set -# CONFIG_BOARD_LENOVO_X201 is not set -CONFIG_BOARD_LENOVO_X220=y -# CONFIG_BOARD_LENOVO_X220I is not set -# CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set -# CONFIG_BOARD_LENOVO_X230 is not set -# CONFIG_BOARD_LENOVO_X230T is not set -# CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set -# CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_DRIVER_LENOVO_SERIALS=y -CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" -CONFIG_GFX_GMA_PANEL_1_PORT="LVDS" -CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 -CONFIG_EC_GPE_SCI=0x50 -# CONFIG_TPM_MEASURED_BOOT is not set -CONFIG_BOARD_ROMSIZE_KB_8192=y -# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set -CONFIG_COREBOOT_ROMSIZE_KB_8192=y -# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set -CONFIG_COREBOOT_ROMSIZE_KB=8192 -CONFIG_ROM_SIZE=0x00800000 -CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y -CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y -CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set -# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set -CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 -# end of Mainboard - -CONFIG_SYSTEM_TYPE_LAPTOP=y - -# -# Chipset -# - -# -# SoC -# -CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" -CONFIG_CBFS_MCACHE_SIZE=0x4000 -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_SMM_RESERVED_SIZE=0x100000 -CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set -CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" -CONFIG_STACK_SIZE=0x2000 -CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 -CONFIG_INTEL_GMA_BCLV_WIDTH=16 -CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 -CONFIG_INTEL_GMA_BCLM_WIDTH=16 -CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 -CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 -CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 -CONFIG_FIXED_SMBUS_IO_BASE=0x400 -CONFIG_CBFS_CACHE_ALIGN=8 - -# -# CPU -# -CONFIG_CPU_INTEL_MODEL_206AX=y -CONFIG_CPU_INTEL_COMMON=y -CONFIG_ENABLE_VMX=y -CONFIG_SET_IA32_FC_LOCK_BIT=y -CONFIG_SET_MSR_AESNI_LOCK_BIT=y -CONFIG_CPU_INTEL_COMMON_TIMEBASE=y -CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y -CONFIG_PARALLEL_MP=y -CONFIG_XAPIC_ONLY=y -# CONFIG_X2APIC_ONLY is not set -# CONFIG_X2APIC_RUNTIME is not set -# CONFIG_X2APIC_LATE_WORKAROUND is not set -CONFIG_UDELAY_TSC=y -CONFIG_TSC_MONOTONIC_TIMER=y -CONFIG_TSC_SYNC_MFENCE=y -CONFIG_HAVE_SMI_HANDLER=y -CONFIG_SMM_TSEG=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 -CONFIG_AP_STACK_SIZE=0x800 -CONFIG_SMP=y -CONFIG_SSE=y -CONFIG_SSE2=y -CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y -CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y -CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set -# CONFIG_CPU_MICROCODE_CBFS_NONE is not set - -# -# Northbridge -# -CONFIG_USE_NATIVE_RAMINIT=y -CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y -# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set -# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set -CONFIG_RAMINIT_ENABLE_ECC=y - -# -# Southbridge -# -CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y -CONFIG_SOUTHBRIDGE_INTEL_C216=y -CONFIG_HIDE_MEI_ON_ERROR=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y -CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y -# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set -CONFIG_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_TCO_SPACE_NOT_YET_SPLIT=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y -CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 -CONFIG_RCBA_LENGTH=0x4000 - -# -# Super I/O -# - -# -# Embedded Controllers -# -CONFIG_EC_ACPI=y -CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set -# CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_EC_LENOVO_PMH7=y - -# -# Intel Firmware -# -CONFIG_HAVE_ME_BIN=y -# CONFIG_STITCH_ME_BIN is not set -# CONFIG_CHECK_ME is not set -# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set -# CONFIG_USE_ME_CLEANER is not set -CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y -CONFIG_HAVE_GBE_BIN=y -# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set -# CONFIG_LOCK_MANAGEMENT_ENGINE is not set -CONFIG_UNLOCK_FLASH_REGIONS=y -CONFIG_ARCH_X86=y -CONFIG_ARCH_BOOTBLOCK_X86_32=y -CONFIG_ARCH_VERSTAGE_X86_32=y -CONFIG_ARCH_ROMSTAGE_X86_32=y -CONFIG_ARCH_POSTCAR_X86_32=y -CONFIG_ARCH_RAMSTAGE_X86_32=y -CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 -CONFIG_PC80_SYSTEM=y -CONFIG_HAVE_CMOS_DEFAULT=y -CONFIG_POSTCAR_STAGE=y -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_COLLECT_TIMESTAMPS_TSC=y -CONFIG_HAVE_CF9_RESET=y -CONFIG_DEBUG_HW_BREAKPOINTS=y -CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set -# end of Chipset - -# -# Devices -# -CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y -CONFIG_HAVE_LINEAR_FRAMEBUFFER=y -CONFIG_MAINBOARD_HAS_LIBGFXINIT=y -CONFIG_MAINBOARD_USE_LIBGFXINIT=y -# CONFIG_VGA_ROM_RUN is not set -# CONFIG_NO_GFX_INIT is not set -CONFIG_NO_EARLY_GFX_INIT=y - -# -# Display -# -CONFIG_VGA_TEXT_FRAMEBUFFER=y -# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set -# end of Display - -CONFIG_PCI=y -CONFIG_ECAM_MMCONF_SUPPORT=y -CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y -CONFIG_ECAM_MMCONF_LENGTH=0x04000000 -CONFIG_PCI_ALLOW_BUS_MASTER=y -CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y -CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y -# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 -# CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -CONFIG_INTEL_GMA_HAVE_VBT=y -CONFIG_INTEL_GMA_ADD_VBT=y -# CONFIG_SOFTWARE_I2C is not set -CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set -CONFIG_USE_DDR3=y -# end of Devices - -# -# Generic Drivers -# -CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 -# CONFIG_ELOG is not set -CONFIG_CACHE_MRC_SETTINGS=y -# CONFIG_MRC_SETTINGS_PROTECT is not set -# CONFIG_SMMSTORE is not set -CONFIG_SPI_FLASH=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y -# CONFIG_SPI_FLASH_NO_FAST_READ is not set -CONFIG_SPI_FLASH_ADESTO=y -CONFIG_SPI_FLASH_AMIC=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_TPM_INIT_RAMSTAGE=y -# CONFIG_TPM_PPI is not set -CONFIG_NO_UART_ON_SUPERIO=y -# CONFIG_DRIVERS_UART_OXPCIE is not set -CONFIG_HAVE_USBDEBUG=y -CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_USBDEBUG is not set -# CONFIG_VPD is not set -# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set -# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set -# CONFIG_DRIVERS_I2C_MAX98396 is not set -CONFIG_INTEL_INT15=y -CONFIG_INTEL_GMA_ACPI=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" -CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y -CONFIG_GFX_GMA_DYN_CPU=y -CONFIG_GFX_GMA_GENERATION="Ironlake" -CONFIG_GFX_GMA_PCH="Cougar_Point" -CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" -CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" -# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set -# CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 -CONFIG_MEMORY_MAPPED_TPM=y -CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 -CONFIG_VGA=y -CONFIG_DRIVERS_RICOH_RCE822=y -# CONFIG_DRIVERS_SIL_3114 is not set -# end of Generic Drivers - -# -# Security -# - -# -# CBFS verification -# -# CONFIG_CBFS_VERIFICATION is not set -# end of CBFS verification - -# -# Verified Boot (vboot) -# -# end of Verified Boot (vboot) - -# -# Trusted Platform Module -# -# CONFIG_NO_TPM is not set -CONFIG_TPM1=y -CONFIG_TPM=y -CONFIG_MAINBOARD_HAS_TPM1=y -# CONFIG_TPM_DEACTIVATE is not set -# CONFIG_DEBUG_TPM is not set -# CONFIG_TPM_RDRESP_NEED_DELAY is not set -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 -# end of Trusted Platform Module - -# -# Memory initialization -# -CONFIG_PLATFORM_HAS_DRAM_CLEAR=y -CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y -# end of Memory initialization - -# CONFIG_INTEL_TXT is not set -# CONFIG_STM is not set -CONFIG_BOOTMEDIA_LOCK_NONE=y -# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set -# CONFIG_BOOTMEDIA_LOCK_CHIP is not set -# CONFIG_BOOTMEDIA_SMM_BWP is not set -# end of Security - -CONFIG_ACPI_HAVE_PCAT_8259=y -CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y -CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y -CONFIG_HAVE_ACPI_TABLES=y -CONFIG_BOOT_DEVICE_SPI_FLASH=y -CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 - -# -# Console -# -CONFIG_BOOTBLOCK_CONSOLE=y -CONFIG_POSTCAR_CONSOLE=y -CONFIG_SQUELCH_EARLY_SMP=y -# CONFIG_SPKMODEM is not set -# CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set -# CONFIG_CONSOLE_SPI_FLASH is not set -# CONFIG_CONSOLE_I2C_SMBUS is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 -CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y -CONFIG_CONSOLE_USE_ANSI_ESCAPES=y -# CONFIG_CMOS_POST is not set -CONFIG_POST_DEVICE_NONE=y -# CONFIG_POST_DEVICE_LPC is not set -# CONFIG_POST_DEVICE_PCI_PCIE is not set -CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_CB=y -# end of Console - -CONFIG_HAVE_ACPI_RESUME=y -CONFIG_RESUME_PATH_SAME_AS_BOOT=y -CONFIG_HAVE_MONOTONIC_TIMER=y -CONFIG_HAVE_OPTION_TABLE=y -CONFIG_IOAPIC=y -CONFIG_USE_WATCHDOG_ON_BOOT=y - -# -# System tables -# -CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" -CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -# end of System tables - -# -# Payload -# -CONFIG_PAYLOAD_NONE=y -# end of Payload - -# -# Debugging -# - -# -# CPU Debug Settings -# -# CONFIG_DISPLAY_MTRRS is not set - -# -# Vendorcode Debug Settings -# - -# -# BLOB Debug Settings -# - -# -# General Debug Settings -# -# CONFIG_FATAL_ASSERTS is not set -# CONFIG_DEBUG_CBFS is not set -CONFIG_HAVE_DEBUG_RAM_SETUP=y -# CONFIG_DEBUG_RAM_SETUP is not set -CONFIG_HAVE_DEBUG_SMBUS=y -# CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_MALLOC is not set -# CONFIG_DEBUG_CONSOLE_INIT is not set -# CONFIG_DEBUG_SPI_FLASH is not set -# CONFIG_DEBUG_BOOT_STATE is not set -# CONFIG_DEBUG_ADA_CODE is not set -CONFIG_HAVE_EM100_SUPPORT=y -# CONFIG_EM100 is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set -# end of Debugging - -CONFIG_RAMSTAGE_ADA=y -CONFIG_RAMSTAGE_LIBHWBASE=y -CONFIG_HWBASE_DYNAMIC_MMIO=y -CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 -CONFIG_HWBASE_DIRECT_PCIDEV=y -CONFIG_DECOMPRESS_OFAST=y -CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_MAX_REBOOT_CNT=3 -CONFIG_RELOCATABLE_MODULES=y -CONFIG_HAVE_BOOTBLOCK=y -CONFIG_HAVE_ROMSTAGE=y -CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/x220edp_8mb/target.cfg b/config/coreboot/x220edp_8mb/target.cfg deleted file mode 100644 index cd477e6f..00000000 --- a/config/coreboot/x220edp_8mb/target.cfg +++ /dev/null @@ -1,9 +0,0 @@ -tree="default" -xarch="i386-elf" -payload_grub="y" -payload_grub_withseabios="y" -payload_seabios="y" -payload_memtest="y" -grub_scan_disk="ahci" -status="broken" # TODO: VCC3P patch -release="n" diff --git a/config/coreboot/x220edp_8mb/warn.txt b/config/coreboot/x220edp_8mb/warn.txt deleted file mode 100644 index a153edeb..00000000 --- a/config/coreboot/x220edp_8mb/warn.txt +++ /dev/null @@ -1 +0,0 @@ -TODO: VCC3P patch diff --git a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb index b5957386..72e1d756 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_12mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set CONFIG_BOARD_LENOVO_X230=y # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230_12mb/config/libgfxinit_txtmode b/config/coreboot/x230_12mb/config/libgfxinit_txtmode index ce252c9a..d8fa1e98 100644 --- a/config/coreboot/x230_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_12mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set CONFIG_BOARD_LENOVO_X230=y # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb index 062652de..2de1cb4a 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230_16mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set CONFIG_BOARD_LENOVO_X230=y # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230_16mb/config/libgfxinit_txtmode b/config/coreboot/x230_16mb/config/libgfxinit_txtmode index c538774f..daaae9f4 100644 --- a/config/coreboot/x230_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230_16mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set CONFIG_BOARD_LENOVO_X230=y # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230edp_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230edp_12mb/config/libgfxinit_corebootfb deleted file mode 100644 index bc1883de..00000000 --- a/config/coreboot/x230edp_12mb/config/libgfxinit_corebootfb +++ /dev/null @@ -1,673 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# coreboot configuration -# - -# -# General setup -# -CONFIG_COREBOOT_BUILD=y -CONFIG_LOCALVERSION="" -CONFIG_CBFS_PREFIX="fallback" -CONFIG_COMPILER_GCC=y -# CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y -# CONFIG_ANY_TOOLCHAIN is not set -# CONFIG_CCACHE is not set -# CONFIG_IWYU is not set -# CONFIG_FMD_GENPARSER is not set -# CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE_LZMA=y -# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y -CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_COLLECT_TIMESTAMPS=y -# CONFIG_TIMESTAMPS_ON_CONSOLE is not set -CONFIG_USE_BLOBS=y -# CONFIG_USE_AMD_BLOBS is not set -# CONFIG_USE_QC_BLOBS is not set -# CONFIG_COVERAGE is not set -# CONFIG_UBSAN is not set -CONFIG_HAVE_ASAN_IN_RAMSTAGE=y -# CONFIG_ASAN is not set -CONFIG_NO_STAGE_CACHE=y -# CONFIG_TSEG_STAGE_CACHE is not set -# CONFIG_UPDATE_IMAGE is not set -# CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set - -# -# Software Bill Of Materials (SBOM) -# -# CONFIG_SBOM is not set -# end of Software Bill Of Materials (SBOM) -# end of General setup - -# -# Mainboard -# - -# -# Important: Run 'make distclean' before switching boards -# -# CONFIG_VENDOR_51NB is not set -# CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set -# CONFIG_VENDOR_AMD is not set -# CONFIG_VENDOR_AOPEN is not set -# CONFIG_VENDOR_APPLE is not set -# CONFIG_VENDOR_ASROCK is not set -# CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BIOSTAR is not set -# CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set -# CONFIG_VENDOR_CAVIUM is not set -# CONFIG_VENDOR_CLEVO is not set -# CONFIG_VENDOR_COMPULAB is not set -# CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_EMULATION is not set -# CONFIG_VENDOR_EXAMPLE is not set -# CONFIG_VENDOR_FACEBOOK is not set -# CONFIG_VENDOR_FOXCONN is not set -# CONFIG_VENDOR_GETAC is not set -# CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GOOGLE is not set -# CONFIG_VENDOR_HP is not set -# CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set -# CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set -# CONFIG_VENDOR_KONTRON is not set -CONFIG_VENDOR_LENOVO=y -# CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_MSI is not set -# CONFIG_VENDOR_OCP is not set -# CONFIG_VENDOR_OPENCELLULAR is not set -# CONFIG_VENDOR_PACKARDBELL is not set -# CONFIG_VENDOR_PCENGINES is not set -# CONFIG_VENDOR_PINE64 is not set -# CONFIG_VENDOR_PORTWELL is not set -# CONFIG_VENDOR_PRODRIVE is not set -# CONFIG_VENDOR_PROTECTLI is not set -# CONFIG_VENDOR_PURISM is not set -# CONFIG_VENDOR_RAZER is not set -# CONFIG_VENDOR_RODA is not set -# CONFIG_VENDOR_SAMSUNG is not set -# CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SIEMENS is not set -# CONFIG_VENDOR_SIFIVE is not set -# CONFIG_VENDOR_STARLABS is not set -# CONFIG_VENDOR_SUPERMICRO is not set -# CONFIG_VENDOR_SYSTEM76 is not set -# CONFIG_VENDOR_TI is not set -# CONFIG_VENDOR_UP is not set -CONFIG_BOARD_SPECIFIC_OPTIONS=y -CONFIG_MAINBOARD_FAMILY="ThinkPad X230" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X230" -CONFIG_MAINBOARD_VERSION="1.0" -CONFIG_MAINBOARD_DIR="lenovo/x230" -CONFIG_VGA_BIOS_ID="8086,0166" -CONFIG_DIMM_MAX=4 -CONFIG_DIMM_SPD_SIZE=256 -CONFIG_FMDFILE="" -# CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 -CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 -CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 -CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set -CONFIG_POST_DEVICE=y -CONFIG_POST_IO=y -CONFIG_DEVICETREE="devicetree.cb" -# CONFIG_VBOOT is not set -CONFIG_VARIANT_DIR="x230" -CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" -# CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_DRAM_RESET_GATE_GPIO=10 -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/x230_edp/data.vbt" -CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" -CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 -CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 -# CONFIG_CONSOLE_POST is not set -CONFIG_TPM_PIRQ=0x0 -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="LEN0020" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" -CONFIG_DCACHE_RAM_BASE=0xfefe0000 -CONFIG_DCACHE_RAM_SIZE=0x20000 -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 -CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 -CONFIG_HAVE_INTEL_FIRMWARE=y -CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 -CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_DRIVERS_INTEL_WIFI is not set -CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd" -CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin" -CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe" -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X230" -CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set -# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set -# CONFIG_BOARD_LENOVO_L520 is not set -# CONFIG_BOARD_LENOVO_S230U is not set -# CONFIG_BOARD_LENOVO_T400 is not set -# CONFIG_BOARD_LENOVO_T500 is not set -# CONFIG_BOARD_LENOVO_R400 is not set -# CONFIG_BOARD_LENOVO_R500 is not set -# CONFIG_BOARD_LENOVO_W500 is not set -# CONFIG_BOARD_LENOVO_T410 is not set -# CONFIG_BOARD_LENOVO_T420 is not set -# CONFIG_BOARD_LENOVO_T420S is not set -# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set -# CONFIG_BOARD_LENOVO_T430S is not set -# CONFIG_BOARD_LENOVO_T431S is not set -# CONFIG_BOARD_LENOVO_T520 is not set -# CONFIG_BOARD_LENOVO_W520 is not set -# CONFIG_BOARD_LENOVO_T530 is not set -# CONFIG_BOARD_LENOVO_W530 is not set -# CONFIG_BOARD_LENOVO_T60 is not set -# CONFIG_BOARD_LENOVO_Z61T is not set -# CONFIG_BOARD_LENOVO_R60 is not set -# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set -# CONFIG_BOARD_LENOVO_X131E is not set -# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set -# CONFIG_BOARD_LENOVO_X200 is not set -# CONFIG_BOARD_LENOVO_X301 is not set -# CONFIG_BOARD_LENOVO_X201 is not set -# CONFIG_BOARD_LENOVO_X220 is not set -# CONFIG_BOARD_LENOVO_X220I is not set -# CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set -# CONFIG_BOARD_LENOVO_X230 is not set -# CONFIG_BOARD_LENOVO_X230T is not set -# CONFIG_BOARD_LENOVO_X230S is not set -CONFIG_BOARD_LENOVO_X230_EDP=y -# CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_VBOOT_SLOTS_RW_AB=y -CONFIG_DRIVER_LENOVO_SERIALS=y -CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" -CONFIG_GFX_GMA_PANEL_1_PORT="eDP" -CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 -CONFIG_EC_GPE_SCI=0x50 -# CONFIG_TPM_MEASURED_BOOT is not set -CONFIG_BOARD_ROMSIZE_KB_12288=y -# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set -CONFIG_COREBOOT_ROMSIZE_KB_12288=y -# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set -CONFIG_COREBOOT_ROMSIZE_KB=12288 -CONFIG_ROM_SIZE=0x00c00000 -CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y -CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y -CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set -# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set -CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 -# end of Mainboard - -CONFIG_SYSTEM_TYPE_LAPTOP=y - -# -# Chipset -# - -# -# SoC -# -CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" -CONFIG_CBFS_MCACHE_SIZE=0x4000 -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_SMM_RESERVED_SIZE=0x100000 -CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set -CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" -CONFIG_STACK_SIZE=0x2000 -CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 -CONFIG_INTEL_GMA_BCLV_WIDTH=16 -CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 -CONFIG_INTEL_GMA_BCLM_WIDTH=16 -CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 -CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 -CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 -CONFIG_FIXED_SMBUS_IO_BASE=0x400 -CONFIG_CBFS_CACHE_ALIGN=8 - -# -# CPU -# -CONFIG_CPU_INTEL_MODEL_206AX=y -CONFIG_CPU_INTEL_COMMON=y -CONFIG_ENABLE_VMX=y -CONFIG_SET_IA32_FC_LOCK_BIT=y -CONFIG_SET_MSR_AESNI_LOCK_BIT=y -CONFIG_CPU_INTEL_COMMON_TIMEBASE=y -CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y -CONFIG_PARALLEL_MP=y -CONFIG_XAPIC_ONLY=y -# CONFIG_X2APIC_ONLY is not set -# CONFIG_X2APIC_RUNTIME is not set -# CONFIG_X2APIC_LATE_WORKAROUND is not set -CONFIG_UDELAY_TSC=y -CONFIG_TSC_MONOTONIC_TIMER=y -CONFIG_TSC_SYNC_MFENCE=y -CONFIG_HAVE_SMI_HANDLER=y -CONFIG_SMM_TSEG=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 -CONFIG_AP_STACK_SIZE=0x800 -CONFIG_SMP=y -CONFIG_SSE=y -CONFIG_SSE2=y -CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y -CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y -CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set -# CONFIG_CPU_MICROCODE_CBFS_NONE is not set - -# -# Northbridge -# -CONFIG_USE_NATIVE_RAMINIT=y -CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y -# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set -# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set -CONFIG_RAMINIT_ENABLE_ECC=y - -# -# Southbridge -# -CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y -CONFIG_SOUTHBRIDGE_INTEL_C216=y -CONFIG_HIDE_MEI_ON_ERROR=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y -CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y -# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set -CONFIG_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_TCO_SPACE_NOT_YET_SPLIT=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y -CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 -CONFIG_RCBA_LENGTH=0x4000 - -# -# Super I/O -# - -# -# Embedded Controllers -# -CONFIG_EC_ACPI=y -CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set -# CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_EC_LENOVO_PMH7=y - -# -# Intel Firmware -# -CONFIG_HAVE_ME_BIN=y -# CONFIG_STITCH_ME_BIN is not set -# CONFIG_CHECK_ME is not set -# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set -# CONFIG_USE_ME_CLEANER is not set -CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y -CONFIG_HAVE_GBE_BIN=y -# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set -# CONFIG_LOCK_MANAGEMENT_ENGINE is not set -CONFIG_UNLOCK_FLASH_REGIONS=y -CONFIG_ARCH_X86=y -CONFIG_ARCH_BOOTBLOCK_X86_32=y -CONFIG_ARCH_VERSTAGE_X86_32=y -CONFIG_ARCH_ROMSTAGE_X86_32=y -CONFIG_ARCH_POSTCAR_X86_32=y -CONFIG_ARCH_RAMSTAGE_X86_32=y -CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 -CONFIG_PC80_SYSTEM=y -CONFIG_HAVE_CMOS_DEFAULT=y -CONFIG_POSTCAR_STAGE=y -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_COLLECT_TIMESTAMPS_TSC=y -CONFIG_HAVE_CF9_RESET=y -CONFIG_DEBUG_HW_BREAKPOINTS=y -CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set -# end of Chipset - -# -# Devices -# -CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y -CONFIG_HAVE_LINEAR_FRAMEBUFFER=y -CONFIG_MAINBOARD_HAS_LIBGFXINIT=y -CONFIG_MAINBOARD_USE_LIBGFXINIT=y -# CONFIG_VGA_ROM_RUN is not set -# CONFIG_NO_GFX_INIT is not set -CONFIG_NO_EARLY_GFX_INIT=y - -# -# Display -# -# CONFIG_VGA_TEXT_FRAMEBUFFER is not set -CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y -CONFIG_LINEAR_FRAMEBUFFER=y -# CONFIG_BOOTSPLASH is not set -# end of Display - -CONFIG_PCI=y -CONFIG_ECAM_MMCONF_SUPPORT=y -CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y -CONFIG_ECAM_MMCONF_LENGTH=0x04000000 -CONFIG_PCI_ALLOW_BUS_MASTER=y -CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y -CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y -# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 -# CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -CONFIG_INTEL_GMA_HAVE_VBT=y -CONFIG_INTEL_GMA_ADD_VBT=y -# CONFIG_SOFTWARE_I2C is not set -CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set -CONFIG_USE_DDR3=y -# end of Devices - -# -# Generic Drivers -# -CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 -# CONFIG_ELOG is not set -CONFIG_CACHE_MRC_SETTINGS=y -# CONFIG_MRC_SETTINGS_PROTECT is not set -# CONFIG_SMMSTORE is not set -CONFIG_SPI_FLASH=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y -# CONFIG_SPI_FLASH_NO_FAST_READ is not set -CONFIG_SPI_FLASH_ADESTO=y -CONFIG_SPI_FLASH_AMIC=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_TPM_INIT_RAMSTAGE=y -# CONFIG_TPM_PPI is not set -CONFIG_NO_UART_ON_SUPERIO=y -# CONFIG_DRIVERS_UART_OXPCIE is not set -CONFIG_HAVE_USBDEBUG=y -CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_USBDEBUG is not set -# CONFIG_VPD is not set -# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set -# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set -# CONFIG_DRIVERS_I2C_MAX98396 is not set -CONFIG_INTEL_INT15=y -CONFIG_INTEL_GMA_ACPI=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" -CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_DYN_CPU=y -CONFIG_GFX_GMA_GENERATION="Ironlake" -CONFIG_GFX_GMA_PCH="Cougar_Point" -CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" -CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" -# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set -# CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 -CONFIG_MEMORY_MAPPED_TPM=y -CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 -CONFIG_DRIVERS_RICOH_RCE822=y -# CONFIG_DRIVERS_SIL_3114 is not set -# end of Generic Drivers - -# -# Security -# - -# -# CBFS verification -# -# CONFIG_CBFS_VERIFICATION is not set -# end of CBFS verification - -# -# Verified Boot (vboot) -# -# end of Verified Boot (vboot) - -# -# Trusted Platform Module -# -# CONFIG_NO_TPM is not set -CONFIG_TPM1=y -CONFIG_TPM=y -CONFIG_MAINBOARD_HAS_TPM1=y -# CONFIG_TPM_DEACTIVATE is not set -# CONFIG_DEBUG_TPM is not set -# CONFIG_TPM_RDRESP_NEED_DELAY is not set -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 -# end of Trusted Platform Module - -# -# Memory initialization -# -CONFIG_PLATFORM_HAS_DRAM_CLEAR=y -CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y -# end of Memory initialization - -# CONFIG_INTEL_TXT is not set -# CONFIG_STM is not set -CONFIG_BOOTMEDIA_LOCK_NONE=y -# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set -# CONFIG_BOOTMEDIA_LOCK_CHIP is not set -# CONFIG_BOOTMEDIA_SMM_BWP is not set -# end of Security - -CONFIG_ACPI_HAVE_PCAT_8259=y -CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y -CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y -CONFIG_HAVE_ACPI_TABLES=y -CONFIG_BOOT_DEVICE_SPI_FLASH=y -CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 - -# -# Console -# -CONFIG_BOOTBLOCK_CONSOLE=y -CONFIG_POSTCAR_CONSOLE=y -CONFIG_SQUELCH_EARLY_SMP=y -# CONFIG_SPKMODEM is not set -# CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set -# CONFIG_CONSOLE_SPI_FLASH is not set -# CONFIG_CONSOLE_I2C_SMBUS is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 -CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y -CONFIG_CONSOLE_USE_ANSI_ESCAPES=y -# CONFIG_CMOS_POST is not set -CONFIG_POST_DEVICE_NONE=y -# CONFIG_POST_DEVICE_LPC is not set -# CONFIG_POST_DEVICE_PCI_PCIE is not set -CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_NULL=y -# end of Console - -CONFIG_HAVE_ACPI_RESUME=y -CONFIG_RESUME_PATH_SAME_AS_BOOT=y -CONFIG_HAVE_MONOTONIC_TIMER=y -CONFIG_HAVE_OPTION_TABLE=y -CONFIG_IOAPIC=y -CONFIG_USE_WATCHDOG_ON_BOOT=y - -# -# System tables -# -CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" -CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -# end of System tables - -# -# Payload -# -CONFIG_PAYLOAD_NONE=y -# end of Payload - -# -# Debugging -# - -# -# CPU Debug Settings -# -# CONFIG_DISPLAY_MTRRS is not set - -# -# Vendorcode Debug Settings -# - -# -# BLOB Debug Settings -# - -# -# General Debug Settings -# -# CONFIG_FATAL_ASSERTS is not set -# CONFIG_DEBUG_CBFS is not set -CONFIG_HAVE_DEBUG_RAM_SETUP=y -# CONFIG_DEBUG_RAM_SETUP is not set -CONFIG_HAVE_DEBUG_SMBUS=y -# CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_CONSOLE_INIT is not set -# CONFIG_DEBUG_SPI_FLASH is not set -# CONFIG_DEBUG_BOOT_STATE is not set -# CONFIG_DEBUG_ADA_CODE is not set -CONFIG_HAVE_EM100_SUPPORT=y -# CONFIG_EM100 is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set -# end of Debugging - -CONFIG_RAMSTAGE_ADA=y -CONFIG_RAMSTAGE_LIBHWBASE=y -CONFIG_HWBASE_DYNAMIC_MMIO=y -CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 -CONFIG_HWBASE_DIRECT_PCIDEV=y -CONFIG_DECOMPRESS_OFAST=y -CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_MAX_REBOOT_CNT=3 -CONFIG_RELOCATABLE_MODULES=y -CONFIG_HAVE_BOOTBLOCK=y -CONFIG_HAVE_ROMSTAGE=y -CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/x230edp_12mb/config/libgfxinit_txtmode b/config/coreboot/x230edp_12mb/config/libgfxinit_txtmode deleted file mode 100644 index 899d3e6b..00000000 --- a/config/coreboot/x230edp_12mb/config/libgfxinit_txtmode +++ /dev/null @@ -1,670 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# coreboot configuration -# - -# -# General setup -# -CONFIG_COREBOOT_BUILD=y -CONFIG_LOCALVERSION="" -CONFIG_CBFS_PREFIX="fallback" -CONFIG_COMPILER_GCC=y -# CONFIG_COMPILER_LLVM_CLANG is not set -CONFIG_ARCH_SUPPORTS_CLANG=y -# CONFIG_ANY_TOOLCHAIN is not set -# CONFIG_CCACHE is not set -# CONFIG_IWYU is not set -# CONFIG_FMD_GENPARSER is not set -# CONFIG_UTIL_GENPARSER is not set -# CONFIG_OPTION_BACKEND_NONE is not set -CONFIG_USE_OPTION_TABLE=y -CONFIG_STATIC_OPTION_TABLE=y -CONFIG_COMPRESS_RAMSTAGE_LZMA=y -# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set -CONFIG_SEPARATE_ROMSTAGE=y -CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_COLLECT_TIMESTAMPS=y -# CONFIG_TIMESTAMPS_ON_CONSOLE is not set -CONFIG_USE_BLOBS=y -# CONFIG_USE_AMD_BLOBS is not set -# CONFIG_USE_QC_BLOBS is not set -# CONFIG_COVERAGE is not set -# CONFIG_UBSAN is not set -CONFIG_HAVE_ASAN_IN_RAMSTAGE=y -# CONFIG_ASAN is not set -CONFIG_NO_STAGE_CACHE=y -# CONFIG_TSEG_STAGE_CACHE is not set -# CONFIG_UPDATE_IMAGE is not set -# CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_FW_CONFIG is not set - -# -# Software Bill Of Materials (SBOM) -# -# CONFIG_SBOM is not set -# end of Software Bill Of Materials (SBOM) -# end of General setup - -# -# Mainboard -# - -# -# Important: Run 'make distclean' before switching boards -# -# CONFIG_VENDOR_51NB is not set -# CONFIG_VENDOR_ACER is not set -# CONFIG_VENDOR_ADLINK is not set -# CONFIG_VENDOR_AMD is not set -# CONFIG_VENDOR_AOPEN is not set -# CONFIG_VENDOR_APPLE is not set -# CONFIG_VENDOR_ASROCK is not set -# CONFIG_VENDOR_ASUS is not set -# CONFIG_VENDOR_BIOSTAR is not set -# CONFIG_VENDOR_BOSTENTECH is not set -# CONFIG_VENDOR_BYTEDANCE is not set -# CONFIG_VENDOR_CAVIUM is not set -# CONFIG_VENDOR_CLEVO is not set -# CONFIG_VENDOR_COMPULAB is not set -# CONFIG_VENDOR_DELL is not set -# CONFIG_VENDOR_EMULATION is not set -# CONFIG_VENDOR_EXAMPLE is not set -# CONFIG_VENDOR_FACEBOOK is not set -# CONFIG_VENDOR_FOXCONN is not set -# CONFIG_VENDOR_GETAC is not set -# CONFIG_VENDOR_GIGABYTE is not set -# CONFIG_VENDOR_GOOGLE is not set -# CONFIG_VENDOR_HP is not set -# CONFIG_VENDOR_IBASE is not set -# CONFIG_VENDOR_IBM is not set -# CONFIG_VENDOR_INTEL is not set -# CONFIG_VENDOR_INVENTEC is not set -# CONFIG_VENDOR_KONTRON is not set -CONFIG_VENDOR_LENOVO=y -# CONFIG_VENDOR_LIBRETREND is not set -# CONFIG_VENDOR_MSI is not set -# CONFIG_VENDOR_OCP is not set -# CONFIG_VENDOR_OPENCELLULAR is not set -# CONFIG_VENDOR_PACKARDBELL is not set -# CONFIG_VENDOR_PCENGINES is not set -# CONFIG_VENDOR_PINE64 is not set -# CONFIG_VENDOR_PORTWELL is not set -# CONFIG_VENDOR_PRODRIVE is not set -# CONFIG_VENDOR_PROTECTLI is not set -# CONFIG_VENDOR_PURISM is not set -# CONFIG_VENDOR_RAZER is not set -# CONFIG_VENDOR_RODA is not set -# CONFIG_VENDOR_SAMSUNG is not set -# CONFIG_VENDOR_SAPPHIRE is not set -# CONFIG_VENDOR_SIEMENS is not set -# CONFIG_VENDOR_SIFIVE is not set -# CONFIG_VENDOR_STARLABS is not set -# CONFIG_VENDOR_SUPERMICRO is not set -# CONFIG_VENDOR_SYSTEM76 is not set -# CONFIG_VENDOR_TI is not set -# CONFIG_VENDOR_UP is not set -CONFIG_BOARD_SPECIFIC_OPTIONS=y -CONFIG_MAINBOARD_FAMILY="ThinkPad X230" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X230" -CONFIG_MAINBOARD_VERSION="1.0" -CONFIG_MAINBOARD_DIR="lenovo/x230" -CONFIG_VGA_BIOS_ID="8086,0166" -CONFIG_DIMM_MAX=4 -CONFIG_DIMM_SPD_SIZE=256 -CONFIG_FMDFILE="" -# CONFIG_NO_POST is not set -CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE0000 -CONFIG_MAX_CPUS=8 -# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set -CONFIG_POST_DEVICE=y -CONFIG_POST_IO=y -CONFIG_DEVICETREE="devicetree.cb" -# CONFIG_VBOOT is not set -CONFIG_VARIANT_DIR="x230" -CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" -# CONFIG_VGA_BIOS is not set -CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" -CONFIG_DRAM_RESET_GATE_GPIO=10 -CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/x230_edp/data.vbt" -CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 -CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" -CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" -CONFIG_USBDEBUG_HCD_INDEX=2 -CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 -# CONFIG_CONSOLE_POST is not set -CONFIG_TPM_PIRQ=0x0 -CONFIG_PS2K_EISAID="PNP0303" -CONFIG_PS2M_EISAID="LEN0020" -CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000 -CONFIG_ECAM_MMCONF_BUS_NUMBER=64 -CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld" -CONFIG_DCACHE_RAM_BASE=0xfefe0000 -CONFIG_DCACHE_RAM_SIZE=0x20000 -CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 -CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 -CONFIG_HAVE_INTEL_FIRMWARE=y -CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 -CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_DRIVERS_INTEL_WIFI is not set -CONFIG_IFD_BIN_PATH="../../../config/ifd/xx30/ifd" -CONFIG_ME_BIN_PATH="../../../vendorfiles/xx30/me.bin" -CONFIG_GBE_BIN_PATH="../../../config/ifd/xx30/gbe" -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -CONFIG_CARDBUS_PLUGIN_SUPPORT=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_STMICRO=y -# CONFIG_DEBUG_SMI is not set -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X230" -CONFIG_HAVE_IFD_BIN=y -CONFIG_PCIEXP_HOTPLUG_BUSES=8 -CONFIG_PCIEXP_HOTPLUG_MEM=0x800000 -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 -# CONFIG_BOARD_LENOVO_THINKPAD_T440P is not set -# CONFIG_BOARD_LENOVO_THINKPAD_W541 is not set -# CONFIG_BOARD_LENOVO_L520 is not set -# CONFIG_BOARD_LENOVO_S230U is not set -# CONFIG_BOARD_LENOVO_T400 is not set -# CONFIG_BOARD_LENOVO_T500 is not set -# CONFIG_BOARD_LENOVO_R400 is not set -# CONFIG_BOARD_LENOVO_R500 is not set -# CONFIG_BOARD_LENOVO_W500 is not set -# CONFIG_BOARD_LENOVO_T410 is not set -# CONFIG_BOARD_LENOVO_T420 is not set -# CONFIG_BOARD_LENOVO_T420S is not set -# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set -# CONFIG_BOARD_LENOVO_T430S is not set -# CONFIG_BOARD_LENOVO_T431S is not set -# CONFIG_BOARD_LENOVO_T520 is not set -# CONFIG_BOARD_LENOVO_W520 is not set -# CONFIG_BOARD_LENOVO_T530 is not set -# CONFIG_BOARD_LENOVO_W530 is not set -# CONFIG_BOARD_LENOVO_T60 is not set -# CONFIG_BOARD_LENOVO_Z61T is not set -# CONFIG_BOARD_LENOVO_R60 is not set -# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set -# CONFIG_BOARD_LENOVO_X131E is not set -# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set -# CONFIG_BOARD_LENOVO_X200 is not set -# CONFIG_BOARD_LENOVO_X301 is not set -# CONFIG_BOARD_LENOVO_X201 is not set -# CONFIG_BOARD_LENOVO_X220 is not set -# CONFIG_BOARD_LENOVO_X220I is not set -# CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set -# CONFIG_BOARD_LENOVO_X230 is not set -# CONFIG_BOARD_LENOVO_X230T is not set -# CONFIG_BOARD_LENOVO_X230S is not set -CONFIG_BOARD_LENOVO_X230_EDP=y -# CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_VBOOT_SLOTS_RW_AB=y -CONFIG_DRIVER_LENOVO_SERIALS=y -CONFIG_THINKPADEC_HKEY_EISAID="LEN0068" -CONFIG_GFX_GMA_PANEL_1_PORT="eDP" -CONFIG_D3COLD_SUPPORT=y -CONFIG_PCIEXP_ASPM=y -# CONFIG_PCIEXP_L1_SUB_STATE is not set -# CONFIG_PCIEXP_CLK_PM is not set -CONFIG_GFX_GMA_PANEL_1_ON_EDP=y -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72 -CONFIG_EC_GPE_SCI=0x50 -# CONFIG_TPM_MEASURED_BOOT is not set -CONFIG_BOARD_ROMSIZE_KB_12288=y -# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set -CONFIG_COREBOOT_ROMSIZE_KB_12288=y -# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set -CONFIG_COREBOOT_ROMSIZE_KB=12288 -CONFIG_ROM_SIZE=0x00c00000 -CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y -CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y -CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set -# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set -CONFIG_MAINBOARD_POWER_FAILURE_STATE=0 -# end of Mainboard - -CONFIG_SYSTEM_TYPE_LAPTOP=y - -# -# Chipset -# - -# -# SoC -# -CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb" -CONFIG_CBFS_MCACHE_SIZE=0x4000 -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 -CONFIG_SMM_TSEG_SIZE=0x800000 -CONFIG_SMM_RESERVED_SIZE=0x100000 -CONFIG_SMM_MODULE_STACK_SIZE=0x400 -# CONFIG_USE_EXP_X86_64_SUPPORT is not set -CONFIG_SERIRQ_CONTINUOUS_MODE=y -CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_ACPI_CPU_STRING="CP%02X" -CONFIG_STACK_SIZE=0x2000 -CONFIG_IED_REGION_SIZE=0x400000 -CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254 -CONFIG_INTEL_GMA_BCLV_WIDTH=16 -CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 -CONFIG_INTEL_GMA_BCLM_WIDTH=16 -CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000 -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 -CONFIG_HPET_MIN_TICKS=0x80 -CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 -CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 -CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000 -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0 -CONFIG_FIXED_SMBUS_IO_BASE=0x400 -CONFIG_CBFS_CACHE_ALIGN=8 - -# -# CPU -# -CONFIG_CPU_INTEL_MODEL_206AX=y -CONFIG_CPU_INTEL_COMMON=y -CONFIG_ENABLE_VMX=y -CONFIG_SET_IA32_FC_LOCK_BIT=y -CONFIG_SET_MSR_AESNI_LOCK_BIT=y -CONFIG_CPU_INTEL_COMMON_TIMEBASE=y -CONFIG_CPU_INTEL_COMMON_SMM=y -CONFIG_MICROCODE_UPDATE_PRE_RAM=y -CONFIG_PARALLEL_MP=y -CONFIG_XAPIC_ONLY=y -# CONFIG_X2APIC_ONLY is not set -# CONFIG_X2APIC_RUNTIME is not set -# CONFIG_X2APIC_LATE_WORKAROUND is not set -CONFIG_UDELAY_TSC=y -CONFIG_TSC_MONOTONIC_TIMER=y -CONFIG_TSC_SYNC_MFENCE=y -CONFIG_HAVE_SMI_HANDLER=y -CONFIG_SMM_TSEG=y -CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8 -CONFIG_AP_STACK_SIZE=0x800 -CONFIG_SMP=y -CONFIG_SSE=y -CONFIG_SSE2=y -CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y -CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y -CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set -# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set -# CONFIG_CPU_MICROCODE_CBFS_NONE is not set - -# -# Northbridge -# -CONFIG_USE_NATIVE_RAMINIT=y -CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y -# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set -# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set -# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set -CONFIG_RAMINIT_ENABLE_ECC=y - -# -# Southbridge -# -CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y -CONFIG_SOUTHBRIDGE_INTEL_C216=y -CONFIG_HIDE_MEI_ON_ERROR=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y -CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y -CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y -# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set -CONFIG_INTEL_CHIPSET_LOCKDOWN=y -CONFIG_TCO_SPACE_NOT_YET_SPLIT=y -CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y -CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000 -CONFIG_RCBA_LENGTH=0x4000 - -# -# Super I/O -# - -# -# Embedded Controllers -# -CONFIG_EC_ACPI=y -CONFIG_EC_LENOVO_H8=y -# CONFIG_H8_BEEP_ON_DEATH is not set -# CONFIG_H8_FLASH_LEDS_ON_DEATH is not set -# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set -# CONFIG_H8_FN_CTRL_SWAP is not set -CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y -CONFIG_EC_LENOVO_PMH7=y - -# -# Intel Firmware -# -CONFIG_HAVE_ME_BIN=y -# CONFIG_STITCH_ME_BIN is not set -# CONFIG_CHECK_ME is not set -# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set -# CONFIG_USE_ME_CLEANER is not set -CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y -CONFIG_HAVE_GBE_BIN=y -# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set -# CONFIG_LOCK_MANAGEMENT_ENGINE is not set -CONFIG_UNLOCK_FLASH_REGIONS=y -CONFIG_ARCH_X86=y -CONFIG_ARCH_BOOTBLOCK_X86_32=y -CONFIG_ARCH_VERSTAGE_X86_32=y -CONFIG_ARCH_ROMSTAGE_X86_32=y -CONFIG_ARCH_POSTCAR_X86_32=y -CONFIG_ARCH_RAMSTAGE_X86_32=y -CONFIG_ARCH_ALL_STAGES_X86_32=y -CONFIG_HAVE_EXP_X86_64_SUPPORT=y -CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y -CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y -CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000 -CONFIG_PC80_SYSTEM=y -CONFIG_HAVE_CMOS_DEFAULT=y -CONFIG_POSTCAR_STAGE=y -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_COLLECT_TIMESTAMPS_TSC=y -CONFIG_HAVE_CF9_RESET=y -CONFIG_DEBUG_HW_BREAKPOINTS=y -CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y -# CONFIG_DUMP_SMBIOS_TYPE17 is not set -# end of Chipset - -# -# Devices -# -CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y -CONFIG_HAVE_LINEAR_FRAMEBUFFER=y -CONFIG_MAINBOARD_HAS_LIBGFXINIT=y -CONFIG_MAINBOARD_USE_LIBGFXINIT=y -# CONFIG_VGA_ROM_RUN is not set -# CONFIG_NO_GFX_INIT is not set -CONFIG_NO_EARLY_GFX_INIT=y - -# -# Display -# -CONFIG_VGA_TEXT_FRAMEBUFFER=y -# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set -# end of Display - -CONFIG_PCI=y -CONFIG_ECAM_MMCONF_SUPPORT=y -CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_AZALIA_HDA_CODEC_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y -CONFIG_ECAM_MMCONF_LENGTH=0x04000000 -CONFIG_PCI_ALLOW_BUS_MASTER=y -CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y -CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y -# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set -# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y -# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set -CONFIG_PCIEXP_HOTPLUG_IO=0x2000 -# CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -CONFIG_INTEL_GMA_HAVE_VBT=y -CONFIG_INTEL_GMA_ADD_VBT=y -# CONFIG_SOFTWARE_I2C is not set -CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set -CONFIG_USE_DDR3=y -# end of Devices - -# -# Generic Drivers -# -CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 -# CONFIG_ELOG is not set -CONFIG_CACHE_MRC_SETTINGS=y -# CONFIG_MRC_SETTINGS_PROTECT is not set -# CONFIG_SMMSTORE is not set -CONFIG_SPI_FLASH=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y -CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y -# CONFIG_SPI_FLASH_NO_FAST_READ is not set -CONFIG_SPI_FLASH_ADESTO=y -CONFIG_SPI_FLASH_AMIC=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_TPM_INIT_RAMSTAGE=y -# CONFIG_TPM_PPI is not set -CONFIG_NO_UART_ON_SUPERIO=y -# CONFIG_DRIVERS_UART_OXPCIE is not set -CONFIG_HAVE_USBDEBUG=y -CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_USBDEBUG is not set -# CONFIG_VPD is not set -# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set -# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set -# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set -# CONFIG_DRIVERS_I2C_MAX98396 is not set -CONFIG_INTEL_INT15=y -CONFIG_INTEL_GMA_ACPI=y -CONFIG_VBT_CBFS_COMPRESSION_LZMA=y -# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set -# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set -CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma" -CONFIG_GFX_GMA=y -CONFIG_GFX_GMA_DYN_CPU=y -CONFIG_GFX_GMA_GENERATION="Ironlake" -CONFIG_GFX_GMA_PCH="Cougar_Point" -CONFIG_GFX_GMA_PANEL_2_PORT="Disabled" -CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC" -# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set -# CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_USE_PC_CMOS_ALTCENTURY is not set -CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70 -CONFIG_MEMORY_MAPPED_TPM=y -CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 -CONFIG_VGA=y -CONFIG_DRIVERS_RICOH_RCE822=y -# CONFIG_DRIVERS_SIL_3114 is not set -# end of Generic Drivers - -# -# Security -# - -# -# CBFS verification -# -# CONFIG_CBFS_VERIFICATION is not set -# end of CBFS verification - -# -# Verified Boot (vboot) -# -# end of Verified Boot (vboot) - -# -# Trusted Platform Module -# -# CONFIG_NO_TPM is not set -CONFIG_TPM1=y -CONFIG_TPM=y -CONFIG_MAINBOARD_HAS_TPM1=y -# CONFIG_TPM_DEACTIVATE is not set -# CONFIG_DEBUG_TPM is not set -# CONFIG_TPM_RDRESP_NEED_DELAY is not set -CONFIG_PCR_BOOT_MODE=1 -CONFIG_PCR_HWID=1 -CONFIG_PCR_SRTM=2 -CONFIG_PCR_FW_VER=10 -CONFIG_PCR_RUNTIME_DATA=3 -# end of Trusted Platform Module - -# -# Memory initialization -# -CONFIG_PLATFORM_HAS_DRAM_CLEAR=y -CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y -# end of Memory initialization - -# CONFIG_INTEL_TXT is not set -# CONFIG_STM is not set -CONFIG_BOOTMEDIA_LOCK_NONE=y -# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set -# CONFIG_BOOTMEDIA_LOCK_CHIP is not set -# CONFIG_BOOTMEDIA_SMM_BWP is not set -# end of Security - -CONFIG_ACPI_HAVE_PCAT_8259=y -CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y -CONFIG_ACPI_SOC_NVS=y -CONFIG_ACPI_NO_CUSTOM_MADT=y -CONFIG_ACPI_COMMON_MADT_LAPIC=y -CONFIG_ACPI_COMMON_MADT_IOAPIC=y -CONFIG_HAVE_ACPI_TABLES=y -CONFIG_BOOT_DEVICE_SPI_FLASH=y -CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y -CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y -CONFIG_RTC=y -CONFIG_HEAP_SIZE=0x100000 - -# -# Console -# -CONFIG_BOOTBLOCK_CONSOLE=y -CONFIG_POSTCAR_CONSOLE=y -CONFIG_SQUELCH_EARLY_SMP=y -# CONFIG_SPKMODEM is not set -# CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y -# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set -# CONFIG_CONSOLE_SPI_FLASH is not set -# CONFIG_CONSOLE_I2C_SMBUS is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set -# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set -CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0 -CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y -CONFIG_CONSOLE_USE_ANSI_ESCAPES=y -# CONFIG_CMOS_POST is not set -CONFIG_POST_DEVICE_NONE=y -# CONFIG_POST_DEVICE_LPC is not set -# CONFIG_POST_DEVICE_PCI_PCIE is not set -CONFIG_POST_IO_PORT=0x80 -CONFIG_HWBASE_DEBUG_NULL=y -# end of Console - -CONFIG_HAVE_ACPI_RESUME=y -CONFIG_RESUME_PATH_SAME_AS_BOOT=y -CONFIG_HAVE_MONOTONIC_TIMER=y -CONFIG_HAVE_OPTION_TABLE=y -CONFIG_IOAPIC=y -CONFIG_USE_WATCHDOG_ON_BOOT=y - -# -# System tables -# -CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_SMBIOS_PROVIDED_BY_MOBO=y -CONFIG_BIOS_VENDOR="coreboot" -CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -# end of System tables - -# -# Payload -# -CONFIG_PAYLOAD_NONE=y -# end of Payload - -# -# Debugging -# - -# -# CPU Debug Settings -# -# CONFIG_DISPLAY_MTRRS is not set - -# -# Vendorcode Debug Settings -# - -# -# BLOB Debug Settings -# - -# -# General Debug Settings -# -# CONFIG_FATAL_ASSERTS is not set -# CONFIG_DEBUG_CBFS is not set -CONFIG_HAVE_DEBUG_RAM_SETUP=y -# CONFIG_DEBUG_RAM_SETUP is not set -CONFIG_HAVE_DEBUG_SMBUS=y -# CONFIG_DEBUG_SMBUS is not set -# CONFIG_DEBUG_CONSOLE_INIT is not set -# CONFIG_DEBUG_SPI_FLASH is not set -# CONFIG_DEBUG_BOOT_STATE is not set -# CONFIG_DEBUG_ADA_CODE is not set -CONFIG_HAVE_EM100_SUPPORT=y -# CONFIG_EM100 is not set -# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set -# end of Debugging - -CONFIG_RAMSTAGE_ADA=y -CONFIG_RAMSTAGE_LIBHWBASE=y -CONFIG_HWBASE_DYNAMIC_MMIO=y -CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000 -CONFIG_HWBASE_DIRECT_PCIDEV=y -CONFIG_DECOMPRESS_OFAST=y -CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_MAX_REBOOT_CNT=3 -CONFIG_RELOCATABLE_MODULES=y -CONFIG_HAVE_BOOTBLOCK=y -CONFIG_HAVE_ROMSTAGE=y -CONFIG_HAVE_RAMSTAGE=y diff --git a/config/coreboot/x230edp_12mb/target.cfg b/config/coreboot/x230edp_12mb/target.cfg deleted file mode 100644 index cd477e6f..00000000 --- a/config/coreboot/x230edp_12mb/target.cfg +++ /dev/null @@ -1,9 +0,0 @@ -tree="default" -xarch="i386-elf" -payload_grub="y" -payload_grub_withseabios="y" -payload_seabios="y" -payload_memtest="y" -grub_scan_disk="ahci" -status="broken" # TODO: VCC3P patch -release="n" diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb index 80ed9c78..ca11d165 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_12mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set CONFIG_BOARD_LENOVO_X230T=y # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode index 1d90b98c..bad2ecd6 100644 --- a/config/coreboot/x230t_12mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_12mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set CONFIG_BOARD_LENOVO_X230T=y # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb index e9d559ed..c98c70d5 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x230t_16mb/config/libgfxinit_corebootfb @@ -196,11 +196,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set CONFIG_BOARD_LENOVO_X230T=y # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode index 3033d446..c0d848d0 100644 --- a/config/coreboot/x230t_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x230t_16mb/config/libgfxinit_txtmode @@ -194,11 +194,9 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000 # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set CONFIG_BOARD_LENOVO_X230T=y # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_VBOOT_SLOTS_RW_AB=y CONFIG_DRIVER_LENOVO_SERIALS=y diff --git a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb index d5ec9e74..61fedae8 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_16mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x301_16mb/config/libgfxinit_txtmode b/config/coreboot/x301_16mb/config/libgfxinit_txtmode index 4fbdc435..d5c24416 100644 --- a/config/coreboot/x301_16mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_16mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb index 94403e77..02a910d7 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_4mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x301_4mb/config/libgfxinit_txtmode b/config/coreboot/x301_4mb/config/libgfxinit_txtmode index b1867a46..f6652cfc 100644 --- a/config/coreboot/x301_4mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_4mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb index b1f49efd..d800eed3 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_corebootfb +++ b/config/coreboot/x301_8mb/config/libgfxinit_corebootfb @@ -193,11 +193,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/coreboot/x301_8mb/config/libgfxinit_txtmode b/config/coreboot/x301_8mb/config/libgfxinit_txtmode index 31bad0d1..ef88107c 100644 --- a/config/coreboot/x301_8mb/config/libgfxinit_txtmode +++ b/config/coreboot/x301_8mb/config/libgfxinit_txtmode @@ -191,11 +191,9 @@ CONFIG_BOARD_LENOVO_X301=y # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X1 is not set -# CONFIG_BOARD_LENOVO_X220_EDP is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X230T is not set # CONFIG_BOARD_LENOVO_X230S is not set -# CONFIG_BOARD_LENOVO_X230_EDP is not set # CONFIG_BOARD_LENOVO_X60 is not set CONFIG_DRIVER_LENOVO_SERIALS=y CONFIG_THINKPADEC_HKEY_EISAID="IBM0068" diff --git a/config/vendor/sources b/config/vendor/sources index 2653c877..516077c5 100644 --- a/config/vendor/sources +++ b/config/vendor/sources @@ -9,13 +9,13 @@ # where previously we used 160-bit SHA-1 algorithm; SHA-1 is not secure, # having demonstrated collisions, so we have switched to using sha512sum -{x230 x230t x230i x230edp t430 t530 w530}{ +{x230 x230t x230i t430 t530 w530}{ DL_hash 4dc908050c91c1227645c900ddee88652937540af4ba222b0239b7f459f260cdf6e5e8113ac14e5543d00cf53abdd6c7bd23e61f690de1ce45a3709a30cbb91c DL_url https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe DL_url_bkup https://web.archive.org/web/20210706183911/https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe } -{x220 x220t x220edp t420 t520 t420s}{ +{x220 x220t t420 t520 t420s}{ DL_hash 81c9917938c4a2a4f128c976250451931efd0f25b51ff34f058ddacb8eec27272691371864a683ec7abcb924fea32592d061584c7b2571a5d3e84eb870281cc3 DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe From 67ddd3f2f675bc1f15e737e0d694fb245dde7715 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Fri, 3 May 2024 16:35:00 -0600 Subject: [PATCH 0080/1319] coreboot/default: Add patches to fix S3 on SNB/IVB Latitudes Signed-off-by: Nicholas Chin --- ...l-mec5035-Add-S3-suspend-SMI-handler.patch | 117 +++++++++++++++ ...S3-SMI-handler-for-SNB-IVB-Latitudes.patch | 133 ++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch create mode 100644 config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch diff --git a/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch b/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch new file mode 100644 index 00000000..97f14314 --- /dev/null +++ b/config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch @@ -0,0 +1,117 @@ +From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 3 May 2024 11:03:32 -0600 +Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler + +Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 +Signed-off-by: Nicholas Chin +--- + src/ec/dell/mec5035/Makefile.mk | 1 + + src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++ + src/ec/dell/mec5035/mec5035.h | 19 +++++++++++++++++++ + src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++ + 4 files changed, 51 insertions(+) + create mode 100644 src/ec/dell/mec5035/smihandler.c + +diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk +index 4ebdd811f9..be557e4599 100644 +--- a/src/ec/dell/mec5035/Makefile.mk ++++ b/src/ec/dell/mec5035/Makefile.mk +@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y) + bootblock-y += mec5035.c + romstage-y += mec5035.c + ramstage-y += mec5035.c ++smm-y += mec5035.c smihandler.c + + endif +diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c +index 68b6b2f7fb..33bf046634 100644 +--- a/src/ec/dell/mec5035/mec5035.c ++++ b/src/ec/dell/mec5035/mec5035.c +@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state) + ec_command(CMD_RADIO_CTRL); + } + ++void mec5035_sleep_enable(void) ++{ ++ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0}; ++ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS); ++ ec_command(CMD_SLEEP_ENABLE); ++} ++ ++void mec5035_change_wake(u8 source, enum ec_wake_change change) ++{ ++ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40}; ++ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS); ++ ec_command(CMD_ACPI_WAKEUP_CHANGE); ++} ++ + void mec5035_early_init(void) + { + /* If this isn't sent the EC shuts down the system after about 15 +diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h +index fa15a9d621..069616fbc5 100644 +--- a/src/ec/dell/mec5035/mec5035.h ++++ b/src/ec/dell/mec5035/mec5035.h +@@ -4,6 +4,7 @@ + #define _EC_DELL_MEC5035_H_ + + #include ++#include + + #define NUM_REGISTERS 32 + +@@ -29,9 +30,27 @@ enum ec_radio_state { + RADIO_ON + }; + ++#define CMD_ACPI_WAKEUP_CHANGE 0x4a ++#define ACPI_WAKEUP_NUM_ARGS 4 ++enum ec_wake_change { ++ WAKE_OFF = 0, ++ WAKE_ON ++}; ++enum ec_acpi_wake_events { ++ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */ ++ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */ ++ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */ ++}; ++ ++#define CMD_SLEEP_ENABLE 0x64 ++#define SLEEP_EN_NUM_ARGS 2 ++ + u8 mec5035_mouse_touchpad(u8 setting); + void mec5035_cpu_ok(void); + void mec5035_early_init(void); + void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state); ++void mec5035_sleep(int slp_type); ++void mec5035_change_wake(u8 source, enum ec_wake_change change); ++void mec5035_sleep_enable(void); + + #endif /* _EC_DELL_MEC5035_H_ */ +diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c +new file mode 100644 +index 0000000000..1db834773d +--- /dev/null ++++ b/src/ec/dell/mec5035/smihandler.c +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include "mec5035.h" ++ ++void mec5035_sleep(int slp_type) ++{ ++ switch (slp_type) { ++ case ACPI_S3: ++ /* System does not yet resume properly if woken by lid */ ++ mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF); ++ mec5035_sleep_enable(); ++ break; ++ } ++} +-- +2.44.0 + diff --git a/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch b/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch new file mode 100644 index 00000000..34d92278 --- /dev/null +++ b/config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch @@ -0,0 +1,133 @@ +From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001 +From: Nicholas Chin +Date: Fri, 3 May 2024 16:31:12 -0600 +Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes + +This should fix S3 suspend on these systems + +Signed-off-by: Nicholas Chin +--- + src/mainboard/dell/e5420/smihandler.c | 9 +++++++++ + src/mainboard/dell/e5520/smihandler.c | 9 +++++++++ + src/mainboard/dell/e5530/smihandler.c | 9 +++++++++ + src/mainboard/dell/e6420/smihandler.c | 9 +++++++++ + src/mainboard/dell/e6430/smihandler.c | 9 +++++++++ + src/mainboard/dell/e6520/smihandler.c | 9 +++++++++ + src/mainboard/dell/e6530/smihandler.c | 9 +++++++++ + 7 files changed, 63 insertions(+) + create mode 100644 src/mainboard/dell/e5420/smihandler.c + create mode 100644 src/mainboard/dell/e5520/smihandler.c + create mode 100644 src/mainboard/dell/e5530/smihandler.c + create mode 100644 src/mainboard/dell/e6420/smihandler.c + create mode 100644 src/mainboard/dell/e6430/smihandler.c + create mode 100644 src/mainboard/dell/e6520/smihandler.c + create mode 100644 src/mainboard/dell/e6530/smihandler.c + +diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e5420/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e5520/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e5530/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e6420/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e6430/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e6520/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c +new file mode 100644 +index 0000000000..334d7b1a5f +--- /dev/null ++++ b/src/mainboard/dell/e6530/smihandler.c +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++ ++void mainboard_smi_sleep(u8 slp_typ) ++{ ++ mec5035_sleep(slp_typ); ++} +-- +2.44.0 + From a9bc6b254b319c69c16e339ec352ea7be10be626 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 00:09:45 +0100 Subject: [PATCH 0081/1319] mark lenovo x301 as stable for release Signed-off-by: Leah Rowe --- config/coreboot/x301_16mb/target.cfg | 3 +-- config/coreboot/x301_4mb/target.cfg | 3 +-- config/coreboot/x301_8mb/target.cfg | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/config/coreboot/x301_16mb/target.cfg b/config/coreboot/x301_16mb/target.cfg index 0867e005..f16a94a4 100644 --- a/config/coreboot/x301_16mb/target.cfg +++ b/config/coreboot/x301_16mb/target.cfg @@ -5,5 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" -release="n" +status="stable" diff --git a/config/coreboot/x301_4mb/target.cfg b/config/coreboot/x301_4mb/target.cfg index 0867e005..f16a94a4 100644 --- a/config/coreboot/x301_4mb/target.cfg +++ b/config/coreboot/x301_4mb/target.cfg @@ -5,5 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" -release="n" +status="stable" diff --git a/config/coreboot/x301_8mb/target.cfg b/config/coreboot/x301_8mb/target.cfg index 0867e005..f16a94a4 100644 --- a/config/coreboot/x301_8mb/target.cfg +++ b/config/coreboot/x301_8mb/target.cfg @@ -5,5 +5,4 @@ payload_grub_withseabios="y" payload_seabios="y" payload_memtest="y" grub_scan_disk="ahci" -status="untested" -release="n" +status="stable" From d839bfa1ed489dfc72e46341375322ecbfe5769a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 00:14:41 +0100 Subject: [PATCH 0082/1319] mark 9020 sff/mt stable for release i initially decided to say unstable, but the default configuration is reliable; the only caveat is that if you enable IOMMU, you must only be using intel graphics. this is already documented in warn.txt files, and on the website, so it's more than ok to call this stable. i use one of these myself as my daily driver and it's rock solid. i haven't had any problems with it. i also sell these to people with libreboot. no problems. mark it as stable, ready for a full release. Signed-off-by: Leah Rowe --- config/coreboot/dell9020mt-nri_12mb/target.cfg | 2 +- config/coreboot/dell9020mt_12mb/target.cfg | 2 +- config/coreboot/dell9020mtbmrc_12mb/target.cfg | 2 +- config/coreboot/dell9020sff-nri_12mb/target.cfg | 2 +- config/coreboot/dell9020sff_12mb/target.cfg | 2 +- config/coreboot/dell9020sffbmrc_12mb/target.cfg | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/config/coreboot/dell9020mt-nri_12mb/target.cfg b/config/coreboot/dell9020mt-nri_12mb/target.cfg index bb76392a..bc4053d4 100644 --- a/config/coreboot/dell9020mt-nri_12mb/target.cfg +++ b/config/coreboot/dell9020mt-nri_12mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index ac0b1792..a3acd5fb 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="unstable" +status="stable" diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg index ac0b1792..a3acd5fb 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="unstable" +status="stable" diff --git a/config/coreboot/dell9020sff-nri_12mb/target.cfg b/config/coreboot/dell9020sff-nri_12mb/target.cfg index bb76392a..bc4053d4 100644 --- a/config/coreboot/dell9020sff-nri_12mb/target.cfg +++ b/config/coreboot/dell9020sff-nri_12mb/target.cfg @@ -5,4 +5,4 @@ payload_seabios_withgrub="y" payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index ac0b1792..a3acd5fb 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="unstable" +status="stable" diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg index ac0b1792..a3acd5fb 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="unstable" +status="stable" From 985870297dd7aa89cb29b4c9b6e9ece82c4355c3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 00:24:27 +0100 Subject: [PATCH 0083/1319] deprecate MRC 9020MT/SFF (NRI 9020 is default now) NRI is libre raminit MRC is binary blob raminit the libre raminit is stable enough now that it's default the MRC-based targets will be removed in a future release Signed-off-by: Leah Rowe --- config/coreboot/dell9020mt_12mb/target.cfg | 2 +- config/coreboot/dell9020mt_12mb/warn.txt | 9 +++++++++ config/coreboot/dell9020mtbmrc_12mb/target.cfg | 2 +- config/coreboot/dell9020mtbmrc_12mb/warn.txt | 9 +++++++++ config/coreboot/dell9020sff_12mb/target.cfg | 2 +- config/coreboot/dell9020sff_12mb/warn.txt | 9 +++++++++ config/coreboot/dell9020sffbmrc_12mb/target.cfg | 2 +- config/coreboot/dell9020sffbmrc_12mb/warn.txt | 9 +++++++++ 8 files changed, 40 insertions(+), 4 deletions(-) diff --git a/config/coreboot/dell9020mt_12mb/target.cfg b/config/coreboot/dell9020mt_12mb/target.cfg index a3acd5fb..0141f142 100644 --- a/config/coreboot/dell9020mt_12mb/target.cfg +++ b/config/coreboot/dell9020mt_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="deprecated" diff --git a/config/coreboot/dell9020mt_12mb/warn.txt b/config/coreboot/dell9020mt_12mb/warn.txt index fe1aa7f9..6c262da4 100644 --- a/config/coreboot/dell9020mt_12mb/warn.txt +++ b/config/coreboot/dell9020mt_12mb/warn.txt @@ -1 +1,10 @@ Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable + +*This* target uses Intel MRC (a binary blob) for memory controller initialisation. +If you want *libre* initialisation (recommended), use the *nri* targets instead, +e.g. dell9020sff-nri_12mb or dell9020mt-nri_12mb + +These MRC-based targets will be *removed* in a future Libreboot release. It is +strongly recommended that you use the NRI-based targets (Native RAM initialisation). + +This version uses Haswell MRC, which is compatible with the machine. diff --git a/config/coreboot/dell9020mtbmrc_12mb/target.cfg b/config/coreboot/dell9020mtbmrc_12mb/target.cfg index a3acd5fb..0141f142 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020mtbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="deprecated" diff --git a/config/coreboot/dell9020mtbmrc_12mb/warn.txt b/config/coreboot/dell9020mtbmrc_12mb/warn.txt index fe1aa7f9..21be619a 100644 --- a/config/coreboot/dell9020mtbmrc_12mb/warn.txt +++ b/config/coreboot/dell9020mtbmrc_12mb/warn.txt @@ -1 +1,10 @@ Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable + +*This* target uses Intel MRC (a binary blob) for memory controller initialisation. +If you want *libre* initialisation (recommended), use the *nri* targets instead, +e.g. dell9020sff-nri_12mb or dell9020mt-nri_12mb + +These MRC-based targets will be *removed* in a future Libreboot release. It is +strongly recommended that you use the NRI-based targets (Native RAM initialisation). + +This version uses Broadwell MRC, which is compatible on Haswell machines. diff --git a/config/coreboot/dell9020sff_12mb/target.cfg b/config/coreboot/dell9020sff_12mb/target.cfg index a3acd5fb..0141f142 100644 --- a/config/coreboot/dell9020sff_12mb/target.cfg +++ b/config/coreboot/dell9020sff_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="deprecated" diff --git a/config/coreboot/dell9020sff_12mb/warn.txt b/config/coreboot/dell9020sff_12mb/warn.txt index fe1aa7f9..6c262da4 100644 --- a/config/coreboot/dell9020sff_12mb/warn.txt +++ b/config/coreboot/dell9020sff_12mb/warn.txt @@ -1 +1,10 @@ Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable + +*This* target uses Intel MRC (a binary blob) for memory controller initialisation. +If you want *libre* initialisation (recommended), use the *nri* targets instead, +e.g. dell9020sff-nri_12mb or dell9020mt-nri_12mb + +These MRC-based targets will be *removed* in a future Libreboot release. It is +strongly recommended that you use the NRI-based targets (Native RAM initialisation). + +This version uses Haswell MRC, which is compatible with the machine. diff --git a/config/coreboot/dell9020sffbmrc_12mb/target.cfg b/config/coreboot/dell9020sffbmrc_12mb/target.cfg index a3acd5fb..0141f142 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/target.cfg +++ b/config/coreboot/dell9020sffbmrc_12mb/target.cfg @@ -6,4 +6,4 @@ payload_seabios_grubonly="y" payload_memtest="y" grub_scan_disk="ahci" release="n" -status="stable" +status="deprecated" diff --git a/config/coreboot/dell9020sffbmrc_12mb/warn.txt b/config/coreboot/dell9020sffbmrc_12mb/warn.txt index fe1aa7f9..21be619a 100644 --- a/config/coreboot/dell9020sffbmrc_12mb/warn.txt +++ b/config/coreboot/dell9020sffbmrc_12mb/warn.txt @@ -1 +1,10 @@ Completely stable with graphics, but IOMMU disabled by default; graphics cards only work with IOMMU turned off. Intel graphics works fine with IOMMU turned on. IOMMU is needed for Qubes to work properly. To turn on IOMMU, do this to your ROM before flashing (ONLY do this if using Intel graphics): ./nvramtool -C libreboot.rom -w iommu=Enable + +*This* target uses Intel MRC (a binary blob) for memory controller initialisation. +If you want *libre* initialisation (recommended), use the *nri* targets instead, +e.g. dell9020sff-nri_12mb or dell9020mt-nri_12mb + +These MRC-based targets will be *removed* in a future Libreboot release. It is +strongly recommended that you use the NRI-based targets (Native RAM initialisation). + +This version uses Broadwell MRC, which is compatible on Haswell machines. From d9c0346a003d6a149e8759bb224daa720b7254ea Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 00:26:52 +0100 Subject: [PATCH 0084/1319] build/roms: more useful status warnings Signed-off-by: Leah Rowe --- script/build/roms | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/script/build/roms b/script/build/roms index 1ed64004..0b10e78a 100755 --- a/script/build/roms +++ b/script/build/roms @@ -157,12 +157,15 @@ configure_target() skip_board() { - [ "$listboards" != "y" ] && [ "$status" != "stable" ] && \ - printf "WARNING: %s not stable (status=%s):\n\n" \ + if [ "$listboards" != "y" ] && [ "$status" != "stable" ]; then + printf "\n\n\t!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" + printf "\t__WARNING: %s has status '%s'__\n" \ "$board" "$status" + printf "\t!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n" + fi if [ -f "$targetdir/warn.txt" ] && [ "$listboards" != "y" ]; then - printf "Regarding board '%s' (status '%s'):\n" \ + printf "Regarding target '%s' (status '%s'):\n\n" \ "$board" "$status" cat -u "$targetdir/warn.txt" || \ $err "!cat $targetdir/warn.txt" @@ -176,7 +179,7 @@ skip_board() printf "\nTo disable this dialog when building, do:\n" printf "export LBMK_STATUS=n\n\n" while true; do - printf "Board %s has status '%s'. Skip? [y/n]" \ + printf "Board %s has status '%s'. Skip? [y/n] " \ "$board" "$status" read -r skip [ "$skip" = "y" ] && return 0 From 7e799e1f16d671b58eb0b1fdbe06069fc175608c Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 04:13:53 +0100 Subject: [PATCH 0085/1319] nb/haswell: lock policy regs when disabling IOMMU Angel Pons told me I should do it. See comments here: https://review.coreboot.org/c/coreboot/+/81016 I see no harm in complying with the request. I'll merge this into the main patch at a later date and try to get this upstreamed. Just a reminder: on Optiplex 9020 variants, Xorg locks up under Linux when tested with a graphics card; disabling IOMMU works around the issue. Intel graphics work just fine with IOMMU turned on. Libreboot disables IOMMU by default, on the 9020, so that users can install graphics cards easily. I'm pretty sure this is the correct way to do it. The machine still seems to boot, in this configuration. Signed-off-by: Leah Rowe --- ...ock-policy-regs-when-disabling-IOMMU.patch | 55 +++++++++++++++++++ ...ock-policy-regs-when-disabling-IOMMU.patch | 55 +++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch create mode 100644 config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch diff --git a/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch new file mode 100644 index 00000000..a7af707e --- /dev/null +++ b/config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -0,0 +1,55 @@ +From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 May 2024 02:00:53 +0100 +Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU + +Angel Pons told me I should do it. See comments here: +https://review.coreboot.org/c/coreboot/+/81016 + +I see no harm in complying with the request. I'll merge +this into the main patch at a later date and try to +get this upstreamed. + +Just a reminder: on Optiplex 9020 variants, Xorg locks up +under Linux when tested with a graphics card; disabling +IOMMU works around the issue. Intel graphics work just fine +with IOMMU turned on. Libreboot disables IOMMU by default, +on the 9020, so that users can install graphics cards easily. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/early_init.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index 1a7e0b1076..e9506ee830 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void) + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + u8 enable_iommu = get_uint_option("iommu", 1); + +- if (!enable_iommu) +- return; +- + if (capid0_a & VTD_DISABLE) + return; + +- /* Setup BARs: zeroize top 32 bits; set enable bit */ +- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); +- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); +- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); +- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ if (enable_iommu) { ++ /* Setup BARs: zeroize top 32 bits; set enable bit */ ++ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); ++ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); ++ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); ++ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ } + + /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ + u32 reg32; +-- +2.39.2 + diff --git a/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch b/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch new file mode 100644 index 00000000..9b6020a2 --- /dev/null +++ b/config/coreboot/haswell/patches/0027-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch @@ -0,0 +1,55 @@ +From b75d9e385137b3b561fc7220c04f742817d319b2 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Sat, 4 May 2024 02:00:53 +0100 +Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU + +Angel Pons told me I should do it. See comments here: +https://review.coreboot.org/c/coreboot/+/81016 + +I see no harm in complying with the request. I'll merge +this into the main patch at a later date and try to +get this upstreamed. + +Just a reminder: on Optiplex 9020 variants, Xorg locks up +under Linux when tested with a graphics card; disabling +IOMMU works around the issue. Intel graphics work just fine +with IOMMU turned on. Libreboot disables IOMMU by default, +on the 9020, so that users can install graphics cards easily. + +Signed-off-by: Leah Rowe +--- + src/northbridge/intel/haswell/early_init.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c +index 1a7e0b1076..e9506ee830 100644 +--- a/src/northbridge/intel/haswell/early_init.c ++++ b/src/northbridge/intel/haswell/early_init.c +@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void) + const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + u8 enable_iommu = get_uint_option("iommu", 1); + +- if (!enable_iommu) +- return; +- + if (capid0_a & VTD_DISABLE) + return; + +- /* Setup BARs: zeroize top 32 bits; set enable bit */ +- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); +- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); +- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); +- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ if (enable_iommu) { ++ /* Setup BARs: zeroize top 32 bits; set enable bit */ ++ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32); ++ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1); ++ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32); ++ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1); ++ } + + /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */ + u32 reg32; +-- +2.39.2 + From 7a955a4c728169f5d09aa95cb173db19e52b3b0d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 04:52:02 +0100 Subject: [PATCH 0086/1319] d510mo and d945gclf: disable for release Signed-off-by: Leah Rowe --- config/coreboot/d510mo/target.cfg | 1 + config/coreboot/d510mo/warn.txt | 1 + config/coreboot/d510mo_16mb/target.cfg | 1 + config/coreboot/d510mo_16mb/warn.txt | 1 + config/coreboot/d945gclf_512kb/target.cfg | 1 + config/coreboot/d945gclf_512kb/warn.txt | 1 + config/coreboot/d945gclf_8mb/target.cfg | 1 + config/coreboot/d945gclf_8mb/warn.txt | 1 + 8 files changed, 8 insertions(+) create mode 100644 config/coreboot/d510mo/warn.txt create mode 100644 config/coreboot/d510mo_16mb/warn.txt create mode 100644 config/coreboot/d945gclf_512kb/warn.txt create mode 100644 config/coreboot/d945gclf_8mb/warn.txt diff --git a/config/coreboot/d510mo/target.cfg b/config/coreboot/d510mo/target.cfg index f07fee9a..5c15f467 100644 --- a/config/coreboot/d510mo/target.cfg +++ b/config/coreboot/d510mo/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="n" payload_seabios="y" payload_memtest="y" status="untested" +release="n" diff --git a/config/coreboot/d510mo/warn.txt b/config/coreboot/d510mo/warn.txt new file mode 100644 index 00000000..7e2498a1 --- /dev/null +++ b/config/coreboot/d510mo/warn.txt @@ -0,0 +1 @@ +this board has never been stable, and has not been tested in Libreboot 20240504 so no ROM images included for it in that release diff --git a/config/coreboot/d510mo_16mb/target.cfg b/config/coreboot/d510mo_16mb/target.cfg index a99b11f0..82e52183 100644 --- a/config/coreboot/d510mo_16mb/target.cfg +++ b/config/coreboot/d510mo_16mb/target.cfg @@ -4,3 +4,4 @@ payload_seabios="y" payload_seabios_withgrub="y" payload_memtest="y" status="untested" +release="n" diff --git a/config/coreboot/d510mo_16mb/warn.txt b/config/coreboot/d510mo_16mb/warn.txt new file mode 100644 index 00000000..7e2498a1 --- /dev/null +++ b/config/coreboot/d510mo_16mb/warn.txt @@ -0,0 +1 @@ +this board has never been stable, and has not been tested in Libreboot 20240504 so no ROM images included for it in that release diff --git a/config/coreboot/d945gclf_512kb/target.cfg b/config/coreboot/d945gclf_512kb/target.cfg index 5899fae2..2c2cf673 100644 --- a/config/coreboot/d945gclf_512kb/target.cfg +++ b/config/coreboot/d945gclf_512kb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" status="untested" +release="n" diff --git a/config/coreboot/d945gclf_512kb/warn.txt b/config/coreboot/d945gclf_512kb/warn.txt new file mode 100644 index 00000000..7e2498a1 --- /dev/null +++ b/config/coreboot/d945gclf_512kb/warn.txt @@ -0,0 +1 @@ +this board has never been stable, and has not been tested in Libreboot 20240504 so no ROM images included for it in that release diff --git a/config/coreboot/d945gclf_8mb/target.cfg b/config/coreboot/d945gclf_8mb/target.cfg index 5899fae2..2c2cf673 100644 --- a/config/coreboot/d945gclf_8mb/target.cfg +++ b/config/coreboot/d945gclf_8mb/target.cfg @@ -5,3 +5,4 @@ payload_grub_withseabios="n" payload_seabios="y" payload_memtest="n" status="untested" +release="n" diff --git a/config/coreboot/d945gclf_8mb/warn.txt b/config/coreboot/d945gclf_8mb/warn.txt new file mode 100644 index 00000000..7e2498a1 --- /dev/null +++ b/config/coreboot/d945gclf_8mb/warn.txt @@ -0,0 +1 @@ +this board has never been stable, and has not been tested in Libreboot 20240504 so no ROM images included for it in that release From 5bf25eac05c0d081aeb7390ffa8529b044b62bf9 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 04:58:20 +0100 Subject: [PATCH 0087/1319] coreboot: update latitude release status working s3 means i'm happy to mark it as being stable. Signed-off-by: Leah Rowe --- config/coreboot/e5420_6mb/target.cfg | 2 +- config/coreboot/e5420_6mb/warn.txt | 2 +- config/coreboot/e5520_6mb/target.cfg | 2 +- config/coreboot/e5520_6mb/warn.txt | 2 +- config/coreboot/e5530_12mb/target.cfg | 2 +- config/coreboot/e5530_12mb/warn.txt | 2 +- config/coreboot/e6400_4mb/target.cfg | 2 +- config/coreboot/e6400_4mb/warn.txt | 2 +- config/coreboot/e6400nvidia_4mb/target.cfg | 2 +- config/coreboot/e6400nvidia_4mb/warn.txt | 2 +- config/coreboot/e6420_10mb/target.cfg | 2 +- config/coreboot/e6420_10mb/warn.txt | 2 +- config/coreboot/e6430_12mb/target.cfg | 2 +- config/coreboot/e6430_12mb/warn.txt | 2 +- config/coreboot/e6520_10mb/target.cfg | 2 +- config/coreboot/e6520_10mb/warn.txt | 2 +- config/coreboot/e6530_12mb/target.cfg | 2 +- config/coreboot/e6530_12mb/warn.txt | 2 +- 18 files changed, 18 insertions(+), 18 deletions(-) diff --git a/config/coreboot/e5420_6mb/target.cfg b/config/coreboot/e5420_6mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5420_6mb/target.cfg +++ b/config/coreboot/e5420_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e5420_6mb/warn.txt b/config/coreboot/e5420_6mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e5420_6mb/warn.txt +++ b/config/coreboot/e5420_6mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e5520_6mb/target.cfg b/config/coreboot/e5520_6mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5520_6mb/target.cfg +++ b/config/coreboot/e5520_6mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e5520_6mb/warn.txt b/config/coreboot/e5520_6mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e5520_6mb/warn.txt +++ b/config/coreboot/e5520_6mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e5530_12mb/target.cfg b/config/coreboot/e5530_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e5530_12mb/target.cfg +++ b/config/coreboot/e5530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e5530_12mb/warn.txt b/config/coreboot/e5530_12mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e5530_12mb/warn.txt +++ b/config/coreboot/e5530_12mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6400_4mb/target.cfg b/config/coreboot/e6400_4mb/target.cfg index d1ea26ad..fb7c7bfb 100644 --- a/config/coreboot/e6400_4mb/target.cfg +++ b/config/coreboot/e6400_4mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" # broken s3 +status="stable" # broken s3 diff --git a/config/coreboot/e6400_4mb/warn.txt b/config/coreboot/e6400_4mb/warn.txt index 30e61da5..9545476b 100644 --- a/config/coreboot/e6400_4mb/warn.txt +++ b/config/coreboot/e6400_4mb/warn.txt @@ -1,3 +1,3 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. If you have the nvidia gpu variant, please use e6400nvidia_4mb instead. diff --git a/config/coreboot/e6400nvidia_4mb/target.cfg b/config/coreboot/e6400nvidia_4mb/target.cfg index d1026eed..a1a8caf1 100644 --- a/config/coreboot/e6400nvidia_4mb/target.cfg +++ b/config/coreboot/e6400nvidia_4mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" # s3, nvidia+nouveau +status="stable" # s3, nvidia+nouveau diff --git a/config/coreboot/e6400nvidia_4mb/warn.txt b/config/coreboot/e6400nvidia_4mb/warn.txt index 5b2e4a00..34f4bdf2 100644 --- a/config/coreboot/e6400nvidia_4mb/warn.txt +++ b/config/coreboot/e6400nvidia_4mb/warn.txt @@ -1,3 +1,3 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. Nvidia GPU on this model doesn't work when you try xorg; xorg will hang. Use "nomodeset" under Linux, when booting. On BSD, the nv driver works ok but can get very slow-slideshow-y when dragging windows, yet rendered video will usually run smooth; use a tiling window manager on BSD systems, or again use software rendering. diff --git a/config/coreboot/e6420_10mb/target.cfg b/config/coreboot/e6420_10mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6420_10mb/target.cfg +++ b/config/coreboot/e6420_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6420_10mb/warn.txt b/config/coreboot/e6420_10mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e6420_10mb/warn.txt +++ b/config/coreboot/e6420_10mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6430_12mb/target.cfg b/config/coreboot/e6430_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6430_12mb/target.cfg +++ b/config/coreboot/e6430_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6430_12mb/warn.txt b/config/coreboot/e6430_12mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e6430_12mb/warn.txt +++ b/config/coreboot/e6430_12mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6520_10mb/target.cfg b/config/coreboot/e6520_10mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6520_10mb/target.cfg +++ b/config/coreboot/e6520_10mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6520_10mb/warn.txt b/config/coreboot/e6520_10mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e6520_10mb/warn.txt +++ b/config/coreboot/e6520_10mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. diff --git a/config/coreboot/e6530_12mb/target.cfg b/config/coreboot/e6530_12mb/target.cfg index e48db5e5..a0cfb47e 100644 --- a/config/coreboot/e6530_12mb/target.cfg +++ b/config/coreboot/e6530_12mb/target.cfg @@ -7,4 +7,4 @@ payload_memtest="y" payload_seabios_withgrub="y" payload_seabios_grubonly="y" grub_scan_disk="ahci" -status="unstable" +status="stable" diff --git a/config/coreboot/e6530_12mb/warn.txt b/config/coreboot/e6530_12mb/warn.txt index 57d05e6a..4709a005 100644 --- a/config/coreboot/e6530_12mb/warn.txt +++ b/config/coreboot/e6530_12mb/warn.txt @@ -1 +1 @@ -Battery indicator not working yet. S3 suspend/resume may be broken. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. +Battery indicator not working yet. May shut down instead of throttle on high CPU temperature; use the intel_pstate driver to cap speeds, and monitor performance via CPU stress test and lm-sensors/xsensors utility, before using the machine regularly. From d3aeb2c79f5effd0bc842a131ac9d9f57daf99db Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 06:22:32 +0100 Subject: [PATCH 0088/1319] config/git: importer newer documentation I'm on a schedule here and don't have time to do the release changelog before actually compiling the release. I'm pushing the release changelog / news announcement *while the release is building*. Therefore, the actual release archive will contain Libreboot documentation, but from the lbwww revision just before the release announcement. (a changelog file is still generated from Git, and included in releases) Signed-off-by: Leah Rowe --- config/git/docs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/git/docs b/config/git/docs index c408423a..c6b7a387 100644 --- a/config/git/docs +++ b/config/git/docs @@ -8,7 +8,7 @@ } {mdfiles}{ - rev: 660d9d87c7424c3311d535e6bb6bbeba66bcacbc + rev: 20fd775c855428ecff647a42823746863fd57efe loc: docs/www/html url: https://codeberg.org/libreboot/lbwww bkup_url: https://git.disroot.org/libreboot/lbwww @@ -16,7 +16,7 @@ } {imgfiles}{ - rev: 54aee63ca18400f8de667ab16146f88f47a05488 + rev: 625bb7535d388a235bec47a8ce822cda10b53692 loc: docs/www/html/site/img url: https://codeberg.org/libreboot/lbwww-img bkup_url: https://git.disroot.org/libreboot/lbwww-img From ae9e73890fa915511464d781ae3109fabd9def0e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 4 May 2024 06:25:42 +0100 Subject: [PATCH 0089/1319] Libreboot 20240504 release Signed-off-by: Leah Rowe --- .../0002-say-the-name-libreboot-in-the-grub-menu.patch | 2 +- script/update/release | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch b/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch index 8cea919d..6ff97979 100644 --- a/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch +++ b/config/grub/patches/0001-borderfix/0002-say-the-name-libreboot-in-the-grub-menu.patch @@ -16,7 +16,7 @@ index bd4431000..31308e16a 100644 grub_term_cls (term); - msg_formatted = grub_xasprintf (_("GNU GRUB version %s"), PACKAGE_VERSION); -+ msg_formatted = grub_xasprintf (_("Libreboot 20240225 release, based on coreboot. https://libreboot.org/")); ++ msg_formatted = grub_xasprintf (_("Libreboot 20240504 release, based on coreboot. https://libreboot.org/")); if (!msg_formatted) return; diff --git a/script/update/release b/script/update/release index fcee49e7..405fdc28 100755 --- a/script/update/release +++ b/script/update/release @@ -220,7 +220,7 @@ mktarball() printf "\nCreating archive: %s\n\n" "$2" if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then tar --sort=name --owner=root:0 --group=root:0 \ - --mtime="UTC 2024-02-25" -c "$1" | xz -T$threads -9e \ + --mtime="UTC 2024-05-04" -c "$1" | xz -T$threads -9e \ > "$2" || $err "mktarball 1, ${1}" else # TODO: reproducible tarballs on non-GNU systems From d13d930804a8854b3b170a06f891ecb0e3cc136d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 May 2024 04:41:51 +0100 Subject: [PATCH 0090/1319] build/roms: allow searching status by mismatch for example: ./build roms list stable this lists all images that are marked "stable" now: ./build roms list _stable this lists all images that are *not* marked stable this will help me keep track during development Signed-off-by: Leah Rowe --- script/build/roms | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/script/build/roms b/script/build/roms index 0b10e78a..0e292243 100755 --- a/script/build/roms +++ b/script/build/roms @@ -74,8 +74,16 @@ main() if [ "$listboards" = "y" ]; then [ -z "$list_type" ] && printf "%s\n" "$board" for _list_type in $list_type; do - [ "$status" != "$_list_type" ] && continue - printf "%s\n" "$board" + if [ "${_list_type#_}" = "$_list_type" ]; then + [ "$status" != "$_list_type" ] && \ + continue + printf "%s\n" "$board" + else + [ "$status" = "${_list_type#_}" ] && \ + continue + printf "%s\n" "$board" + break + fi done; continue fi From 2fcbff68fc79112a06a76933c1d5fdb167c259b3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 May 2024 05:09:23 +0100 Subject: [PATCH 0091/1319] build/roms: split up main() it's starting to get a big big, so break it up Signed-off-by: Leah Rowe --- script/build/roms | 81 +++++++++++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 35 deletions(-) diff --git a/script/build/roms b/script/build/roms index 0e292243..3d5a3f5c 100755 --- a/script/build/roms +++ b/script/build/roms @@ -62,41 +62,7 @@ main() $err "Cannot generate list of boards for building" for x in ${boards}; do - eval "$(setvars "n" ${pv}) $(setvars "" ${v})" - grub_background="background1280x800.png" - board="${x}" - status="unknown" - - configure_target - [ "$board" = "$tree" ] && \ - continue - - if [ "$listboards" = "y" ]; then - [ -z "$list_type" ] && printf "%s\n" "$board" - for _list_type in $list_type; do - if [ "${_list_type#_}" = "$_list_type" ]; then - [ "$status" != "$_list_type" ] && \ - continue - printf "%s\n" "$board" - else - [ "$status" = "${_list_type#_}" ] && \ - continue - printf "%s\n" "$board" - break - fi - done; continue - fi - - # exclude certain targets from the release - skip_board && \ - printf "Skip target %s(%s)\n" "$board" "$status" && \ - skipped="* $board($status)\n$skipped" && continue - - build_payloads - build_target_mainboard - - [ -d "bin/${board}" ] || continue - targets="* bin/${board}\n${targets}" + handle_target done [ "$listboards" = "y" ] && return 0 @@ -115,6 +81,31 @@ main() printf "DO NOT flash images from elf/ - please use bin/ instead.\n" } +handle_target() +{ + eval "$(setvars "n" ${pv}) $(setvars "" ${v})" + grub_background="background1280x800.png" + board="${x}" + status="unknown" + + configure_target + [ "$board" = "$tree" ] && \ + return 0 + + print_target_name && return 0 + + # exclude certain targets from the release + skip_board && \ + printf "Skip target %s(%s)\n" "$board" "$status" && \ + skipped="* $board($status)\n$skipped" && return 0 + + build_payloads + build_target_mainboard + + [ -d "bin/${board}" ] || return 0 + targets="* bin/${board}\n${targets}" +} + configure_target() { targetdir="${cfgsdir}/${board}" @@ -163,6 +154,26 @@ configure_target() eval "payload_${_payload}=y" } +print_target_name() +{ + [ "$listboards" = "y" ] || return 1 + + [ -z "$list_type" ] && printf "%s\n" "$board" + + for _list_type in $list_type; do + if [ "${_list_type#_}" = "$_list_type" ]; then + [ "$status" != "$_list_type" ] && \ + continue + printf "%s\n" "$board" + break + elif [ "$status" != "${_list_type#_}" ]; then + printf "%s\n" "$board" + break + fi + done + return 0 +} + skip_board() { if [ "$listboards" != "y" ] && [ "$status" != "stable" ]; then From 580a5559480153f4b3e1983ccdce8e5a2c82c68d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 May 2024 05:18:12 +0100 Subject: [PATCH 0092/1319] build/roms: don't use exit status from skip_board the printf could potentially return non-zero, which might make the script not skip a given target Signed-off-by: Leah Rowe --- script/build/roms | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/script/build/roms b/script/build/roms index 3d5a3f5c..81ecd879 100755 --- a/script/build/roms +++ b/script/build/roms @@ -95,9 +95,11 @@ handle_target() print_target_name && return 0 # exclude certain targets from the release - skip_board && \ - printf "Skip target %s(%s)\n" "$board" "$status" && \ - skipped="* $board($status)\n$skipped" && return 0 + if skip_board; then + printf "Skip target %s(%s)\n" "$board" "$status" + skipped="* $board($status)\n$skipped" + return 0 + fi build_payloads build_target_mainboard From aa5937edd52a80a5385b8feb4275e5f005fb92d9 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 5 May 2024 05:28:06 +0100 Subject: [PATCH 0093/1319] build/roms: don't rely on x in handle_target x is part of the for loop in main() and may or not still be available from handle_target, depending on your implementation of sh, but this should not be assumed do it properly Signed-off-by: Leah Rowe --- script/build/roms | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/script/build/roms b/script/build/roms index 81ecd879..032c0a57 100755 --- a/script/build/roms +++ b/script/build/roms @@ -62,7 +62,7 @@ main() $err "Cannot generate list of boards for building" for x in ${boards}; do - handle_target + handle_target "$x" done [ "$listboards" = "y" ] && return 0 @@ -85,7 +85,7 @@ handle_target() { eval "$(setvars "n" ${pv}) $(setvars "" ${v})" grub_background="background1280x800.png" - board="${x}" + board="$1" status="unknown" configure_target From 58400fc4a5b2a8e9d7eecffe3d9097db43599c5d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 6 May 2024 16:13:13 +0100 Subject: [PATCH 0094/1319] err.sh: correct copyright info i replaced 2022, 2023 with 2022, 2024 when updating the years, as per modifications, but the 2023 copyright doesn't become invalidated change it to 2022-2024 instead, which is correct Signed-off-by: Leah Rowe --- include/err.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/err.sh b/include/err.sh index a25effe6..66338337 100755 --- a/include/err.sh +++ b/include/err.sh @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: 2022, 2024 Leah Rowe +# SPDX-FileCopyrightText: 2022-2024 Leah Rowe export LC_COLLATE=C export LC_ALL=C From 5e4009b539b0c1bbb14eea8f8cd892d3933c3355 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 6 May 2024 22:54:55 +0100 Subject: [PATCH 0095/1319] merge include/err.sh with include/option.sh Signed-off-by: Leah Rowe --- build | 1 - include/err.sh | 95 -------------------------------------- include/option.sh | 101 ++++++++++++++++++++++++++++++++++++++--- script/build/roms | 1 - script/build/serprog | 2 +- script/update/release | 1 - script/update/trees | 1 - script/vendor/download | 1 - script/vendor/inject | 1 - 9 files changed, 95 insertions(+), 109 deletions(-) delete mode 100755 include/err.sh diff --git a/build b/build index 277390fd..4c6a2916 100755 --- a/build +++ b/build @@ -7,7 +7,6 @@ set -u -e -. "include/err.sh" . "include/option.sh" eval "$(setvars "" option aur_notice)" diff --git a/include/err.sh b/include/err.sh deleted file mode 100755 index 66338337..00000000 --- a/include/err.sh +++ /dev/null @@ -1,95 +0,0 @@ -# SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: 2022-2024 Leah Rowe - -export LC_COLLATE=C -export LC_ALL=C - -version=""; versiondate=""; projectname=""; _nogit="" -err="err_"; tmpdir=""; lbmk_status="" - -# if "y": a coreboot target won't be built if target.cfg says release="n" -# (this is used to exclude certain build targets from releases) -lbmk_release= -set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : -[ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE" -[ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" -export LBMK_RELEASE="$lbmk_release" - -# if set to n via export, status checks will be skipped during -# all builds, and all targets will be built regardless of status. -# this replicates the old behaviour of lbmk, prior to the checks. -set | grep LBMK_STATUS 1>/dev/null 2>/dev/null && lbmk_status="$LBMK_STATUS" -[ "$lbmk_status" = "y" ] || [ "$lbmk_status" = "n" ] || lbmk_status="y" -export LBMK_STATUS="$lbmk_status" - -tmpdir_was_set="y" -set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" -if [ "${tmpdir_was_set}" = "y" ]; then - [ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n" -fi -if [ "${tmpdir_was_set}" = "n" ]; then - export TMPDIR="/tmp" - tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)" - export TMPDIR="${tmpdir}" -else - export TMPDIR="${TMPDIR}" - tmpdir="${TMPDIR}" -fi - -x_() { - [ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0 -} - -check_git() -{ - which git 1>/dev/null 2>/dev/null || \ - git_err "git not installed. please install git-scm." - git config --global user.name 1>/dev/null 2>/dev/null || \ - git_err "git config --global user.name \"John Doe\"" - git config --global user.email 1>/dev/null 2>/dev/null || \ - git_err "git config --global user.email \"john.doe@example.com\"" -} - -git_err() -{ - printf "You need to set git name/email, like so:\n%s\n\n" "$1" 1>&2 - $err "Git name/email not configured" -} - -check_project() -{ - read -r projectname < projectname || : - - [ ! -f version ] || read -r version < version || : - version_="${version}" - [ ! -e ".git" ] || version="$(git describe --tags HEAD 2>&1)" || \ - version="git-$(git rev-parse HEAD 2>&1)" || version="${version_}" - - [ ! -f versiondate ] || read -r versiondate < versiondate || : - versiondate_="${versiondate}" - [ ! -e ".git" ] || versiondate="$(git show --no-patch --no-notes \ - --pretty='%ct' HEAD)" || versiondate="${versiondate_}" - - for p in projectname version versiondate; do - eval "[ -n \"\$$p\" ] || $err \"$p unset\"" - eval "x_ printf \"%s\\n\" \"\$$p\" > $p" - done - export LOCALVERSION="-${projectname}-${version%%-*}" -} - -setvars() -{ - _setvars="" - [ $# -lt 2 ] && $err "setvars: too few arguments" - val="${1}" && shift 1 - for var in $@; do - _setvars="${var}=\"${val}\"; ${_setvars}" - done - printf "%s\n" "${_setvars% }" -} - -err_() -{ - printf "ERROR %s: %s\n" "${0}" "${1}" 1>&2 - exit 1 -} diff --git a/include/option.sh b/include/option.sh index eb792775..a117958d 100755 --- a/include/option.sh +++ b/include/option.sh @@ -3,6 +3,10 @@ # SPDX-FileCopyrightText: 2022 Ferass El Hafidi # SPDX-FileCopyrightText: 2020-2024 Leah Rowe +export LC_COLLATE=C +export LC_ALL=C + +tmpdir_was_set="y" vendir="vendorfiles" appdir="${vendir}/app" cbdir="src/coreboot/default" @@ -13,22 +17,64 @@ grubcfgsdir="config/grub" layoutdir="/boot/grub/layouts" . "${grubcfgsdir}/modules.list" tmpgit="${PWD}/tmp/gitclone" +err="err_" +err_() +{ + printf "ERROR %s: %s\n" "${0}" "${1}" 1>&2 + exit 1 +} + +setvars() +{ + _setvars="" + [ $# -lt 2 ] && $err "setvars: too few arguments" + val="${1}" && shift 1 + for var in $@; do + _setvars="${var}=\"${val}\"; ${_setvars}" + done + printf "%s\n" "${_setvars% }" +} eval "$(setvars "" CONFIG_BOARD_DELL_E6400 CONFIG_HAVE_MRC CONFIG_HAVE_ME_BIN \ - CONFIG_ME_BIN_PATH CONFIG_KBC1126_FIRMWARE CONFIG_KBC1126_FW1 \ + CONFIG_ME_BIN_PATH CONFIG_KBC1126_FIRMWARE CONFIG_KBC1126_FW1 _nogit \ CONFIG_KBC1126_FW1_OFFSET CONFIG_KBC1126_FW2 CONFIG_KBC1126_FW2_OFFSET \ - CONFIG_VGA_BIOS_FILE CONFIG_VGA_BIOS_ID CONFIG_GBE_BIN_PATH \ + CONFIG_VGA_BIOS_FILE CONFIG_VGA_BIOS_ID CONFIG_GBE_BIN_PATH tmpdir \ CONFIG_INCLUDE_SMSC_SCH5545_EC_FW CONFIG_SMSC_SCH5545_EC_FW_FILE \ - CONFIG_IFD_BIN_PATH CONFIG_MRC_FILE _dest board boarddir \ - CONFIG_HAVE_REFCODE_BLOB CONFIG_REFCODE_BLOB_FILE)" + CONFIG_IFD_BIN_PATH CONFIG_MRC_FILE _dest board boarddir lbmk_release \ + CONFIG_HAVE_REFCODE_BLOB CONFIG_REFCODE_BLOB_FILE lbmk_status threads \ + version versiondate projectname)" + +# if "y": a coreboot target won't be built if target.cfg says release="n" +# (this is used to exclude certain build targets from releases) +set | grep LBMK_RELEASE 1>/dev/null 2>/dev/null || lbmk_release="n" || : +[ -z "$lbmk_release" ] && lbmk_release="$LBMK_RELEASE" +[ "$lbmk_release" = "n" ] || [ "$lbmk_release" = "y" ] || lbmk_release="n" +export LBMK_RELEASE="$lbmk_release" + +# if set to n via export, status checks will be skipped during +# all builds, and all targets will be built regardless of status. +# this replicates the old behaviour of lbmk, prior to the checks. +set | grep LBMK_STATUS 1>/dev/null 2>/dev/null && lbmk_status="$LBMK_STATUS" +[ "$lbmk_status" = "y" ] || [ "$lbmk_status" = "n" ] || lbmk_status="y" +export LBMK_STATUS="$lbmk_status" + +set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n" +if [ "${tmpdir_was_set}" = "y" ]; then + [ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n" +fi +if [ "${tmpdir_was_set}" = "n" ]; then + export TMPDIR="/tmp" + tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)" + export TMPDIR="${tmpdir}" +else + export TMPDIR="${TMPDIR}" + tmpdir="${TMPDIR}" +fi -threads= set | grep LBMK_THREADS 1>/dev/null 2>/dev/null && threads="$LBMK_THREADS" [ -z "$threads" ] && threads=1 - expr "X$threads" : "X-\{0,1\}[0123456789][0123456789]*$" \ 1>/dev/null 2>/dev/null || threads=1 # user specified a non-integer - export LBMK_THREADS="$threads" items() @@ -92,3 +138,44 @@ remkdir() rm -Rf "${1}" || $err "remkdir: !rm -Rf \"${1}\"" mkdir -p "${1}" || $err "remkdir: !mkdir -p \"${1}\"" } + +x_() { + [ $# -lt 1 ] || ${@} || $err "Unhandled non-zero exit: $@"; return 0 +} + +check_git() +{ + which git 1>/dev/null 2>/dev/null || \ + git_err "git not installed. please install git-scm." + git config --global user.name 1>/dev/null 2>/dev/null || \ + git_err "git config --global user.name \"John Doe\"" + git config --global user.email 1>/dev/null 2>/dev/null || \ + git_err "git config --global user.email \"john.doe@example.com\"" +} + +git_err() +{ + printf "You need to set git name/email, like so:\n%s\n\n" "$1" 1>&2 + $err "Git name/email not configured" +} + +check_project() +{ + read -r projectname < projectname || : + + [ ! -f version ] || read -r version < version || : + version_="${version}" + [ ! -e ".git" ] || version="$(git describe --tags HEAD 2>&1)" || \ + version="git-$(git rev-parse HEAD 2>&1)" || version="${version_}" + + [ ! -f versiondate ] || read -r versiondate < versiondate || : + versiondate_="${versiondate}" + [ ! -e ".git" ] || versiondate="$(git show --no-patch --no-notes \ + --pretty='%ct' HEAD)" || versiondate="${versiondate_}" + + for p in projectname version versiondate; do + eval "[ -n \"\$$p\" ] || $err \"$p unset\"" + eval "x_ printf \"%s\\n\" \"\$$p\" > $p" + done + export LOCALVERSION="-${projectname}-${version%%-*}" +} diff --git a/script/build/roms b/script/build/roms index 032c0a57..6049848f 100755 --- a/script/build/roms +++ b/script/build/roms @@ -8,7 +8,6 @@ set -u -e -. "include/err.sh" . "include/option.sh" seavgabiosrom="elf/seabios/default/libgfxinit/vgabios.bin" diff --git a/script/build/serprog b/script/build/serprog index ea2c02bf..b830f26d 100755 --- a/script/build/serprog +++ b/script/build/serprog @@ -5,7 +5,7 @@ set -u -e -. "include/err.sh" +. "include/option.sh" eval "$(setvars "" pico_sdk_dir pico_src_dir stm32_src_dir boards_dir)" diff --git a/script/update/release b/script/update/release index 405fdc28..aebe6fbf 100755 --- a/script/update/release +++ b/script/update/release @@ -4,7 +4,6 @@ set -u -e -. "include/err.sh" . "include/option.sh" eval "$(setvars "" vdir relname src_dirname srcdir _xm target romdir mode)" diff --git a/script/update/trees b/script/update/trees index af80d99a..615fbbf2 100755 --- a/script/update/trees +++ b/script/update/trees @@ -6,7 +6,6 @@ set -u -e -. "include/err.sh" . "include/option.sh" . "include/git.sh" diff --git a/script/vendor/download b/script/vendor/download index b40810cc..6f1fdbbf 100755 --- a/script/vendor/download +++ b/script/vendor/download @@ -4,7 +4,6 @@ # SPDX-FileCopyrightText: 2022 Ferass El Hafidi # SPDX-FileCopyrightText: 2023-2024 Leah Rowe -. "include/err.sh" . "include/option.sh" . "include/mrc.sh" diff --git a/script/vendor/inject b/script/vendor/inject index dc12d7b5..9b6b52ea 100755 --- a/script/vendor/inject +++ b/script/vendor/inject @@ -4,7 +4,6 @@ # SPDX-FileCopyrightText: 2022 Ferass El Hafidi # SPDX-FileCopyrightText: 2023-2024 Leah Rowe -. "include/err.sh" . "include/option.sh" nvmutil="util/nvmutil/nvm" From 297af7e6d3dbf17791bffb1ede55e990b313fa0b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 9 May 2024 13:03:35 +0100 Subject: [PATCH 0096/1319] build/roms: remove unnecessary command there is no need to return 0 at the end of a function. sh does that anyway Signed-off-by: Leah Rowe --- script/build/roms | 1 - 1 file changed, 1 deletion(-) diff --git a/script/build/roms b/script/build/roms index 6049848f..3e8b77be 100755 --- a/script/build/roms +++ b/script/build/roms @@ -172,7 +172,6 @@ print_target_name() break fi done - return 0 } skip_board() From e3cb3a4072ffc2d3db9c9363d5b2ebd58adbdfb7 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 9 May 2024 13:52:49 +0100 Subject: [PATCH 0097/1319] merge script/build/serprog with script/build/roms previous command: ./build serprog now it is: ./build roms serprog after that, it's the same arguments e.g. ./build roms serprog stm32 ./build roms serprog rp2040 further cleanup to commence Signed-off-by: Leah Rowe --- script/build/roms | 90 ++++++++++++++++++++++++++++++++++++++----- script/build/serprog | 77 ------------------------------------ script/update/release | 4 +- 3 files changed, 82 insertions(+), 89 deletions(-) delete mode 100755 script/build/serprog diff --git a/script/build/roms b/script/build/roms index 3e8b77be..4be00f85 100755 --- a/script/build/roms +++ b/script/build/roms @@ -10,10 +10,14 @@ set -u -e . "include/option.sh" +serprog_usage="usage: ./build roms serprog [board]" seavgabiosrom="elf/seabios/default/libgfxinit/vgabios.bin" grub_background="background1280x800.png" grubelf="elf/grub/grub.elf" cfgsdir="config/coreboot" +pico_src_dir="src/pico-serprog" +pico_sdk_dir="src/pico-sdk" +stm32_src_dir="src/stm32-vserprog" # Disable all payloads by default. # target.cfg files have to specifically enable [a] payload(s) @@ -21,16 +25,15 @@ pv="payload_grub payload_grub_withseabios payload_seabios payload_memtest t" pv="${pv} payload_seabios_withgrub payload_seabios_grubonly payload_uboot memtest_bin" v="romdir cbrom initmode displaymode cbcfg targetdir tree keymaps release" v="${v} grub_timeout ubdir board grub_scan_disk uboot_config status" -eval "$(setvars "n" ${pv})" +eval "$(setvars "n" ${pv} serprog)" eval "$(setvars "" ${v} boards _displaymode _payload _keyboard all targets \ - skipped listboards list_type)" + skipped listboards list_type serprog_boards_dir)" main() { check_project while [ $# -gt 0 ]; do - if [ "$listboards" = "y" ]; then list_type="$list_type $1" list_type="${list_type# }" @@ -46,6 +49,9 @@ main() $err "Cannot generate list of boards for list" listboards="y" shift 1; continue ;; + serprog) + serprog="y" + shift 1; break ;; -d) _displaymode="${2}" ;; -p) _payload="${2}" ;; -k) _keyboard="${2}" ;; @@ -57,12 +63,16 @@ main() shift 2 done - [ "${all}" != "y" ] || boards=$(items config/coreboot) || \ - $err "Cannot generate list of boards for building" - - for x in ${boards}; do - handle_target "$x" - done + if [ "$serprog" = "y" ]; then + handle_serprog $@ + return 0 + else + [ "${all}" != "y" ] || boards=$(items config/coreboot) || \ + $err "Cannot generate list of boards for building" + for x in ${boards}; do + handle_coreboot_target "$x" + done + fi [ "$listboards" = "y" ] && return 0 @@ -80,7 +90,67 @@ main() printf "DO NOT flash images from elf/ - please use bin/ instead.\n" } -handle_target() +handle_serprog() +{ + [ -z "${1+x}" ] && $err "${serprog_usage}" + [ "$1" != "rp2040" ] && [ "$1" != "stm32" ] && $err "$serprog_usage" + if [ "${1}" = "rp2040" ]; then + serprog_boards_dir=${pico_sdk_dir}/src/boards/include/boards + [ -d "$pico_src_dir" ] || x_ ./update trees -f "pico-serprog" + elif [ "${1}" = "stm32" ]; then + serprog_boards_dir=${stm32_src_dir}/boards + [ -d "$stm32_src_dir" ] || x_ ./update trees -f "stm32-vserprog" + fi + x_ mkdir -p "bin/serprog_${1}" + + if [ $# -gt 1 ] && [ "${2}" = "list" ]; then + print_serprog_boards ${serprog_boards_dir} + elif [ $# -gt 1 ]; then + build_${1}_rom "${2}" + else + printf "Building all serprog targets\n" + list_serprog_boards "${serprog_boards_dir}" | \ + while read -r board; do + build_${1}_rom "${board}" + done + fi +} + +build_rp2040_rom() +{ + board=${1} + printf "Building pico-serprog for %s\n" "${board}" + x_ cmake -DPICO_BOARD="$board" -DPICO_SDK_PATH="$pico_sdk_dir" \ + -B "${pico_src_dir}/build" "${pico_src_dir}" + x_ cmake --build "${pico_src_dir}/build" + x_ mv ${pico_src_dir}/build/pico_serprog.uf2 \ + bin/serprog_rp2040/serprog_${board}.uf2 + printf "output to bin/serprog_rp2040/serprog_%s.uf2\n" "$board" +} + +build_stm32_rom() +{ + board=${1} + printf "Building stm32-vserprog for %s\n" "${board}" + x_ make -C $stm32_src_dir libopencm3-just-make BOARD=$board + x_ make -C ${stm32_src_dir} BOARD=${board} + x_ mv ${stm32_src_dir}/stm32-vserprog.hex \ + bin/serprog_stm32/serprog_${board}.hex + printf "output to bin/serprog_stm32/serprog_%s.hex\n" "$board" +} + +print_serprog_boards() +{ + printf "Available boards:\n" + list_serprog_boards "${1}" +} + +list_serprog_boards() +{ + basename -a -s .h "${1}/"*.h || $err "list_boards $1: can't list boards" +} + +handle_coreboot_target() { eval "$(setvars "n" ${pv}) $(setvars "" ${v})" grub_background="background1280x800.png" diff --git a/script/build/serprog b/script/build/serprog deleted file mode 100755 index b830f26d..00000000 --- a/script/build/serprog +++ /dev/null @@ -1,77 +0,0 @@ -#!/usr/bin/env sh -# SPDX-License-Identifier: GPL-3.0-or-later -# SPDX-FileCopyrightText: 2023 Riku Viitanen -# SPDX-FileCopyrightText: 2023 Leah Rowe - -set -u -e - -. "include/option.sh" - -eval "$(setvars "" pico_sdk_dir pico_src_dir stm32_src_dir boards_dir)" - -pico_src_dir=src/pico-serprog -pico_sdk_dir=src/pico-sdk -stm32_src_dir=src/stm32-vserprog - -usage="usage: ./build firmware serprog [board]" - -main() -{ - [ -z "${1+x}" ] && $err "${usage}" - [ "$1" != "rp2040" ] && [ "$1" != "stm32" ] && $err "$usage" - if [ "${1}" = "rp2040" ]; then - boards_dir=${pico_sdk_dir}/src/boards/include/boards - [ -d "$pico_src_dir" ] || x_ ./update trees -f "pico-serprog" - elif [ "${1}" = "stm32" ]; then - boards_dir=${stm32_src_dir}/boards - [ -d "$stm32_src_dir" ] || x_ ./update trees -f "stm32-vserprog" - fi - x_ mkdir -p "bin/serprog_${1}" - - if [ $# -gt 1 ] && [ "${2}" = "list" ]; then - print_boards ${boards_dir} - elif [ $# -gt 1 ]; then - build_${1}_rom "${2}" - else - printf "Building all serprog targets\n" - list_boards "${boards_dir}" | while read -r board; do - build_${1}_rom "${board}" - done - fi -} - -build_rp2040_rom() -{ - board=${1} - printf "Building pico-serprog for %s\n" "${board}" - x_ cmake -DPICO_BOARD="$board" -DPICO_SDK_PATH="$pico_sdk_dir" \ - -B "${pico_src_dir}/build" "${pico_src_dir}" - x_ cmake --build "${pico_src_dir}/build" - x_ mv ${pico_src_dir}/build/pico_serprog.uf2 \ - bin/serprog_rp2040/serprog_${board}.uf2 - printf "output to bin/serprog_rp2040/serprog_%s.uf2\n" "$board" -} - -build_stm32_rom() -{ - board=${1} - printf "Building stm32-vserprog for %s\n" "${board}" - x_ make -C $stm32_src_dir libopencm3-just-make BOARD=$board - x_ make -C ${stm32_src_dir} BOARD=${board} - x_ mv ${stm32_src_dir}/stm32-vserprog.hex \ - bin/serprog_stm32/serprog_${board}.hex - printf "output to bin/serprog_stm32/serprog_%s.hex\n" "$board" -} - -print_boards() -{ - printf "Available boards:\n" - list_boards "${1}" -} - -list_boards() -{ - basename -a -s .h "${1}/"*.h || $err "list_boards $1: can't list boards" -} - -main $@ diff --git a/script/update/release b/script/update/release index aebe6fbf..c78b5fce 100755 --- a/script/update/release +++ b/script/update/release @@ -106,8 +106,8 @@ fetch_trees() mkrom_images() { ./build roms all || $err "${_xm}: roms-all" - ./build serprog rp2040 || $err "${_xm}: rp2040" - ./build serprog stm32 || $err "${_xm}: stm32" + ./build roms serprog rp2040 || $err "${_xm}: rp2040" + ./build roms serprog stm32 || $err "${_xm}: stm32" for rombuild in bin/*; do [ -d "${rombuild}" ] || continue From 38aaaecf6b8aa9b58f56dff930139e070b1649dc Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 9 May 2024 13:56:35 +0100 Subject: [PATCH 0098/1319] build/roms: print serprog help Signed-off-by: Leah Rowe --- script/build/roms | 3 +++ 1 file changed, 3 insertions(+) diff --git a/script/build/roms b/script/build/roms index 4be00f85..0525091b 100755 --- a/script/build/roms +++ b/script/build/roms @@ -558,6 +558,9 @@ usage() ./build roms list + Can also build serprog images: + ${serprog_usage} + to see targets of only a given status (stable, unstable, broken, untested and unknown), try e.g. From fb8d0c86c44ba98cc770222edcb18f0a492aa37a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 9 May 2024 14:31:43 +0100 Subject: [PATCH 0099/1319] build: exit if not running from lbmk directory there's no portable(posix) way to check when running from a symlink to lbmk in the current work directory for example: ln -s lbmk/build lbmktest ./lbmktest roms list this would pass the new test, and first try to include option.sh. in practise, the user probably doesn't happen to have include/option.sh in their current path i can use readlink here, but again not portable the current check will suffice. it also works when the symlink is called from $PATH e.g. /usr/bin/lbmktest exists and you do: lbmktest roms list Signed-off-by: Leah Rowe --- build | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/build b/build index 4c6a2916..59bd78d8 100755 --- a/build +++ b/build @@ -7,6 +7,11 @@ set -u -e +if [ "./${0##*/}" != "${0}" ]; then + printf "You must run this in the lbmk work directory.\n" 1>&2 + exit 1 +fi + . "include/option.sh" eval "$(setvars "" option aur_notice)" From 052414c0ca9c965abc2181491344aa27bc4501f4 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 9 May 2024 14:48:14 +0100 Subject: [PATCH 0100/1319] build: further prevent non-lbmk-work-directory this is a follow-up to the previous commit again, there's no posix way to check the path to the file at argument 0, because readlink (utility) isn't defined in posix (the C function is defined, but not the utility included on many unices) check whether "build" (file) exists, and whether it is a symlink; if the latter, then we are definitely not in the lbmk work directory! Signed-off-by: Leah Rowe --- build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build b/build index 59bd78d8..1c78f280 100755 --- a/build +++ b/build @@ -7,7 +7,7 @@ set -u -e -if [ "./${0##*/}" != "${0}" ]; then +if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then printf "You must run this in the lbmk work directory.\n" 1>&2 exit 1 fi From e1ea5dd0fdfa017f05a5a828ae6091145b349578 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 10 May 2024 05:48:57 +0100 Subject: [PATCH 0101/1319] bump seabios to e5f2e4c69643bc3cd385306a9e5d29e11578148c changes upstream, relative to the previous revision: * e5f2e4c6 pciinit: don't misalign large BARs * 731c88d5 stdvgaio: Only read/write one color palette entry at a time * c5a361c0 stdvga: Add stdvga_set_vertical_size() helper function * 22c91412 stdvga: Rename stdvga_get_vde() to stdvga_get_vertical_size() * 549463db stdvga: Rename stdvga_set_scan_lines() to stdvga_set_character_height() * c67914ac stdvga: Rename stdvga_set_text_block_specifier() to stdvga_set_font_location() * aa94925d stdvga: Rework stdvga palette index paging interface functions * 8de51a5a stdvga: Rename stdvga_toggle_intensity() to stdvga_set_palette_blinking() * 96c7781f stdvga: Add comments to interface functions in stdvga.c * 2996819f stdvga: Rename CGA palette functions * 91368088 stdvgamodes: Improve naming of dac palette tables * 70f43981 stdvgamodes: No need to store pelmask in vga_modes[] * 1588fd14 vgasrc: Rename vgahw_get_linesize() to vgahw_minimum_linelength() * d73e18bb vgasrc: Use curmode_g instead of vmode_g when mode is the current video mode * 192e23b7 vbe: implement function 09h (get/set palette data) * 3722c21d vgasrc: round up save/restore size * 5d87ff25 vbe: Add VBE 2.0+ OemData field to struct vbe_info * 163fd9f0 fix smbios blob length overflow * 82faf1d5 Add LBA 64bit support for reads beyond 2TB. * 3f082f38 Add AHCI Power ON + ICC_ACTIVE into port setup code * 3ae88886 esp-scsi: terminate DMA transfer when ESP data transfer completes * a6ed6b70 limit address space used for pci devices. Signed-off-by: Leah Rowe --- config/seabios/default/target.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/seabios/default/target.cfg b/config/seabios/default/target.cfg index 8ab09802..bc7cc9fc 100644 --- a/config/seabios/default/target.cfg +++ b/config/seabios/default/target.cfg @@ -1,2 +1,2 @@ tree="default" -rev="1e1da7a963007d03a4e0e9a9e0ff17990bb1608d" +rev="e5f2e4c69643bc3cd385306a9e5d29e11578148c" From 5f63b594fa3b0f111518f1e292bfb7163bec8be9 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 11 May 2024 03:52:52 +0100 Subject: [PATCH 0102/1319] merge script/update/release into build the main script isn't that big, and since the main purpose of lbmk is geared toward the releases, it makes sense to reduce the number of scripts by merging into the main one the way this works, "./update release" still works afterward so, the way lbmk is used shall remain unchanged Signed-off-by: Leah Rowe --- build | 231 ++++++++++++++++++++++++++++++++++++++++- script/update/release | 236 ------------------------------------------ 2 files changed, 229 insertions(+), 238 deletions(-) delete mode 100755 script/update/release diff --git a/build b/build index 1c78f280..884d69de 100755 --- a/build +++ b/build @@ -1,6 +1,6 @@ #!/usr/bin/env sh # SPDX-License-Identifier: GPL-3.0-or-later -# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe +# SPDX-FileCopyrightText: 2014,2015,2020-2024 Leah Rowe # SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott # SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni # SPDX-FileCopyrightText: 2022, Caleb La Grange @@ -14,7 +14,8 @@ fi . "include/option.sh" -eval "$(setvars "" option aur_notice)" +eval "$(setvars "" option aur_notice vdir relname src_dirname srcdir _xm \ + target romdir mode)" err="fail" linkpath="${0}" @@ -44,6 +45,7 @@ initcmd() help) usage ${0} ;; list) items "${buildpath}" ;; version) mkversion ;; + release) shift 1; mkrelease $@ ;; *) option="${1}" return 0 ;; @@ -111,6 +113,231 @@ usage() EOF } +mkrelease() +{ + export LBMK_RELEASE="y" + export LBMK_STATUS="n" + + vdir="release" + while getopts d:m: option; do + [ -z "${OPTARG}" ] && $err "Empty argument not allowed" + case "${option}" in + d) vdir="${OPTARG}" ;; + m) mode="${OPTARG}" ;; + *) $err "Invalid option" ;; + esac + done + + check_project + + vdir="${vdir}/${version}" + relname="${projectname}-${version}" + [ "${mode}" = "u-boot" ] && relname="u-boot-for-${relname}" + src_dirname="${relname}_src" + srcdir="${vdir}/${src_dirname}" + + [ -e "${vdir}" ] && $err "already exists: \"${vdir}\"" + + mkvdir + build_release + + printf "DONE! Check release files under %s\n" "${vdir}" +} + +mkvdir() +{ + mkdir -p "${vdir}" || $err "mkvdir: !mkdir -p \"${vdir}\"" + git clone . "${srcdir}" || $err "mkdir: !gitclone \"${srcdir}\"" + insert_version_files "$srcdir" || $err "mkvdir $srcdir: versionfile" +} + +build_release() +{ + _xm="build_release ${vdir}" + ( + cd "${srcdir}" || $err "${_xm}: !cd \"${srcdir}\"" + fetch_trees + [ "${mode}" = "u-boot" ] || x_ mv src/docs docs + ) || $err "can't create release files" + + git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \ + --abbrev-commit > "${srcdir}/CHANGELOG" || \ + $err "build_release $srcdir: couldn't generate changelog" + + ( + if [ "${mode}" = "u-boot" ]; then + cd "${srcdir}/src/" || $err "${_xm}: mktarball \"${srcdir}\"" + mktarball u-boot "../../${srcdir##*/}.tar.xz" || \ + $err "$_xm: mksrc" + # make a src archive containing only u-boot + else + cd "${srcdir%/*}" || $err "${_xm}: mktarball \"${srcdir}\"" + mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || \ + $err "$_xm: mksrc" + fi + ) || $err "can't create src tarball" + [ "${mode}" = "src" ] && return 0 + [ "${mode}" = "u-boot" ] && return 0 + + ( + cd "${srcdir}" || $err "${_xm}: 2 !cd \"${srcdir}\"" + mkrom_images + ) || $err "can't build rom images" + + rm -Rf "${srcdir}" || $err "!rm -Rf ${srcdir}" +} + +fetch_trees() +{ + for x in config/git/*; do + [ "${mode}" = "u-boot" ] && break + [ ! -f "${x}" ] || ./update trees -f "${x#config/git/}" || \ + $err "${_xm}: fetch ${x#config/git/}" + done + [ "${mode}" = "u-boot" ] && x_ ./update trees -f u-boot + + for x in config/*/build.list; do + [ -f "${x}" ] || continue + xp="${x#*/}"; xp="${xp%/*}" + [ -L "${xp}" ] || rm -Rf "src/${xp}/${xp}" || \ + $err "!rm -Rf \"src/${xp}/${xp}\"" + done + + find . -name ".git" -exec rm -Rf {} + || $err "$_xm: rm .git" + find . -name ".gitmodules" -exec rm -Rf {} + || $err "$_xm: rm .gitmod" + x_ rm -Rf tmp .git +} + +mkrom_images() +{ + ./build roms all || $err "${_xm}: roms-all" + ./build roms serprog rp2040 || $err "${_xm}: rp2040" + ./build roms serprog stm32 || $err "${_xm}: stm32" + + for rombuild in bin/*; do + [ -d "${rombuild}" ] || continue + handle_rom_archive "${rombuild}" + done + + mv "release/${version}/roms/" ../roms || $err "${_xm}: copy roms/" +} + +handle_rom_archive() +{ + builddir="${1}" + romdir="tmp/romdir" + rm -Rf "${romdir}" || $err "!rm romdir, handle_rom_archive" + target="${builddir##*/}" + + if [ ! -f "config/coreboot/${target}/target.cfg" ]; then + # No config, just make a tarball + tarball="release/${version}/roms/${relname}_${target}.tar.xz" + insert_copying_files "${builddir}" || \ + $err "!insert copy, handle, ${builddir}" + mktarball "${builddir}" "${tarball}" + return 0 + fi + + romdir="${romdir}/bin/${target}" + mkdir -p "${romdir}" || $err "!mkdir -p romdir, handle_rom_archive" + cp "$builddir/"* "$romdir" || $err "!cp romdir, handle_rom_archive" + + nukerom + + printf "Generating release/%s/roms/%s-%s_%s.tar.xz\n" \ + "${version}" "${projectname}" "${version}" "${target##*/}" + insert_version_files "${romdir}" || \ + $err "mkrom_tarball ${romdir}: versionfile" + + insert_copying_files "$romdir" || $err "!insert copy, handle 2, $romdir" + mkrom_tarball +} + +nukerom() +{ + . "config/coreboot/${target}/target.cfg" + + # Hash the images before removing vendor files + # which "./vendor inject" uses for verification + rm -f "${romdir}/vendorhashes" || $err "!rm ${romdir}/vendorhashes" + touch "${romdir}/vendorhashes" || $err "!touch ${romdir}/vendorhashes" + ( + cd "${romdir}" || $err "!cd romdir ${romdir}, nukerom" + sha512sum ./*.rom >> vendorhashes || \ + $err "!create vendorhashes, nukerom" + ) || $err "can't create vendor hashes" + + for romfile in "${romdir}"/*.rom; do + [ -f "${romfile}" ] || continue + ./vendor inject -r "$romfile" -b "$target" -n nuke || \ + $err "!vendor inject (nuke) ${romfile}, nukerom" + done +} + +insert_copying_files() +{ + remkdir "${1}/licenses" + l="${1}/licenses" + # copy licenses to rom image archive, for completion + cp "src/grub/COPYING" "${l}/COPYING.grub" || return 1 + cp "src/coreboot/default/COPYING" "${l}/COPYING.coreboot" || return 1 + cp -R "src/coreboot/default/LICENSES" "${l}/LICENSES.coreboot" || \ + return 1 + cp "src/seabios/default/COPYING" "${l}/COPYING.coreboot" || return 1 + cp "src/seabios/default/COPYING.LESSER" "$l/COPYING.LESSER.seabios" \ + || return 1 + cp -R "src/u-boot/default/Licenses" "${l}/COPYING.u-boot" || return 1 + printf "Multiple licenses. Check corresponding %s source archive\n" \ + "${projectname}" > "${1}/COPYING" || return 1 + rm -f src/u-boot/*/test/lib/strlcat.c || return 1 +} + +mkrom_tarball() +{ + archivename="${relname}_${target##*/}" + f="release/${version}/roms/${archivename}" + mkdir -p "${f%/*}" || $err "mkrom_tarball: !mkdir -p ${f%/*}" + ( + cd "${romdir%"/bin/$target"}" || $err "!cd ${romdir%"/bin/$target"}" + mktarball "bin/${target}" "${archivename}.tar.xz" + ) || $err "can't create rom tarball" + mv "${romdir%"/bin/${target}"}/${archivename}.tar.xz"* "${f%/*}" || \ + $err "mktar ${f%/*}/${romdir%"/bin/$target"}/$archivename.tar.xz" + + printf "Created ROM archive: %s" "${f%/*}/${archivename}.tar.xz" +} + +insert_version_files() +{ + printf "%s\n" "${version}" > "${1}/version" || return 1 + printf "%s\n" "${versiondate}" > "${1}/versiondate" || return 1 + printf "%s\n" "${projectname}" > "${1}/projectname" || return 1 +} + +mktarball() +{ + # preserve timestamps for reproducible tarballs + tar_implementation=$(tar --version | head -n1) || : + + [ "${2%/*}" = "${2}" ] || \ + mkdir -p "${2%/*}" || $err "mk, !mkdir -p \"${2%/*}\"" + printf "\nCreating archive: %s\n\n" "$2" + if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then + tar --sort=name --owner=root:0 --group=root:0 \ + --mtime="UTC 2024-05-04" -c "$1" | xz -T$threads -9e \ + > "$2" || $err "mktarball 1, ${1}" + else + # TODO: reproducible tarballs on non-GNU systems + tar -c "$1" | xz -T$threads -9e > "$2" || \ + $err "mktarball 2, $1" + fi + ( + [ "${2%/*}" != "${2}" ] && x_ cd "${2%/*}" + sha512sum "${2##*/}" > "${2##*/}.sha512" || \ + $err "!sha512sum \"${2##*/}\" > \"${2##*/}.sha512\"" + ) || $err "failed to create tarball checksum" +} + mkversion() { printf "revision: %s %s\n" "$projectname" "$version" diff --git a/script/update/release b/script/update/release deleted file mode 100755 index c78b5fce..00000000 --- a/script/update/release +++ /dev/null @@ -1,236 +0,0 @@ -#!/usr/bin/env sh -# SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: 2020-2024 Leah Rowe - -set -u -e - -. "include/option.sh" - -eval "$(setvars "" vdir relname src_dirname srcdir _xm target romdir mode)" - -export LBMK_RELEASE="y" -export LBMK_STATUS="n" - -main() -{ - vdir="release" - while getopts d:m: option; do - [ -z "${OPTARG}" ] && $err "Empty argument not allowed" - case "${option}" in - d) vdir="${OPTARG}" ;; - m) mode="${OPTARG}" ;; - *) $err "Invalid option" ;; - esac - done - - check_project - - vdir="${vdir}/${version}" - relname="${projectname}-${version}" - [ "${mode}" = "u-boot" ] && relname="u-boot-for-${relname}" - src_dirname="${relname}_src" - srcdir="${vdir}/${src_dirname}" - - [ -e "${vdir}" ] && $err "already exists: \"${vdir}\"" - - mkvdir - build_release - - printf "DONE! Check release files under %s\n" "${vdir}" -} - -mkvdir() -{ - mkdir -p "${vdir}" || $err "mkvdir: !mkdir -p \"${vdir}\"" - git clone . "${srcdir}" || $err "mkdir: !gitclone \"${srcdir}\"" - insert_version_files "$srcdir" || $err "mkvdir $srcdir: versionfile" -} - -build_release() -{ - _xm="build_release ${vdir}" - ( - cd "${srcdir}" || $err "${_xm}: !cd \"${srcdir}\"" - fetch_trees - [ "${mode}" = "u-boot" ] || x_ mv src/docs docs - ) || $err "can't create release files" - - git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \ - --abbrev-commit > "${srcdir}/CHANGELOG" || \ - $err "build_release $srcdir: couldn't generate changelog" - - ( - if [ "${mode}" = "u-boot" ]; then - cd "${srcdir}/src/" || $err "${_xm}: mktarball \"${srcdir}\"" - mktarball u-boot "../../${srcdir##*/}.tar.xz" || \ - $err "$_xm: mksrc" - # make a src archive containing only u-boot - else - cd "${srcdir%/*}" || $err "${_xm}: mktarball \"${srcdir}\"" - mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || \ - $err "$_xm: mksrc" - fi - ) || $err "can't create src tarball" - [ "${mode}" = "src" ] && return 0 - [ "${mode}" = "u-boot" ] && return 0 - - ( - cd "${srcdir}" || $err "${_xm}: 2 !cd \"${srcdir}\"" - mkrom_images - ) || $err "can't build rom images" - - rm -Rf "${srcdir}" || $err "!rm -Rf ${srcdir}" -} - -fetch_trees() -{ - for x in config/git/*; do - [ "${mode}" = "u-boot" ] && break - [ ! -f "${x}" ] || ./update trees -f "${x#config/git/}" || \ - $err "${_xm}: fetch ${x#config/git/}" - done - [ "${mode}" = "u-boot" ] && x_ ./update trees -f u-boot - - for x in config/*/build.list; do - [ -f "${x}" ] || continue - xp="${x#*/}"; xp="${xp%/*}" - [ -L "${xp}" ] || rm -Rf "src/${xp}/${xp}" || \ - $err "!rm -Rf \"src/${xp}/${xp}\"" - done - - find . -name ".git" -exec rm -Rf {} + || $err "$_xm: rm .git" - find . -name ".gitmodules" -exec rm -Rf {} + || $err "$_xm: rm .gitmod" - x_ rm -Rf tmp .git -} - -mkrom_images() -{ - ./build roms all || $err "${_xm}: roms-all" - ./build roms serprog rp2040 || $err "${_xm}: rp2040" - ./build roms serprog stm32 || $err "${_xm}: stm32" - - for rombuild in bin/*; do - [ -d "${rombuild}" ] || continue - handle_rom_archive "${rombuild}" - done - - mv "release/${version}/roms/" ../roms || $err "${_xm}: copy roms/" -} - -handle_rom_archive() -{ - builddir="${1}" - romdir="tmp/romdir" - rm -Rf "${romdir}" || $err "!rm romdir, handle_rom_archive" - target="${builddir##*/}" - - if [ ! -f "config/coreboot/${target}/target.cfg" ]; then - # No config, just make a tarball - tarball="release/${version}/roms/${relname}_${target}.tar.xz" - insert_copying_files "${builddir}" || \ - $err "!insert copy, handle, ${builddir}" - mktarball "${builddir}" "${tarball}" - return 0 - fi - - romdir="${romdir}/bin/${target}" - mkdir -p "${romdir}" || $err "!mkdir -p romdir, handle_rom_archive" - cp "$builddir/"* "$romdir" || $err "!cp romdir, handle_rom_archive" - - nukerom - - printf "Generating release/%s/roms/%s-%s_%s.tar.xz\n" \ - "${version}" "${projectname}" "${version}" "${target##*/}" - insert_version_files "${romdir}" || \ - $err "mkrom_tarball ${romdir}: versionfile" - - insert_copying_files "$romdir" || $err "!insert copy, handle 2, $romdir" - mkrom_tarball -} - -nukerom() -{ - . "config/coreboot/${target}/target.cfg" - - # Hash the images before removing vendor files - # which "./vendor inject" uses for verification - rm -f "${romdir}/vendorhashes" || $err "!rm ${romdir}/vendorhashes" - touch "${romdir}/vendorhashes" || $err "!touch ${romdir}/vendorhashes" - ( - cd "${romdir}" || $err "!cd romdir ${romdir}, nukerom" - sha512sum ./*.rom >> vendorhashes || \ - $err "!create vendorhashes, nukerom" - ) || $err "can't create vendor hashes" - - for romfile in "${romdir}"/*.rom; do - [ -f "${romfile}" ] || continue - ./vendor inject -r "$romfile" -b "$target" -n nuke || \ - $err "!vendor inject (nuke) ${romfile}, nukerom" - done -} - -insert_copying_files() -{ - remkdir "${1}/licenses" - l="${1}/licenses" - # copy licenses to rom image archive, for completion - cp "src/grub/COPYING" "${l}/COPYING.grub" || return 1 - cp "src/coreboot/default/COPYING" "${l}/COPYING.coreboot" || return 1 - cp -R "src/coreboot/default/LICENSES" "${l}/LICENSES.coreboot" || \ - return 1 - cp "src/seabios/default/COPYING" "${l}/COPYING.coreboot" || return 1 - cp "src/seabios/default/COPYING.LESSER" "$l/COPYING.LESSER.seabios" \ - || return 1 - cp -R "src/u-boot/default/Licenses" "${l}/COPYING.u-boot" || return 1 - printf "Multiple licenses. Check corresponding %s source archive\n" \ - "${projectname}" > "${1}/COPYING" || return 1 - rm -f src/u-boot/*/test/lib/strlcat.c || return 1 -} - -mkrom_tarball() -{ - archivename="${relname}_${target##*/}" - f="release/${version}/roms/${archivename}" - mkdir -p "${f%/*}" || $err "mkrom_tarball: !mkdir -p ${f%/*}" - ( - cd "${romdir%"/bin/$target"}" || $err "!cd ${romdir%"/bin/$target"}" - mktarball "bin/${target}" "${archivename}.tar.xz" - ) || $err "can't create rom tarball" - mv "${romdir%"/bin/${target}"}/${archivename}.tar.xz"* "${f%/*}" || \ - $err "mktar ${f%/*}/${romdir%"/bin/$target"}/$archivename.tar.xz" - - printf "Created ROM archive: %s" "${f%/*}/${archivename}.tar.xz" -} - -insert_version_files() -{ - printf "%s\n" "${version}" > "${1}/version" || return 1 - printf "%s\n" "${versiondate}" > "${1}/versiondate" || return 1 - printf "%s\n" "${projectname}" > "${1}/projectname" || return 1 -} - -mktarball() -{ - # preserve timestamps for reproducible tarballs - tar_implementation=$(tar --version | head -n1) || : - - [ "${2%/*}" = "${2}" ] || \ - mkdir -p "${2%/*}" || $err "mk, !mkdir -p \"${2%/*}\"" - printf "\nCreating archive: %s\n\n" "$2" - if [ "${tar_implementation% *}" = "tar (GNU tar)" ]; then - tar --sort=name --owner=root:0 --group=root:0 \ - --mtime="UTC 2024-05-04" -c "$1" | xz -T$threads -9e \ - > "$2" || $err "mktarball 1, ${1}" - else - # TODO: reproducible tarballs on non-GNU systems - tar -c "$1" | xz -T$threads -9e > "$2" || \ - $err "mktarball 2, $1" - fi - ( - [ "${2%/*}" != "${2}" ] && x_ cd "${2%/*}" - sha512sum "${2##*/}" > "${2##*/}.sha512" || \ - $err "!sha512sum \"${2##*/}\" > \"${2##*/}.sha512\"" - ) || $err "failed to create tarball checksum" -} - -main $@ From c8fb24bb7bd0918c4c684c13a3b2946ba67439eb Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 11 May 2024 05:17:41 +0100 Subject: [PATCH 0103/1319] build: print usage for special commands Signed-off-by: Leah Rowe --- build | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/build b/build index 884d69de..3854f3e5 100755 --- a/build +++ b/build @@ -106,6 +106,11 @@ usage() possible values for 'OPTION': $(items "${buildpath}") + Special commands (consult $projectname documentation): + ./update release + ./build dependencies distroname + (replace distroname with a filename from config/dependencies/) + To know what ${projectname} version you're on, type: ${progname} version From 029291e5495bf679cb36a7500b73ff9fa1dfff35 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 11 May 2024 05:33:43 +0100 Subject: [PATCH 0104/1319] merge script/vendor/* into include/vendor.sh stub it from the main build script the commands remain identical: ./vendor download arguments_here ./vendor inject arguments_here Signed-off-by: Leah Rowe --- build | 7 + script/vendor/download => include/vendor.sh | 235 ++++++++++++++++++- script/vendor/inject | 238 -------------------- 3 files changed, 231 insertions(+), 249 deletions(-) rename script/vendor/download => include/vendor.sh (56%) delete mode 100755 script/vendor/inject diff --git a/build b/build index 3854f3e5..60877d8e 100755 --- a/build +++ b/build @@ -13,6 +13,8 @@ if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then fi . "include/option.sh" +. "include/vendor.sh" +. "include/mrc.sh" eval "$(setvars "" option aur_notice vdir relname src_dirname srcdir _xm \ target romdir mode)" @@ -46,10 +48,13 @@ initcmd() list) items "${buildpath}" ;; version) mkversion ;; release) shift 1; mkrelease $@ ;; + inject) shift 1; vendor_inject $@ ;; + download) shift 1; vendor_download $@ ;; *) option="${1}" return 0 ;; esac + set -u -e # some commands disable them. turn them on! lbmk_exit 0 } @@ -107,6 +112,8 @@ usage() $(items "${buildpath}") Special commands (consult $projectname documentation): + ./vendor inject + ./vendor download ./update release ./build dependencies distroname (replace distroname with a filename from config/dependencies/) diff --git a/script/vendor/download b/include/vendor.sh similarity index 56% rename from script/vendor/download rename to include/vendor.sh index 6f1fdbbf..a987c4aa 100755 --- a/script/vendor/download +++ b/include/vendor.sh @@ -1,14 +1,8 @@ -#!/usr/bin/env sh # SPDX-License-Identifier: GPL-3.0-only # SPDX-FileCopyrightText: 2022 Caleb La Grange # SPDX-FileCopyrightText: 2022 Ferass El Hafidi # SPDX-FileCopyrightText: 2023-2024 Leah Rowe -. "include/option.sh" -. "include/mrc.sh" - -export PATH="${PATH}:/sbin" - _ua="Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Firefox/91.0" _7ztest="a" @@ -16,14 +10,19 @@ e6400_unpack="${PWD}/src/bios_extract/dell_inspiron_1100_unpacker.py" me7updateparser="${PWD}/util/me7_update_parser/me7_update_parser.py" pfs_extract="${PWD}/src/biosutilities/Dell_PFS_Extract.py" uefiextract="${PWD}/src/uefitool/uefiextract" +nvmutil="util/nvmutil/nvm" eval "$(setvars "" _b _dl EC_url EC_url_bkup EC_hash DL_hash DL_url DL_url_bkup \ E6400_VGA_DL_hash E6400_VGA_DL_url E6400_VGA_DL_url_bkup E6400_VGA_offset \ E6400_VGA_romname SCH5545EC_DL_url SCH5545EC_DL_url_bkup SCH5545EC_DL_hash \ - tree mecleaner kbc1126_ec_dump MRC_refcode_cbtree cbfstoolref MRC_refcode_gbe)" + tree mecleaner kbc1126_ec_dump MRC_refcode_cbtree MRC_refcode_gbe new_mac \ + cbfstoolref release nukemode modifygbe rom archive)" -main() +vendor_download() { + set +u +e + export PATH="${PATH}:/sbin" + [ $# -gt 0 ] || $err "No argument given" board="${1}" boarddir="${cbcfgsdir}/${board}" @@ -33,7 +32,7 @@ main() detect_firmware && exit 0 scan_config "${_b}" "config/vendor" - build_dependencies + build_dependencies_download download_vendorfiles } @@ -48,6 +47,7 @@ detect_firmware() set -- "${boarddir}/config/"* . "${1}" 2>/dev/null . "${boarddir}/target.cfg" 2>/dev/null + [ -z "$tree" ] && $err "detect_firmware $boarddir: tree undefined" cbdir="src/coreboot/$tree" cbfstool="cbutils/$tree/cbfstool" @@ -62,7 +62,7 @@ detect_firmware() printf "Vendor files not needed for: %s\n" "${board}" 1>&2 } -build_dependencies() +build_dependencies_download() { [ -d "${cbdir}" ] || x_ ./update trees -f coreboot ${cbdir##*/} for d in uefitool biosutilities bios_extract; do @@ -169,6 +169,7 @@ extract_intel_me() [ -f "${_me}" ] && return 0 sdir="$(mktemp -d)" + [ -z "$sdir" ] && return 0 mkdir -p "$sdir" || $err "extract_intel_me: !mkdir -p \"$sdir\"" ( [ "${cdir#/a}" != "$cdir" ] && cdir="${cdir#/}" @@ -262,4 +263,216 @@ extract_sch5545ec() $err "extract_sch5545ec: cannot copy sch5545ec firmware file" } -main $@ +vendor_inject() +{ + set +u +e + + [ $# -lt 1 ] && $err "No options specified." + [ "${1}" = "listboards" ] && eval "items config/coreboot || :; exit 0" + + archive="${1}" + + while getopts n:r:b:m: option; do + case "${option}" in + n) nukemode="${OPTARG}" ;; + r) rom=${OPTARG} ;; + b) board=${OPTARG} ;; + m) modifygbe=true + new_mac=${OPTARG} ;; + *) : ;; + esac + done + + check_board + build_dependencies_inject + inject_vendorfiles + [ "${nukemode}" = "nuke" ] && return 0 + printf "Friendly reminder (this is *not* an error message):\n" + printf "Please ensure that the files were inserted correctly.\n" +} + +check_board() +{ + failcheck="n" + check_release "${archive}" || failcheck="y" + if [ "${failcheck}" = "y" ]; then + [ -f "$rom" ] || $err "check_board \"$rom\": invalid path" + [ -z "${rom+x}" ] && $err "check_board: no rom specified" + [ -n "${board+x}" ] || board=$(detect_board "${rom}") + else + release="y" + board=$(detect_board "${archive}") + fi + + boarddir="${cbcfgsdir}/${board}" + [ -d "$boarddir" ] || $err "check_board: board $board missing" + [ -f "$boarddir/target.cfg" ] || \ + $err "check_board $board: target.cfg missing" + . "$boarddir/target.cfg" 2>/dev/null + [ -z "$tree" ] && $err "check_board $board: tree undefined"; return 0 +} + +check_release() +{ + [ -f "${archive}" ] || return 1 + [ "${archive##*.}" = "xz" ] || return 1 + printf "%s\n" "Release archive ${archive} detected" +} + +# This function tries to determine the board from the filename of the rom. +# It will only succeed if the filename is not changed from the build/download +detect_board() +{ + path="${1}" + filename=$(basename "${path}") + case ${filename} in + grub_*) + board=$(echo "${filename}" | cut -d '_' -f2-3) ;; + seabios_withgrub_*) + board=$(echo "${filename}" | cut -d '_' -f3-4) ;; + *.tar.xz) + _stripped_prefix=${filename#*_} + board="${_stripped_prefix%.tar.xz}" ;; + *) + $err "detect_board $filename: could not detect board type" + esac + printf "%s\n" "${board}" +} + +build_dependencies_inject() +{ + cbdir="src/coreboot/$tree" + cbfstool="cbutils/$tree/cbfstool" + ifdtool="cbutils/$tree/ifdtool" + [ -d "${cbdir}" ] || x_ ./update trees -f coreboot $tree + if [ ! -f "${cbfstool}" ] || [ ! -f "${ifdtool}" ]; then + x_ ./update trees -b coreboot utils $tree + fi + [ -z "$new_mac" ] || [ -f "$nvmutil" ] || x_ make -C util/nvmutil + [ "$nukemode" = "nuke" ] || x_ ./vendor download $board; return 0 +} + +inject_vendorfiles() +{ + [ "${release}" != "y" ] && eval "patch_rom \"$rom\"; return 0" + patch_release_roms +} + +patch_release_roms() +{ + _tmpdir="tmp/romdir" + remkdir "${_tmpdir}" + tar -xf "${archive}" -C "${_tmpdir}" || \ + $err "patch_release_roms: !tar -xf \"$archive\" -C \"$_tmpdir\"" + + for x in "${_tmpdir}"/bin/*/*.rom ; do + printf "patching rom: %s\n" "$x" + patch_rom "${x}" + done + + ( + cd "${_tmpdir}/bin/"* || \ + $err "patch_release_roms: !cd ${_tmpdir}/bin/*" + + # NOTE: For compatibility with older rom releases, defer to sha1 + [ "${nukemode}" = "nuke" ] || sha512sum --status -c vendorhashes || \ + sha1sum --status -c vendorhashes || sha512sum --status -c \ + blobhashes || sha1sum --status -c blobhashes || \ + $err "patch_release_roms: ROMs did not match expected hashes" + ) || $err "can't verify vendor hashes" + + [ "${modifygbe}" = "true" ] && \ + for x in "${_tmpdir}"/bin/*/*.rom ; do + modify_gbe "${x}" + done + + [ -d bin/release ] || x_ mkdir -p bin/release + x_ mv "${_tmpdir}"/bin/* bin/release/ + x_ rm -Rf "${_tmpdir}" + + printf "Success! Your ROMs are in bin/release\n" +} + +patch_rom() +{ + rom="${1}" + + check_defconfig "$boarddir" && $err "patch_rom $boarddir: no configs" + + set -- "${boarddir}/config/"* + . "${1}" 2>/dev/null + + [ "$CONFIG_HAVE_MRC" = "y" ] && \ + inject "mrc.bin" "${CONFIG_MRC_FILE}" "mrc" "0xfffa0000" + [ -n "$CONFIG_HAVE_REFCODE_BLOB" ] && \ + inject "fallback/refcode" "$CONFIG_REFCODE_BLOB_FILE" "stage" + [ "${CONFIG_HAVE_ME_BIN}" = "y" ] && \ + inject "IFD" "${CONFIG_ME_BIN_PATH}" "me" + [ "${CONFIG_KBC1126_FIRMWARE}" = "y" ] && \ + inject "ecfw1.bin" "$CONFIG_KBC1126_FW1" "raw" \ + "${CONFIG_KBC1126_FW1_OFFSET}" && \ + inject "ecfw2.bin" "$CONFIG_KBC1126_FW2" "raw" \ + "${CONFIG_KBC1126_FW2_OFFSET}" + [ -n "$CONFIG_VGA_BIOS_FILE" ] && [ -n "$CONFIG_VGA_BIOS_ID" ] && \ + inject "pci${CONFIG_VGA_BIOS_ID}.rom" \ + "${CONFIG_VGA_BIOS_FILE}" "optionrom" + [ "${CONFIG_INCLUDE_SMSC_SCH5545_EC_FW}" = "y" ] && \ + [ -n "${CONFIG_SMSC_SCH5545_EC_FW_FILE}" ] && \ + inject "sch5545_ecfw.bin" "$CONFIG_SMSC_SCH5545_EC_FW_FILE" raw + [ "${modifygbe}" = "true" ] && ! [ "${release}" = "y" ] && \ + inject "IFD" "${CONFIG_GBE_BIN_PATH}" "GbE" + + printf "ROM image successfully patched: %s\n" "${rom}" +} + +inject() +{ + [ $# -lt 3 ] && \ + $err "inject $@, $rom: usage: inject name path type (offset)" + + eval "$(setvars "" cbfsname _dest _t _offset)" + cbfsname="${1}" + _dest="${2##*../}" + _t="${3}" + [ $# -gt 3 ] && _offset="-b ${4}" && [ -z "${4}" ] && \ + $err "inject $@, $rom: offset passed, but empty (not defined)" + + [ -z "${_dest}" ] && $err "inject $@, ${rom}: empty destination path" + [ ! -f "${_dest}" ] && [ "${nukemode}" != "nuke" ] && \ + $err "inject_${dl_type}: file missing, ${_dest}" + + [ "$nukemode" = "nuke" ] || \ + printf "Inserting %s/%s in file: %s\n" "$cbfsname" "$_t" "$rom" + + if [ "${_t}" = "GbE" ]; then + x_ mkdir -p tmp + cp "${_dest}" "tmp/gbe.bin" || \ + $err "inject: !cp \"${_dest}\" \"tmp/gbe.bin\"" + _dest="tmp/gbe.bin" + "${nvmutil}" "${_dest}" setmac "${new_mac}" || \ + $err "inject ${_dest}: can't change mac address" + fi + if [ "${cbfsname}" = "IFD" ]; then + if [ "${nukemode}" != "nuke" ]; then + "$ifdtool" -i ${_t}:${_dest} "$rom" -O "$rom" || \ + $err "inject: can't insert $_t ($dest) into $rom" + else + "$ifdtool" --nuke $_t "$rom" -O "$rom" || \ + $err "inject $rom: can't nuke $_t in IFD" + fi + else + if [ "${nukemode}" != "nuke" ]; then + if [ "$_t" = "stage" ]; then # broadwell refcode + "$cbfstool" "$rom" add-stage -f "$_dest" \ + -n "$cbfsname" -t stage -c lzma + else + "$cbfstool" "$rom" add -f "$_dest" \ + -n "$cbfsname" -t $_t $_offset || \ + $err "$rom: can't insert $_t file $_dest" + fi + else + "$cbfstool" "$rom" remove -n "$cbfsname" || \ + $err "inject $rom: can't remove $cbfsname" + fi + fi +} diff --git a/script/vendor/inject b/script/vendor/inject deleted file mode 100755 index 9b6b52ea..00000000 --- a/script/vendor/inject +++ /dev/null @@ -1,238 +0,0 @@ -#!/usr/bin/env sh -# SPDX-License-Identifier: GPL-3.0-only -# SPDX-FileCopyrightText: 2022 Caleb La Grange -# SPDX-FileCopyrightText: 2022 Ferass El Hafidi -# SPDX-FileCopyrightText: 2023-2024 Leah Rowe - -. "include/option.sh" - -nvmutil="util/nvmutil/nvm" - -eval "$(setvars "" archive rom modifygbe nukemode release new_mac tree)" - -main() -{ - [ $# -lt 1 ] && $err "No options specified." - [ "${1}" = "listboards" ] && eval "items config/coreboot || :; exit 0" - - archive="${1}" - - while getopts n:r:b:m: option; do - case "${option}" in - n) nukemode="${OPTARG}" ;; - r) rom=${OPTARG} ;; - b) board=${OPTARG} ;; - m) modifygbe=true - new_mac=${OPTARG} ;; - *) : ;; - esac - done - - check_board - build_dependencies - inject_vendorfiles - [ "${nukemode}" = "nuke" ] && return 0 - printf "Friendly reminder (this is *not* an error message):\n" - printf "Please ensure that the files were inserted correctly.\n" -} - -check_board() -{ - failcheck="n" - check_release "${archive}" || failcheck="y" - if [ "${failcheck}" = "y" ]; then - [ -f "$rom" ] || $err "check_board \"$rom\": invalid path" - [ -z "${rom+x}" ] && $err "check_board: no rom specified" - [ -n "${board+x}" ] || board=$(detect_board "${rom}") - else - release="y" - board=$(detect_board "${archive}") - fi - - boarddir="${cbcfgsdir}/${board}" - [ -d "$boarddir" ] || $err "check_board: board $board missing" - [ -f "$boarddir/target.cfg" ] || \ - $err "check_board $board: target.cfg missing" - . "$boarddir/target.cfg" 2>/dev/null - [ -z "$tree" ] && $err "check_board $board: tree undefined"; return 0 -} - -check_release() -{ - [ -f "${archive}" ] || return 1 - [ "${archive##*.}" = "xz" ] || return 1 - printf "%s\n" "Release archive ${archive} detected" -} - -# This function tries to determine the board from the filename of the rom. -# It will only succeed if the filename is not changed from the build/download -detect_board() -{ - path="${1}" - filename=$(basename "${path}") - case ${filename} in - grub_*) - board=$(echo "${filename}" | cut -d '_' -f2-3) ;; - seabios_withgrub_*) - board=$(echo "${filename}" | cut -d '_' -f3-4) ;; - *.tar.xz) - _stripped_prefix=${filename#*_} - board="${_stripped_prefix%.tar.xz}" ;; - *) - $err "detect_board $filename: could not detect board type" - esac - printf "%s\n" "${board}" -} - -build_dependencies() -{ - cbdir="src/coreboot/$tree" - cbfstool="cbutils/$tree/cbfstool" - ifdtool="cbutils/$tree/ifdtool" - [ -d "${cbdir}" ] || x_ ./update trees -f coreboot $tree - if [ ! -f "${cbfstool}" ] || [ ! -f "${ifdtool}" ]; then - x_ ./update trees -b coreboot utils $tree - fi - [ -z "$new_mac" ] || [ -f "$nvmutil" ] || x_ make -C util/nvmutil - [ "$nukemode" = "nuke" ] || x_ ./vendor download $board; return 0 -} - -inject_vendorfiles() -{ - [ "${release}" != "y" ] && eval "patch_rom \"$rom\"; return 0" - patch_release_roms -} - -patch_release_roms() -{ - _tmpdir="tmp/romdir" - remkdir "${_tmpdir}" - tar -xf "${archive}" -C "${_tmpdir}" || \ - $err "patch_release_roms: !tar -xf \"$archive\" -C \"$_tmpdir\"" - - for x in "${_tmpdir}"/bin/*/*.rom ; do - printf "patching rom: %s\n" "$x" - patch_rom "${x}" - done - - ( - cd "${_tmpdir}/bin/"* || \ - $err "patch_release_roms: !cd ${_tmpdir}/bin/*" - - # NOTE: For compatibility with older rom releases, defer to sha1 - [ "${nukemode}" = "nuke" ] || sha512sum --status -c vendorhashes || \ - sha1sum --status -c vendorhashes || sha512sum --status -c \ - blobhashes || sha1sum --status -c blobhashes || \ - $err "patch_release_roms: ROMs did not match expected hashes" - ) || $err "can't verify vendor hashes" - - [ "${modifygbe}" = "true" ] && \ - for x in "${_tmpdir}"/bin/*/*.rom ; do - modify_gbe "${x}" - done - - [ -d bin/release ] || x_ mkdir -p bin/release - x_ mv "${_tmpdir}"/bin/* bin/release/ - x_ rm -Rf "${_tmpdir}" - - printf "Success! Your ROMs are in bin/release\n" -} - -patch_rom() -{ - rom="${1}" - - check_defconfig "$boarddir" && $err "patch_rom $boarddir: no configs" - - set -- "${boarddir}/config/"* - . "${1}" 2>/dev/null - - [ "$CONFIG_HAVE_MRC" = "y" ] && \ - inject "mrc.bin" "${CONFIG_MRC_FILE}" "mrc" "0xfffa0000" - [ -n "$CONFIG_HAVE_REFCODE_BLOB" ] && \ - inject "fallback/refcode" "$CONFIG_REFCODE_BLOB_FILE" "stage" - [ "${CONFIG_HAVE_ME_BIN}" = "y" ] && \ - inject "IFD" "${CONFIG_ME_BIN_PATH}" "me" - [ "${CONFIG_KBC1126_FIRMWARE}" = "y" ] && \ - inject "ecfw1.bin" "$CONFIG_KBC1126_FW1" "raw" \ - "${CONFIG_KBC1126_FW1_OFFSET}" && \ - inject "ecfw2.bin" "$CONFIG_KBC1126_FW2" "raw" \ - "${CONFIG_KBC1126_FW2_OFFSET}" - [ -n "$CONFIG_VGA_BIOS_FILE" ] && [ -n "$CONFIG_VGA_BIOS_ID" ] && \ - inject "pci${CONFIG_VGA_BIOS_ID}.rom" \ - "${CONFIG_VGA_BIOS_FILE}" "optionrom" - [ "${CONFIG_INCLUDE_SMSC_SCH5545_EC_FW}" = "y" ] && \ - [ -n "${CONFIG_SMSC_SCH5545_EC_FW_FILE}" ] && \ - inject "sch5545_ecfw.bin" "$CONFIG_SMSC_SCH5545_EC_FW_FILE" raw - [ "${modifygbe}" = "true" ] && ! [ "${release}" = "y" ] && \ - inject "IFD" "${CONFIG_GBE_BIN_PATH}" "GbE" - - printf "ROM image successfully patched: %s\n" "${rom}" -} - -inject() -{ - [ $# -lt 3 ] && \ - $err "inject $@, $rom: usage: inject name path type (offset)" - - eval "$(setvars "" cbfsname _dest _t _offset)" - cbfsname="${1}" - _dest="${2##*../}" - _t="${3}" - [ $# -gt 3 ] && _offset="-b ${4}" && [ -z "${4}" ] && \ - $err "inject $@, $rom: offset passed, but empty (not defined)" - - [ -z "${_dest}" ] && $err "inject $@, ${rom}: empty destination path" - [ ! -f "${_dest}" ] && [ "${nukemode}" != "nuke" ] && \ - $err "inject_${dl_type}: file missing, ${_dest}" - - [ "$nukemode" = "nuke" ] || \ - printf "Inserting %s/%s in file: %s\n" "$cbfsname" "$_t" "$rom" - - if [ "${_t}" = "GbE" ]; then - x_ mkdir -p tmp - cp "${_dest}" "tmp/gbe.bin" || \ - $err "inject: !cp \"${_dest}\" \"tmp/gbe.bin\"" - _dest="tmp/gbe.bin" - "${nvmutil}" "${_dest}" setmac "${new_mac}" || \ - $err "inject ${_dest}: can't change mac address" - fi - if [ "${cbfsname}" = "IFD" ]; then - if [ "${nukemode}" != "nuke" ]; then - "$ifdtool" -i ${_t}:${_dest} "$rom" -O "$rom" || \ - $err "inject: can't insert $_t ($dest) into $rom" - else - "$ifdtool" --nuke $_t "$rom" -O "$rom" || \ - $err "inject $rom: can't nuke $_t in IFD" - fi - else - if [ "${nukemode}" != "nuke" ]; then - if [ "$_t" = "stage" ]; then # broadwell refcode - "$cbfstool" "$rom" add-stage -f "$_dest" \ - -n "$cbfsname" -t stage -c lzma - else - "$cbfstool" "$rom" add -f "$_dest" \ - -n "$cbfsname" -t $_t $_offset || \ - $err "$rom: can't insert $_t file $_dest" - fi - else - "$cbfstool" "$rom" remove -n "$cbfsname" || \ - $err "inject $rom: can't remove $cbfsname" - fi - fi -} - -usage() -{ - cat <<- EOF - USAGE: ./vendor inject -r [rom path] -b [boardname] -m [macaddress] - Example: ./vendor inject -r x230_12mb.rom -b x230_12mb - - Adding a macadress to the gbe is optional. - If the [-m] parameter is left blank, the gbe will not be touched. - - Type './vendor inject listboards' to get a list of valid boards - EOF -} - -main $@ From d7ce26dc23ccd797bd4cb904c378ee6dc701f42b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 11 May 2024 06:22:56 +0100 Subject: [PATCH 0105/1319] move script/*/* to script/ there are only two scripts under script/ now, and there probably won't be many more. lbmk's design has simplified to such a degree that the two-level directory structure is no longer necessary. the existing command structure has not changed. for example: ./build roms list ./update trees -f coreboot default these will still work, but the symlinks to "build" are now strictly for backwards compatibility; they may be removed at a later date, but i'll keep the current design for now. this also leads to a quirk, for example: ./build roms all ./update roms all these now do the exact same thing, whereas "./update roms all" would have previously been an invalid command. Signed-off-by: Leah Rowe --- build | 16 +++++++--------- script/{build => }/roms | 0 script/{update => }/trees | 0 3 files changed, 7 insertions(+), 9 deletions(-) rename script/{build => }/roms (100%) rename script/{update => }/trees (100%) diff --git a/build b/build index 60877d8e..71620308 100755 --- a/build +++ b/build @@ -16,13 +16,12 @@ fi . "include/vendor.sh" . "include/mrc.sh" -eval "$(setvars "" option aur_notice vdir relname src_dirname srcdir _xm \ - target romdir mode)" +eval "$(setvars "" script_path aur_notice vdir relname src_dirname srcdir \ + _xm target romdir mode)" err="fail" linkpath="${0}" linkname="${linkpath##*/}" -buildpath="./script/${linkname}" main() { @@ -45,13 +44,13 @@ initcmd() case "${1}" in help) usage ${0} ;; - list) items "${buildpath}" ;; + list) items "script" ;; version) mkversion ;; release) shift 1; mkrelease $@ ;; inject) shift 1; vendor_inject $@ ;; download) shift 1; vendor_download $@ ;; *) - option="${1}" + script_path="script/${1}" return 0 ;; esac set -u -e # some commands disable them. turn them on! @@ -95,9 +94,8 @@ git_init() excmd() { - lbmkcmd="${buildpath}/${option}" - [ -f "${lbmkcmd}" ] || $err "Invalid command. Run: ${linkpath} help" - shift 1; "$lbmkcmd" $@ || $err "excmd: ${lbmkcmd} ${@}" + [ -f "${script_path}" ] || $err "Bad command. Run: ${linkpath} help" + shift 1; "$script_path" $@ || $err "excmd: ${script_path} ${@}" } usage() @@ -109,7 +107,7 @@ usage() USAGE: ${progname}