stm32g4: irq.json: use fdcanX_itY consistently

Other families used fdcanX_itY already, and that matches the terminology
of the reference manual, so move to that style for consistency.

Signed-off-by: Karl Palsson <karlp@tweak.au>

.gitignore

@@ -47,6 +47,7 @@ include/libopencmsis/lpc13xx/
 include/libopencmsis/lpc17xx/
 include/libopencmsis/lpc43xx/
 include/libopencmsis/msp432/
+include/libopencmsis/nrf/
 include/libopencmsis/pac55xx/
 include/libopencmsis/sam/
 include/libopencmsis/stm32/

.travis.yml

@@ -13,5 +13,5 @@ addons:
 notifications:
   irc:
     channels:
-      - "chat.freenode.net#libopencm3"
+      - "irc.libera.chat#libopencm3"
     use_notice: true

Makefile

@@ -31,6 +31,7 @@ TARGETS ?=	stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \
 		lm3s lm4f msp432/e4 \
 		efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \
 		efm32/ezr32wg \
+		nrf/51 nrf/52 \
 		sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \
 		sam/d \
 		vf6xx \
@@ -124,5 +125,7 @@ genlinktests.clean:
 		printf "  TEST FAIL : $*\n";		\
 	fi;
 
+list-targets:
+	@echo $(TARGETS)
 
-.PHONY: build lib $(LIB_DIRS) doc clean generatedheaders cleanheaders stylecheck genlinktests genlinktests.clean
+.PHONY: build lib $(LIB_DIRS) doc clean generatedheaders cleanheaders stylecheck genlinktests genlinktests.clean list-targets

README.md

@@ -19,6 +19,7 @@ Currently (at least partly) supported microcontrollers:
  - Freescale Vybrid VF6xx
  - Qorvo (formerly ActiveSemi) PAC55XX
  - Synwit SWM050
+ - Nordic NRF51x and NRF52x
 
 The library is written completely from scratch based on the vendor datasheets,
 programming manuals, and application notes. The code is meant to be used
@@ -29,12 +30,24 @@ code to a microcontroller can be done using the OpenOCD ARM JTAG software.
 Status and API
 --------------
 
-The libopencm3 project is currently work in progress. Not all subsystems
+The libopencm3 project is (and presumably, always will be) a work in progress.
-of the microcontrollers are supported, yet.
+Not all subsystems of all microcontrollers are supported, yet, though some parts
+have more complete support than others.
 
-**IMPORTANT**: The API of the library is _NOT_ yet considered stable! Please do
+Prior to version 0.8.0, the api was largely in flux.  Attempts were made to provide
-           not rely on it, yet! Changes to function names, macro names, etc.
+backwards compatibility, but this was not always considered critical.
-           can happen at any time without prior notice!
+
+From 0.8.0 to 1.0, we'll atempt to follow semver, but **EXPECT CHANGES**, as we
+attempt to clear up old APIs and remove deprecated functions.  The 0.8.0 tag was
+placed to provide the "old stable" point before all the new code started landing.
+
+_preview_ code often lands in the "wildwest-N" branches that appear and disappear
+in the repository.  Pull requests marked as "merged-dev" will be in this branch,
+and will be closed when they merge to master.  This is useful for bigger
+interdependent patch sets, and also allows review of merge conflicts in public.
+
+From 1.0, expect to follow semver, with functions (and defines!) being deprecated for
+a release before being removed.
 
 _TIP_: Include this repository as a Git submodule in your project to make sure
      your users get the right version of the library to compile your project.
@@ -55,27 +68,27 @@ Building requires Python (some code is generated).
  Download and install:
 
  - msys - http://sourceforge.net/projects/mingw/files/MSYS/Base/msys-core/msys-1.0.11/MSYS-1.0.11.exe
- - Python - http://www.python.org/ftp/python/2.7/python-2.7.msi (any 2.7 release)
+ - Python - https://www.python.org/downloads/windows/ (any release)
  - arm-none-eabi/arm-elf toolchain (for example this one https://launchpad.net/gcc-arm-embedded)
 
-Run msys shell and set the path without standard Windows paths, so Windows programs such as 'find' won't interfere:
+Run msys shell and set the path without standard Windows paths (adjusting to your version of Python), so Windows programs such as 'find' won't interfere:
 
-    export PATH="/c//Python27:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin"
+    export PATH="/c//Program Files/Python 3.9:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin"
 
 After that you can navigate to the folder where you've extracted libopencm3 and build it.
 
 Toolchain
 ---------
 
-The most heavily tested toolchain is "gcc-arm-embedded"
+The most heavily tested toolchain is ["gcc-arm-embedded"](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain)
-https://launchpad.net/gcc-arm-embedded
+This used to be available at https://launchpad.net/gcc-arm-embedded
 
 Other toolchains _should_ work, but they have not been nearly as well tested.
 Toolchains targeting Linux, such as "gcc-arm-linux-gnu" or the like are
 _not_ appropriate.
 
-_NOTE_: We recommend that you use gcc-arm-embedded version 4.8 2014q3 or newer
+_NOTE_: GCC version 6 or later is required, as we're using attributes on enumerators
-to build all platforms covered by libopencm3 successfully.
+to help mark deprecations.
 
 Building
 --------
@@ -91,6 +104,14 @@ For a more verbose build you can use
 
     $ make V=1
 
+You can reduce the build time by specifying a particular MCU series
+
+    $ make TARGETS='stm32/f1 stm32/f4'
+
+Supported targets can be listed using:
+
+    $ make list-targets
+
 Fine-tuning the build
 ---------------------
 
@@ -179,7 +200,7 @@ Community
 ---------
 
  * Our [![Gitter channel](https://badges.gitter.im/libopencm3/discuss.svg)](https://gitter.im/libopencm3/discuss)
- * Our IRC channel on the freenode IRC network is called #libopencm3
+ * Our IRC channel on the libera.chat IRC network is called #libopencm3
 
 Mailing lists
 -------------
@@ -194,5 +215,5 @@ Mailing lists
 Website
 -------
 
- * http://libopencm3.org
+ * http://libopencm3.org - contains daily autogenerated API documentation
 

doc/Makefile

@@ -12,6 +12,7 @@ TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 stm32/h7 \
 		   efm32/wg efm32/ezr32wg \
 		   lm3s lm4f \
 		   msp432/e4 \
+		   nrf/51 nrf/52 \
 		   lpc13xx lpc17xx lpc43xx \
 		   sam/3a sam/3n sam/3s sam/3u sam/3x \
 		   sam/d sam/4l \

doc/nrf51/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

doc/nrf52/doxy.custom

@@ -0,0 +1 @@
+PREDEFINED += __ARM_ARCH_7EM__

include/libopencm3/cm3/mpu.h

@@ -46,11 +46,11 @@
  *
  *@{*/
 /** MPU_TYPE is always available, even if the MPU is not implemented */
-#define MPU_TYPE			MMIO32(MPU_BASE + 0x00)
+#define MPU_TYPE			MMIO32(MPU_BASE + 0x00) /**< See also \ref CM3_mpu_type */
-#define MPU_CTRL			MMIO32(MPU_BASE + 0x04)
+#define MPU_CTRL			MMIO32(MPU_BASE + 0x04) /**< See also \ref CM3_mpu_ctrl */
-#define MPU_RNR				MMIO32(MPU_BASE + 0x08)
+#define MPU_RNR				MMIO32(MPU_BASE + 0x08) /**< See also \ref CM3_mpu_rnr */
-#define MPU_RBAR			MMIO32(MPU_BASE + 0x0C)
+#define MPU_RBAR			MMIO32(MPU_BASE + 0x0C) /**< See also \ref CM3_mpu_rbar */
-#define MPU_RASR			MMIO32(MPU_BASE + 0x10)
+#define MPU_RASR			MMIO32(MPU_BASE + 0x10) /**< See also \ref CM3_mpu_rasr */
 /**@}*/
 
 /* --- MPU values ---------------------------------------------------------- */
@@ -60,23 +60,20 @@
  * The MPU_TYPE register is always available, even if the MPU is not implemented.
  * In that case, the DREGION field will read as 0.
  *@{*/
-/** v6m/v7m only support a unified MPU (IREGION always 0) */
 #define MPU_TYPE_IREGION_LSB		16
-#define MPU_TYPE_IREGION		(0xFF << MPU_TYPE_IREGION_LSB)
+#define MPU_TYPE_IREGION		(0xFF << MPU_TYPE_IREGION_LSB) /**< Number of protected instruction regions; always 0 on v6m/v7m */
-/** DREGION is non zero if the MPU is available */
 #define MPU_TYPE_DREGION_LSB		8
-#define MPU_TYPE_DREGION		(0xFF << MPU_TYPE_DREGION_LSB)
+#define MPU_TYPE_DREGION		(0xFF << MPU_TYPE_DREGION_LSB) /**< Number of protected data regions */
-/** v6m/v7m only support a unifed MPU (Separate always 0) */
+#define MPU_TYPE_SEPARATE		(1<<0) /**< Indicates if instruction regions are separate from data regions; always 0 on v6m/v7m */
-#define MPU_TYPE_SEPARATE		(1<<0)
 /**@}*/
 
 /** @defgroup CM3_mpu_ctrl MPU CTRL register fields
  * @ingroup CM3_mpu_defines
  * Defines for the Control Register.
  *@{*/
-#define MPU_CTRL_PRIVDEFENA		(1<<2)
+#define MPU_CTRL_PRIVDEFENA		(1<<2) /**< Enable default map in privileged mode */
-#define MPU_CTRL_HFNMIENA		(1<<1)
+#define MPU_CTRL_HFNMIENA		(1<<1) /**< Enable MPU during hard fault, NMI, and FAULTMASK handlers */
-#define MPU_CTRL_ENABLE			(1<<0)
+#define MPU_CTRL_ENABLE			(1<<0) /**< MPU enable */
 /**@}*/
 
 /** @defgroup CM3_mpu_rnr MPU RNR register fields
@@ -84,7 +81,7 @@
  * Defines for the Region Number Register.
  *@{*/
 #define MPU_RNR_REGION_LSB		0
-#define MPU_RNR_REGION			(0xFF << MPU_RNR_REGION_LSB)
+#define MPU_RNR_REGION			(0xFF << MPU_RNR_REGION_LSB) /**< Determines the region affected by RBAR and RASR */
 /**@}*/
 
 /** @defgroup CM3_mpu_rbar MPU RBAR register fields
@@ -93,9 +90,9 @@
  *@{*/
 /** minimum size supported is by writing all ones to ADDR, then reading back */
 #define MPU_RBAR_ADDR			0xFFFFFFE0
-#define MPU_RBAR_VALID			(1<<4)
+#define MPU_RBAR_VALID			(1<<4) /**< Use REGION to determine region to be accessed instead of MPU_RNR */
 #define MPU_RBAR_REGION_LSB		0
-#define MPU_RBAR_REGION			(0xF << MPU_RBAR_REGION_LSB)
+#define MPU_RBAR_REGION			(0xF << MPU_RBAR_REGION_LSB) /**< Region to change if MPU_RBAR_VALID is set */
 /**@}*/
 
 /** @defgroup CM3_mpu_rasr MPU RASR register fields
@@ -103,31 +100,31 @@
  * Defines for the Region Attribute and Size Register.
  *@{*/
 #define MPU_RASR_ATTRS_LSB		16
-#define MPU_RASR_ATTRS			(0xFFFF << MPU_RASR_ATTRS_LSB)
+#define MPU_RASR_ATTRS			(0xFFFF << MPU_RASR_ATTRS_LSB) /** Region attributes */
 #define MPU_RASR_SRD_LSB		8
-#define MPU_RASR_SRD			(0xFF << MPU_RASR_SRD_LSB)
+#define MPU_RASR_SRD			(0xFF << MPU_RASR_SRD_LSB) /**< Subregion disable bits */
 #define MPU_RASR_SIZE_LSB		1
-#define MPU_RASR_SIZE			(0x1F << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_SIZE			(0x1F << MPU_RASR_SIZE_LSB) /**< Region size */
-#define MPU_RASR_ENABLE			(1 << 0)
+#define MPU_RASR_ENABLE			(1 << 0) /**< Region enable bit */
 
 /** @defgroup mpu_rasr_attributes MPU RASR Attributes
  * @ingroup CM3_mpu_rasr
  * Not all attributes are available on v6m.
  *
  *@{*/
-#define MPU_RASR_ATTR_XN		(1 << 28)
+#define MPU_RASR_ATTR_XN		(1 << 28) /**< Execute never */
-#define MPU_RASR_ATTR_AP		(7 << 24)
+#define MPU_RASR_ATTR_AP		(7 << 24) /**< Access permissions mask */
-#define MPU_RASR_ATTR_AP_PNO_UNO	(0 << 24)
+#define MPU_RASR_ATTR_AP_PNO_UNO	(0 << 24) /**< Priv.: no, Unpriv.: no */
-#define MPU_RASR_ATTR_AP_PRW_UNO	(1 << 24)
+#define MPU_RASR_ATTR_AP_PRW_UNO	(1 << 24) /**< Priv.: RW, Unpriv.: no */
-#define MPU_RASR_ATTR_AP_PRW_URO	(2 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URO	(2 << 24) /**< Priv.: RW, Unpriv.: RO */
-#define MPU_RASR_ATTR_AP_PRW_URW	(3 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URW	(3 << 24) /**< Priv.: RW, Unpriv.: RW */
-#define MPU_RASR_ATTR_AP_PRO_UNO	(5 << 24)
+#define MPU_RASR_ATTR_AP_PRO_UNO	(5 << 24) /**< Priv.: RO, Unpriv.: no */
-#define MPU_RASR_ATTR_AP_PRO_URO	(6 << 24)
+#define MPU_RASR_ATTR_AP_PRO_URO	(6 << 24) /**< Priv.: RO, Unpriv.: RO */
-#define MPU_RASR_ATTR_TEX		(7 << 19)
+#define MPU_RASR_ATTR_TEX		(7 << 19) /**< Type extension (e.g., memory ordering) */
-#define MPU_RASR_ATTR_S			(1 << 18)
+#define MPU_RASR_ATTR_S			(1 << 18) /**< Shareable */
-#define MPU_RASR_ATTR_C			(1 << 17)
+#define MPU_RASR_ATTR_C			(1 << 17) /**< Cacheable */
-#define MPU_RASR_ATTR_B			(1 << 16)
+#define MPU_RASR_ATTR_B			(1 << 16) /**< Bufferable */
-#define MPU_RASR_ATTR_SCB		(7 << 16)
+#define MPU_RASR_ATTR_SCB		(7 << 16) /**< SCB mask */
 /**@}*/
 /**@}*/
 

include/libopencm3/cm3/scb.h

@@ -149,6 +149,51 @@
 #define SCB_MVFR1				MMIO32(SCB_BASE + 0x244)
 #endif
 
+/* Those defined only on ARMv7EM and above */
+#if defined(__ARM_ARCH_7EM__)
+/** CLIDR: Cache Level ID Register */
+#define SCB_CLIDR				MMIO32(SCB_BASE + 0x78)
+
+/** CTR: Cache Type Register */
+#define SCB_CTR				MMIO32(SCB_BASE + 0x7C)
+
+/** CCSIDR: Cache Size ID Registers */
+#define SCB_CCSIDR				MMIO32(SCB_BASE + 0x80)
+
+/** CSSELR: Cache Size Selection Register */
+#define SCB_CCSELR				MMIO32(SCB_BASE + 0x84)
+
+/** ICIALLU: I-cache invalidate all to Point of Unification */
+#define SCB_ICIALLU				MMIO32(SCB_BASE + 0x250)
+
+/** ICIMVAU: I-cache invalidate by MVA to Point of Unification */
+#define SCB_ICIMVAU				MMIO32(SCB_BASE + 0x258)
+
+/** DCIMVAC: D-cache invalidate by MVA to Point of Coherency */
+#define SCB_DCIMVAC				MMIO32(SCB_BASE + 0x25C)
+
+/** DCISW: D-cache invalidate by set-way */
+#define SCB_DCISW				MMIO32(SCB_BASE + 0x260)
+
+/** DCCMVAU: D-cache clean by MVA to Point of Unification */
+#define SCB_DCCMVAU				MMIO32(SCB_BASE + 0x264)
+
+/** DCCMVAC: D-cache clean by MVA to Point of Coherency */
+#define SCB_DCCMVAC				MMIO32(SCB_BASE + 0x268)
+
+/** DCISW: D-cache clean by set-way */
+#define SCB_DCCSW				MMIO32(SCB_BASE + 0x26C)
+
+/** DCCIMVAC: D-cache clean and invalidate by MVA to Point of Coherency */
+#define SCB_DCCIMVAC			MMIO32(SCB_BASE + 0x270)
+
+/** DCCISW: D-cache clean and invalidate by set-way */
+#define SCB_DCCISW				MMIO32(SCB_BASE + 0x274)
+
+/** BPIALL: Branch predictor invalidate all */
+#define SCB_BPIALL				MMIO32(SCB_BASE + 0x278)
+#endif
+
 /**@}*/
 
 /* --- SCB values ---------------------------------------------------------- */
@@ -320,6 +365,17 @@
 /** NONBASETHRDENA set to allow non base priority threads */
 #define SCB_CCR_NONBASETHRDENA			(1 << 0)
 #endif
+
+/* Those defined only on ARMv7EM and above */
+#if defined(__ARM_ARCH_7EM__)
+/** BP set to enable branch predictor */
+#define SCB_CCR_BP					(1 << 18)
+/** IC set to enable instruction cache */
+#define SCB_CCR_IC					(1 << 17)
+/** DC set to enable data cache */
+#define SCB_CCR_DC					(1 << 16)
+#endif
+
 /**@}*/
 
 /* These numbers are designed to be used with the SCB_SHPR() macro */
@@ -443,6 +499,26 @@
 
 /* BFAR [31:0]: Bus fault address */
 
+#if defined(__ARM_ARCH_7EM__)
+/* --- SCB_CTR values ------------------------------------------------------ */
+/* FORMAT: implemented CTR format */
+#define SCB_CTR_FORMAT_SHIFT	29
+#define SCB_CTR_FORMAT_MASK		0x7
+/* CWG: Cache Write-back Granule */
+#define SCB_CTR_CWG_SHIFT		24
+#define SCB_CTR_CWG_MASK		0xf
+/* ERG: Exclusives Reservation Granule */
+#define SCB_CTR_ERG_SHIFT		20
+#define SCB_CTR_ERG_MASK		0xf
+/* DMINLINE: log2 of number of words in smallest cache line of all data caches */
+#define SCB_CTR_DMINLINE_SHIFT	16
+#define SCB_CTR_DMINLINE_MASK	0x1f
+/* IMINLINE: log2 of number of words in smallest cache line of all instruction caches */
+#define SCB_CTR_IMINLINE_SHIFT	0
+#define SCB_CTR_IMINLINE_MASK	0xf
+
+#endif
+
 /* --- SCB_CPACR values ---------------------------------------------------- */
 
 /* CPACR CPn: Access privileges values */
@@ -473,7 +549,7 @@ struct scb_exception_stack_frame {
 
 #define SCB_GET_EXCEPTION_STACK_FRAME(f)				\
 	do {								\
-		asm volatile ("mov %[frameptr], sp"			\
+		__asm__ volatile ("mov %[frameptr], sp"			\
 			      : [frameptr]"=r" (f));			\
 	} while (0)
 

include/libopencm3/dispatch/nvic.h

@@ -76,6 +76,12 @@
 #elif defined(MSP432E4)
 #   include <libopencm3/msp432/e4/nvic.h>
 
+#elif defined(NRF51)
+#	include <libopencm3/nrf/51/nvic.h>
+
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/nvic.h>
+
 #elif defined(VF6XX)
 #	include <libopencm3/vf6xx/nvic.h>
 

include/libopencm3/ethernet/mac_stm32fxx7.h

@@ -58,8 +58,7 @@
 #define ETH_MACVLANTR			MMIO32(ETHERNET_BASE + 0x1C)
 #define ETH_MACRWUFFR			MMIO32(ETHERNET_BASE + 0x28)
 #define ETH_MACPMTCSR			MMIO32(ETHERNET_BASE + 0x2C)
-/* not available on F1 ?*/
+#define ETH_MACDBGR			MMIO32(ETHERNET_BASE + 0x34) /* Not on STM32F1 */
-#define ETH_MACDBGR			MMIO32(ETHERNET_BASE + 0x34)
 #define ETH_MACSR			MMIO32(ETHERNET_BASE + 0x38)
 #define ETH_MACIMR			MMIO32(ETHERNET_BASE + 0x3C)
 
@@ -81,7 +80,7 @@
 #define ETH_MMCRFAECR			MMIO32(ETHERNET_BASE + 0x198)
 #define ETH_MMCRGUFCR			MMIO32(ETHERNET_BASE + 0x1C4)
 
-/* Ethrenet IEEE 1588 time stamp registers */
+/* Ethernet IEEE 1588 time stamp registers */
 #define ETH_PTPTSCR			MMIO32(ETHERNET_BASE + 0x700)
 #define ETH_PTPSSIR			MMIO32(ETHERNET_BASE + 0x704)
 #define ETH_PTPTSHR			MMIO32(ETHERNET_BASE + 0x708)
@@ -91,8 +90,8 @@
 #define ETH_PTPTSAR			MMIO32(ETHERNET_BASE + 0x718)
 #define ETH_PTPTTHR			MMIO32(ETHERNET_BASE + 0x71C)
 #define ETH_PTPTTLR			MMIO32(ETHERNET_BASE + 0x720)
-/* not available on F1 ?*/
+#define ETH_PTPTSSR			MMIO32(ETHERNET_BASE + 0x728) /* Not on STM32F1 */
-#define ETH_PTPTSSR			MMIO32(ETHERNET_BASE + 0x728)
+#define ETH_PTPPPSCR			MMIO32(ETHERNET_BASE + 0x72C) /* Not on STM32F1 */
 
 /* Ethernet DMA registers */
 #define ETH_DMABMR			MMIO32(ETHERNET_BASE + 0x1000)
@@ -104,6 +103,7 @@
 #define ETH_DMAOMR			MMIO32(ETHERNET_BASE + 0x1018)
 #define ETH_DMAIER			MMIO32(ETHERNET_BASE + 0x101C)
 #define ETH_DMAMFBOCR			MMIO32(ETHERNET_BASE + 0x1020)
+#define ETH_DMARSWTR			MMIO32(ETHERNET_BASE + 0x1024) /* Not on STM32F1 */
 #define ETH_DMACHTDR			MMIO32(ETHERNET_BASE + 0x1048)
 #define ETH_DMACHRDR			MMIO32(ETHERNET_BASE + 0x104C)
 #define ETH_DMACHTBAR			MMIO32(ETHERNET_BASE + 0x1050)
@@ -154,7 +154,7 @@
 
 #define ETH_MACCR_JD			(1<<22)
 #define ETH_MACCR_WD			(1<<23)
-#define ETH_MACCR_CSTF			(1<<25)
+#define ETH_MACCR_CSTF			(1<<25) /* Not on STM32F1 */
 
 /*---------------------------------------------------------------------------*/
 /* MACFFR -------------------------------------------------------------------*/
@@ -247,6 +247,7 @@
 /*---------------------------------------------------------------------------*/
 /* MACDBGR -------------------------------------------------------------------*/
 
+/* Not on STM32F1 */
 #define ETH_MACDBGR_MMRPEA		(1<<0)
 #define ETH_MACDBGR_MSFRWCS		(3<<1)
 #define ETH_MACDBGR_RFWRA		(1<<4)
@@ -331,8 +332,9 @@
 #define ETH_MMCCR_CSR			(1<<1)
 #define ETH_MMCCR_ROR			(1<<2)
 #define ETH_MMCCR_MCF			(1<<3)
-#define ETH_MMCCR_MCP			(1<<4)
+#define ETH_MMCCR_MCP			(1<<4) /* Not on STM32F1 */
-#define ETH_MMCCR_MCFHP			(1<<5)
+#define ETH_MMCCR_MCFHP			(1<<5) /* Not on STM32F1 */
+
 
 /*---------------------------------------------------------------------------*/
 /* MMCRIR -------------------------------------------------------------------*/
@@ -371,6 +373,8 @@
 #define ETH_PTPTSCR_TSSTU		(1<<3)
 #define ETH_PTPTSCR_TSITE		(1<<4)
 #define ETH_PTPTSCR_TTSARU		(1<<5)
+
+/* Not on STM32F1 */
 #define ETH_PTPTSCR_TSSARFE		(1<<8)
 #define ETH_PTPTSCR_TSSSR		(1<<9)
 #define ETH_PTPTSCR_TSPTPPSV2E		(1<<10)
@@ -410,29 +414,33 @@
 /*---------------------------------------------------------------------------*/
 /* PTPTSSR ------------------------------------------------------------------*/
 
+/* Not on STM32F1 */
 #define ETH_PTPTSSR_TSSO		(1<<0)
 #define ETH_PTPTSSR_TSTTR		(1<<1)
 
-/*---------------------------------------------------------------------------*/
-/* PTPTSCR ------------------------------------------------------------------*/
 
-#define ETH_PTPTSCR_PPSFREQ		(0x0F<<0)
+/*---------------------------------------------------------------------------*/
-#define ETH_PTPTSCR_PPSFREQ_1HZ		(0x00<<0)
+/* PTPPPSCR -----------------------------------------------------------------*/
-#define ETH_PTPTSCR_PPSFREQ_2HZ		(0x01<<0)
+
-#define ETH_PTPTSCR_PPSFREQ_4HZ		(0x02<<0)
+/* Not on STM32F1 */
-#define ETH_PTPTSCR_PPSFREQ_8HZ		(0x03<<0)
+#define ETH_PTPPPSCR_PPSFREQ_MASK			(0x0F<<0)
-#define ETH_PTPTSCR_PPSFREQ_16HZ	(0x04<<0)
+#define ETH_PTPPPSCR_PPSFREQ_1HZ			(0x00<<0)
-#define ETH_PTPTSCR_PPSFREQ_32HZ	(0x05<<0)
+#define ETH_PTPPPSCR_PPSFREQ_2HZ			(0x01<<0)
-#define ETH_PTPTSCR_PPSFREQ_64HZ	(0x06<<0)
+#define ETH_PTPPPSCR_PPSFREQ_4HZ			(0x02<<0)
-#define ETH_PTPTSCR_PPSFREQ_128HZ	(0x07<<0)
+#define ETH_PTPPPSCR_PPSFREQ_8HZ			(0x03<<0)
-#define ETH_PTPTSCR_PPSFREQ_256HZ	(0x08<<0)
+#define ETH_PTPPPSCR_PPSFREQ_16HZ			(0x04<<0)
-#define ETH_PTPTSCR_PPSFREQ_512HZ	(0x09<<0)
+#define ETH_PTPPPSCR_PPSFREQ_32HZ			(0x05<<0)
-#define ETH_PTPTSCR_PPSFREQ_1024HZ	(0x0A<<0)
+#define ETH_PTPPPSCR_PPSFREQ_64HZ			(0x06<<0)
-#define ETH_PTPTSCR_PPSFREQ_2048HZ	(0x0B<<0)
+#define ETH_PTPPPSCR_PPSFREQ_128HZ			(0x07<<0)
-#define ETH_PTPTSCR_PPSFREQ_4096HZ	(0x0C<<0)
+#define ETH_PTPPPSCR_PPSFREQ_256HZ			(0x08<<0)
-#define ETH_PTPTSCR_PPSFREQ_8192HZ	(0x0D<<0)
+#define ETH_PTPPPSCR_PPSFREQ_512HZ			(0x09<<0)
-#define ETH_PTPTSCR_PPSFREQ_16384HZ	(0x0E<<0)
+#define ETH_PTPPPSCR_PPSFREQ_1024HZ			(0x0A<<0)
-#define ETH_PTPTSCR_PPSFREQ_32768HZ	(0x0F<<0)
+#define ETH_PTPPPSCR_PPSFREQ_2048HZ			(0x0B<<0)
+#define ETH_PTPPPSCR_PPSFREQ_4096HZ			(0x0C<<0)
+#define ETH_PTPPPSCR_PPSFREQ_8192HZ			(0x0D<<0)
+#define ETH_PTPPPSCR_PPSFREQ_16384HZ			(0x0E<<0)
+#define ETH_PTPPPSCR_PPSFREQ_32768HZ			(0x0F<<0)
+
 
 /*---------------------------------------------------------------------------*/
 /* DMABMR -------------------------------------------------------------------*/
@@ -463,7 +471,7 @@
 #define ETH_DMABMR_USP			(1<<23)
 #define ETH_DMABMR_FPM			(1<<24)
 #define ETH_DMABMR_AAB			(1<<25)
-#define ETH_DMABMR_MB			(1<<26)
+#define ETH_DMABMR_MB			(1<<26) /* Not on STM32F1 */
 
 /*---------------------------------------------------------------------------*/
 /* DMASR --------------------------------------------------------------------*/
@@ -574,6 +582,7 @@
 /*---------------------------------------------------------------------------*/
 /* DMARSWTR -----------------------------------------------------------------*/
 
+/* Not on STM32F1 */
 #define ETH_DMARSWTR_RSWTC		0xFF
 
 /*---------------------------------------------------------------------------*/

include/libopencm3/gd32/f1x0/rcc.h

@@ -174,44 +174,39 @@
 /** @defgroup rcc_cfgr_adcpre ADCPRE: ADC prescaler
  * @{
  */
-#define RCC_CFGR_ADCPRE_PCLK2_DIV2		0x0
+#define RCC_CFGR_ADCPRE_DIV2		0x0
-#define RCC_CFGR_ADCPRE_PCLK2_DIV4		0x1
+#define RCC_CFGR_ADCPRE_DIV4		0x1
-#define RCC_CFGR_ADCPRE_PCLK2_DIV6		0x2
+#define RCC_CFGR_ADCPRE_DIV6		0x2
-#define RCC_CFGR_ADCPRE_PCLK2_DIV8		0x3
+#define RCC_CFGR_ADCPRE_DIV8		0x3
 /**@}*/
 
-/** @defgroup rcc_cfgr_apb2pre PPRE2: APB high-speed prescaler (APB2)
+#define RCC_CFGR_PPRE2_SHIFT			11
+#define RCC_CFGR_PPRE2_MASK			0x7
+#define RCC_CFGR_PPRE1_SHIFT			8
+#define RCC_CFGR_PPRE1_MASK			0x7
+/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors
+ * These can be used for both APB1 and APB2 prescaling
  * @{
  */
-#define RCC_CFGR_PPRE2_HCLK_NODIV		0x0
+#define RCC_CFGR_PPRE_NODIV			0x0
-#define RCC_CFGR_PPRE2_HCLK_DIV2		0x4
+#define RCC_CFGR_PPRE_DIV2			0x4
-#define RCC_CFGR_PPRE2_HCLK_DIV4		0x5
+#define RCC_CFGR_PPRE_DIV4			0x5
-#define RCC_CFGR_PPRE2_HCLK_DIV8		0x6
+#define RCC_CFGR_PPRE_DIV8			0x6
-#define RCC_CFGR_PPRE2_HCLK_DIV16		0x7
+#define RCC_CFGR_PPRE_DIV16			0x7
-/**@}*/
-
-/** @defgroup rcc_cfgr_apb1pre PPRE1: APB low-speed prescaler (APB1)
- * @{
- */
-#define RCC_CFGR_PPRE1_HCLK_NODIV		0x0
-#define RCC_CFGR_PPRE1_HCLK_DIV2		0x4
-#define RCC_CFGR_PPRE1_HCLK_DIV4		0x5
-#define RCC_CFGR_PPRE1_HCLK_DIV8		0x6
-#define RCC_CFGR_PPRE1_HCLK_DIV16		0x7
 /**@}*/
 
 /** @defgroup rcc_cfgr_ahbpre HPRE: AHB prescaler
  * @{
  */
-#define RCC_CFGR_HPRE_SYSCLK_NODIV		0x0
+#define RCC_CFGR_HPRE_NODIV		0x0
-#define RCC_CFGR_HPRE_SYSCLK_DIV2		0x8
+#define RCC_CFGR_HPRE_DIV2		0x8
-#define RCC_CFGR_HPRE_SYSCLK_DIV4		0x9
+#define RCC_CFGR_HPRE_DIV4		0x9
-#define RCC_CFGR_HPRE_SYSCLK_DIV8		0xa
+#define RCC_CFGR_HPRE_DIV8		0xa
-#define RCC_CFGR_HPRE_SYSCLK_DIV16		0xb
+#define RCC_CFGR_HPRE_DIV16		0xb
-#define RCC_CFGR_HPRE_SYSCLK_DIV64		0xc
+#define RCC_CFGR_HPRE_DIV64		0xc
-#define RCC_CFGR_HPRE_SYSCLK_DIV128		0xd
+#define RCC_CFGR_HPRE_DIV128		0xd
-#define RCC_CFGR_HPRE_SYSCLK_DIV256		0xe
+#define RCC_CFGR_HPRE_DIV256		0xe
-#define RCC_CFGR_HPRE_SYSCLK_DIV512		0xf
+#define RCC_CFGR_HPRE_DIV512		0xf
 /**@}*/
 
 /* SWS: System clock switch status */
@@ -227,6 +222,39 @@
 #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK		0x2
 /**@}*/
 
+/** Older compatible definitions to ease migration
+ * @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers
+ * @deprecated Use _CFGR_xPRE_DIVn form instead, across all families
+ * @{
+ */
+#define RCC_CFGR_ADCPRE_PCLK2_DIV2		0x0
+#define RCC_CFGR_ADCPRE_PCLK2_DIV4		0x1
+#define RCC_CFGR_ADCPRE_PCLK2_DIV6		0x2
+#define RCC_CFGR_ADCPRE_PCLK2_DIV8		0x3
+
+#define RCC_CFGR_PPRE2_HCLK_NODIV		0x0
+#define RCC_CFGR_PPRE2_HCLK_DIV2		0x4
+#define RCC_CFGR_PPRE2_HCLK_DIV4		0x5
+#define RCC_CFGR_PPRE2_HCLK_DIV8		0x6
+#define RCC_CFGR_PPRE2_HCLK_DIV16		0x7
+
+#define RCC_CFGR_PPRE1_HCLK_NODIV		0x0
+#define RCC_CFGR_PPRE1_HCLK_DIV2		0x4
+#define RCC_CFGR_PPRE1_HCLK_DIV4		0x5
+#define RCC_CFGR_PPRE1_HCLK_DIV8		0x6
+#define RCC_CFGR_PPRE1_HCLK_DIV16		0x7
+
+#define RCC_CFGR_HPRE_SYSCLK_NODIV		0x0
+#define RCC_CFGR_HPRE_SYSCLK_DIV2		0x8
+#define RCC_CFGR_HPRE_SYSCLK_DIV4		0x9
+#define RCC_CFGR_HPRE_SYSCLK_DIV8		0xa
+#define RCC_CFGR_HPRE_SYSCLK_DIV16		0xb
+#define RCC_CFGR_HPRE_SYSCLK_DIV64		0xc
+#define RCC_CFGR_HPRE_SYSCLK_DIV128		0xd
+#define RCC_CFGR_HPRE_SYSCLK_DIV256		0xe
+#define RCC_CFGR_HPRE_SYSCLK_DIV512		0xf
+/**@}*/
+
 /* --- RCC_CIR values ------------------------------------------------------ */
 
 /* Clock security system interrupt clear bit */

include/libopencm3/lm4f/systemcontrol.h

@@ -40,155 +40,294 @@ LGPL License Terms @ref lgpl_license
 #include <libopencm3/cm3/common.h>
 #include <libopencm3/lm4f/memorymap.h>
 
-#define SYSCTL_DID0			MMIO32(SYSCTL_BASE + 0x000)
+#define SYSCTL_DID0_OFFSET	0x000
-#define SYSCTL_DID1			MMIO32(SYSCTL_BASE + 0x004)
+#define SYSCTL_DID0			MMIO32(SYSCTL_BASE + SYSCTL_DID0_OFFSET)
-#define SYSCTL_PBORCTL			MMIO32(SYSCTL_BASE + 0x030)
+#define SYSCTL_DID1_OFFSET	0x004
-#define SYSCTL_LDORCTL			MMIO32(SYSCTL_BASE + 0x034)
+#define SYSCTL_DID1			MMIO32(SYSCTL_BASE + SYSCTL_DID1_OFFSET)
-#define SYSCTL_RIS			MMIO32(SYSCTL_BASE + 0x050)
+#define SYSCTL_PBORCTL_OFFSET	0x030
-#define SYSCTL_IMC			MMIO32(SYSCTL_BASE + 0x054)
+#define SYSCTL_PBORCTL			MMIO32(SYSCTL_BASE + SYSCTL_PBORCTL_OFFSET)
-#define SYSCTL_MISC			MMIO32(SYSCTL_BASE + 0x058)
+#define SYSCTL_LDORCTL_OFFSET	0x034
-#define SYSCTL_RESC			MMIO32(SYSCTL_BASE + 0x05C)
+#define SYSCTL_LDORCTL			MMIO32(SYSCTL_BASE + SYSCTL_LDORCTL_OFFSET)
-#define SYSCTL_RCC			MMIO32(SYSCTL_BASE + 0x060)
+#define SYSCTL_RIS_OFFSET	0x050
-#define SYSCTL_PLLCFG			MMIO32(SYSCTL_BASE + 0x064)
+#define SYSCTL_RIS			MMIO32(SYSCTL_BASE + SYSCTL_RIS_OFFSET)
-#define SYSCTL_GPIOHBCTL		MMIO32(SYSCTL_BASE + 0x06C)
+#define SYSCTL_IMC_OFFSET	0x054
-#define SYSCTL_RCC2			MMIO32(SYSCTL_BASE + 0x070)
+#define SYSCTL_IMC			MMIO32(SYSCTL_BASE + SYSCTL_IMC_OFFSET)
-#define SYSCTL_MOSCCTL			MMIO32(SYSCTL_BASE + 0x07C)
+#define SYSCTL_MISC_OFFSET	0x058
-#define SYSCTL_DSLPCLKCFG		MMIO32(SYSCTL_BASE + 0x144)
+#define SYSCTL_MISC			MMIO32(SYSCTL_BASE + SYSCTL_MISC_OFFSET)
-#define SYSCTL_SYSPROP			MMIO32(SYSCTL_BASE + 0x14C)
+#define SYSCTL_RESC_OFFSET	0x05C
-#define SYSCTL_PIOSCCAL			MMIO32(SYSCTL_BASE + 0x150)
+#define SYSCTL_RESC			MMIO32(SYSCTL_BASE + SYSCTL_RESC_OFFSET)
-#define SYSCTL_PIOSCSTAT		MMIO32(SYSCTL_BASE + 0x154)
+#define SYSCTL_RCC_OFFSET	0x060
-#define SYSCTL_PLLFREQ0			MMIO32(SYSCTL_BASE + 0x160)
+#define SYSCTL_RCC			MMIO32(SYSCTL_BASE + SYSCTL_RCC_OFFSET)
-#define SYSCTL_PLLFREQ1			MMIO32(SYSCTL_BASE + 0x164)
+#define SYSCTL_PLLCFG_OFFSET	0x064
-#define SYSCTL_PLLSTAT			MMIO32(SYSCTL_BASE + 0x168)
+#define SYSCTL_PLLCFG			MMIO32(SYSCTL_BASE + SYSCTL_PLLCFG_OFFSET)
+#define SYSCTL_GPIOHBCTL_OFFSET	0x06C
+#define SYSCTL_GPIOHBCTL		MMIO32(SYSCTL_BASE + SYSCTL_GPIOHBCTL_OFFSET)
+#define SYSCTL_RCC2_OFFSET	0x070
+#define SYSCTL_RCC2			MMIO32(SYSCTL_BASE + SYSCTL_RCC2_OFFSET)
+#define SYSCTL_MOSCCTL_OFFSET	0x07C
+#define SYSCTL_MOSCCTL			MMIO32(SYSCTL_BASE + SYSCTL_MOSCCTL_OFFSET)
+#define SYSCTL_DSLPCLKCFG_OFFSET	0x144
+#define SYSCTL_DSLPCLKCFG		MMIO32(SYSCTL_BASE + SYSCTL_DSLPCLKCFG_OFFSET)
+#define SYSCTL_SYSPROP_OFFSET	0x14C
+#define SYSCTL_SYSPROP			MMIO32(SYSCTL_BASE + SYSCTL_SYSPROP_OFFSET)
+#define SYSCTL_PIOSCCAL_OFFSET	0x150
+#define SYSCTL_PIOSCCAL			MMIO32(SYSCTL_BASE + SYSCTL_PIOSCCAL_OFFSET)
+#define SYSCTL_PIOSCSTAT_OFFSET	0x154
+#define SYSCTL_PIOSCSTAT		MMIO32(SYSCTL_BASE + SYSCTL_PIOSCSTAT_OFFSET)
+#define SYSCTL_PLLFREQ0_OFFSET	0x160
+#define SYSCTL_PLLFREQ0			MMIO32(SYSCTL_BASE + SYSCTL_PLLFREQ0_OFFSET)
+#define SYSCTL_PLLFREQ1_OFFSET	0x164
+#define SYSCTL_PLLFREQ1			MMIO32(SYSCTL_BASE + SYSCTL_PLLFREQ1_OFFSET)
+#define SYSCTL_PLLSTAT_OFFSET	0x168
+#define SYSCTL_PLLSTAT			MMIO32(SYSCTL_BASE + SYSCTL_PLLSTAT_OFFSET)
 /* Peripheral present */
-#define SYSCTL_PPWD			MMIO32(SYSCTL_BASE + 0x300)
+#define SYSCTL_PPWD_OFFSET	0x300
-#define SYSCTL_PPTIMER			MMIO32(SYSCTL_BASE + 0x304)
+#define SYSCTL_PPWD			MMIO32(SYSCTL_BASE + SYSCTL_PPWD_OFFSET)
-#define SYSCTL_PPGPIO			MMIO32(SYSCTL_BASE + 0x308)
+#define SYSCTL_PPTIMER_OFFSET	0x304
-#define SYSCTL_PPDMA			MMIO32(SYSCTL_BASE + 0x30C)
+#define SYSCTL_PPTIMER			MMIO32(SYSCTL_BASE + SYSCTL_PPTIMER_OFFSET)
-#define SYSCTL_PPHIB			MMIO32(SYSCTL_BASE + 0x314)
+#define SYSCTL_PPGPIO_OFFSET	0x308
-#define SYSCTL_PPUART			MMIO32(SYSCTL_BASE + 0x318)
+#define SYSCTL_PPGPIO			MMIO32(SYSCTL_BASE + SYSCTL_PPGPIO_OFFSET)
-#define SYSCTL_PPSSI			MMIO32(SYSCTL_BASE + 0x31C)
+#define SYSCTL_PPDMA_OFFSET		0x30C
-#define SYSCTL_PPI2C			MMIO32(SYSCTL_BASE + 0x320)
+#define SYSCTL_PPDMA			MMIO32(SYSCTL_BASE + SYSCTL_PPDMA_OFFSET)
-#define SYSCTL_PPUSB			MMIO32(SYSCTL_BASE + 0x328)
+#define SYSCTL_PPHIB_OFFSET		0x314
-#define SYSCTL_PPCAN			MMIO32(SYSCTL_BASE + 0x334)
+#define SYSCTL_PPHIB			MMIO32(SYSCTL_BASE + SYSCTL_PPHIB_OFFSET)
-#define SYSCTL_PPADC			MMIO32(SYSCTL_BASE + 0x338)
+#define SYSCTL_PPUART_OFFSET	0x318
-#define SYSCTL_PPACMP			MMIO32(SYSCTL_BASE + 0x33C)
+#define SYSCTL_PPUART			MMIO32(SYSCTL_BASE + SYSCTL_PPUART_OFFSET)
-#define SYSCTL_PPPWM			MMIO32(SYSCTL_BASE + 0x340)
+#define SYSCTL_PPSSI_OFFSET		0x31C
-#define SYSCTL_PPQEI			MMIO32(SYSCTL_BASE + 0x344)
+#define SYSCTL_PPSSI			MMIO32(SYSCTL_BASE + SYSCTL_PPSSI_OFFSET)
-#define SYSCTL_PPEEPROM			MMIO32(SYSCTL_BASE + 0x358)
+#define SYSCTL_PPI2C_OFFSET		0x320
-#define SYSCTL_PPWTIMER			MMIO32(SYSCTL_BASE + 0x35C)
+#define SYSCTL_PPI2C			MMIO32(SYSCTL_BASE + SYSCTL_PPI2C_OFFSET)
+#define SYSCTL_PPUSB_OFFSET		0x328
+#define SYSCTL_PPUSB			MMIO32(SYSCTL_BASE + SYSCTL_PPUSB_OFFSET)
+#define SYSCTL_PPCAN_OFFSET		0x334
+#define SYSCTL_PPCAN			MMIO32(SYSCTL_BASE + SYSCTL_PPCAN_OFFSET)
+#define SYSCTL_PPADC_OFFSET		0x338
+#define SYSCTL_PPADC			MMIO32(SYSCTL_BASE + SYSCTL_PPADC_OFFSET)
+#define SYSCTL_PPACMP_OFFSET	0x33C
+#define SYSCTL_PPACMP			MMIO32(SYSCTL_BASE + SYSCTL_PPACMP_OFFSET)
+#define SYSCTL_PPPWM_OFFSET		0x340
+#define SYSCTL_PPPWM			MMIO32(SYSCTL_BASE + SYSCTL_PPPWM_OFFSET)
+#define SYSCTL_PPQEI_OFFSET		0x344
+#define SYSCTL_PPQEI			MMIO32(SYSCTL_BASE + SYSCTL_PPQEI_OFFSET)
+#define SYSCTL_PPEEPROM_OFFSET	0x358
+#define SYSCTL_PPEEPROM			MMIO32(SYSCTL_BASE + SYSCTL_PPEEPROM_OFFSET)
+#define SYSCTL_PPWTIMER_OFFSET	0x35C
+#define SYSCTL_PPWTIMER			MMIO32(SYSCTL_BASE + SYSCTL_PPWTIMER_OFFSET)
 /* Peripheral software reset */
-#define SYSCTL_SRWD			MMIO32(SYSCTL_BASE + 0x500)
+#define SYSCTL_SRWD_OFFSET	0x500
-#define SYSCTL_SRTIMER			MMIO32(SYSCTL_BASE + 0x504)
+#define SYSCTL_SRWD			MMIO32(SYSCTL_BASE + SYSCTL_SRWD_OFFSET)
-#define SYSCTL_SRGPIO			MMIO32(SYSCTL_BASE + 0x508)
+#define SYSCTL_SRTIMER_OFFSET	0x504
-#define SYSCTL_SRDMA			MMIO32(SYSCTL_BASE + 0x50C)
+#define SYSCTL_SRTIMER			MMIO32(SYSCTL_BASE + SYSCTL_SRTIMER_OFFSET)
-#define SYSCTL_SRHIB			MMIO32(SYSCTL_BASE + 0x514)
+#define SYSCTL_SRGPIO_OFFSET	0x508
-#define SYSCTL_SRUART			MMIO32(SYSCTL_BASE + 0x518)
+#define SYSCTL_SRGPIO			MMIO32(SYSCTL_BASE + SYSCTL_SRGPIO_OFFSET)
-#define SYSCTL_SRSSI			MMIO32(SYSCTL_BASE + 0x51C)
+#define SYSCTL_SRDMA_OFFSET		0x50C
-#define SYSCTL_SRI2C			MMIO32(SYSCTL_BASE + 0x520)
+#define SYSCTL_SRDMA			MMIO32(SYSCTL_BASE + SYSCTL_SRDMA_OFFSET)
-#define SYSCTL_SRUSB			MMIO32(SYSCTL_BASE + 0x528)
+#define SYSCTL_SRHIB_OFFSET		0x514
-#define SYSCTL_SRCAN			MMIO32(SYSCTL_BASE + 0x534)
+#define SYSCTL_SRHIB			MMIO32(SYSCTL_BASE + SYSCTL_SRHIB_OFFSET)
-#define SYSCTL_SRADC			MMIO32(SYSCTL_BASE + 0x538)
+#define SYSCTL_SRUART_OFFSET	0x518
-#define SYSCTL_SRACMP			MMIO32(SYSCTL_BASE + 0x53C)
+#define SYSCTL_SRUART			MMIO32(SYSCTL_BASE + SYSCTL_SRUART_OFFSET)
-#define SYSCTL_SRPWM			MMIO32(SYSCTL_BASE + 0x540)
+#define SYSCTL_SRSSI_OFFSET		0x51C
-#define SYSCTL_SRQEI			MMIO32(SYSCTL_BASE + 0x544)
+#define SYSCTL_SRSSI			MMIO32(SYSCTL_BASE + SYSCTL_SRSSI_OFFSET)
-#define SYSCTL_SREEPROM			MMIO32(SYSCTL_BASE + 0x558)
+#define SYSCTL_SRI2C_OFFSET		0x520
-#define SYSCTL_SRWTIMER			MMIO32(SYSCTL_BASE + 0x55C)
+#define SYSCTL_SRI2C			MMIO32(SYSCTL_BASE + SYSCTL_SRI2C_OFFSET)
+#define SYSCTL_SRUSB_OFFSET		0x528
+#define SYSCTL_SRUSB			MMIO32(SYSCTL_BASE + SYSCTL_SRUSB_OFFSET)
+#define SYSCTL_SRCAN_OFFSET		0x534
+#define SYSCTL_SRCAN			MMIO32(SYSCTL_BASE + SYSCTL_SRCAN_OFFSET)
+#define SYSCTL_SRADC_OFFSET		0x538
+#define SYSCTL_SRADC			MMIO32(SYSCTL_BASE + SYSCTL_SRADC_OFFSET)
+#define SYSCTL_SRACMP_OFFSET	0x53C
+#define SYSCTL_SRACMP			MMIO32(SYSCTL_BASE + SYSCTL_SRACMP_OFFSET)
+#define SYSCTL_SRPWM_OFFSET		0x540
+#define SYSCTL_SRPWM			MMIO32(SYSCTL_BASE + SYSCTL_SRPWM_OFFSET)
+#define SYSCTL_SRQEI_OFFSET		0x544
+#define SYSCTL_SRQEI			MMIO32(SYSCTL_BASE + SYSCTL_SRQEI_OFFSET)
+#define SYSCTL_SREEPROM_OFFSET	0x558
+#define SYSCTL_SREEPROM			MMIO32(SYSCTL_BASE + SYSCTL_SREEPROM_OFFSET)
+#define SYSCTL_SRWTIMER_OFFSET	0x55C
+#define SYSCTL_SRWTIMER			MMIO32(SYSCTL_BASE + SYSCTL_SRWTIMER_OFFSET)
 /* Peripheral run mode clock gating control */
-#define SYSCTL_RCGCWD			MMIO32(SYSCTL_BASE + 0x600)
+#define SYSCTL_RCGCWD_OFFSET	0x600
-#define SYSCTL_RCGCTIMER		MMIO32(SYSCTL_BASE + 0x604)
+#define SYSCTL_RCGCWD			MMIO32(SYSCTL_BASE + SYSCTL_RCGCWD_OFFSET)
-#define SYSCTL_RCGCGPIO			MMIO32(SYSCTL_BASE + 0x608)
+#define SYSCTL_RCGCTIMER_OFFSET	0x604
-#define SYSCTL_RCGCDMA			MMIO32(SYSCTL_BASE + 0x60C)
+#define SYSCTL_RCGCTIMER		MMIO32(SYSCTL_BASE + SYSCTL_RCGCTIMER_OFFSET)
-#define SYSCTL_RCGCHIB			MMIO32(SYSCTL_BASE + 0x614)
+#define SYSCTL_RCGCGPIO_OFFSET	0x608
-#define SYSCTL_RCGCUART			MMIO32(SYSCTL_BASE + 0x618)
+#define SYSCTL_RCGCGPIO			MMIO32(SYSCTL_BASE + SYSCTL_RCGCGPIO_OFFSET)
-#define SYSCTL_RCGCSSI			MMIO32(SYSCTL_BASE + 0x61C)
+#define SYSCTL_RCGCDMA_OFFSET	0x60C
-#define SYSCTL_RCGCI2C			MMIO32(SYSCTL_BASE + 0x620)
+#define SYSCTL_RCGCDMA			MMIO32(SYSCTL_BASE + SYSCTL_RCGCDMA_OFFSET)
-#define SYSCTL_RCGCUSB			MMIO32(SYSCTL_BASE + 0x628)
+#define SYSCTL_RCGCHIB_OFFSET	0x614
-#define SYSCTL_RCGCCAN			MMIO32(SYSCTL_BASE + 0x634)
+#define SYSCTL_RCGCHIB			MMIO32(SYSCTL_BASE + SYSCTL_RCGCHIB_OFFSET)
-#define SYSCTL_RCGCADC			MMIO32(SYSCTL_BASE + 0x638)
+#define SYSCTL_RCGCUART_OFFSET	0x618
-#define SYSCTL_RCGCACMP			MMIO32(SYSCTL_BASE + 0x63C)
+#define SYSCTL_RCGCUART			MMIO32(SYSCTL_BASE + SYSCTL_RCGCUART_OFFSET)
-#define SYSCTL_RCGCPWM			MMIO32(SYSCTL_BASE + 0x640)
+#define SYSCTL_RCGCSSI_OFFSET	0x61C
-#define SYSCTL_RCGCQEI			MMIO32(SYSCTL_BASE + 0x644)
+#define SYSCTL_RCGCSSI			MMIO32(SYSCTL_BASE + SYSCTL_RCGCSSI_OFFSET)
-#define SYSCTL_RCGCEEPROM		MMIO32(SYSCTL_BASE + 0x658)
+#define SYSCTL_RCGCI2C_OFFSET	0x620
-#define SYSCTL_RCGCWTIMER		MMIO32(SYSCTL_BASE + 0x65C)
+#define SYSCTL_RCGCI2C			MMIO32(SYSCTL_BASE + SYSCTL_RCGCI2C_OFFSET)
+#define SYSCTL_RCGCUSB_OFFSET	0x628
+#define SYSCTL_RCGCUSB			MMIO32(SYSCTL_BASE + SYSCTL_RCGCUSB_OFFSET)
+#define SYSCTL_RCGCCAN_OFFSET	0x634
+#define SYSCTL_RCGCCAN			MMIO32(SYSCTL_BASE + SYSCTL_RCGCCAN_OFFSET)
+#define SYSCTL_RCGCADC_OFFSET	0x638
+#define SYSCTL_RCGCADC			MMIO32(SYSCTL_BASE + SYSCTL_RCGCADC_OFFSET)
+#define SYSCTL_RCGCACMP_OFFSET	0x63C
+#define SYSCTL_RCGCACMP			MMIO32(SYSCTL_BASE + SYSCTL_RCGCACMP_OFFSET)
+#define SYSCTL_RCGCPWM_OFFSET	0x640
+#define SYSCTL_RCGCPWM			MMIO32(SYSCTL_BASE + SYSCTL_RCGCPWM_OFFSET)
+#define SYSCTL_RCGCQEI_OFFSET	0x644
+#define SYSCTL_RCGCQEI			MMIO32(SYSCTL_BASE + SYSCTL_RCGCQEI_OFFSET)
+#define SYSCTL_RCGCEEPROM_OFFSET	0x658
+#define SYSCTL_RCGCEEPROM		MMIO32(SYSCTL_BASE + SYSCTL_RCGCEEPROM_OFFSET)
+#define SYSCTL_RCGCWTIMER_OFFSET	0x65C
+#define SYSCTL_RCGCWTIMER		MMIO32(SYSCTL_BASE + SYSCTL_RCGCWTIMER_OFFSET)
 /* Peripheral sleep mode clock gating control */
-#define SYSCTL_SCGCWD			MMIO32(SYSCTL_BASE + 0x700)
+#define SYSCTL_SCGCWD_OFFSET	0x700
-#define SYSCTL_SCGCTIMER		MMIO32(SYSCTL_BASE + 0x704)
+#define SYSCTL_SCGCWD			MMIO32(SYSCTL_BASE + SYSCTL_SCGCWD_OFFSET)
-#define SYSCTL_SCGCGPIO			MMIO32(SYSCTL_BASE + 0x708)
+#define SYSCTL_SCGCTIMER_OFFSET	0x704
-#define SYSCTL_SCGCDMA			MMIO32(SYSCTL_BASE + 0x70C)
+#define SYSCTL_SCGCTIMER		MMIO32(SYSCTL_BASE + SYSCTL_SCGCTIMER_OFFSET)
-#define SYSCTL_SCGCHIB			MMIO32(SYSCTL_BASE + 0x714)
+#define SYSCTL_SCGCGPIO_OFFSET	0x708
-#define SYSCTL_SCGCUART			MMIO32(SYSCTL_BASE + 0x718)
+#define SYSCTL_SCGCGPIO			MMIO32(SYSCTL_BASE + SYSCTL_SCGCGPIO_OFFSET)
-#define SYSCTL_SCGCSSI			MMIO32(SYSCTL_BASE + 0x71C)
+#define SYSCTL_SCGCDMA_OFFSET	0x70C
-#define SYSCTL_SCGCI2C			MMIO32(SYSCTL_BASE + 0x720)
+#define SYSCTL_SCGCDMA			MMIO32(SYSCTL_BASE + SYSCTL_SCGCDMA_OFFSET)
-#define SYSCTL_SCGCUSB			MMIO32(SYSCTL_BASE + 0x728)
+#define SYSCTL_SCGCHIB_OFFSET	0x714
-#define SYSCTL_SCGCCAN			MMIO32(SYSCTL_BASE + 0x734)
+#define SYSCTL_SCGCHIB			MMIO32(SYSCTL_BASE + SYSCTL_SCGCHIB_OFFSET)
-#define SYSCTL_SCGCADC			MMIO32(SYSCTL_BASE + 0x738)
+#define SYSCTL_SCGCUART_OFFSET	0x718
-#define SYSCTL_SCGCACMP			MMIO32(SYSCTL_BASE + 0x73C)
+#define SYSCTL_SCGCUART			MMIO32(SYSCTL_BASE + SYSCTL_SCGCUART_OFFSET)
-#define SYSCTL_SCGCPWM			MMIO32(SYSCTL_BASE + 0x740)
+#define SYSCTL_SCGCSSI_OFFSET	0x71C
-#define SYSCTL_SCGCQEI			MMIO32(SYSCTL_BASE + 0x744)
+#define SYSCTL_SCGCSSI			MMIO32(SYSCTL_BASE + SYSCTL_SCGCSSI_OFFSET)
-#define SYSCTL_SCGCEEPROM		MMIO32(SYSCTL_BASE + 0x758)
+#define SYSCTL_SCGCI2C_OFFSET	0x720
-#define SYSCTL_SCGCWTIMER		MMIO32(SYSCTL_BASE + 0x75C)
+#define SYSCTL_SCGCI2C			MMIO32(SYSCTL_BASE + SYSCTL_SCGCI2C_OFFSET)
+#define SYSCTL_SCGCUSB_OFFSET	0x728
+#define SYSCTL_SCGCUSB			MMIO32(SYSCTL_BASE + SYSCTL_SCGCUSB_OFFSET)
+#define SYSCTL_SCGCCAN_OFFSET	0x734
+#define SYSCTL_SCGCCAN			MMIO32(SYSCTL_BASE + SYSCTL_SCGCCAN_OFFSET)
+#define SYSCTL_SCGCADC_OFFSET	0x738
+#define SYSCTL_SCGCADC			MMIO32(SYSCTL_BASE + SYSCTL_SCGCADC_OFFSET)
+#define SYSCTL_SCGCACMP_OFFSET	0x73C
+#define SYSCTL_SCGCACMP			MMIO32(SYSCTL_BASE + SYSCTL_SCGCACMP_OFFSET)
+#define SYSCTL_SCGCPWM_OFFSET	0x740
+#define SYSCTL_SCGCPWM			MMIO32(SYSCTL_BASE + SYSCTL_SCGCPWM_OFFSET)
+#define SYSCTL_SCGCQEI_OFFSET	0x744
+#define SYSCTL_SCGCQEI			MMIO32(SYSCTL_BASE + SYSCTL_SCGCQEI_OFFSET)
+#define SYSCTL_SCGCEEPROM_OFFSET	0x758
+#define SYSCTL_SCGCEEPROM		MMIO32(SYSCTL_BASE + SYSCTL_SCGCEEPROM_OFFSET)
+#define SYSCTL_SCGCWTIMER_OFFSET	0x75C
+#define SYSCTL_SCGCWTIMER		MMIO32(SYSCTL_BASE + SYSCTL_SCGCWTIMER_OFFSET)
 /* Peripheral deep-sleep mode clock gating control */
-#define SYSCTL_DCGCWD			MMIO32(SYSCTL_BASE + 0x800)
+#define SYSCTL_DCGCWD_OFFSET	0x800
-#define SYSCTL_DCGCTIMER		MMIO32(SYSCTL_BASE + 0x804)
+#define SYSCTL_DCGCWD			MMIO32(SYSCTL_BASE + SYSCTL_DCGCWD_OFFSET)
-#define SYSCTL_DCGCGPIO			MMIO32(SYSCTL_BASE + 0x808)
+#define SYSCTL_DCGCTIMER_OFFSET	0x804
-#define SYSCTL_DCGCDMA			MMIO32(SYSCTL_BASE + 0x80C)
+#define SYSCTL_DCGCTIMER		MMIO32(SYSCTL_BASE + SYSCTL_DCGCTIMER_OFFSET)
-#define SYSCTL_DCGCHIB			MMIO32(SYSCTL_BASE + 0x814)
+#define SYSCTL_DCGCGPIO_OFFSET	0x808
-#define SYSCTL_DCGCUART			MMIO32(SYSCTL_BASE + 0x818)
+#define SYSCTL_DCGCGPIO			MMIO32(SYSCTL_BASE + SYSCTL_DCGCGPIO_OFFSET)
-#define SYSCTL_DCGCSSI			MMIO32(SYSCTL_BASE + 0x81C)
+#define SYSCTL_DCGCDMA_OFFSET	0x80C
-#define SYSCTL_DCGCI2C			MMIO32(SYSCTL_BASE + 0x820)
+#define SYSCTL_DCGCDMA			MMIO32(SYSCTL_BASE + SYSCTL_DCGCDMA_OFFSET)
-#define SYSCTL_DCGCUSB			MMIO32(SYSCTL_BASE + 0x828)
+#define SYSCTL_DCGCHIB_OFFSET	0x814
-#define SYSCTL_DCGCCAN			MMIO32(SYSCTL_BASE + 0x834)
+#define SYSCTL_DCGCHIB			MMIO32(SYSCTL_BASE + SYSCTL_DCGCHIB_OFFSET)
-#define SYSCTL_DCGCADC			MMIO32(SYSCTL_BASE + 0x838)
+#define SYSCTL_DCGCUART_OFFSET	0x818
-#define SYSCTL_DCGCACMP			MMIO32(SYSCTL_BASE + 0x83C)
+#define SYSCTL_DCGCUART			MMIO32(SYSCTL_BASE + SYSCTL_DCGCUART_OFFSET)
-#define SYSCTL_DCGCPWM			MMIO32(SYSCTL_BASE + 0x840)
+#define SYSCTL_DCGCSSI_OFFSET	0x81C
-#define SYSCTL_DCGCQEI			MMIO32(SYSCTL_BASE + 0x844)
+#define SYSCTL_DCGCSSI			MMIO32(SYSCTL_BASE + SYSCTL_DCGCSSI_OFFSET)
-#define SYSCTL_DCGCEEPROM		MMIO32(SYSCTL_BASE + 0x858)
+#define SYSCTL_DCGCI2C_OFFSET	0x820
-#define SYSCTL_DCGCWTIMER		MMIO32(SYSCTL_BASE + 0x85C)
+#define SYSCTL_DCGCI2C			MMIO32(SYSCTL_BASE + SYSCTL_DCGCI2C_OFFSET)
+#define SYSCTL_DCGCUSB_OFFSET	0x828
+#define SYSCTL_DCGCUSB			MMIO32(SYSCTL_BASE + SYSCTL_DCGCUSB_OFFSET)
+#define SYSCTL_DCGCCAN_OFFSET	0x834
+#define SYSCTL_DCGCCAN			MMIO32(SYSCTL_BASE + SYSCTL_DCGCCAN_OFFSET)
+#define SYSCTL_DCGCADC_OFFSET	0x838
+#define SYSCTL_DCGCADC			MMIO32(SYSCTL_BASE + SYSCTL_DCGCADC_OFFSET)
+#define SYSCTL_DCGCACMP_OFFSET	0x83C
+#define SYSCTL_DCGCACMP			MMIO32(SYSCTL_BASE + SYSCTL_DCGCACMP_OFFSET)
+#define SYSCTL_DCGCPWM_OFFSET	0x840
+#define SYSCTL_DCGCPWM			MMIO32(SYSCTL_BASE + SYSCTL_DCGCPWM_OFFSET)
+#define SYSCTL_DCGCQEI_OFFSET	0x844
+#define SYSCTL_DCGCQEI			MMIO32(SYSCTL_BASE + SYSCTL_DCGCQEI_OFFSET)
+#define SYSCTL_DCGCEEPROM_OFFSET	0x858
+#define SYSCTL_DCGCEEPROM		MMIO32(SYSCTL_BASE + SYSCTL_DCGCEEPROM_OFFSET)
+#define SYSCTL_DCGCWTIMER_OFFSET	0x85C
+#define SYSCTL_DCGCWTIMER		MMIO32(SYSCTL_BASE + SYSCTL_DCGCWTIMER_OFFSET)
 /* Peripheral ready */
-#define SYSCTL_PRWD			MMIO32(SYSCTL_BASE + 0xA00)
+#define SYSCTL_PRWD_OFFSET	0xA00
-#define SYSCTL_PRTIMER			MMIO32(SYSCTL_BASE + 0xA04)
+#define SYSCTL_PRWD			MMIO32(SYSCTL_BASE + SYSCTL_PRWD_OFFSET)
-#define SYSCTL_PRGPIO			MMIO32(SYSCTL_BASE + 0xA08)
+#define SYSCTL_PRTIMER_OFFSET	0xA04
-#define SYSCTL_PRDMA			MMIO32(SYSCTL_BASE + 0xA0C)
+#define SYSCTL_PRTIMER			MMIO32(SYSCTL_BASE + SYSCTL_PRTIMER_OFFSET)
-#define SYSCTL_PRHIB			MMIO32(SYSCTL_BASE + 0xA14)
+#define SYSCTL_PRGPIO_OFFSET	0xA08
-#define SYSCTL_PRUART			MMIO32(SYSCTL_BASE + 0xA18)
+#define SYSCTL_PRGPIO			MMIO32(SYSCTL_BASE + SYSCTL_PRGPIO_OFFSET)
-#define SYSCTL_PRSSI			MMIO32(SYSCTL_BASE + 0xA1C)
+#define SYSCTL_PRDMA_OFFSET		0xA0C
-#define SYSCTL_PRI2C			MMIO32(SYSCTL_BASE + 0xA20)
+#define SYSCTL_PRDMA			MMIO32(SYSCTL_BASE + SYSCTL_PRDMA_OFFSET)
-#define SYSCTL_PRUSB			MMIO32(SYSCTL_BASE + 0xA28)
+#define SYSCTL_PRHIB_OFFSET		0xA14
-#define SYSCTL_PRCAN			MMIO32(SYSCTL_BASE + 0xA34)
+#define SYSCTL_PRHIB			MMIO32(SYSCTL_BASE + SYSCTL_PRHIB_OFFSET)
-#define SYSCTL_PRADC			MMIO32(SYSCTL_BASE + 0xA38)
+#define SYSCTL_PRUART_OFFSET	0xA18
-#define SYSCTL_PRACMP			MMIO32(SYSCTL_BASE + 0xA3C)
+#define SYSCTL_PRUART			MMIO32(SYSCTL_BASE + SYSCTL_PRUART_OFFSET)
-#define SYSCTL_PRPWM			MMIO32(SYSCTL_BASE + 0xA40)
+#define SYSCTL_PRSSI_OFFSET		0xA1C
-#define SYSCTL_PRQEI			MMIO32(SYSCTL_BASE + 0xA44)
+#define SYSCTL_PRSSI			MMIO32(SYSCTL_BASE + SYSCTL_PRSSI_OFFSET)
-#define SYSCTL_PREEPROM			MMIO32(SYSCTL_BASE + 0xA58)
+#define SYSCTL_PRI2C_OFFSET		0xA20
-#define SYSCTL_PRWTIMER			MMIO32(SYSCTL_BASE + 0xA5C)
+#define SYSCTL_PRI2C			MMIO32(SYSCTL_BASE + SYSCTL_PRI2C_OFFSET)
+#define SYSCTL_PRUSB_OFFSET		0xA28
+#define SYSCTL_PRUSB			MMIO32(SYSCTL_BASE + SYSCTL_PRUSB_OFFSET)
+#define SYSCTL_PRCAN_OFFSET		0xA34
+#define SYSCTL_PRCAN			MMIO32(SYSCTL_BASE + SYSCTL_PRCAN_OFFSET)
+#define SYSCTL_PRADC_OFFSET		0xA38
+#define SYSCTL_PRADC			MMIO32(SYSCTL_BASE + SYSCTL_PRADC_OFFSET)
+#define SYSCTL_PRACMP_OFFSET	0xA3C
+#define SYSCTL_PRACMP			MMIO32(SYSCTL_BASE + SYSCTL_PRACMP_OFFSET)
+#define SYSCTL_PRPWM_OFFSET		0xA40
+#define SYSCTL_PRPWM			MMIO32(SYSCTL_BASE + SYSCTL_PRPWM_OFFSET)
+#define SYSCTL_PRQEI_OFFSET		0xA44
+#define SYSCTL_PRQEI			MMIO32(SYSCTL_BASE + SYSCTL_PRQEI_OFFSET)
+#define SYSCTL_PREEPROM_OFFSET	0xA58
+#define SYSCTL_PREEPROM			MMIO32(SYSCTL_BASE + SYSCTL_PREEPROM_OFFSET)
+#define SYSCTL_PRWTIMER_OFFSET	0xA5C
+#define SYSCTL_PRWTIMER			MMIO32(SYSCTL_BASE + SYSCTL_PRWTIMER_OFFSET)
 /* =============================================================================
  * System Control Legacy Registers
  * ---------------------------------------------------------------------------*/
 #ifdef LM4F_LEGACY_SYSCTL
-#define SYSCTL_DC0			MMIO32(SYSCTL_BASE + 0x008)
+#define SYSCTL_DC0_OFFSET	0x008
-#define SYSCTL_DC1			MMIO32(SYSCTL_BASE + 0x010)
+#define SYSCTL_DC0			MMIO32(SYSCTL_BASE + SYSCTL_DC0_OFFSET)
-#define SYSCTL_DC2			MMIO32(SYSCTL_BASE + 0x014)
+#define SYSCTL_DC1_OFFSET	0x010
-#define SYSCTL_DC3			MMIO32(SYSCTL_BASE + 0x018)
+#define SYSCTL_DC1			MMIO32(SYSCTL_BASE + SYSCTL_DC1_OFFSET)
-#define SYSCTL_DC4			MMIO32(SYSCTL_BASE + 0x01C)
+#define SYSCTL_DC2_OFFSET	0x014
-#define SYSCTL_DC5			MMIO32(SYSCTL_BASE + 0x020)
+#define SYSCTL_DC2			MMIO32(SYSCTL_BASE + SYSCTL_DC2_OFFSET)
-#define SYSCTL_DC6			MMIO32(SYSCTL_BASE + 0x024)
+#define SYSCTL_DC3_OFFSET	0x018
-#define SYSCTL_DC7			MMIO32(SYSCTL_BASE + 0x028)
+#define SYSCTL_DC3			MMIO32(SYSCTL_BASE + SYSCTL_DC3_OFFSET)
-#define SYSCTL_DC8			MMIO32(SYSCTL_BASE + 0x02C)
+#define SYSCTL_DC4_OFFSET	0x01C
-#define SYSCTL_SRCR0			MMIO32(SYSCTL_BASE + 0x040)
+#define SYSCTL_DC4			MMIO32(SYSCTL_BASE + SYSCTL_DC4_OFFSET)
-#define SYSCTL_SRCR1			MMIO32(SYSCTL_BASE + 0x044)
+#define SYSCTL_DC5_OFFSET	0x020
-#define SYSCTL_SRCR2			MMIO32(SYSCTL_BASE + 0x048)
+#define SYSCTL_DC5			MMIO32(SYSCTL_BASE + SYSCTL_DC5_OFFSET)
-#define SYSCTL_RCGC0			MMIO32(SYSCTL_BASE + 0x100)
+#define SYSCTL_DC6_OFFSET	0x024
-#define SYSCTL_RCGC1			MMIO32(SYSCTL_BASE + 0x104)
+#define SYSCTL_DC6			MMIO32(SYSCTL_BASE + SYSCTL_DC6_OFFSET)
-#define SYSCTL_RCGC2			MMIO32(SYSCTL_BASE + 0x108)
+#define SYSCTL_DC7_OFFSET	0x028
-#define SYSCTL_SCGC0			MMIO32(SYSCTL_BASE + 0x110)
+#define SYSCTL_DC7			MMIO32(SYSCTL_BASE + SYSCTL_DC7_OFFSET)
-#define SYSCTL_SCGC1			MMIO32(SYSCTL_BASE + 0x114)
+#define SYSCTL_DC8_OFFSET	0x02C
-#define SYSCTL_SCGC2			MMIO32(SYSCTL_BASE + 0x118)
+#define SYSCTL_DC8			MMIO32(SYSCTL_BASE + SYSCTL_DC8_OFFSET)
-#define SYSCTL_DCGC0			MMIO32(SYSCTL_BASE + 0x120)
+#define SYSCTL_SRCR0_OFFSET		0x040
-#define SYSCTL_DCGC1			MMIO32(SYSCTL_BASE + 0x124)
+#define SYSCTL_SRCR0			MMIO32(SYSCTL_BASE + SYSCTL_SRCR0_OFFSET)
-#define SYSCTL_DCGC2			MMIO32(SYSCTL_BASE + 0x128)
+#define SYSCTL_SRCR1_OFFSET		0x044
-#define SYSCTL_DC9			MMIO32(SYSCTL_BASE + 0x190)
+#define SYSCTL_SRCR1			MMIO32(SYSCTL_BASE + SYSCTL_SRCR1_OFFSET)
-#define SYSCTL_NVMSTAT			MMIO32(SYSCTL_BASE + 0x1A0)
+#define SYSCTL_SRCR2_OFFSET		0x048
+#define SYSCTL_SRCR2			MMIO32(SYSCTL_BASE + SYSCTL_SRCR2_OFFSET)
+#define SYSCTL_RCGC0_OFFSET		0x100
+#define SYSCTL_RCGC0			MMIO32(SYSCTL_BASE + SYSCTL_RCGC0_OFFSET)
+#define SYSCTL_RCGC1_OFFSET		0x104
+#define SYSCTL_RCGC1			MMIO32(SYSCTL_BASE + SYSCTL_RCGC1_OFFSET)
+#define SYSCTL_RCGC2_OFFSET		0x108
+#define SYSCTL_RCGC2			MMIO32(SYSCTL_BASE + SYSCTL_RCGC2_OFFSET)
+#define SYSCTL_SCGC0_OFFSET		0x110
+#define SYSCTL_SCGC0			MMIO32(SYSCTL_BASE + SYSCTL_SCGC0_OFFSET)
+#define SYSCTL_SCGC1_OFFSET		0x114
+#define SYSCTL_SCGC1			MMIO32(SYSCTL_BASE + SYSCTL_SCGC1_OFFSET)
+#define SYSCTL_SCGC2_OFFSET		0x118
+#define SYSCTL_SCGC2			MMIO32(SYSCTL_BASE + SYSCTL_SCGC2_OFFSET)
+#define SYSCTL_DCGC0_OFFSET		0x120
+#define SYSCTL_DCGC0			MMIO32(SYSCTL_BASE + SYSCTL_DCGC0_OFFSET)
+#define SYSCTL_DCGC1_OFFSET		0x124
+#define SYSCTL_DCGC1			MMIO32(SYSCTL_BASE + SYSCTL_DCGC1_OFFSET)
+#define SYSCTL_DCGC2_OFFSET		0x128
+#define SYSCTL_DCGC2			MMIO32(SYSCTL_BASE + SYSCTL_DCGC2_OFFSET)
+#define SYSCTL_DC9_OFFSET		0x190
+#define SYSCTL_DC9			MMIO32(SYSCTL_BASE + SYSCTL_DC9_OFFSET)
+#define SYSCTL_NVMSTAT_OFFSET	0x1A0
+#define SYSCTL_NVMSTAT			MMIO32(SYSCTL_BASE + SYSCTL_NVMSTAT_OFFSET)
 #endif /* LM4F_LEGACY_SYSCTL */
 
 /* =============================================================================
@@ -490,17 +629,17 @@ enum lm4f_clken {
 	/*
 	 * Run clock control
 	 */
-	RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
+	RCC_WD0 = SYSCTL_RCGCWD_OFFSET << 5,
 	RCC_WD1,
 
-	RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
+	RCC_TIMER0 = SYSCTL_RCGCTIMER_OFFSET << 5,
 	RCC_TIMER1,
 	RCC_TIMER2,
 	RCC_TIMER3,
 	RCC_TIMER4,
 	RCC_TIMER5,
 
-	RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+	RCC_GPIOA = SYSCTL_RCGCGPIO_OFFSET << 5,
 	RCC_GPIOB,
 	RCC_GPIOC,
 	RCC_GPIOD,
@@ -516,11 +655,11 @@ enum lm4f_clken {
 	RCC_GPIOP,
 	RCC_GPIOQ,
 
-	RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
+	RCC_DMA = SYSCTL_RCGCDMA_OFFSET << 5,
 
-	RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+	RCC_HIB = SYSCTL_RCGCGPIO_OFFSET << 5,
 
-	RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
+	RCC_UART0 = SYSCTL_RCGCUART_OFFSET << 5,
 	RCC_UART1,
 	RCC_UART2,
 	RCC_UART3,
@@ -529,37 +668,37 @@ enum lm4f_clken {
 	RCC_UART6,
 	RCC_UART7,
 
-	RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
+	RCC_SSI0 = SYSCTL_RCGCSSI_OFFSET << 5,
 	RCC_SSI1,
 	RCC_SSI2,
 	RCC_SSI3,
 
-	RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
+	RCC_I2C0 = SYSCTL_RCGCI2C_OFFSET << 5,
 	RCC_I2C1,
 	RCC_I2C2,
 	RCC_I2C3,
 	RCC_I2C4,
 	RCC_I2C5,
 
-	RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
+	RCC_USB0 = SYSCTL_RCGCUSB_OFFSET << 5,
 
-	RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
+	RCC_CAN0 = SYSCTL_RCGCCAN_OFFSET << 5,
 	RCC_CAN1,
 
-	RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
+	RCC_ADC0 = SYSCTL_RCGCADC_OFFSET << 5,
 	RCC_ADC1,
 
-	RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
+	RCC_ACMP0 = SYSCTL_RCGCACMP_OFFSET << 5,
 
-	RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
+	RCC_PWM0 = SYSCTL_RCGCPWM_OFFSET << 5,
 	RCC_PWM1,
 
-	RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
+	RCC_QEI0 = SYSCTL_RCGCQEI_OFFSET << 5,
 	RCC_QEI1,
 
-	RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
+	RCC_EEPROM0 = SYSCTL_RCGCEEPROM_OFFSET << 5,
 
-	RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
+	RCC_WTIMER0 = SYSCTL_RCGCWTIMER_OFFSET << 5,
 	RCC_WTIMER1,
 	RCC_WTIMER2,
 	RCC_WTIMER3,
@@ -570,17 +709,17 @@ enum lm4f_clken {
 	/*
 	 * Sleep clock control
 	 */
-	SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
+	SCC_WD0 = SYSCTL_SCGCWD_OFFSET << 5,
 	SCC_WD1,
 
-	SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
+	SCC_TIMER0 = SYSCTL_SCGCTIMER_OFFSET << 5,
 	SCC_TIMER1,
 	SCC_TIMER2,
 	SCC_TIMER3,
 	SCC_TIMER4,
 	SCC_TIMER5,
 
-	SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+	SCC_GPIOA = SYSCTL_SCGCGPIO_OFFSET << 5,
 	SCC_GPIOB,
 	SCC_GPIOC,
 	SCC_GPIOD,
@@ -596,11 +735,11 @@ enum lm4f_clken {
 	SCC_GPIOP,
 	SCC_GPIOQ,
 
-	SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
+	SCC_DMA = SYSCTL_SCGCDMA_OFFSET << 5,
 
-	SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+	SCC_HIB = SYSCTL_SCGCGPIO_OFFSET << 5,
 
-	SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
+	SCC_UART0 = SYSCTL_SCGCUART_OFFSET << 5,
 	SCC_UART1,
 	SCC_UART2,
 	SCC_UART3,
@@ -609,37 +748,37 @@ enum lm4f_clken {
 	SCC_UART6,
 	SCC_UART7,
 
-	SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
+	SCC_SSI0 = SYSCTL_SCGCSSI_OFFSET << 5,
 	SCC_SSI1,
 	SCC_SSI2,
 	SCC_SSI3,
 
-	SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
+	SCC_I2C0 = SYSCTL_SCGCI2C_OFFSET << 5,
 	SCC_I2C1,
 	SCC_I2C2,
 	SCC_I2C3,
 	SCC_I2C4,
 	SCC_I2C5,
 
-	SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
+	SCC_USB0 = SYSCTL_SCGCUSB_OFFSET << 5,
 
-	SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
+	SCC_CAN0 = SYSCTL_SCGCCAN_OFFSET << 5,
 	SCC_CAN1,
 
-	SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
+	SCC_ADC0 = SYSCTL_SCGCADC_OFFSET << 5,
 	SCC_ADC1,
 
-	SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
+	SCC_ACMP0 = SYSCTL_SCGCACMP_OFFSET << 5,
 
-	SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
+	SCC_PWM0 = SYSCTL_SCGCPWM_OFFSET << 5,
 	SCC_PWM1,
 
-	SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
+	SCC_QEI0 = SYSCTL_SCGCQEI_OFFSET << 5,
 	SCC_QEI1,
 
-	SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
+	SCC_EEPROM0 = SYSCTL_SCGCEEPROM_OFFSET << 5,
 
-	SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
+	SCC_WTIMER0 = SYSCTL_SCGCWTIMER_OFFSET << 5,
 	SCC_WTIMER1,
 	SCC_WTIMER2,
 	SCC_WTIMER3,
@@ -649,17 +788,17 @@ enum lm4f_clken {
 	/*
 	 * Deep-sleep clock control
 	 */
-	DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
+	DCC_WD0 = SYSCTL_DCGCWD_OFFSET << 5,
 	DCC_WD1,
 
-	DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
+	DCC_TIMER0 = SYSCTL_DCGCTIMER_OFFSET << 5,
 	DCC_TIMER1,
 	DCC_TIMER2,
 	DCC_TIMER3,
 	DCC_TIMER4,
 	DCC_TIMER5,
 
-	DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+	DCC_GPIOA = SYSCTL_DCGCGPIO_OFFSET << 5,
 	DCC_GPIOB,
 	DCC_GPIOC,
 	DCC_GPIOD,
@@ -675,11 +814,11 @@ enum lm4f_clken {
 	DCC_GPIOP,
 	DCC_GPIOQ,
 
-	DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
+	DCC_DMA = SYSCTL_DCGCDMA_OFFSET << 5,
 
-	DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+	DCC_HIB = SYSCTL_DCGCGPIO_OFFSET << 5,
 
-	DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
+	DCC_UART0 = SYSCTL_DCGCUART_OFFSET << 5,
 	DCC_UART1,
 	DCC_UART2,
 	DCC_UART3,
@@ -688,37 +827,37 @@ enum lm4f_clken {
 	DCC_UART6,
 	DCC_UART7,
 
-	DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
+	DCC_SSI0 = SYSCTL_DCGCSSI_OFFSET << 5,
 	DCC_SSI1,
 	DCC_SSI2,
 	DCC_SSI3,
 
-	DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
+	DCC_I2C0 = SYSCTL_DCGCI2C_OFFSET << 5,
 	DCC_I2C1,
 	DCC_I2C2,
 	DCC_I2C3,
 	DCC_I2C4,
 	DCC_I2C5,
 
-	DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
+	DCC_USB0 = SYSCTL_DCGCUSB_OFFSET << 5,
 
-	DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
+	DCC_CAN0 = SYSCTL_DCGCCAN_OFFSET << 5,
 	DCC_CAN1,
 
-	DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
+	DCC_ADC0 = SYSCTL_DCGCADC_OFFSET << 5,
 	DCC_ADC1,
 
-	DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
+	DCC_ACMP0 = SYSCTL_DCGCACMP_OFFSET << 5,
 
-	DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
+	DCC_PWM0 = SYSCTL_DCGCPWM_OFFSET << 5,
 	DCC_PWM1,
 
-	DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
+	DCC_QEI0 = SYSCTL_DCGCQEI_OFFSET << 5,
 	DCC_QEI1,
 
-	DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
+	DCC_EEPROM0 = SYSCTL_DCGCEEPROM_OFFSET << 5,
 
-	DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
+	DCC_WTIMER0 = SYSCTL_DCGCWTIMER_OFFSET << 5,
 	DCC_WTIMER1,
 	DCC_WTIMER2,
 	DCC_WTIMER3,

include/libopencm3/lm4f/uart.h

@@ -444,8 +444,11 @@ BEGIN_DECLS
 
 void uart_set_baudrate(uint32_t uart, uint32_t baud);
 void uart_set_databits(uint32_t uart, uint8_t databits);
+uint8_t uart_get_databits(uint32_t uart);
 void uart_set_stopbits(uint32_t uart, uint8_t stopbits);
+uint8_t uart_get_stopbits(uint32_t uart);
 void uart_set_parity(uint32_t uart, enum uart_parity parity);
+enum uart_parity uart_get_parity(uint32_t uart);
 void uart_set_mode(uint32_t uart, uint32_t mode);
 void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow);
 void uart_enable(uint32_t uart);

include/libopencm3/nrf/51/clock.h

@@ -0,0 +1,56 @@
+/** @defgroup clock_defines CLOCK Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Clock control</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/clock.h>
+
+/* Clock registers */
+#define CLOCK_XTALFREQ          MMIO32(CLOCK_BASE + 0x550)
+
+#define CLOCK_PCLK              16000000
+
+enum clock_xtal_freq {
+	CLOCK_XTAL_FREQ_32MHZ,
+	CLOCK_XTAL_FREQ_16MHZ = 0xff,
+};
+
+BEGIN_DECLS
+
+void clock_set_xtal_freq(enum clock_xtal_freq freq);
+
+END_DECLS
+

include/libopencm3/nrf/51/doc-nrf51.h

@@ -0,0 +1,32 @@
+/** @page libopencm3 NRF51
+
+@version 1.0.0
+
+@date April 2020
+
+API documentation for Nordic Semiconductor NRF51 Cortex M0 series
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup peripheral_apis Peripheral APIs
+ * APIs for device peripherals
+ */
+
+/** @defgroup NRF51xx NRF51xx
+Libraries for Nordic Semiconductor NRF51xx series.
+
+@version 1.0.0
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup NRF51xx_defines NRF51xx Defines
+
+@brief Defined Constants and Types for the NRF51xx series
+
+@version 1.0.0
+
+LGPL License Terms @ref lgpl_license
+*/
+

include/libopencm3/nrf/51/ficr.h

@@ -0,0 +1,73 @@
+/** @defgroup ficr_defines FICR Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Factory information
+ * configuration registers</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/ficr.h>
+
+/* Deprecated by Nordic */
+#define FICR_CLENR0         MMIO32(FICR_BASE + 0x028)
+/* Deprecated by Nordic */
+#define FICR_PPFC           MMIO32(FICR_BASE + 0x02C)
+
+#define FICR_NUMRAMBLOCK    MMIO32(FICR_BASE + 0x034)
+#define FICR_SIZERAMBLOCKS  MMIO32(FICR_BASE + 0x038)
+
+/* Deprecated by Nordic */
+#define FICR_SIZERAMBLOCK(n)    MMIO32(FICR_BASE + 0x038 + 0x4 * (n))
+
+#define FICR_CONFIGID           MMIO32(FICR_BASE + 0x05C)
+
+#define FICR_OVERRIDEEN         MMIO32(FICR_BASE + 0x0AC)
+
+/* Override values for Nordic Semi proprietary NRF 1Mbit mode */
+#define FICR_NRF_1MBIT(n)       MMIO32(FICR_BASE + 0x0B0 + 0x4 * (n))
+#define FICR_NRF_1MBIT0         FICR_NRF_1MBIT(0)
+#define FICR_NRF_1MBIT1         FICR_NRF_1MBIT(1)
+#define FICR_NRF_1MBIT2         FICR_NRF_1MBIT(2)
+#define FICR_NRF_1MBIT3         FICR_NRF_1MBIT(3)
+#define FICR_NRF_1MBIT4         FICR_NRF_1MBIT(4)
+
+/* Override values for BLE 1Mbit mode */
+#define FICR_BLE_1MBIT(n)       MMIO32(FICR_BASE + 0x0EC + 0x4 * (n))
+#define FICR_BLE_1MBIT0         FICR_BLE_1MBIT(0)
+#define FICR_BLE_1MBIT1         FICR_BLE_1MBIT(1)
+#define FICR_BLE_1MBIT2         FICR_BLE_1MBIT(2)
+#define FICR_BLE_1MBIT3         FICR_BLE_1MBIT(3)
+#define FICR_BLE_1MBIT4         FICR_BLE_1MBIT(4)
+
+#define FICR_OVERRIDEEN_NRF_1MBIT           (1 << 0)
+#define FICR_OVERRIDEEN_BLE_1MBIT           (1 << 3)
+

include/libopencm3/nrf/51/gpio.h

@@ -0,0 +1,37 @@
+/** @defgroup gpio_defines GPIO Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx General Purpose I/O</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/nrf/common/gpio.h>
+
+

include/libopencm3/nrf/51/i2c.h

@@ -0,0 +1,40 @@
+/** @defgroup i2c_defines I2C Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx I2C</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/i2c.h>
+
+

include/libopencm3/nrf/51/irq.json

@@ -0,0 +1,33 @@
+{
+    "irqs": [
+        "power_clock",
+        "radio",
+        "uart0",
+        "spi0_twi0",
+        "spi1_twi1",
+        "reserved0",
+        "gpiote",
+        "adc",
+        "timer0",
+        "timer1",
+        "timer2",
+        "rtc0",
+        "temp",
+        "rng",
+        "ecb",
+        "ccm_aar",
+        "wdt",
+        "rtc1",
+        "qdec",
+        "lpcomp",
+        "swi0",
+        "swi1",
+        "swi2",
+        "swi3",
+        "swi4",
+        "swi5"
+    ],
+    "partname_humanreadable": "Nordic Semi NRF51 series",
+    "partname_doxygen": "NRF51",
+    "includeguard": "LIBOPENCM3_NRF51_NVIC_H"
+}

include/libopencm3/nrf/51/memorymap.h

@@ -1,6 +1,9 @@
 /*
  * This file is part of the libopencm3 project.
  *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
  * This library is free software: you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
  * the Free Software Foundation, either version 3 of the License, or
@@ -15,14 +18,9 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* Linker script for EFM32HG309F64, 64K flash, 8K RAM. */
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/common/memorymap.h>
 
-/* Define memory regions. */
-MEMORY
-{
-	rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K
-	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
-}
 
-/* Include the common ld script. */
-INCLUDE cortex-m-generic.ld

include/libopencm3/nrf/51/periph.h

@@ -1,7 +1,8 @@
 /*
  * This file is part of the libopencm3 project.
  *
- * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
  *
  * This library is free software: you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
@@ -17,16 +18,11 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* Linker script for STM32L0xx6, 32K flash, 8K RAM. */
+#pragma once
 
-/* Define memory regions. */
+#include <libopencm3/cm3/common.h>
-MEMORY
+#include <libopencm3/cm3/nvic.h>
-{
+#include <libopencm3/nrf/memorymap.h>
-	rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
-	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
-	eep (r) : ORIGIN = 0x08080000, LENGTH = 2K
-}
 
-/* Include the common ld script. */
+#include <libopencm3/nrf/common/periph.h>
-INCLUDE cortex-m-generic.ld
 

include/libopencm3/nrf/51/power.h

@@ -0,0 +1,40 @@
+/** @defgroup power_defines POWER Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Power control</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/periph.h>
+
+

include/libopencm3/nrf/51/ppi.h

@@ -0,0 +1,39 @@
+/** @defgroup ppi_defines PPI Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Programmable peripheral
+ * interconnect</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/ppi.h>
+

include/libopencm3/nrf/51/radio.h

@@ -0,0 +1,52 @@
+/** @defgroup radio_defines RADIO Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx 2.4GHz radio</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/radio.h>
+
+enum radio_mode {
+	RADIO_MODE_NRF_1MBIT,
+	RADIO_MODE_NRF_2MBIT,
+	RADIO_MODE_NRF_250KBIT,
+	RADIO_MODE_BLE_1MBIT,
+};
+
+BEGIN_DECLS
+
+void radio_set_mode(enum radio_mode mode);
+
+END_DECLS
+

include/libopencm3/nrf/51/rtc.h

@@ -0,0 +1,40 @@
+/** @defgroup rtc_defines RTC Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Realtime clock</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+
+#include <libopencm3/nrf/common/rtc.h>
+

include/libopencm3/nrf/51/timer.h

@@ -0,0 +1,40 @@
+/** @defgroup timer_defines TIMER Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx Timer</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/timer.h>
+
+

include/libopencm3/nrf/51/uart.h

@@ -0,0 +1,39 @@
+/** @defgroup uart_defines UART Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx UART</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/uart.h>
+

include/libopencm3/nrf/51/uicr.h

@@ -0,0 +1,40 @@
+/** @defgroup uicr_defines UICR Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF51xx User information configuraton
+ * registers</b>
+ *
+ * @ingroup NRF51xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/uicr.h>
+
+

include/libopencm3/nrf/52/clock.h

@@ -0,0 +1,45 @@
+/** @defgroup clock_defines CLOCK Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Clock control</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/clock.h>
+
+/* Clock registers */
+#define CLOCK_TRACECONFIG       MMIO32(CLOCK_BASE + 0x55C)
+
+#define CLOCK_PCLK              32000000
+

include/libopencm3/nrf/52/doc-nrf52.h

@@ -0,0 +1,32 @@
+/** @page libopencm3 NRF52
+
+@version 1.0.0
+
+@date November 2021
+
+API documentation for Nordic Semiconductor nRF52 Cortex M4 series
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup peripheral_apis Peripheral APIs
+ * APIs for device peripherals
+ */
+
+/** @defgroup NRF52xx NRF52xx
+Libraries for Nordic Semiconductor NRF52xx series.
+
+@version 1.0.0
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup NRF52xx_defines NRF52xx Defines
+
+@brief Defined Constants and Types for the NRF52xx series
+
+@version 1.0.0
+
+LGPL License Terms @ref lgpl_license
+*/
+

include/libopencm3/nrf/52/ficr.h

@@ -0,0 +1,39 @@
+/** @defgroup ficr_defines FICR Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Factory information
+ * configuration registers</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/ficr.h>
+

include/libopencm3/nrf/52/gpio.h

@@ -0,0 +1,37 @@
+/** @defgroup gpio_defines GPIO Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx General Purpose I/O</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/nrf/common/gpio.h>
+
+

include/libopencm3/nrf/52/i2c.h

@@ -0,0 +1,104 @@
+/** @defgroup i2c_defines I2C Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx I2C</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/i2c.h>
+
+/**@{*/
+
+#define I2C_EVENT_RXSTARTED(i2c)	MMIO32((i2c) + 0x14C)
+#define I2C_EVENT_TXSTARTED(i2c)	MMIO32((i2c) + 0x150)
+#define I2C_EVENT_LASTRX(i2c)		MMIO32((i2c) + 0x15C)
+#define I2C_EVENT_LASTTX(i2c)		MMIO32((i2c) + 0x160)
+
+#define I2C_RXDPTR(i2c)				MMIO32((i2c) + 0x534)
+#define I2C_RXDMAXCNT(i2c)			MMIO32((i2c) + 0x538)
+#define I2C_RXDAMOUNT(i2c)			MMIO32((i2c) + 0x53C)
+#define I2C_RXDLIST(i2c)			MMIO32((i2c) + 0x540)
+#define I2C_TXDPTR(i2c)				MMIO32((i2c) + 0x544)
+#define I2C_TXDMAXCNT(i2c)			MMIO32((i2c) + 0x548)
+#define I2C_TXDAMOUNT(i2c)			MMIO32((i2c) + 0x54C)
+#define I2C_TXDLIST(i2c)			MMIO32((i2c) + 0x550)
+
+/** @addtogroup i2c_shorts
+ * @{
+ */
+
+/** On start of last byte transmission, activate start of reception task */
+#define I2C_SHORTS_LASTTX_STARTRX	(1 << 7)
+
+/** On start of last byte transmission, activate suspend task */
+#define I2C_SHORTS_LASTTX_SUSPEND	(1 << 8)
+
+/** On start of last byte transmission, activate stop task */
+#define I2C_SHORTS_LASTTX_STOP		(1 << 9)
+
+/** On start of last byte reception, activate start of transmission task */
+#define I2C_SHORTS_LASTRX_STARTTX	(1 << 10)
+
+/** On start of last byte reception, activate stop task */
+#define I2C_SHORTS_LASTRX_STOP		(1 << 12)
+/** @} */
+
+/** @addtogroup i2c_inten I2C interrupt enable flags
+ * @{ */
+
+#define I2C_INTEN_SUSPENDED			(1 << 18)
+#define I2C_INTEN_RXSTARTED			(1 << 19)
+#define I2C_INTEN_TXSTARTED			(1 << 20)
+#define I2C_INTEN_LASTRX			(1 << 23)
+#define I2C_INTEN_LASTTX			(1 << 24)
+
+/** @} */
+
+/** @addtogroup i2c_mode I2C peripheral mode 
+ * @{
+ */
+
+/** NRF52 I2C Master mode with EasyDMA support */
+#define I2C_MODE_MASTER           (6)
+/**@}*/
+
+
+BEGIN_DECLS
+
+void i2c_set_tx_buffer(uint32_t i2c, const uint8_t * buffer, uint8_t len);
+void i2c_set_rx_buffer(uint32_t i2c, uint8_t * buffer, uint8_t len);
+
+END_DECLS
+
+/** @} */
+

include/libopencm3/nrf/52/irq.json

@@ -0,0 +1,35 @@
+{
+    "irqs": [
+        "power_clock",
+        "radio",
+        "uart0",
+        "spi0_twi0",
+        "spi1_twi1",
+        "reserved0",
+        "gpiote",
+        "adc",
+        "timer0",
+        "timer1",
+        "timer2",
+        "timer3",
+        "timer4",
+        "rtc0",
+        "temp",
+        "rng",
+        "ecb",
+        "ccm_aar",
+        "wdt",
+        "rtc1",
+        "qdec",
+        "lpcomp",
+        "swi0",
+        "swi1",
+        "swi2",
+        "swi3",
+        "swi4",
+        "swi5"
+    ],
+    "partname_humanreadable": "Nordic Semi NRF52 series",
+    "partname_doxygen": "NRF52",
+    "includeguard": "LIBOPENCM3_NRF52_NVIC_H"
+}

include/libopencm3/nrf/52/memorymap.h

@@ -1,7 +1,8 @@
 /*
  * This file is part of the libopencm3 project.
  *
- * Copyright (C) 2016 Daniele Lacamera <root@danielinux.net>
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
  *
  * This library is free software: you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
@@ -17,15 +18,11 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* Linker script for the LM3S6965 chip (256K flash, 64K RAM). */
+#pragma once
 
-/* Define memory regions. */
+#include <libopencm3/cm3/common.h>
-MEMORY
+#include <libopencm3/nrf/common/memorymap.h>
-{
-	rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
-	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
-}
 
-/* Include the common ld script. */
+#define TIMER3_BASE			(APB_BASE + 0x1A000)
-INCLUDE cortex-m-generic.ld
+#define TIMER4_BASE			(APB_BASE + 0x1B000)
 

include/libopencm3/nrf/52/periph.h

@@ -1,7 +1,8 @@
 /*
  * This file is part of the libopencm3 project.
  *
- * Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
  *
  * This library is free software: you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
@@ -17,15 +18,11 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/* Linker script for STM32F03xz6, 32k flash, 4k RAM. */
+#pragma once
 
-/* Define memory regions. */
+#include <libopencm3/cm3/common.h>
-MEMORY
+#include <libopencm3/cm3/nvic.h>
-{
+#include <libopencm3/nrf/memorymap.h>
-	rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
-	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
-}
 
-/* Include the common ld script. */
+#include <libopencm3/nrf/common/periph.h>
-INCLUDE cortex-m-generic.ld
 

include/libopencm3/nrf/52/power.h

@@ -0,0 +1,40 @@
+/** @defgroup power_defines POWER Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Power control</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/periph.h>
+
+

include/libopencm3/nrf/52/ppi.h

@@ -0,0 +1,39 @@
+/** @defgroup ppi_defines PPI Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Programmable peripheral
+ * interconnect</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/ppi.h>
+

include/libopencm3/nrf/52/radio.h

@@ -0,0 +1,40 @@
+/** @defgroup radio_defines RADIO Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx 2.4GHz radio</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/radio.h>
+
+

include/libopencm3/nrf/52/rtc.h

@@ -0,0 +1,40 @@
+/** @defgroup rtc_defines RTC Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Realtime clock</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+
+#include <libopencm3/nrf/common/rtc.h>
+

include/libopencm3/nrf/52/timer.h

@@ -0,0 +1,51 @@
+/** @defgroup timer_defines TIMER Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx Timer</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/timer.h>
+
+/**@{*/
+/* Timer/Counter */
+/** @addtogroup timer_block TIMER instances
+ * @{
+ */
+#define TIMER4			TIMER4_BASE
+#define TIMER3			TIMER3_BASE
+
+/**@}*/
+
+/**@}*/
+

include/libopencm3/nrf/52/uart.h

@@ -0,0 +1,39 @@
+/** @defgroup uart_defines UART Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx UART</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+#include <libopencm3/nrf/common/uart.h>
+

include/libopencm3/nrf/52/uicr.h

@@ -0,0 +1,40 @@
+/** @defgroup uicr_defines UICR Defines
+ *
+ * @brief <b>Defined Constants and Types for the NRF52xx User information configuraton
+ * registers</b>
+ *
+ * @ingroup NRF52xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date Nov 2021
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/common/uicr.h>
+
+

include/libopencm3/nrf/clock.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/clock.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/clock.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/common/clock.h

@@ -0,0 +1,98 @@
+/** @addtogroup clock_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+/**@{*/
+
+/* Clock tasks */
+#define CLOCK_TASK_HFCLKSTART       MMIO32(CLOCK_BASE + 0x000)
+#define CLOCK_TASK_HFCLKSTOP        MMIO32(CLOCK_BASE + 0x004)
+#define CLOCK_TASK_LFCLKSTART       MMIO32(CLOCK_BASE + 0x008)
+#define CLOCK_TASK_LFCLKSTOP        MMIO32(CLOCK_BASE + 0x00C)
+#define CLOCK_TASK_CAL              MMIO32(CLOCK_BASE + 0x010)
+#define CLOCK_TASK_CTSTART          MMIO32(CLOCK_BASE + 0x014)
+#define CLOCK_TASK_CTSTOP           MMIO32(CLOCK_BASE + 0x018)
+
+/* Clock events */
+#define CLOCK_EVENT_HFCLKSTARTED    MMIO32(CLOCK_BASE + 0x100)
+#define CLOCK_EVENT_LFCLKSTARTED    MMIO32(CLOCK_BASE + 0x104)
+#define CLOCK_EVENT_DONE            MMIO32(CLOCK_BASE + 0x10C)
+#define CLOCK_EVENT_CTTO            MMIO32(CLOCK_BASE + 0x110)
+
+/* Clock registers */
+#define CLOCK_INTENSET              MMIO32(CLOCK_BASE + 0x304)
+#define CLOCK_INTENCLR              MMIO32(CLOCK_BASE + 0x308)
+#define CLOCK_HFCLKRUN              MMIO32(CLOCK_BASE + 0x408)
+#define CLOCK_HFCLKSTAT             MMIO32(CLOCK_BASE + 0x40C)
+#define CLOCK_LFCLKRUN              MMIO32(CLOCK_BASE + 0x414)
+#define CLOCK_LFCLKSTAT             MMIO32(CLOCK_BASE + 0x418)
+#define CLOCK_LFCLKSRCCOPY          MMIO32(CLOCK_BASE + 0x41C)
+#define CLOCK_LFCLKSRC              MMIO32(CLOCK_BASE + 0x518)
+#define CLOCK_CTIV                  MMIO32(CLOCK_BASE + 0x538)
+
+/* Register contents */
+#define CLOCK_INTEN_HFCLKSTARTED    (1 << 0)
+#define CLOCK_INTEN_LFCLKSTARTED    (1 << 1)
+#define CLOCK_INTEN_DONE            (1 << 3)
+#define CLOCK_INTEN_CTTO            (1 << 4)
+
+#define CLOCK_HFCLKRUN_STATUS       (1 << 0)
+
+#define CLOCK_HFCLKSTAT_SRC         (1 << 0)
+#define CLOCK_HFCLKSTAT_STATE       (1 << 16)
+
+#define CLOCK_LFCLKRUN_STATUS       (1 << 0)
+
+#define CLOCK_LFCLK_SRC_SHIFT       (0)
+#define CLOCK_LFCLK_SRC_MASK        (3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+#define CLOCK_LFCLK_SRC_MASKED(V)   (((V) << CLOCK_LFCLKSTAT_SRC_SHIFT) & CLOCK_LFCLKSTAT_SRC_MASK)
+
+#define CLOCK_LFCLKSTAT_STATE       (1 << 16)
+
+enum clock_lfclk_src {
+	CLOCK_LFCLK_SRC_RC,
+	CLOCK_LFCLK_SRC_XTAL,
+	CLOCK_LFCLK_SRC_SYNTH,
+};
+/**@}*/
+
+BEGIN_DECLS
+
+void clock_start_lfclk(bool wait);
+void clock_stop_lfclk(void);
+void clock_start_hfclk(bool wait);
+void clock_stop_hfclk(void);
+void clock_set_lfclk_src(enum clock_lfclk_src lfclk_src);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/ficr.h

@@ -0,0 +1,52 @@
+/** @addtogroup ficr_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+/**@{*/
+
+/* Factory Information Configuration Register */
+
+#define FICR_CODEPAGESIZE   MMIO32(FICR_BASE + 0x010)
+#define FICR_CODESIZE       MMIO32(FICR_BASE + 0x014)
+
+#define FICR_DEVICEID0          MMIO32(FICR_BASE + 0x060)
+#define FICR_DEVICEID1          MMIO32(FICR_BASE + 0x064)
+
+/* Encryption Root */
+#define FICR_ER(n)          MMIO32(FICR_BASE + 0x080 + 0x4 * (n))
+/* Identity Root */
+#define FICR_IR(n)          MMIO32(FICR_BASE + 0x090 + 0x4 * (n))
+#define FICR_DEVICEADDRTYPE         MMIO32(FICR_BASE + 0x0A0)
+#define FICR_DEVICEADDR0            MMIO32(FICR_BASE + 0x0A4)
+#define FICR_DEVICEADDR1            MMIO32(FICR_BASE + 0x0A8)
+
+
+/**@}*/
+

include/libopencm3/nrf/common/gpio.h

@@ -0,0 +1,236 @@
+/** @addtogroup gpio_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+/**@{*/
+
+/** @addtogroup gpio_port_id GPIO ports
+ * @{
+ */
+/** GPIO port */
+#define GPIO				(GPIO_BASE)
+
+/**@}*/
+
+#define GPIO_OUT			MMIO32(GPIO_BASE + 0x504)
+#define GPIO_OUTSET		MMIO32(GPIO_BASE + 0x508)
+#define GPIO_OUTCLR		MMIO32(GPIO_BASE + 0x50C)
+
+#define GPIO_IN			MMIO32(GPIO_BASE + 0x510)
+
+#define GPIO_DIR			MMIO32(GPIO_BASE + 0x514)
+#define GPIO_DIRSET		MMIO32(GPIO_BASE + 0x518)
+#define GPIO_DIRCLR		MMIO32(GPIO_BASE + 0x51C)
+
+#define GPIO_PIN_CNF(N)	MMIO32(GPIO_BASE + 0x700 + 0x4 * (N))
+
+
+/* Pin mode (CPIO_CNF[1:0] - combines direction and analog/digital */
+
+#define GPIO_CNF_MODE_MASK			2
+#define GPIO_CNF_MODE_SHIFT			0
+
+/* Pin mode (MODE[1:0]) values */
+/** @defgroup gpio_mode GPIO Pin Mode
+@ingroup gpio_defines
+@{*/
+#define GPIO_MODE_INPUT				0
+#define GPIO_MODE_OUTPUT			1
+#define GPIO_MODE_ANALOG			2
+/**@}*/
+
+#define GPIO_CNF_PUPD_MASK			2
+#define GPIO_CNF_PUPD_SHIFT			2
+
+/** @defgroup gpio_pupd GPIO Output Pin Pullup
+@ingroup gpio_defines
+@{*/
+#define GPIO_PUPD_NONE		0x0
+#define GPIO_PUPD_PULLDOWN	0x1
+#define GPIO_PUPD_PULLUP		0x2
+/**@}*/
+
+#define GPIO_CNF_DRIVE_SHIFT		8
+#define GPIO_CNF_DRIVE_MASK			7
+
+/** @addtogroup gpio_drive GPIO drive configuration
+ * @{ */
+
+/** Standard 0, standard 1 */
+#define GPIO_CNF_DRIVE_S0S1					0
+
+/** High drive 0, standard 1 */
+#define GPIO_CNF_DRIVE_H0S1					1
+
+/** Standard 0, high drive 1 */
+#define GPIO_CNF_DRIVE_S0H1					2
+
+/** High drive 0, high drive 1 */
+#define GPIO_CNF_DRIVE_H0H1					3
+
+/** Disconnect 0, standard 1 (wired-or connections) */
+#define GPIO_CNF_DRIVE_D0S1					4
+
+/** Disconnect 0, high drive 1 (wired-or connections) */
+#define GPIO_CNF_DRIVE_D0H1					5
+
+/** Standard 0, disconnect 1 (wired-and connections) */
+#define GPIO_CNF_DRIVE_S0D1					6
+
+/** High drive 0, disconnect 1 (wired-and connections) */
+#define GPIO_CNF_DRIVE_H0D1					7
+
+/**@}*/
+
+#define GPIO_CNF_SENSE_SHIFT				16
+#define GPIO_CNF_SENSE_MASK					3
+
+/** @addtogroup gpio_sense GPIO sensing mechanism
+ * @{ */
+
+/** Pin sensing is disabled */
+#define GPIO_CNF_SENSE_DISABLE				0
+
+/** Pin sensing is active for high level */
+#define GPIO_CNF_SENSE_HIGH					2
+
+/** Pin sensing is active for low level */
+#define GPIO_CNF_SENSE_LOW					3
+
+/**@}*/
+
+/* GPIO Tasks and Events (GPIOTE) */
+#define GPIO_TASK_OUT(n)				MMIO32(GPIOTE_BASE + 0x4 * (n))
+#define GPIO_EVENT_IN(n)				MMIO32(GPIOTE_BASE + 0x100 + 0x4 * (n))
+
+#define GPIO_EVENT_PORT					MMIO32(GPIOTE_BASE + 0x17C)
+
+#define GPIO_INTEN						MMIO32(GPIOTE_BASE + 0x300)
+#define GPIO_INTENSET					MMIO32(GPIOTE_BASE + 0x304)
+#define GPIO_INTENCLR					MMIO32(GPIOTE_BASE + 0x308)
+
+#define GPIO_TE_CONFIG(n)				MMIO32(GPIOTE_BASE + 0x510 + 0x4 * (n))
+
+/* Register Details */
+#define GPIO_INTEN_IN(n)					(1 << (n))
+
+#define GPIO_INTEN_PORT						(1 << 31)
+
+/* TODO: clean this up */
+
+#define GPIO_TE_CONFIG_MODE_SHIFT			0
+#define GPIO_TE_CONFIG_MODE_MASK			3
+
+#define GPIO_TE_CONFIG_PSEL_SHIFT			8
+#define GPIO_TE_CONFIG_PSEL_MASK			0x1f
+
+#define GPIO_TE_CONFIG_POLARITY_SHIFT		16
+#define GPIO_TE_CONFIG_POLARITY_MASK		3
+
+#define GPIO_TE_CONFIG_OUTINIT				(1 << 20)
+
+#define GPIO_TE_MODE_DISABLED				0
+#define GPIO_TE_MODE_EVENT					1
+#define GPIO_TE_MODE_TASK					3
+
+#define GPIO_TE_POLARITY_NONE				0
+#define GPIO_TE_POLARITY_LO_TO_HI			1
+#define GPIO_TE_POLARITY_HI_TO_LO			2
+#define GPIO_TE_POLARITY_TOGGLE				3
+
+#define GPIO_TE_OUTINIT_LOW					0
+#define GPIO_TE_OUTINIT_HIGH				1
+
+/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup gpio_defines
+
+@{*/
+#define GPIO0								(1 << 0)
+#define GPIO1								(1 << 1)
+#define GPIO2								(1 << 2)
+#define GPIO3								(1 << 3)
+#define GPIO4								(1 << 4)
+#define GPIO5								(1 << 5)
+#define GPIO6								(1 << 6)
+#define GPIO7								(1 << 7)
+#define GPIO8								(1 << 8)
+#define GPIO9								(1 << 9)
+#define GPIO10								(1 << 10)
+#define GPIO11								(1 << 11)
+#define GPIO12								(1 << 12)
+#define GPIO13								(1 << 13)
+#define GPIO14								(1 << 14)
+#define GPIO15								(1 << 15)
+#define GPIO16								(1 << 16)
+#define GPIO17								(1 << 17)
+#define GPIO18								(1 << 18)
+#define GPIO19								(1 << 19)
+#define GPIO20								(1 << 20)
+#define GPIO21								(1 << 21)
+#define GPIO22								(1 << 22)
+#define GPIO23								(1 << 23)
+#define GPIO24								(1 << 24)
+#define GPIO25								(1 << 25)
+#define GPIO26								(1 << 26)
+#define GPIO27								(1 << 27)
+#define GPIO28								(1 << 28)
+#define GPIO29								(1 << 29)
+#define GPIO30								(1 << 30)
+#define GPIO31								(1 << 31)
+#define GPIO_ALL							0xffffffff
+/**@}*/
+
+/**@}*/
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpioport, uint32_t gpios);
+void gpio_clear(uint32_t gpioport, uint32_t gpios);
+uint32_t gpio_get(uint32_t gpioport, uint32_t gpios);
+void gpio_toggle(uint32_t gpioport, uint32_t gpios);
+
+void gpio_mode_setup(uint32_t gpioport, uint32_t mode, uint32_t pull_up_down,
+		uint32_t gpios);
+
+void gpio_set_options(uint32_t gpioport, uint32_t drive, uint32_t sense,
+		uint32_t gpios);
+
+void gpio_configure_task(uint8_t task_num,
+		uint8_t pin_num, uint8_t polarity, uint32_t init);
+
+void gpio_configure_event(uint8_t event_num, uint8_t pin_num, uint8_t polarity);
+
+void gpio_enable_interrupts(uint32_t mask);
+void gpio_disable_interrupts(uint32_t mask);
+void gpio_clear_interrupts(void);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/i2c.h

@@ -0,0 +1,162 @@
+/** @addtogroup i2c_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+/**@{*/
+
+/* I2C bus */
+/** @addtogroup i2c_block I2C instances
+ * @{
+ */
+
+#define I2C0            I2C0_BASE
+#define I2C1            I2C1_BASE
+
+/**@}*/
+
+/* Tasks */
+
+#define I2C_TASK_STARTRX(i2c)      MMIO32((i2c) + 0x000)
+#define I2C_TASK_STARTTX(i2c)      MMIO32((i2c) + 0x008)
+#define I2C_TASK_STOP(i2c)         MMIO32((i2c) + 0x014)
+#define I2C_TASK_SUSPEND(i2c)      MMIO32((i2c) + 0x01c)
+#define I2C_TASK_RESUME(i2c)       MMIO32((i2c) + 0x020)
+/* Events */
+
+#define I2C_EVENT_STOPPED(i2c)     MMIO32((i2c) + 0x104)
+#define I2C_EVENT_RXDREADY(i2c)    MMIO32((i2c) + 0x108)
+#define I2C_EVENT_TXDSENT(i2c)     MMIO32((i2c) + 0x11c)
+#define I2C_EVENT_ERROR(i2c)       MMIO32((i2c) + 0x124)
+#define I2C_EVENT_BB(i2c)          MMIO32((i2c) + 0x138)
+#define I2C_EVENT_SUSPENDED(i2c)   MMIO32((i2c) + 0x148)
+/* Registers */
+
+#define I2C_SHORTS(i2c)            MMIO32((i2c) + 0x200)
+#define I2C_INTEN(i2c)             MMIO32((i2c) + 0x300)
+#define I2C_INTENSET(i2c)          MMIO32((i2c) + 0x304)
+#define I2C_INTENCLR(i2c)          MMIO32((i2c) + 0x308)
+#define I2C_ERRORSRC(i2c)          MMIO32((i2c) + 0x4c4)
+#define I2C_ENABLE(i2c)            MMIO32((i2c) + 0x500)
+#define I2C_PSELSCL(i2c)           MMIO32((i2c) + 0x508)
+#define I2C_PSELSDA(i2c)           MMIO32((i2c) + 0x50c)
+#define I2C_RXD(i2c)               MMIO32((i2c) + 0x518)
+#define I2C_TXD(i2c)               MMIO32((i2c) + 0x51c)
+#define I2C_FREQUENCY(i2c)         MMIO32((i2c) + 0x524)
+#define I2C_ADDRESS(i2c)           MMIO32((i2c) + 0x588)
+
+/* Register Contents */
+
+/** @addtogroup i2c_shorts I2C event -> task shortcuts
+ * The effect of activated shortcut is, that upon I2C event
+ * triggering, the hardware will automatically start chosen
+ * task without intervention of the software.
+ * @{
+ */
+
+/** On byte boundary, activate suspend task. */
+#define I2C_SHORTS_BB_SUSPEND      (1 << 0)
+
+/** On byte boundary, activate stop task. */
+#define I2C_SHORTS_BB_STOP         (1 << 1)
+
+/**@}*/
+
+/** @addtogroup i2c_interrupts I2C interrupts
+ * @{
+ */
+#define I2C_INTEN_STOPPED          (1 << 1)
+#define I2C_INTEN_RXDREADY         (1 << 2)
+#define I2C_INTEN_TXDSENT          (1 << 7)
+#define I2C_INTEN_ERROR            (1 << 9)
+#define I2C_INTEN_BB               (1 << 14)
+
+/**@}*/
+
+#define I2C_ERRORSRC_OVERRUN       (1 << 0)
+#define I2C_ERRORSRC_ANACK         (1 << 1)
+#define I2C_ERRORSRC_DNACK         (1 << 2)
+
+/** @addtogroup i2c_mode I2C peripheral mode 
+ * @{
+ */
+/** NRF51 legacy mode. 
+ * On NRF51, this is the only mode available.
+ * On NRF52, this mode does not support EasyDMA.
+ */
+#define I2C_MODE_LEGACY           (5)
+/**@}*/
+
+/** @addtogroup i2c_freq_const I2C frequency constants
+ * @{
+ */
+
+/** 100kHz */
+#define I2C_FREQUENCY_100K         (0x01980000)
+/** 250kHz */
+#define I2C_FREQUENCY_250K         (0x04000000)
+/** 390kHz
+ * @note: This value is not documented in datasheet. It provides
+ * ~390kHz clock with correct timing.
+ */
+#define I2C_FREQUENCY_390K         (0x06200000)
+/** 400kHz
+ * @note: According to datasheet, there is HW bug which prevents
+ * MCU from generating correct timings, therefore it might be
+ * unusable. Use @ref I2C_FREQUENCY_390K instead, if this affects
+ * you.
+ */
+#define I2C_FREQUENCY_400K         (0x06680000)
+/**@}*/
+
+#define I2C_PSEL_OFF               (0xffffffff)
+
+/**@}*/
+
+BEGIN_DECLS
+
+void i2c_enable(uint32_t i2c, uint32_t mode);
+void i2c_disable(uint32_t i2c);
+void i2c_start_tx(uint32_t i2c);
+void i2c_start_rx(uint32_t i2c);
+void i2c_send_stop(uint32_t i2c);
+void i2c_set_fast_mode(uint32_t i2c);
+void i2c_set_standard_mode(uint32_t i2c);
+void i2c_set_frequency(uint32_t i2c, uint32_t freq);
+void i2c_send_data(uint32_t i2c, uint8_t data);
+uint8_t i2c_get_data(uint32_t i2c);
+void i2c_select_pins(uint32_t i2c, uint32_t scl_pin, uint32_t sda_pin);
+void i2c_set_address(uint32_t i2c, uint8_t addr);
+void i2c_resume(uint32_t i2c);
+void i2c_set_shorts(uint32_t i2c, uint32_t shorts);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/memorymap.h

@@ -0,0 +1,97 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+
+/* Factory Information Configuration Registers */
+#define FICR_BASE			(0x10000000U)
+
+/* User Information Configuration Registers */
+#define UICR_BASE			(0x10001000U)
+
+#define APB_BASE			(0x40000000U)
+#define AHB_BASE			(0x50000000U)
+#define PPB_BASE			(0xE0000000U)
+
+
+#define CLOCK_BASE			(APB_BASE)
+
+/* Power Control */
+#define POWER_BASE			(APB_BASE)
+
+/* 2.4 GHz Radio */
+#define RADIO_BASE			(APB_BASE + 0x1000)
+
+#define UART0_BASE			(APB_BASE + 0x2000)
+
+#define SPI0_BASE			(APB_BASE + 0x3000)
+#define TWI0_BASE			(APB_BASE + 0x3000)
+#define I2C0_BASE			(APB_BASE + 0x3000)
+
+#define SPI1_BASE			(APB_BASE + 0x4000)
+#define SPIS1_BASE			(APB_BASE + 0x4000)
+#define TWI1_BASE			(APB_BASE + 0x4000)
+#define I2C1_BASE			(APB_BASE + 0x4000)
+
+#define GPIOTE_BASE			(APB_BASE + 0x6000)
+
+#define ADC_BASE			(APB_BASE + 0x7000)
+
+#define TIMER0_BASE			(APB_BASE + 0x8000)
+#define TIMER1_BASE			(APB_BASE + 0x9000)
+#define TIMER2_BASE			(APB_BASE + 0xA000)
+
+#define RTC0_BASE			(APB_BASE + 0xB000)
+
+#define TEMP_BASE			(APB_BASE + 0xC000)
+
+#define RNG_BASE			(APB_BASE + 0xD000)
+
+/* AES ECB Mode Encryption */
+#define ECB_BASE			(APB_BASE + 0xE000)
+
+/* Accelerated Address Resolver */
+#define AAR_BASE			(APB_BASE + 0xF000)
+
+/* AES CCM Mode Encryption */
+#define CCM_BASE			(APB_BASE + 0xF000)
+
+#define WDT_BASE			(APB_BASE + 0x10000)
+#define RTC1_BASE			(APB_BASE + 0x11000)
+#define QDEC_BASE			(APB_BASE + 0x12000)
+#define LPCOMP_BASE			(APB_BASE + 0x13000)
+#define SWI0_BASE			(APB_BASE + 0x14000)
+#define SWI1_BASE			(APB_BASE + 0x15000)
+#define SWI2_BASE			(APB_BASE + 0x16000)
+#define SWI3_BASE			(APB_BASE + 0x17000)
+#define SWI4_BASE			(APB_BASE + 0x18000)
+#define SWI5_BASE			(APB_BASE + 0x19000)
+
+/* Non-Volatile Memory Controller */
+#define NVMC_BASE			(APB_BASE + 0x1E000)
+#define PPI_BASE			(APB_BASE + 0x1F000)
+#define RTC2_BASE			(APB_BASE + 0x24000)
+
+#define GPIO_BASE			(AHB_BASE)
+
+#define NVMC_BASE			(APB_BASE + 0x1E000)
+

include/libopencm3/nrf/common/periph.h

@@ -0,0 +1,148 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/nrf/memorymap.h>
+
+/* Common Peripheral Interface.
+ * The implementation only applies to peripherals on APB
+ * bus, which for this part excludes only GPIO.
+ */
+
+/* Peripheral IDs
+ *
+ * For peripherals on the APB bus there is a direct relationship between its ID
+ * and its base address. A peripheral with base address 0x40000000 is therefore
+ * assigned ID=0, and a peripheral with base address 0x40001000 is assigned
+ * ID=1. The peripheral with base address 0x4001F000 is assigned ID=31
+ */
+
+#define PERIPH_CLOCK_ID            (0x00)
+#define PERIPH_POWER_ID            (0x00)
+#define PERIPH_MPU_ID              (0x00)
+#define PERIPH_RADIO_ID            (0x01)
+#define PERIPH_UART_ID             (0x02)
+#define PERIPH_SPI0_ID             (0x03)
+#define PERIPH_TWI0_ID             (0x03)
+#define PERIPH_I2C0_ID             (0x03)
+#define PERIPH_SPI1_ID             (0x04)
+#define PERIPH_SPIS1_ID            (0x04)
+#define PERIPH_TWI1_ID             (0x04)
+#define PERIPH_I2C1_ID             (0x04)
+#define PERIPH_GPIOTE_ID           (0x06)
+#define PERIPH_ADC_ID              (0x07)
+#define PERIPH_TIMER0_ID           (0x08)
+#define PERIPH_TIMER1_ID           (0x09)
+#define PERIPH_TIMER2_ID           (0x0a)
+#define PERIPH_RTC0_ID             (0x0b)
+#define PERIPH_TEMP_ID             (0x0c)
+#define PERIPH_RNG_ID              (0x0d)
+#define PERIPH_ECB_ID              (0x0e)
+#define PERIPH_AAR_ID              (0x0f)
+#define PERIPH_CCM_ID              (0x0f)
+#define PERIPH_WDT_ID              (0x10)
+#define PERIPH_RTC1_ID             (0x11)
+#define PERIPH_QDEC_ID             (0x12)
+#define PERIPH_LPCOMP_ID           (0x13)
+#define PERIPH_SWI0_ID             (0x14)
+#define PERIPH_SWI1_ID             (0x15)
+#define PERIPH_SWI2_ID             (0x16)
+#define PERIPH_SWI3_ID             (0x17)
+#define PERIPH_SWI4_ID             (0x18)
+#define PERIPH_SWI5_ID             (0x19)
+#define PERIPH_NVMC_ID             (0x1e)
+#define PERIPH_PPI_ID              (0x1f)
+
+#define PERIPH_BASE_FROM_ID(periph_id)       (ABP_BASE + 0x1000 * (periph_id))
+#define PERIPH_ID_FROM_BASE(base)            (((base) - APB_BASE) >> 12)
+#define PERIPH_BASE_FROM_REG(reg)            (((uint32_t) &(reg)) & 0xfffff000)
+
+/*
+ * Tasks are used to trigger actions in a peripheral, for example, to start a
+ * particular behavior. A peripheral can implement multiple tasks with each
+ * task having a separate register in that peripheral's task register group.
+ *
+ * A task is triggered when firmware writes a '1' to the task register or when
+ * the peripheral itself, or another peripheral, toggles the corresponding task
+ * signal.
+ */
+
+/** Starting address of all the tasks in the peripheral. */
+#define PERIPH_TASK_OFFSET         (0x000)
+
+/*
+ * Events are used to notify peripherals and the CPU about events that have
+ * happened, for example, a state change in a peripheral. A peripheral may
+ * generate multiple events with each event having a separate register in that
+ * peripheral’s event register group.  An event is generated when the
+ * peripheral itself toggles the corresponding event signal, whereupon the
+ * event register is updated to reflect that the event has been generated.
+ */
+
+/** Starting address of all the events in the peripheral. */
+#define PERIPH_EVENT_OFFSET        (0x100)
+
+#define PERIPH_TRIGGER_TASK(task)  (task) = (1)
+
+/* All peripherals on the APB bus support interrupts. A peripheral only
+ * occupies one interrupt, and the interrupt number follows the peripheral ID,
+ * for example, the peripheral with ID=4 is connected to interrupt number 4 in
+ * the Nested Vector Interrupt Controller (NVIC).
+ */
+
+#define PERIPH_ENABLE_IRQ(base)    nvic_enable_irq(periph_id_from_base(base))
+#define PERIPH_DISABLE_IRQ(base)   nvic_disable_irq(periph_id_from_base(base))
+
+/* Common regisgers. Not all peripherals have these registers, but when they
+ * are present, they are at this offset.
+ */
+#define PERIPH_SHORTS_OFFSET       (0x200)
+#define PERIPH_INTEN_OFFSET        (0x300)
+#define PERIPH_INTENSET_OFFSET     (0x304)
+#define PERIPH_INTENCLR_OFFSET     (0x308)
+
+#define _PERIPH_SHORTS(base)        MMIO32((base) + PERIPH_SHORTS_OFFSET)
+#define _PERIPH_INTEN(base)         MMIO32((base) + PERIPH_INTEN_OFFSET)
+#define _PERIPH_INTENSET(base)      MMIO32((base) + PERIPH_INTENSET_OFFSET)
+#define _PERIPH_INTENCLR(base)      MMIO32((base) + PERIPH_INTENCLR_OFFSET)
+
+/* TODO: convert these to functions */
+#define periph_enable_shorts(base, shorts)    periph_shorts(base) |= (shorts)
+#define periph_disable_shorts(base, shorts)   periph_shorts(base) &= (~(shorts))
+#define periph_clear_shorts(base)             periph_shorts(base) = (0)
+
+#define periph_enable_interrupts(base, mask)     periph_intenset(base) |= (mask)
+#define periph_disable_interrupts(base, mask)    periph_intenclr(base) = (mask)
+#define periph_clear_interrupts(base)            periph_intenclr(base) = (0xffffffff)
+
+/** Mark the signal as not connected to any pin. */
+#define GPIO_UNCONNECTED		0xFFFFFFFFU
+
+/** This is an approximation of log2. As used here, works correctly
+ * only for single bit set, which should be the case when used to.
+ * convert above GPIOxy macros to pin numbers as needed for PSEL
+ * registers of peripherals.
+ */
+#define __GPIO2PIN(x)			(31 - __builtin_clz((uint32_t) (x)))
+
+

include/libopencm3/nrf/common/power.h

@@ -0,0 +1,106 @@
+/** @addtogroup power_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+/**@{*/
+
+/* Tasks */
+#define POWER_TASK_CONSTLAT			MMIO32(POWER_BASE + 0x078)
+#define POWER_TASK_LOWPWR			MMIO32(POWER_BASE + 0x07C)
+
+/* Events */
+#define POWER_EVENT_POFWARN			MMIO32(POWER_BASE + 0x108)
+
+/* Registers */
+#define POWER_INTENSET			_PERIPH_INTENSET(POWER_BASE)
+#define POWER_INTENCLR			_PERIPH_INTENCLR(POWER_BASE)
+#define POWER_RESETREAS			MMIO32(POWER_BASE + 0x400)
+#define POWER_RAMSTATUS			MMIO32(POWER_BASE + 0x428)
+#define POWER_SYSTEMOFF			MMIO32(POWER_BASE + 0x500)
+#define POWER_POFCON			MMIO32(POWER_BASE + 0x510)
+#define POWER_GPREGRET			MMIO32(POWER_BASE + 0x51C)
+#define POWER_RAMON			MMIO32(POWER_BASE + 0x524)
+#define POWER_RESET			MMIO32(POWER_BASE + 0x544)
+#define POWER_RAMONB			MMIO32(POWER_BASE + 0x554)
+#define POWER_DCDCEN			MMIO32(POWER_BASE + 0x578)
+
+/* Register Contents */
+#define POWER_INTEN_POFWARN			(1 << 2)
+
+#define POWER_RESETREAS_RESETPIN			(1 << 0)
+#define POWER_RESETREAS_DOG			(1 << 1)
+#define POWER_RESETREAS_SREQ			(1 << 2)
+#define POWER_RESETREAS_LOCKUP			(1 << 3)
+
+#define POWER_RESETREAS_OFF	(1 << 16)
+#define POWER_RESETREAS_LPCOMP	(1 << 17)
+#define POWER_RESETREAS_DIF	(1 << 18)
+
+#define POWER_RAMSTATUS_RAMBLOCK(n)			(1 << (n))
+#define POWER_RAMSTATUS_RAMBLOCK0			POWER_RAMSTATUS_RAMBLOCK(0)
+#define POWER_RAMSTATUS_RAMBLOCK1			POWER_RAMSTATUS_RAMBLOCK(1)
+#define POWER_RAMSTATUS_RAMBLOCK2			POWER_RAMSTATUS_RAMBLOCK(2)
+#define POWER_RAMSTATUS_RAMBLOCK3			POWER_RAMSTATUS_RAMBLOCK(3)
+
+#define POWER_SYSTEMOFF_SYSTEMOFF			(1 << 0)
+
+#define POWER_POFCON_POF			(1 << 0)
+#define POWER_POFCON_THRESHOLD_SHIFT			(1)
+#define POWER_POFCON_THRESHOLD_MASK			(3 << POWER_POFCON_THRESHOLD_SHIFT)
+#define POWER_POFCON_THRESHOLD_MASKED(V)	(((V) << POWER_POFCON_THRESHOLD_SHIFT) \
+		& POWER_POFCON_THRESHOLD_MASK)
+
+#define POWER_RAMON_ONRAM0			(1 << 0)
+#define POWER_RAMON_ONRAM1			(1 << 1)
+
+#define POWER_RAMON_OFFRAM0			(1 << 16)
+#define POWER_RAMON_OFFRAM1			(1 << 17)
+
+#define POWER_RAMONB_ONRAM2			(1 << 2)
+#define POWER_RAMONB_ONRAM3			(3 << 3)
+
+#define POWER_RAMONB_OFFRAM2			(1 << 16)
+#define POWER_RAMONB_OFFRAM3			(3 << 37)
+
+#define POWER_RESET_RESET			(1 << 0)
+
+#define POWER_DCDCEN_DCDCEN			(1 << 0)
+
+
+enum power_pofcon_threshold {
+	POWER_POFCON_THRESHOLD_V21,
+	POWER_POFCON_THRESHOLD_V23,
+	POWER_POFCON_THRESHOLD_V25,
+	POWER_POFCON_THRESHOLD_V27,
+};
+
+/**@}*/
+

include/libopencm3/nrf/common/ppi.h

@@ -0,0 +1,147 @@
+/** @addtogroup ppi_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+/**@{*/
+
+/* Programmable Peripheral Interconnect */
+
+/* Tasks */
+
+#define PPI_TASK_CHG_EN(n)			MMIO32(PPI_BASE + 0x8 * (n))
+#define PPI_TASK_CHG_DIS(n)			MMIO32(PPI_BASE + 0x8 * (n) + 0x4)
+
+/* Registers */
+
+#define PPI_CHEN			MMIO32(PPI_BASE + 0x500)
+#define PPI_CHENSET			MMIO32(PPI_BASE + 0x504)
+#define PPI_CHENCLR			MMIO32(PPI_BASE + 0x508)
+
+/* Event End Point n = 0 .. 15 */
+#define PPI_CH_EEP(n)			MMIO32(PPI_BASE + 0x510 + 0x8 * (n))
+/* Task End Point n = 0 .. 15 */
+#define PPI_CH_TEP(n)			MMIO32(PPI_BASE + 0x514 + 0x8 * (n))
+
+/* Channel Groups */
+#define PPI_CHG(n)			MMIO32(PPI_BASE + 0x800 + 0x4 * (n))
+
+#define PPI_CH(n)			(1 << (n))
+/** @addtogroup PPI Channel identifiers
+ * @{
+ */
+#define PPI_CH0			(1 << 0)
+#define PPI_CH1			(1 << 1)
+#define PPI_CH2			(1 << 2)
+#define PPI_CH3			(1 << 3)
+#define PPI_CH4			(1 << 4)
+#define PPI_CH5			(1 << 5)
+#define PPI_CH6			(1 << 6)
+#define PPI_CH7			(1 << 7)
+#define PPI_CH8			(1 << 8)
+#define PPI_CH9			(1 << 9)
+#define PPI_CH10			(1 << 10)
+#define PPI_CH11			(1 << 11)
+#define PPI_CH12			(1 << 12)
+#define PPI_CH13			(1 << 13)
+#define PPI_CH14			(1 << 14)
+#define PPI_CH15			(1 << 15)
+/* Channels 16-19 are reserved */
+#define PPI_CH20			(1 << 20)
+#define PPI_CH21			(1 << 21)
+#define PPI_CH22			(1 << 22)
+#define PPI_CH23			(1 << 23)
+#define PPI_CH24			(1 << 24)
+#define PPI_CH25			(1 << 25)
+#define PPI_CH26			(1 << 26)
+#define PPI_CH27			(1 << 27)
+#define PPI_CH28			(1 << 28)
+#define PPI_CH29			(1 << 29)
+#define PPI_CH30			(1 << 30)
+#define PPI_CH31			(1 << 31)
+
+/**@}*/
+
+#define PPI_MAX_PROG_CHANNEL			(15)
+
+/* Preprogrammed channels */
+/* TIMER0->EVENTS_COMPARE0 -- RADIO->TASKS_TXEN */
+#define PPI_CH_TMR0CC0_RADIOTXEN			PPI_CH20
+
+/* TIMER0->EVENTS_COMPARE0 -- RADIO->TASKS_RXEN */
+#define PPI_CH_TMR0CC0_RADIORXEN			PPI_CH21
+
+/* TIMER0->EVENTS_COMPARE1 -- RADIO->TASKS_DISABLE */
+#define PPI_CH_TMR0CC1_RADIODIS			PPI_CH22
+
+/* RADIO->EVENTS_BCMATCH -- AAR->TASKS_START */
+#define PPI_CH_RADIOBCMATCH_AARSTART			PPI_CH23
+
+/* RADIO->EVENTS_READY -- CCM->TASKS_KSGEN */
+#define PPI_CH_RADIOREADY_CCMKSGEN			PPI_CH24
+
+/* RADIO->EVENTS_ADDRESS -- CCM->TASKS_CRYPT */
+#define PPI_CH_RADIOADDR_CCMCRYPT			PPI_CH25
+
+/* RADIO->EVENTS_ADDRESS -- TIMER0->TASKS_CAPTURE1 */
+#define PPI_CH_RADIOADDR_TMR0CAPT1			PPI_CH26
+
+/* RADIO->EVENTS_END -- TIMER0->TASKS_CAPTURE2 */
+#define PPI_CH_RADIOEND_TMR0CAPT2			PPI_CH27
+
+/* RTC0->EVENTS_COMPARE[0] -- RADIO->TASKS_TXEN */
+#define PPI_CH_RTC0CC0_RADIOTXEN			PPI_CH28
+
+/* RTC0->EVENTS_COMPARE[0] -- RADIO->TASKS_RXEN */
+#define PPI_CH_RTC0CC0_RADIORXEN			PPI_CH29
+
+/* RTC0->EVENTS_COMPARE[0] -- TIMER0->TASKS_CLEAR */
+#define PPI_CH_RTC0CC0_TMR0CLEAR			PPI_CH30
+
+/* RTC0->EVENTS_COMPARE[0] -- TIMER0->TASKS_START */
+#define PPI_CH_RTC0CC0_TMR0START			PPI_CH31
+/**@}*/
+
+BEGIN_DECLS
+
+void ppi_configure_channel(uint8_t chan_num, uint32_t eep, uint32_t tep);
+void ppi_enable_channels(uint32_t channels);
+void ppi_disable_channels(uint32_t channels);
+
+void ppi_set_group(uint8_t group, uint32_t channels);
+void ppi_enable_group(uint8_t group);
+void ppi_disable_group(uint8_t group);
+
+/* Simpler API, that requires the client to store channel map. */
+uint8_t ppi_add_channel(uint32_t *chan_map, uint32_t eep, uint32_t tep, bool enable);
+void ppi_remove_channel(uint32_t *chan_map, uint8_t chan_num);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/radio.h

@@ -0,0 +1,325 @@
+/** @addtogroup radio_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+/**@{*/
+
+/* 2.4 GHz Radio */
+
+/* Tasks */
+
+#define RADIO_TASK_TXEN			MMIO32(RADIO_BASE + 0x000)
+#define RADIO_TASK_RXEN			MMIO32(RADIO_BASE + 0x004)
+#define RADIO_TASK_START			MMIO32(RADIO_BASE + 0x008)
+#define RADIO_TASK_STOP			MMIO32(RADIO_BASE + 0x00C)
+#define RADIO_TASK_DISABLE			MMIO32(RADIO_BASE + 0x010)
+#define RADIO_TASK_RSSISTART			MMIO32(RADIO_BASE + 0x014)
+#define RADIO_TASK_RSSISTOP			MMIO32(RADIO_BASE + 0x018)
+#define RADIO_TASK_BCSTART			MMIO32(RADIO_BASE + 0x01C)
+#define RADIO_TASK_BCSTOP			MMIO32(RADIO_BASE + 0x020)
+
+/* Events */
+
+#define RADIO_EVENT_READY			MMIO32(RADIO_BASE + 0x100)
+#define RADIO_EVENT_ADDRESS			MMIO32(RADIO_BASE + 0x104)
+#define RADIO_EVENT_PAYLOAD			MMIO32(RADIO_BASE + 0x108)
+#define RADIO_EVENT_END			MMIO32(RADIO_BASE + 0x10C)
+#define RADIO_EVENT_DISABLED			MMIO32(RADIO_BASE + 0x110)
+#define RADIO_EVENT_DEVMATCH			MMIO32(RADIO_BASE + 0x114)
+#define RADIO_EVENT_DEVMISS			MMIO32(RADIO_BASE + 0x118)
+#define RADIO_EVENT_RSSIEND			MMIO32(RADIO_BASE + 0x11C)
+
+/* Registers */
+
+#define RADIO_SHORTS			_PERIPH_SHORTS(RADIO_BASE)
+#define RADIO_INTENSET			_PERIPH_INTENSET(RADIO_BASE)
+#define RADIO_INTENCLR			_PERIPH_INTENCLR(RADIO_BASE)
+#define RADIO_CRCSTATUS			MMIO32(RADIO_BASE + 0x400)
+#define RADIO_RXMATCH			MMIO32(RADIO_BASE + 0x408)
+#define RADIO_RXCRC			MMIO32(RADIO_BASE + 0x40C)
+#define RADIO_DAI			MMIO32(RADIO_BASE + 0x410)
+#define RADIO_PACKETPTR			MMIO32(RADIO_BASE + 0x504)
+#define RADIO_FREQUENCY			MMIO32(RADIO_BASE + 0x508)
+#define RADIO_TXPOWER			MMIO32(RADIO_BASE + 0x50C)
+#define RADIO_MODE			MMIO32(RADIO_BASE + 0x510)
+#define RADIO_PCNF0			MMIO32(RADIO_BASE + 0x514)
+#define RADIO_PCNF1			MMIO32(RADIO_BASE + 0x518)
+#define RADIO_BASE0			MMIO32(RADIO_BASE + 0x51C)
+#define RADIO_BASE1			MMIO32(RADIO_BASE + 0x520)
+#define RADIO_PREFIX0			MMIO32(RADIO_BASE + 0x524)
+#define RADIO_PREFIX1			MMIO32(RADIO_BASE + 0x528)
+#define RADIO_TXADDRESS			MMIO32(RADIO_BASE + 0x52C)
+#define RADIO_RXADDRESSES			MMIO32(RADIO_BASE + 0x530)
+#define RADIO_CRCCNF			MMIO32(RADIO_BASE + 0x534)
+#define RADIO_CRCPOLY			MMIO32(RADIO_BASE + 0x538)
+#define RADIO_CRCINIT			MMIO32(RADIO_BASE + 0x53C)
+#define RADIO_TEST			MMIO32(RADIO_BASE + 0x540)
+#define RADIO_TIFS			MMIO32(RADIO_BASE + 0x544)
+#define RADIO_RSSISAMPLE			MMIO32(RADIO_BASE + 0x548)
+#define RADIO_STATE			MMIO32(RADIO_BASE + 0x550)
+#define RADIO_DATAWHITEIV			MMIO32(RADIO_BASE + 0x554)
+#define RADIO_BCC			MMIO32(RADIO_BASE + 0x560)
+
+/* Device Address Base segment */
+#define RADIO_DAB(n)			MMIO32(RADIO_BASE + 0x600 + 0x4 * (n))
+/* Device Address Prefix segment */
+#define RADIO_DAP(n)			MMIO32(RADIO_BASE + 0x620 + 0x4 * (n))
+#define RADIO_DACNF			MMIO32(RADIO_BASE + 0x640)
+
+/* Override Registers */
+#define RADIO_OVERRIDE(n)			MMIO32(RADIO_BASE + 0x724 + 0x4 * (n))
+#define RADIO_POWER			MMIO32(RADIO_BASE + 0xFFC)
+
+/* Register Details */
+
+/** @addtogroup radio_shorts Radio event -> task shortcuts
+ * @{
+ */
+#define RADIO_SHORTS_READY_START			(1 << 0)
+#define RADIO_SHORTS_END_DISABLE			(1 << 1)
+#define RADIO_SHORTS_DISABLED_TXEN			(1 << 2)
+#define RADIO_SHORTS_DISABLED_RXEN			(1 << 3)
+#define RADIO_SHORTS_ADDRESS_RSSISTART			(1 << 4)
+#define RADIO_SHORTS_END_START			(1 << 5)
+#define RADIO_SHORTS_ADDRESS_BCSTART			(1 << 6)
+#define RADIO_SHORTS_DISABLED_RSSISTOP			(1 << 8)
+
+/**@}*/
+
+/** @addtogroup radio_inten Radio interrupts
+ * @{
+ */
+#define RADIO_INTEN_READY			(1 << 0)
+#define RADIO_INTEN_ADDRESS			(1 << 1)
+#define RADIO_INTEN_PAYLOAD			(1 << 2)
+#define RADIO_INTEN_END			(1 << 3)
+#define RADIO_INTEN_DISABLED			(1 << 4)
+#define RADIO_INTEN_DEVMATCH			(1 << 5)
+#define RADIO_INTEN_DEVMISS			(1 << 6)
+#define RADIO_INTEN_RSSIEND			(1 << 7)
+#define RADIO_INTEN_BCMATCH			(1 << 10)
+
+/**@}*/
+
+#define RADIO_PCNF0_LFLEN_SHIFT			(0)
+#define RADIO_PCNF0_LFLEN_MASK			(0xf << RADIO_PCNF0_LFLEN_SHIFT)
+#define RADIO_PCNF0_LFLEN_MASKED(V)			(((V) << RADIO_PCNF0_LFLEN_SHIFT) \
+		& RADIO_PCNF0_LFLEN_MASK)
+
+#define RADIO_PCNF0_S0LEN_SHIFT			(8)
+#define RADIO_PCNF0_S0LEN_MASK			(1 << RADIO_PCNF0_S0LEN_SHIFT)
+#define RADIO_PCNF0_S0LEN_MASKED(V)			(((V) << RADIO_PCNF0_S0LEN_SHIFT) \
+		& RADIO_PCNF0_S0LEN_MASK)
+
+#define RADIO_PCNF0_S1LEN_SHIFT			(16)
+#define RADIO_PCNF0_S1LEN_MASK			(0xf << RADIO_PCNF0_S1LEN_SHIFT)
+#define RADIO_PCNF0_S1LEN_MASKED(V)			(((V) << RADIO_PCNF0_S1LEN_SHIFT) & \
+		RADIO_PCNF0_S1LEN_MASK)
+
+#define RADIO_PCNF1_MAXLEN_SHIFT			(0)
+#define RADIO_PCNF1_MAXLEN_MASK			(0xff << RADIO_PCNF1_MAXLEN_SHIFT)
+#define RADIO_PCNF1_MAXLEN_MASKED(V)			(((V) << RADIO_PCNF1_MAXLEN_SHIFT) & \
+		RADIO_PCNF1_MAXLEN_MASK)
+
+#define RADIO_PCNF1_STATLEN_SHIFT			(8)
+#define RADIO_PCNF1_STATLEN_MASK			(0xff << RADIO_PCNF1_STATLEN_SHIFT)
+#define RADIO_PCNF1_STATLEN_MASKED(V)			(((V) << RADIO_PCNF1_STATLEN_SHIFT) & \
+		RADIO_PCNF1_STATLEN_MASK)
+
+#define RADIO_PCNF1_BALEN_SHIFT			(16)
+#define RADIO_PCNF1_BALEN_MASK			(7 << RADIO_PCNF1_BALEN_SHIFT)
+#define RADIO_PCNF1_BALEN_MASKED(V)			(((V) << RADIO_PCNF1_BALEN_SHIFT) & \
+		RADIO_PCNF1_BALEN_MASK)
+
+#define RADIO_PCNF1_ENDIAN_BIG			(1 << 24)
+#define RADIO_PCNF1_WHITEEN			(1 << 25)
+
+#define RADIO_PREFIX0_AP0_SHIFT			(0)
+#define RADIO_PREFIX0_AP0_MASK			(0xff << RADIO_PREFIX0_AP0_SHIFT)
+#define RADIO_PREFIX0_AP0_MASKED(V)			(((V) << RADIO_PREFIX0_AP0_SHIFT) & \
+		RADIO_PREFIX0_AP0_MASK)
+
+#define RADIO_PREFIX0_AP1_SHIFT			(8)
+#define RADIO_PREFIX0_AP1_MASK			(0xff << RADIO_PREFIX0_AP1_SHIFT)
+#define RADIO_PREFIX0_AP1_MASKED(V)			(((V) << RADIO_PREFIX0_AP1_SHIFT) & \
+		RADIO_PREFIX0_AP1_MASK)
+
+#define RADIO_PREFIX0_AP2_SHIFT			(16)
+#define RADIO_PREFIX0_AP2_MASK			(0xff << RADIO_PREFIX0_AP2_SHIFT)
+#define RADIO_PREFIX0_AP2_MASKED(V)			(((V) << RADIO_PREFIX0_AP2_SHIFT) & \
+		RADIO_PREFIX0_AP2_MASK)
+
+#define RADIO_PREFIX0_AP3_SHIFT			(24)
+#define RADIO_PREFIX0_AP3_MASK			(0xff << RADIO_PREFIX0_AP3_SHIFT)
+#define RADIO_PREFIX0_AP3_MASKED(V)			(((V) << RADIO_PREFIX0_AP3_SHIFT) & \
+		RADIO_PREFIX0_AP3_MASK)
+
+#define RADIO_PREFIX1_AP4_SHIFT			(0)
+#define RADIO_PREFIX1_AP4_MASK			(0xff << RADIO_PREFIX1_AP4_SHIFT)
+#define RADIO_PREFIX1_AP4_MASKED(V)			(((V) << RADIO_PREFIX1_AP4_SHIFT) & \
+		RADIO_PREFIX1_AP4_MASK)
+
+#define RADIO_PREFIX1_AP5_SHIFT			(8)
+#define RADIO_PREFIX1_AP5_MASK			(0xff << RADIO_PREFIX1_AP5_SHIFT)
+#define RADIO_PREFIX1_AP5_MASKED(V)			(((V) << RADIO_PREFIX1_AP5_SHIFT) & \
+		RADIO_PREFIX1_AP5_MASK)
+
+#define RADIO_PREFIX1_AP6_SHIFT			(16)
+#define RADIO_PREFIX1_AP6_MASK			(0xff << RADIO_PREFIX1_AP6_SHIFT)
+#define RADIO_PREFIX1_AP6_MASKED(V)			(((V) << RADIO_PREFIX1_AP6_SHIFT) & \
+		RADIO_PREFIX1_AP6_MASK)
+
+#define RADIO_PREFIX1_AP7_SHIFT			(24)
+#define RADIO_PREFIX1_AP7_MASK			(0xff << RADIO_PREFIX1_AP7_SHIFT)
+#define RADIO_PREFIX1_AP7_MASKED(V)			(((V) << RADIO_PREFIX1_AP7_SHIFT) & \
+		RADIO_PREFIX1_AP7_MASK)
+
+#define RADIO_PREFIX_AP(n)			((n) < 4 ? RADIO_PREFIX0 : RADIO_PREFIX1)
+#define RADIO_PREFIX_AP_SHIFT(n)			(8 * (n & 3))
+#define RADIO_PREFIX_AP_MASK(n)			(0xff << RADIO_PREFIX_AP_SHIFT(n))
+#define RADIO_PREFIX_AP_MASKED(n, V)			(((V) << RADIO_PREFIX_AP_SHIFT(n)) & \
+		RADIO_PREFIX_AP_MASK(n))
+
+/* TODO: Get rid of this */
+#define RADIO_PREFIX_AP_SET(n, V)			if ((n) < 4) {\
+		RADIO_PREFIX0 = (V); } \
+	else {\
+		RADIO_PREFIX1 = (V); }
+
+#define RADIO_TXADDRESSES_ADDR0			(1 << 0)
+#define RADIO_TXADDRESSES_ADDR1			(1 << 1)
+#define RADIO_TXADDRESSES_ADDR2			(1 << 2)
+#define RADIO_TXADDRESSES_ADDR3			(1 << 3)
+#define RADIO_TXADDRESSES_ADDR4			(1 << 4)
+#define RADIO_TXADDRESSES_ADDR5			(1 << 5)
+#define RADIO_TXADDRESSES_ADDR6			(1 << 6)
+#define RADIO_TXADDRESSES_ADDR7			(1 << 7)
+#define RADIO_TXADDRESSES_ADDR(n)			(1 << (n))
+
+#define RADIO_CRCCNF_LEN_SHIFT			(0)
+#define RADIO_CRCCNF_LEN_MASK			(3 << RADIO_CRCCNF_LEN_SHIFT)
+#define RADIO_CRCCNF_LEN_MASKED(V)			(((V) << RADIO_CRCCNF_LEN_SHIFT) & \
+		RADIO_CRCCNF_LEN_MASK)
+
+#define RADIO_CRCCNF_SKIPADDR			(1 << 8)
+
+#define RADIO_TEST_CONSTCARRIER			(1 << 0)
+#define RADIO_TEST_PLLLOCK			(1 << 1)
+
+#define RADIO_DACNF_ENA(n)			(1 << (n))
+#define RADIO_DACNF_ENA0			RADIO_DACNF_ENA(0)
+#define RADIO_DACNF_ENA1			RADIO_DACNF_ENA(1)
+#define RADIO_DACNF_ENA2			RADIO_DACNF_ENA(2)
+#define RADIO_DACNF_ENA3			RADIO_DACNF_ENA(3)
+#define RADIO_DACNF_ENA4			RADIO_DACNF_ENA(4)
+#define RADIO_DACNF_ENA5			RADIO_DACNF_ENA(5)
+#define RADIO_DACNF_ENA6			RADIO_DACNF_ENA(6)
+#define RADIO_DACNF_ENA7			RADIO_DACNF_ENA(7)
+
+#define RADIO_DACNF_TXADD(n)			(1 << ((n) + 8))
+#define RADIO_DACNF_TXADD0			RADIO_DACNF_TXADD(0)
+#define RADIO_DACNF_TXADD1			RADIO_DACNF_TXADD(1)
+#define RADIO_DACNF_TXADD2			RADIO_DACNF_TXADD(2)
+#define RADIO_DACNF_TXADD3			RADIO_DACNF_TXADD(3)
+#define RADIO_DACNF_TXADD4			RADIO_DACNF_TXADD(4)
+#define RADIO_DACNF_TXADD5			RADIO_DACNF_TXADD(5)
+#define RADIO_DACNF_TXADD6			RADIO_DACNF_TXADD(6)
+#define RADIO_DACNF_TXADD7			RADIO_DACNF_TXADD(7)
+
+/* Override 4 register has special bit and the override value is masked. */
+#define RADIO_OVERRIDE4_ENABLE			(1 << 31)
+#define RADIO_OVERRIDE4_OVERRIDE_MASK			(0x0fffffff)
+
+#define RADIO_POWER_ENABLED			(1)
+#define RADIO_POWER_DISABLED			(0)
+
+/* Bluetooth Low Energy parameters */
+#define RADIO_BLE_TIFS			(150)
+#define RADIO_BLE_CRCLEN			(3)
+#define RADIO_BLE_CRCPOLY			(0x65B)
+#define RADIO_BLE_CRCINIT			(0x555555)
+
+enum radio_txpower {
+	RADIO_TXPOWER_POS_4DBM = 0x4,
+	RADIO_TXPOWER_0DBM = 0,
+	RADIO_TXPOWER_NEG_4DBM = 0xFC,
+	RADIO_TXPOWER_NEG_8DBM = 0xF8,
+	RADIO_TXPOWER_NEG_12DBM = 0xF4,
+	RADIO_TXPOWER_NEG_16DBM = 0xF0,
+	RADIO_TXPOWER_NEG_20DBM = 0xEC,
+	RADIO_TXPOWER_NEG_30DBM = 0xD8,
+};
+
+enum radio_state {
+	RADIO_STATE_DISABLED,
+	RADIO_STATE_RXRU,
+	RADIO_STATE_RXIDLE,
+	RADIO_STATE_RX,
+	RADIO_STATE_RXDISABLE,
+	RADIO_STATE_TXRU = 9,
+	RADIO_STATE_TXIDLE,
+	RADIO_STATE_TX,
+	RADIO_STATE_TXDISABLE,
+};
+
+/**@}*/
+
+BEGIN_DECLS
+
+void radio_configure_ble(void);
+void radio_disable_crc(void);
+void radio_disable(void);
+void radio_enable(void);
+void radio_set_crclen(uint8_t crc_len);
+void radio_set_lsbfirst(void);
+void radio_set_msbfirst(void);
+void radio_set_txpower(enum radio_txpower txpower);
+void radio_disable_whitening(void);
+void radio_enable_whitening(void);
+void radio_configure_packet(uint8_t lf_len_bits, uint8_t s0_len_bytes, uint8_t s1_len_bits);
+void radio_set_balen(uint8_t ba_len);
+void radio_set_frequency(uint8_t freq);
+void radio_set_datawhiteiv(uint8_t iv);
+void radio_set_addr(uint8_t addr_index, uint32_t base, uint8_t prefix);
+void radio_set_tx_address(uint8_t addr_index);
+void radio_set_packet_ptr(uint8_t *packet_ptr);
+void radio_enable_shorts(uint16_t shorts);
+void radio_disable_shorts(uint16_t shorts);
+void radio_clear_shorts(void);
+void radio_enable_tx(void);
+void radio_enable_rx(void);
+void radio_set_maxlen(uint8_t maxlen);
+void radio_set_crc_skipaddr(bool is_skip_addr);
+
+END_DECLS
+
+
+

include/libopencm3/nrf/common/rtc.h

@@ -0,0 +1,85 @@
+/** @addtogroup rtc_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+/**@{*/
+
+/* Only two RTCs on this device. */
+/** @addtogroup rtc_block RTC instances
+ * @{
+ */
+#define RTC0			RTC0_BASE
+#define RTC1			RTC1_BASE
+
+/**@}*/
+
+/* Tasks */
+#define RTC_TASK_START(rtc)			MMIO32((rtc) + 0x000)
+#define RTC_TASK_STOP(rtc)			MMIO32((rtc) + 0x004)
+#define RTC_TASK_CLEAR(rtc)			MMIO32((rtc) + 0x008)
+#define RTC_TASK_TRIGOVRFLW(rtc)			MMIO32((rtc) + 0x00C)
+
+/* Events */
+#define RTC_EVENT_TICK(rtc)			MMIO32((rtc) + 0x100)
+#define RTC_EVENT_OVRFLW(rtc)			MMIO32((rtc) + 0x104)
+#define RTC_EVENT_COMPARE(rtc, i)			MMIO32((rtc) + 0x140 + 0x4 * (i))
+
+/* Registers */
+#define RTC_INTEN(rtc)				_PERIPH_INTEN(rtc)
+#define RTC_INTENSET(rtc)			_PERIPH_INTENSET(rtc)
+#define RTC_INTENCLR(rtc)			_PERIPH_INTENCLR(rtc)
+#define RTC_EVTEN(rtc)				MMIO32((rtc) + 0x340)
+#define RTC_EVTENSET(rtc)			MMIO32((rtc) + 0x344)
+#define RTC_EVTENCLR(rtc)			MMIO32((rtc) + 0x348)
+#define RTC_COUNTER(rtc)			MMIO32((rtc) + 0x504)
+#define RTC_PRESCALER(rtc)			MMIO32((rtc) + 0x508)
+#define RTC_CC(rtc, i)		MMIO32((rtc) + 0x540 + 0x4 * (i))
+
+/* Register Contents */
+#define RTC_INTEN_TICK			(1 << 0)
+#define RTC_INTEN_OVRFLW			(1 << 1)
+#define RTC_INTEN_COMPARE(n)			(1 << (16 + (n)))
+/**@}*/
+
+BEGIN_DECLS
+
+void rtc_set_prescaler(uint32_t rtc, uint16_t presc);
+uint32_t rtc_get_counter(uint32_t rtc);
+void rtc_enable_events(uint32_t rtc, uint32_t mask);
+void rtc_disable_events(uint32_t rtc, uint32_t mask);
+void rtc_start(uint32_t rtc);
+void rtc_stop(uint32_t rtc);
+void rtc_clear(uint32_t rtc);
+void rtc_set_compare(uint32_t rtc, uint8_t cmp, uint32_t value);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/timer.h

@@ -0,0 +1,120 @@
+/** @addtogroup timer_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+
+/**@{*/
+/* Timer/Counter */
+/** @addtogroup timer_block
+ * @{
+ */
+
+#define TIMER0						TIMER0_BASE
+#define TIMER1						TIMER1_BASE
+#define TIMER2						TIMER2_BASE
+
+/**@}*/
+
+/* Tasks */
+
+#define TIMER_TASK_START(T)			MMIO32((T) + 0x000)
+#define TIMER_TASK_STOP(T)			MMIO32((T) + 0x004)
+#define TIMER_TASK_COUNT(T)			MMIO32((T) + 0x008)
+#define TIMER_TASK_CLEAR(T)			MMIO32((T) + 0x00C)
+#define TIMER_TASK_SHUTDOWN(T)			MMIO32((T) + 0x010)
+#define TIMER_TASK_CAPTURE(T, C)			MMIO32((T) + 0x040 + (uint32_t)(0x4 * (C)))
+
+
+
+
+/* Events */
+
+#define TIMER_EVENT_COMPARE(T, C)			MMIO32((T) + 0x140 + (uint32_t)(0x4 * (C)))
+
+/* Registers */
+
+#define TIMER_SHORTS(T)			_PERIPH_SHORTS(T)
+#define TIMER_INTENSET(T)			_PERIPH_INTENSET(T)
+#define TIMER_INTENCLR(T)			_PERIPH_INTENCLR(T)
+#define TIMER_MODE(T)			MMIO32((T) + 0x504)
+#define TIMER_BITMODE(T)			MMIO32((T) + 0x508)
+#define TIMER_PRESCALER(T)			MMIO32((T) + 0x510)
+#define TIMER_PRESCALER_MASK			(0xf)
+
+#define TIMER_CC(T, C)			MMIO32((T) + 0x540 + 0x4 * (C))
+
+
+
+
+/* Register Contents */
+
+/** @addtogroup timer_shorts Timer event -> task shortcuts
+ * @{
+ */
+
+#define TIMER_SHORTS_COMPARE_CLEAR(C)			(1 << (C))
+#define TIMER_SHORTS_COMPARE_STOP(C)			(1 << (8 + (C)))
+/**@}*/
+
+#define TIMER_INTEN_COMPARE(C)					(1 << (16 + (C)))
+
+#define TIMER_MODE_SELECT			(1 << 0)
+
+enum timer_mode {
+	TIMER_MODE_TIMER,
+	TIMER_MODE_COUNTER,
+};
+
+enum timer_bitmode {
+	TIMER_BITMODE_16BIT,
+	TIMER_BITMODE_08BIT,
+	TIMER_BITMODE_24BIT,
+	TIMER_BITMODE_32BIT,
+};
+
+/**@}*/
+
+BEGIN_DECLS
+
+uint32_t timer_get_ticks(uint32_t timer);
+void timer_set_mode(uint32_t timer, enum timer_mode mode);
+void timer_set_bitmode(uint32_t timer, enum timer_bitmode bitmode);
+void timer_start(uint32_t timer);
+void timer_stop(uint32_t timer);
+void timer_clear(uint32_t timer);
+void timer_set_prescaler(uint32_t timer, uint8_t presc);
+void timer_set_compare(uint32_t timer, uint8_t compare_num, uint32_t compare_val);
+uint32_t timer_get_cc(uint32_t timer, uint8_t compare_num);
+uint32_t timer_get_freq(uint32_t timer);
+
+END_DECLS
+
+

include/libopencm3/nrf/common/uart.h

@@ -0,0 +1,150 @@
+/** @addtogroup uart_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+#include <libopencm3/nrf/periph.h>
+
+/**@{*/
+
+/* Universal Asynchronous Receiver/Transmitter */
+
+/** @addtogroup uart_block UART instance
+ * @{
+ */
+#define UART0     UART0_BASE
+
+/**@}*/
+
+/* Tasks */
+
+#define UART_TASK_STARTRX(uart)  MMIO32((uart) + 0x000)
+#define UART_TASK_STOPRX(uart)   MMIO32((uart) + 0x004)
+#define UART_TASK_STARTTX(uart)  MMIO32((uart) + 0x008)
+#define UART_TASK_STOPTX(uart)   MMIO32((uart) + 0x00C)
+#define UART_TASK_SUSPEND(uart)  MMIO32((uart) + 0x01C)
+
+/* Events */
+
+#define UART_EVENT_CTS(uart)     MMIO32((uart) + 0x100)
+#define UART_EVENT_NCTS(uart)    MMIO32((uart) + 0x104)
+#define UART_EVENT_RXDRDY(uart)  MMIO32((uart) + 0x108)
+#define UART_EVENT_TXDRDY(uart)  MMIO32((uart) + 0x11C)
+#define UART_EVENT_ERROR(uart)   MMIO32((uart) + 0x124)
+#define UART_EVENT_RXTO(uart)    MMIO32((uart) + 0x144)
+
+/* Registers */
+
+#define UART_INTEN(uart)         _PERIPH_INTEN(uart)
+#define UART_INTENSET(uart)      _PERIPH_INTENSET(uart)
+#define UART_INTENCLR(uart)      _PERIPH_INTENCLR(uart)
+#define UART_ERRORSRC(uart)      MMIO32((uart) + 0x480)
+#define UART_ENABLE(uart)        MMIO32((uart) + 0x500)
+#define UART_PSELRTS(uart)       MMIO32((uart) + 0x508)
+#define UART_PSELTXD(uart)       MMIO32((uart) + 0x50C)
+#define UART_PSELCTS(uart)       MMIO32((uart) + 0x510)
+#define UART_PSELRXD(uart)       MMIO32((uart) + 0x514)
+#define UART_RXD(uart)           MMIO32((uart) + 0x518)
+#define UART_TXD(uart)           MMIO32((uart) + 0x51C)
+#define UART_BAUDRATE(uart)      MMIO32((uart) + 0x524)
+#define UART_CONFIG(uart)        MMIO32((uart) + 0x56C)
+
+/* Register Contents */
+
+/** @addtogroup uart_inten UART interrupt sources
+ * @{
+ */
+#define UART_INTEN_CTS           (1 << 0)
+#define UART_INTEN_NCTS          (1 << 1)
+#define UART_INTEN_RXDRDY        (1 << 2)
+#define UART_INTEN_TXDRDY        (1 << 7)
+#define UART_INTEN_ERROR         (1 << 9)
+#define UART_INTEN_RXTO          (1 << 17)
+
+/**@}*/
+
+#define UART_ERRORSRC_OVERRUN    (1 << 0)
+#define UART_ERRORSRC_PARITY     (1 << 1)
+#define UART_ERRORSRC_FRAMING    (1 << 2)
+#define UART_ERRORSRC_BREAK      (1 << 3)
+
+#define UART_ENABLE_ENABLED      (4)
+#define UART_ENABLE_DISABLED     (0)
+#define UART_CONFIG_HWFC         (1)
+#define UART_CONFIG_PARITY       (7 << 1)
+
+#define UART_PSEL_OFF            (0xff)
+#define UART_MAX_PIN             (31)
+#define UART_PSEL_VAL(p)         (p <= UART_MAX_PIN ? (uint32_t) p : 0xffffffff)
+
+
+enum uart_baud {
+	UART_BAUD_1200 = 0x0004F000,
+	UART_BAUD_2400 = 0x0009D000,
+	UART_BAUD_4800 = 0x0013B000,
+	UART_BAUD_9600 = 0x00275000,
+	UART_BAUD_14400 = 0x003B0000,
+	UART_BAUD_19200 = 0x004EA000,
+	UART_BAUD_28800 = 0x0075F000,
+	UART_BAUD_38400 = 0x009D5000,
+	UART_BAUD_57600 = 0x00EBF000,
+	UART_BAUD_76800 = 0x013A9000,
+	UART_BAUD_115200 = 0x01D7E000,
+	UART_BAUD_230400 = 0x03AFB000,
+	UART_BAUD_250000 = 0x04000000,
+	UART_BAUD_460800 = 0x075F7000,
+	UART_BAUD_921600 = 0x0EBEDFA4,
+	UART_BAUD_1M = 0x10000000,
+};
+
+
+BEGIN_DECLS
+
+void uart_enable(uint32_t uart);
+void uart_disable(uint32_t uart);
+void uart_configure(uint32_t uart,
+uint32_t txd, uint32_t rxd, uint32_t rts, uint32_t cts,
+enum uart_baud br, bool enable_parity);
+void uart_set_baudrate(uint32_t uart, enum uart_baud br);
+void uart_set_parity(uint32_t uart, int parity);
+void uart_set_flow_control(uint32_t uart, int flow);
+void uart_send_stop(uint32_t uart);
+
+void uart_start_tx(uint32_t uart);
+void uart_stop_tx(uint32_t uart);
+void uart_send(uint32_t uart, uint16_t byte);
+void uart_start_rx(uint32_t uart);
+void uart_stop_rx(uint32_t uart);
+uint16_t uart_recv(uint32_t uart);
+void uart_set_pins(uint32_t uart, uint32_t rx, uint32_t tx, uint32_t cts, uint32_t rts);
+
+END_DECLS
+
+/**@}*/
+

include/libopencm3/nrf/common/uicr.h

@@ -0,0 +1,53 @@
+/** @addtogroup uicr_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+
+/**@{*/
+/* User Information Configuration Register */
+
+#define UICR_CLENR0			MMIO32(UICR_BASE + 0x000)
+#define UICR_RBPCONF			MMIO32(UICR_BASE + 0x004)
+#define UICR_XTALFREQ			MMIO32(UICR_BASE + 0x008)
+#define UICR_FWID			MMIO32(UICR_BASE + 0x010)
+#define UICR_BOOTLOADERADDR			MMIO32(UICR_BASE + 0x014)
+
+/* Reserved for Nordic firmware design, n = 1..14 */
+#define UICR_NRFFW(n)			MMIO32(UICR_BASE + 0x014 + 0x4 * (n))
+
+/* Reserved for Nordic hardware design, n = 0..11 */
+#define UICR_NRFHW(n)			MMIO32(UICR_BASE + 0x050 + 0x4 * (n))
+
+/* Reserved for customer n = 0..31 */
+#define UICR_CUSTOMER(n)			MMIO32(UICR_BASE + 0x080 + 0x4 * (n))
+
+
+/**@}*/
+

include/libopencm3/nrf/ficr.h

@@ -0,0 +1,38 @@
+/** @addtogroup ficr_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/ficr.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/ficr.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/gpio.h

@@ -0,0 +1,40 @@
+/** @addtogroup gpio_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/nrf/memorymap.h>
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/gpio.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/gpio.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/i2c.h

@@ -0,0 +1,37 @@
+/** @addtogroup i2c_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/i2c.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/i2c.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/memorymap.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/memorymap.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/memorymap.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/periph.h

@@ -0,0 +1,30 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/periph.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/periph.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/power.h

@@ -0,0 +1,37 @@
+/** @addtogroup power_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/power.h>
+#elif defined(NRF51)
+#	include <libopencm3/nrf/52/power.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/ppi.h

@@ -0,0 +1,37 @@
+/** @addtogroup ppi_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/ppi.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/ppi.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/radio.h

@@ -0,0 +1,37 @@
+/** @addtogroup radio_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/radio.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/radio.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/rtc.h

@@ -0,0 +1,37 @@
+/** @addtogroup rtc_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/rtc.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/rtc.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/timer.h

@@ -0,0 +1,37 @@
+/** @addtogroup timer_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/timer.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/timer.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/uart.h

@@ -0,0 +1,37 @@
+/** @addtogroup uart_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/uart.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/uart.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/nrf/uicr.h

@@ -0,0 +1,37 @@
+/** @addtogroup uicr_defines
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2016 Maxim Sloyko <maxims@google.com>
+ * @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
+ *
+ **/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
+ * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#if defined(NRF51)
+#	include <libopencm3/nrf/51/uicr.h>
+#elif defined(NRF52)
+#	include <libopencm3/nrf/52/uicr.h>
+#else
+#	error "Processor family not defined."
+#endif
+

include/libopencm3/pac55xx/can.h

@@ -0,0 +1,307 @@
+/**
+ * @brief CAN definitions for the Qorvo PAC55xx series of microcontrollers.
+ *
+ * @addtogroup PAC55xx_can CAN
+ * @ingroup PAC55xx_defines
+ * @author Kevin Stefanik <kevin@allocor.tech>
+ * LGPL License Terms @ref lgpl_license
+ * @date February 13, 2020
+ *
+ * Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
+ * by Active-Semi dated November 19, 2019.
+ *
+ * Note: all memory-mapped writes must be performed using 32-bit registers.
+ * Any 8-bit memory-mapped registers below may only be used to read.
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef LIBOPENCM3_PAC55XX_CAN_H_
+#define LIBOPENCM3_PAC55XX_CAN_H_
+
+#include <libopencm3/pac55xx/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/**
+ * @defgroup can_isr_sr_cmr_mr CAN ISR/SR/CMR/MR Registers
+ * @{*/
+/** This is the 32-bit memory mapped read/write accessor for:
+ * - ISR - bits 31:24 - Interrupt Status/ACK Register RW, default 00h
+ * - SR  - bits 23:16 - Status Register RO, default 00h
+ * - CMR - bits 15:8  - Command RW, default 00h
+ * - MR  - bits  7:0  - Mode RW, default 04h
+ * When writing, be sure to use CAN_ISR_SR_CMR_MR_SET and CAN_ISR_SR_CMR_MR_CLEAR
+ * so as to avoid inadvertently Acknowledging an ISR bit. Writing '1' to one
+ * of the ISR bits when it is triggered/set will ACK/clear the bit.
+ */
+#define CAN_ISR_SR_CMR_MR(can_base)             MMIO32((can_base) + 0x0000)
+#define CAN_ISR_SR_CMR_MR_SET(can_base, bits)   (CAN_ISR_SR_CMR_MR(can_base) = \
+				(CAN_ISR_SR_CMR_MR(can_base) & 0x00FFFFFF) | (bits))
+#define CAN_ISR_SR_CMR_MR_CLEAR(can_base, bits) (CAN_ISR_SR_CMR_MR(can_base) = \
+				(CAN_ISR_SR_CMR_MR(can_base) & 0x00FFFFFF) & ~(bits))
+/**@}*/
+
+/**
+ * @defgroup can_btr01_rmc_imr CAN BTR1/BTR0/RMC/IMR Registers
+ * @{*/
+/** This is the 32-bit memory mapped read/write accessor for:
+ * - BTR1 - bits 31:24 - Bus Timing 1 Register RW, default 00h
+ * - BTR0 - bits 23:16 - Bus Timing 0 Register RW, default 00h
+ * - RMC  - bits 15:8  - Receive Message Counter RO, default 00h
+ * - IMR  - bits  7:0  - Interrupt Mask Register RW, default 00h
+ */
+#define CAN_BTR1_BTR0_RMC_IMR(can_base)         MMIO32((can_base) + 0x0004)
+/**@}*/
+
+/** CAN Transmit Buffer Register RW, default 00000000h */
+#define CAN_TXBUF(can_base)     MMIO32((can_base) + 0x0008)
+/** CAN Receive Buffer Register RO, default 00000000h */
+#define CAN_RXBUF(can_base)     MMIO32((can_base) + 0x000C)
+/** CAN Acceptance Code Register RW, default 00000000h */
+#define CAN_ACR(can_base)       MMIO32((can_base) + 0x0010)
+/** CAN Acceptance Mask Register RW, default 00000000h */
+#define CAN_AMR(can_base)       MMIO32((can_base) + 0x0014)
+
+/**
+ * @defgroup can_alc_txrxerr_ecc CAN ALC/TXERR/RXERR/ECC Registers
+ * @{*/
+#define CAN_ALC_TXERR_RXERR_ECC(can_base)   MMIO32((can_base) + 0x0018)
+/** CAN Error Code Capture Register RO, default 00h */
+#define CAN_ECC(can_base)       (CAN_ALC_TXERR_RXERR_ECC(can_base) & 0xFF)
+/** CAN RX Error Counter Register RO, default 00h */
+#define CAN_RXERR(can_base)     ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 8) & 0xFF)
+/** CAN TX Error Counter Register RO, default 00h */
+#define CAN_TXERR(can_base)     ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 16) & 0xFF)
+/** CAN Arbitration Lost Code Capture Register RO, default 00h */
+#define CAN_ALC(can_base)       ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 24) & 0xFF)
+/**@}*/
+
+/** CAN Mode Register bit definitions. This register controls high level modes of the CAN peripheral.
+ * @defgroup can_mr_bits CAN Mode Register
+ * @{*/
+/** AFM: Acceptance Filter Mode */
+#define CAN_MR_AFM      BIT0
+/** LOM: Listen only mode */
+#define CAN_MR_LOM      BIT1
+/** RM: Reset Mode */
+#define CAN_MR_RM       BIT2
+/**@}*/
+
+/** CAN Command Register. This register commands the CAN peripheral to either transmit or abort.
+ * @defgroup can_cmr_bits CAN Command Register
+ * @{*/
+/** AT: Abort transmission */
+#define CAN_CMR_AT      BIT9
+/** TR: Transmit Request */
+#define CAN_CMR_TR      BIT10
+/**@}*/
+
+/** CAN Status Register. This register provides read-only status of the CAN peripheral.
+ * @defgroup can_sr_bits CAN Status Register
+ * @{*/
+/** BS: Bus Off Status */
+#define CAN_SR_BS       BIT16
+/** ES: Error Status */
+#define CAN_SR_ES       BIT17
+/** TS: Transmit Status */
+#define CAN_SR_TS       BIT18
+/** RS: Receive Status */
+#define CAN_SR_RS       BIT19
+/** TBS: Transmit Buffer Status */
+#define CAN_SR_TBS      BIT21
+/** DSO: Data Overrun Status */
+#define CAN_SR_DSO      BIT22
+/** RBS: Receive Buffer Status */
+#define CAN_SR_RBS      BIT23
+/**@}*/
+
+/** CAN Interrupt Status Register bit definitions.
+ * - 1: interrupt triggered
+ * - 0: no interrupt
+ * - Writing a 1 to a triggered interrupt clears the bit.
+ * @defgroup can_isr_bits CAN Interrupt Status Register
+ * @{*/
+/** DOI: Data Overflow Interrupt */
+#define CAN_ISR_DOI     BIT24
+/** BEI: Bus Error Interrupt */
+#define CAN_ISR_BEI     BIT25
+/** TI: Transmit Interrupt */
+#define CAN_ISR_TI      BIT26
+/** RI: Receive Interrupt */
+#define CAN_ISR_RI      BIT27
+/** EPI: Error Passive Interrupt */
+#define CAN_ISR_EPI     BIT28
+/** EWI: Error Warning Interrupt */
+#define CAN_ISR_EWI     BIT29
+/** ALI: Arbitration Lost Interrupt */
+#define CAN_ISR_ALI     BIT30
+/** This is a helper to acknowledge an ISR */
+#define CAN_ISR_ACKNOWLEDGE(can_base, isr)  CAN_ISR_SR_CMR_MR_SET(can_base, ((isr) & 0x7F000000))
+/**@}*/
+
+/** CAN Interrupt Mask Register bit definitions.
+ * 0: disables/masks interrupt
+ * 1: enables interrupt
+ * @defgroup can_imr_bits CAN Mask Register
+ * @{*/
+/** DOIM: DOI Interrupt Mask */
+#define CAN_IMR_DOIM    BIT0
+/** BEIM: BEI Interrupt Mask */
+#define CAN_IMR_BEIM    BIT1
+/** TIM: TI Interrupt Mask */
+#define CAN_IMR_TIM     BIT2
+/** RIM: RI Interrupt Mask */
+#define CAN_IMR_RIM     BIT3
+/** EPIM: EPI Interrupt Mask */
+#define CAN_IMR_EPIM    BIT4
+/** EWIM: EWI Interrupt Mask */
+#define CAN_IMR_EWIM    BIT5
+/** ALIM: ALI Interrupt Mask */
+#define CAN_IMR_ALIM    BIT6
+/**@}*/
+
+/** CAN Receive Message Counter Register bit definitions.
+ * @defgroup can_rmc_bits CAN Receive Message Counter Register.
+ * @{*/
+#define CAN_RMC(can_base)   ((CAN_BTR1_BTR0_RMC_IMR(can_base) >> 8) & 0x1F)
+/**@}*/
+
+/** CAN Bus Timing 0 Register bit definitions.
+ * @defgroup can_btr0_bits CAN Bus Timing 0 Register.
+ * @{*/
+#define CAN_BTR0_BRP_MASK   (0x3F)
+#define CAN_BTR0_BRP_SHIFT  16
+#define CAN_BTR0_BRP(val)   (((val) & CAN_BTR0_BRP_MASK) << CAN_BTR0_BRP_SHIFT)
+#define CAN_BTR0_SJW_MASK   (0x03)
+#define CAN_BTR0_SJW_SHIFT  22
+#define CAN_BTR0_SJW(val)   (((val) & CAN_BTR0_SJW_MASK) << CAN_BTR0_SJW_SHIFT)
+/**@}*/
+
+/** CAN Bus Timing 1 Register bit definitions.
+ * @defgroup can_btr1_bits CAN Bus Timing 1 Register
+ * @{*/
+#define CAN_BTR1_TSEG1_MASK     (0x0F)
+#define CAN_BTR1_TSEG1_SHIFT    24
+#define CAN_BTR1_TSEG1(val)     (((val) & CAN_BTR1_TSEG1_MASK) << CAN_BTR1_TSEG1_SHIFT)
+
+#define CAN_BTR1_TSEG2_MASK     (0x07)
+#define CAN_BTR1_TSEG2_SHIFT    28
+#define CAN_BTR1_TSEG2(val)     (((val) & CAN_BTR1_TSEG2_MASK) << CAN_BTR1_TSEG2_SHIFT)
+#define CAN_BTR1_SAM            BIT31
+/**@}*/
+
+/** CAN Error Code Capture Register bit definitions.
+ * @defgroup can_ecc_bits CAN Error Code Capture Register
+ * @{*/
+/** BER: Bit error ocurred */
+#define CAN_ECC_BER     BIT0
+/** STFER: Stuff error occurred */
+#define CAN_ECC_STFER   BIT1
+/** CRCER: CRC error occurred */
+#define CAN_ECC_CRCER   BIT2
+/** FRMER: Form error occurred */
+#define CAN_ECC_FRMER   BIT3
+/** ACKER: ACK error occurred */
+#define CAN_ECC_ACKER   BIT4
+/** EDIR: Direction of transfer 0:TX, 1:RX */
+#define CAN_ECC_EDIR    BIT5
+/** TXWRN: set when CAN_TXERR >= 96 */
+#define CAN_ECC_TXWRN   BIT6
+/** RXWRN: set when CAN_RXERR >= 96 */
+#define CAN_ECC_RXWRN   BIT7
+/**@}*/
+
+/** CAN Acceptance Code/Mask Register. This is used for filtering messages.
+ * Mask value of 1 ignores the bit. Mask value of 0 checks the bit.
+ * @defgroup can_acr_bits CAN Acceptance Code Register
+ * @{*/
+#define CAN_ACR_DUAL_DB_UPPER   0x000F0000U /* 19:16 */
+#define CAN_ACR_DUAL_DB_LOWER   0x0000000FU /* 3:0 */
+#define CAN_ACR_DUAL_ID1        0xFFE00000U /* 31:21 */
+#define CAN_ACR_DUAL_ID2        0x0000FFE0U /* 15:5 */
+#define CAN_ACR_DUAL_RTR1       0x00100000U /* 20 */
+#define CAN_ACR_DUAL_RTR2       0x00000010U /* 4 */
+
+#define CAN_ACR_SINGLE_STD_ID   0xFFE00000U /* 31:21 */
+#define CAN_ACR_SINGLE_STD_RTR  0x00100000U /* 20 */
+#define CAN_ACR_SINGLE_STD_DB1  0x0000FF00U /* 15:8 */
+#define CAN_ACR_SINGLE_STD_DB2  0x000000FFU /* 7:0 */
+
+#define CAN_ACR_SINGLE_EXT_ID   0xFFFFFFF8U /* 31:3 */
+#define CAN_ACR_SINGLE_EXT_RTR  0x00000004U /* 2 */
+/**@}*/
+
+/**
+ * @defgroup can_bit_masks CAN Miscellaneous Bit Masks
+ * @{*/
+#define CAN_BITS_2_0    (0x07)
+#define CAN_BITS_3_0    (0x0F)
+#define CAN_BITS_4_0    (0x1F)
+#define CAN_BITS_7_3    (0xF8)
+#define CAN_BITS_10_3   (0x07F8)
+#define CAN_BITS_12_5   (0x00001FE0U)
+#define CAN_BITS_20_13  (0x001FE000U)
+#define CAN_BITS_28_21  (0x1FE00000U)
+#define CAN_BITS_15_8   (0x0000FF00U)
+#define CAN_BITS_23_16  (0x00FF0000U)
+#define CAN_BITS_31_24  (0xFF000000U)
+#define CAN_BITS_23_21  (0x00E00000U)
+/**@}*/
+
+/**@}*/
+
+BEGIN_DECLS
+/** CAN Application Programming Interface.
+ * @addtogroup can_api CAN Peripheral API
+ * @ingroup peripheral_apis
+ @{*/
+void can_enable(uint32_t canport);
+void can_disable(uint32_t canport);
+void can_init(uint32_t canport, bool listen_only, uint32_t sjw,
+			uint32_t tseg1, uint32_t tseg2,
+			bool sam3, uint32_t brp);
+void can_filter_clear(uint32_t canport);
+void can_filter_dual(uint32_t canport, uint32_t id1, uint32_t id1_mask,
+			uint32_t id2, uint32_t id2_mask,
+			uint8_t db, uint8_t db_mask);
+void can_filter_single_std(uint32_t canport, uint32_t id, uint32_t id_mask,
+			uint8_t db1, uint8_t db1_mask,
+			uint8_t db2, uint8_t db2_mask);
+void can_filter_single_std_rtr(uint32_t canport, uint32_t id, uint32_t id_mask,
+			uint8_t db1, uint8_t db1_mask,
+			uint8_t db2, uint8_t db2_mask);
+void can_filter_single_ext(uint32_t canport, uint32_t id, uint32_t id_mask);
+void can_filter_single_ext_rtr(uint32_t canport, uint32_t id, uint32_t id_mask);
+void can_enable_irq(uint32_t canport, uint8_t imr);
+void can_disable_irq(uint32_t canport, uint8_t imr);
+
+bool can_transmit_std(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
+			const uint8_t *data);
+bool can_transmit_ext(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
+			const uint8_t *data);
+void can_abort_transmit(uint32_t canport);
+
+void can_receive(uint32_t canport, uint32_t *id, bool *ext, bool *rtr, uint8_t *length,
+			uint8_t *data);
+/**@}*/
+
+END_DECLS
+
+#endif /* LIBOPENCM3_PAC55XX_CAN_H_ */

include/libopencm3/pac55xx/ccs.h

@@ -4,6 +4,7 @@
  *  @defgroup system_defines Clock Config and System Defines
  *  @ingroup PAC55xx_defines
  *  @author Brian Viele <vielster@allocor.tech>
+ *  @author Kevin Stefanik <kevin@allocor.tech>
  *  LGPL License Terms @ref lgpl_license
  *  @date 1 Dec 2019
  *
@@ -26,18 +27,95 @@
  * You should have received a copy of the GNU Lesser General Public License
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
-#ifndef INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
+#ifndef LIBOPENCM3_PAC55XX_CCS_H_
-#define INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
+#define LIBOPENCM3_PAC55XX_CCS_H_
 
 #include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/pac55xx/memorymap.h>
+#include <libopencm3/pac55xx/memctl.h>
 
 /**@{*/
 
-/** Clock Control Registers
+/** @defgroup ccs_frequencies CCS Frequencies
- * @defgroup clock_config_regs Clock Config Registers.
+@{*/
- * @{*/
+/** Ring Oscillator Frequency */
+#define CCS_ROSC_FREQ       (16000000U)
+/** Internally generated and trimmed 4MHz clock */
+#define CCS_CLKREF_FREQ     (4000000U)
+/** Maximum external clock frequency */
+#define CCS_EXTCLK_MAX_FREQ (20000000U)
+/**@}*/
+
+/** @defgroup ccs_ctl_reg Clock Control Register
+@{*/
 #define CCSCTL MMIO32(SCC_BASE)
+#define CCS_CTL_FRCLKMUXSEL_MASK (0x03)
+#define CCS_CTL_FRCLKMUXSEL(sel) ((sel) & CCS_CTL_FRCLKMUXSEL_MASK)
+#define CCS_CTL_FRCLKMUXSEL_ROSC    (0)
+#define CCS_CTL_FRCLKMUXSEL_CLKREF  (1)
+#define CCS_CTL_FRCLKMUXSEL_EXTCLK  (3)
+#define CCS_CTL_ROSCEN BIT2
+#define CCS_CTL_SCLKMUXSEL BIT4
+#define CCS_CTL_SCLKMUXSEL_FRCLK    (0)
+#define CCS_CTL_SCLKMUXSEL_PLLCLK   (1)
+#define CCS_CTL_CLKFAILEN BIT5
+#define CCS_CTL_CLKFAILMUXSEL BIT6
+#define CCS_CTL_CLKFAILIF BIT7
+#define CCS_CTL_LDOEN BIT8
+#define CCS_CTL_SWRESET BIT11
+#define CCS_CTL_PCLKEN BIT12
+#define CCS_CTL_ACLKEN BIT13
+#define CCS_CTL_ADCCLKEN BIT14
+#define CCS_CTL_STCLKSLPEN BIT15
+#define CCS_CTL_PCLKDIV_MASK (0x07)
+#define CCS_CTL_PCLKDIV_SHIFT (16)
+/* Supported PCLK divisors: 1-8 */
+#define CCS_CTL_PCLKDIV(div) (((div-1) & CCS_CTL_PCLKDIV_MASK) << CCS_CTL_PCLKDIV_SHIFT)
+#define CCS_CTL_ACLKDIV_MASK (0x07)
+#define CCS_CTL_ACLKDIV_SHIFT (20)
+/* Supported ACLK divisors: 1-8 */
+#define CCS_CTL_ACLKDIV(div) (((div-1) & CCS_CTL_ACLKDIV_MASK) << CCS_CTL_ACLKDIV_SHIFT)
+#define CCS_CTL_HCLKDIV_MASK (0x07)
+#define CCS_CTL_HCLKDIV_SHIFT (24)
+/* Supported HCLK divisors: 1-8 */
+#define CCS_CTL_HCLKDIV(div) (((div-1) & CCS_CTL_HCLKDIV_MASK) << CCS_CTL_HCLKDIV_SHIFT)
+#define CCS_CTL_USAMODE BIT28
+#define CCS_CTL_USBMODE BIT29
+#define CCS_CTL_USCMODE BIT30
+#define CCS_CTL_USDMODE BIT31
+/**@}*/
+
+/** @defgroup ccs_pllctl_reg CCS PLL Control Register
+@{*/
 #define CCSPLLCTL MMIO32(SCC_BASE + 0x04)
+/** PLL Enable */
+#define CCS_PLLCTL_PLLEN BIT0
+/** PLL Bypass */
+#define CCS_PLLCTL_PLLBP BIT1
+#define CCS_PLLCTL_PLLOUTDIV_MASK (0x03)
+#define CCS_PLLCTL_PLLOUTDIV_SHIFT (2)
+/** PLL Output Divisor */
+#define CCS_PLLCTL_PLLOUTDIV(div) (((div) & CCS_PLLCTL_PLLOUTDIV_MASK) << CCS_PLLCTL_PLLOUTDIV_SHIFT)
+#define CCS_PLLCTL_PLLOUTDIV1     (0)
+#define CCS_PLLCTL_PLLOUTDIV2     (1)
+#define CCS_PLLCTL_PLLOUTDIV4     (2)
+#define CCS_PLLCTL_PLLOUTDIV8     (3)
+#define CCS_PLLCTL_PLLINDIV_MASK (0x0F)
+#define CCS_PLLCTL_PLLINDIV_SHIFT (4)
+/** PLL Input Divisor */
+#define CCS_PLLCTL_PLLINDIV(div) (((div) & CCS_PLLCTL_PLLINDIV_MASK) << CCS_PLLCTL_PLLINDIV_SHIFT)
+#define CCS_PLLCTL_PLLFBDIV_MASK (0x3FFF)
+#define CCS_PLLCTL_PLLFBDIV_SHIFT (8)
+/** PLL Feedback Divisor */
+#define CCS_PLLCTL_PLLFBDIV(div) (((div) & CCS_PLLCTL_PLLFBDIV_MASK) << CCS_PLLCTL_PLLFBDIV_SHIFT)
+/** PLL Lock */
+#define CCS_PLLCTL_PLLLOCK BIT24
+/**@}*/
+
+/** @defgroup ccs_rosctrim Ring Oscillator Trim Control Register
+@{*/
+#define CCSROSCTRIM_MASK (0x7F)
 #define CCSROSCTRIM MMIO32(SCC_BASE + 0x08)
 /**@}*/
 
@@ -136,6 +214,162 @@ typedef enum {
 	CCS_DSR_DS_25MA = 0x07,
 } ccs_drive_strength_t;
 /**@}*/
+
 /**@}*/
 
-#endif /* INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ */
+BEGIN_DECLS
+
+/**
+ * @defgroup ccs_api Clock Control System API
+ * @ingroup peripheral_apis
+ * @brief <b>PAC5xx CCS Driver</b>
+ * @author @htmlonly &copy; @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
+ * @date March 7, 2020
+ *
+ * This library supports the CCS module in the PAC55xx SoC from Qorvo.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/**@{*/
+
+/**
+ * Select the source for FRCLK.
+ * @param[in] sel  one of:
+ *   - /ref CCS_CTL_FRCLKMUXSEL_ROSC - 16MHz ring oscillator
+ *   - /ref CCS_CTL_FRCLKMUXSEL_CLKREF - trimmed 4MHz clock
+ *   - /ref CCS_CTL_FRCLKMUXSEL_EXTCLK
+ */
+void ccs_frclkmux_select(uint32_t sel);
+/** Enable the 16MHz Ring oscillator */
+void ccs_rosc_enable(void);
+/** Disable the 16MHz Ring oscillator */
+void ccs_rosc_disable(void);
+/** Select FRCLK for SCLK */
+void ccs_sclkmux_select_frclk(void);
+/** Select PLLCLK for SCLK */
+void ccs_sclkmux_select_pllclk(void);
+/** Enable Clock Fail Detection */
+void ccs_clkfail_enable(void);
+/** Disable Clock Fail Detection */
+void ccs_clkfail_disable(void);
+/** Select FRCLK for Clock Fail Detection */
+void ccs_clkfailmux_select_frclk(void);
+/** Select PLLCLK for Clock Fail Detection */
+void ccs_clkfailmux_select_pllclk(void);
+/** Enable the LDO */
+void ccs_ldo_enable(void);
+/** Disable the LDO */
+void ccs_ldo_disable(void);
+/** Enable the Peripheral Clock */
+void ccs_pclk_enable(void);
+/** Disable the Peripheral Clock */
+void ccs_pclk_disable(void);
+/** Enable the Auxiliary Clock */
+void ccs_aclk_enable(void);
+/** Disable the Auxiliary Clock */
+void ccs_aclk_disable(void);
+/** Enable the ADC Clock */
+void ccs_adcclk_enable(void);
+/** Disable the ADC Clock */
+void ccs_adcclk_disable(void);
+/** Enable SysTick clock gating in deep sleep mode */
+void ccs_stclk_sleep_enable(void);
+/** Disable SysTick clock gating in deep sleep mode */
+void ccs_stclk_sleep_disable(void);
+/**
+ * Set the divisor for the Peripheral Clock.
+ * @param[in] div  PCLK Divisor: 1-8.
+ */
+void ccs_set_pclkdiv(uint32_t div);
+/**
+ * Set the divisor for the Auxiliary Clock.
+ * @param[in] div  ACLK Divisor: 1-8.
+ */
+void ccs_set_aclkdiv(uint32_t div);
+/**
+ * Set the divisor for the AHB Clock.
+ * @param[in] div  HCLK Divisor: 1-8.
+ */
+void ccs_set_hclkdiv(uint32_t div);
+/** Enable the PLL */
+void ccs_pll_enable(void);
+/** Disable the PLL */
+void ccs_pll_disable(void);
+/** Check if the PLL is locked.
+ * @return true if locked.
+ */
+bool ccs_pll_locked(void);
+/** Enable the PLL bypass */
+void ccs_pll_bypass_enable(void);
+/** Disable the PLL bypass */
+void ccs_pll_bypass_disable(void);
+/**
+ * Set the output divisor.
+ * @param[in] div  Output divisor, one of:
+ *   - /ref CCS_PLLCTL_PLLOUTDIV1
+ *   - /ref CCS_PLLCTL_PLLOUTDIV2
+ *   - /ref CCS_PLLCTL_PLLOUTDIV4
+ *   - /ref CCS_PLLCTL_PLLOUTDIV8
+ */
+void ccs_pll_set_outdiv(uint32_t div);
+/**
+ * Set the PLL input divisor.
+ * @param[in] div  Input divisor, 1-15.
+ */
+void ccs_pll_set_indiv(uint32_t div);
+/**
+ * Set the PLL feedback divisor.
+ * @param[in] div  Feedback divisor, 4-16383.
+ */
+void ccs_pll_set_fbdiv(uint32_t div);
+/**
+ * Configure the CCS PLL, enable it, and wait for lock.
+ * @param[in] indiv  Input divisor, 1-15.
+ * @param[in] fbdiv  Feedback divisor, 4-16383.
+ * @param[in] outdiv  Output divisor, one of:
+ *   - /ref CCS_PLLCTL_PLLOUTDIV1
+ *   - /ref CCS_PLLCTL_PLLOUTDIV2
+ *   - /ref CCS_PLLCTL_PLLOUTDIV4
+ *   - /ref CCS_PLLCTL_PLLOUTDIV8
+ */
+void css_pll_config_enable(uint32_t indiv, uint32_t fbdiv, uint32_t outdiv);
+/**
+ * Get the clock rate (in Hz) of the specified peripheral. This will pull the
+ * proper sources out of the clock tree and calculate the clock for the
+ * peripheral for return to the user, based on current settings.
+ * @param[in] periph  Peripheral base address to get the clock rate for.
+ * @param[in] select  Peripheral-controlled clock select value. Set to 0 when not applicable.
+ * @return Clock rate in Hz for the specified peripheral. 0 if undefined or error.
+ */
+uint32_t ccs_get_peripheral_clk_freq(uint32_t periph, uint32_t select);
+/** Restores CCSCTL and CCSPLLCTL registers to default/safe values */
+void ccs_reset_clocks(void);
+
+/** CCS Clock Configuration structure. */
+struct ccs_clk_config {
+	uint32_t frclk_source;              /**< FRCLK source input selection */
+	uint32_t extclk_frequency;          /**< EXTCLK frequency, 0 if none. */
+	uint32_t sclk_source;               /**< SCLK source selection */
+	uint32_t pll_indiv;                 /**< PLL Input Divider 1-15 */
+	uint32_t pll_fbdiv;                 /**< PLL Feedback Divider 4-16383 */
+	uint32_t pll_outdiv;                /**< PLL Output Divider */
+	uint32_t hclkdiv;                   /**< Divisor from SCLK to HCLK */
+	uint32_t aclkdiv;                   /**< Divisor from SCLK to ACLK */
+	uint32_t pclkdiv;                   /**< Divisor from HCLK to PCLK */
+	uint32_t mem_wstate;                /**< Number of Flash Read wait states */
+	uint32_t mem_mclkdiv;               /**< Divisor from HCLK to MCLK */
+	bool mem_mclksel;                   /**< false: ROSCLK, true: HCLK/MCLK */
+	bool mem_enable_cache;              /**< false: disable cache, true: enable cache */
+};
+/**
+ * Setup the PAC55xx clocks with the given struct.
+ * @param[in] config CCS Clock configuration struct /ref ccs_clk_config
+ */
+void ccs_configure_clocks(const struct ccs_clk_config *config);
+
+/**@}*/
+
+END_DECLS
+
+#endif /* LIBOPENCM3_PAC55XX_CCS_H_ */

include/libopencm3/pac55xx/memctl.h

@@ -0,0 +1,163 @@
+/**
+ * @brief Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers
+ *
+ * @addtogroup PAC55xx_memctl Memory Controller Defines
+ * @ingroup PAC55xx_defines
+ * @author Kevin Stefanik <kevin@allocor.tech>
+ * LGPL License Terms @ref lgpl_license
+ * @date 17 Mar 2020
+ *
+ * Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
+ * by Active-Semi dated November 19, 2019.
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef LIBOPENCM3_PAC55XX_MEMCTL_H_
+#define LIBOPENCM3_PAC55XX_MEMCTL_H_
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/pac55xx/memorymap.h>
+/**@{*/
+
+/** @defgroup memctl_reg Memory Controller Configuration Register
+@{*/
+/** Memory Controller Configuration Register */
+#define MEMCTL_MEMCTLR          MMIO32(MEMCTL_BASE)
+#define MEMCTL_MEMCTLR_WSTATE_MASK              (0xF)
+#define MEMCTL_MEMCTLR_WSTATE(ws)               ((ws) & MEMCTL_MEMCTLR_WSTATE_MASK)
+#define MEMCTL_MEMCTLR_MCLKDIV_MASK             (0xF)
+#define MEMCTL_MEMCTLR_MCLKDIV_SHIFT            4
+/* Supported MCLK divisors: 1-16 */
+#define MEMCTL_MEMCTLR_MCLKDIV(div)             (((div-1) & MEMCTL_MEMCTLR_MCLKDIV_MASK) << MEMCTL_MEMCTLR_MCLKDIV_SHIFT)
+#define MEMCTL_MEMCTLR_WRITEWORDCNT_MASK        (0x3)
+#define MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT       8
+#define MEMCTL_MEMCTLR_WRITEWORDCNT(cnt)        (((cnt) & MEMCTL_MEMCTLR_WRITEWORDCNT_MASK) << MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT)
+#define MEMCTL_MEMCTLR_SEIE                     BIT16
+#define MEMCTL_MEMCTLR_DEIE                     BIT17
+#define MEMCTL_MEMCTLR_INVADDRIE                BIT18
+#define MEMCTL_MEMCTLR_STBY                     BIT19
+#define MEMCTL_MEMCTLR_ECCDIS                   BIT20
+#define MEMCTL_MEMCTLR_CACHEDIS                 BIT21
+#define MEMCTL_MEMCTLR_MCLKSEL                  BIT22
+/**@}*/
+
+/** @defgroup memstatus_reg Memory Controller Status Register
+@{*/
+/** Memory Controller Status Register */
+#define MEMCTL_MEMSTATUS       MMIO32(MEMCTL_BASE + 0x0004)
+#define MEMCTL_MEMSTATUS_WBUSY                 BIT0
+#define MEMCTL_MEMSTATUS_EBUSY                 BIT1
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK     (0x3)
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT    8
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT          ((MEMCTL_MEMSTATUS >> MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT) & MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK)
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_4BYTES   (0)
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_8BYTES   (1)
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_12BYTES  (2)
+#define MEMCTL_MEMSTATUS_WRITEWORDCNT_16BYTES  (3)
+#define MEMCTL_MEMSTATUS_SE                    BIT16
+#define MEMCTL_MEMSTATUS_DE                    BIT17
+#define MEMCTL_MEMSTATUS_INVADDR               BIT18
+/**@}*/
+
+/** @defgroup flashlock_vals Flash Lock/Write Enable Register values
+@{*/
+/** Flash Lock Access Register */
+#define MEMCTL_FLASHLOCK       MMIO32(MEMCTL_BASE + 0x0008)
+#define MEMCTL_FLASHLOCK_CLEAR                 (0)
+#define MEMCTL_FLASHLOCK_ALLOW_FLASH_WRITE     (0x43DF140A)
+#define MEMCTL_FLASHLOCK_ALLOW_MEMCTL_WRITE    (0xD513B490)
+#define MEMCTL_FLASHLOCK_ALLOW_INFO2_SWDFUSE   (0x79B4F762)
+/**@}*/
+
+/** Flash Page Address Register */
+#define MEMCTL_FLASHPAGE       MMIO32(MEMCTL_BASE + 0x000C)
+/** SWD Unlock Register */
+#define MEMCTL_SWDUNLOCK       MMIO32(MEMCTL_BASE + 0x0010)
+
+/** @defgroup flasherase_vals Flash Erase Enable Register values
+@{*/
+/** Flash Erase Enable Register */
+#define MEMCTL_FLASHERASE      MMIO32(MEMCTL_BASE + 0x0020)
+#define MEMCTL_FLASHERASE_PAGE_ERASE           (0x8C799CA7)
+#define MEMCTL_FLASHERASE_MASS_PAGE_ERASE      (0x09EE76C9)
+#define MEMCTL_FLASHERASE_INFO3_ERASE          (0x1266FF45)
+/**@}*/
+
+/**@}*/
+
+BEGIN_DECLS
+
+/**
+ * @defgroup memctl_api Memory Controller API
+ * @ingroup peripheral_apis
+ * @brief <b>PAC5xx MEMCTL Driver</b>
+ * @author @htmlonly &copy; @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
+ * @date March 7, 2020
+ *
+ * This library supports the MEMCTL module in the PAC55xx SoC from Qorvo.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*@{*/
+
+/** Set the number of wait states for Flash reads.
+ * @param[in] wstate  Wait states: 0-15
+ */
+void memctl_flash_set_wstate(uint32_t wstate);
+/** Set the MCLK divisor.
+ * @param[in] div  HCLK to MCLK divisor: 1-16
+ */
+void memctl_flash_set_mclkdiv(uint32_t div);
+/** Set WRITEWORDCOUNT to 0 to reset the Flash write data buffer */
+void memctl_flash_reset_write_buffer(void);
+/** Enable Flash Standby Mode */
+void memctl_flash_standby_mode_enable(void);
+/** Disable Flash Standby Mode */
+void memctl_flash_standby_mode_disable(void);
+/** Enable Flash cache */
+void memctl_flash_cache_enable(void);
+/** Disable Flash cache */
+void memctl_flash_cache_disable(void);
+/** Select ROSCCLK as input to Flash Memory Controller */
+void memctl_flash_select_roscclk(void);
+/** Select MCLK as input to Flash Memory Controller */
+void memctl_flash_select_mclk(void);
+/** Enable SRAM ECC */
+void memctl_sram_ecc_enable(void);
+/** Disable SRAM ECC */
+void memctl_sram_ecc_disable(void);
+/** Enable SRAM ECC Single Bit Detection Interrupt */
+void memctl_sram_ecc_single_bit_interrupt_enable(void);
+/** Disable SRAM ECC Single Bit Detection Interrupt */
+void memctl_sram_ecc_single_bit_interrupt_disable(void);
+/** Enable SRAM ECC Dual Bit Detection Interrupt */
+void memctl_sram_ecc_dual_bit_interrupt_enable(void);
+/** Disable SRAM ECC Dual Bit Detection Interrupt */
+void memctl_sram_ecc_dual_bit_interrupt_disable(void);
+/** Enable Invalid Memory Access Interrupt */
+void memctl_invaddr_interrupt_enable(void);
+/** Disable Invalid Memory Access Interrupt */
+void memctl_invaddr_interrupt_disable(void);
+
+/**@}*/
+
+END_DECLS
+
+#endif /* LIBOPENCM3_PAC55XX_MEMCTL_H_ */

include/libopencm3/pac55xx/usart.h

@@ -0,0 +1,214 @@
+/**
+ * @brief USART definitions for the Qorvo PAC55xx series of microcontrollers
+ *
+ * @addtogroup PAC55xx_usart USART
+ * @ingroup PAC55xx_defines
+ * @author Kevin Stefanik <kevin@allocor.tech>
+ * LGPL License Terms @ref lgpl_license
+ * @date 25 Feb 2020
+ *
+ * Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
+ * by Active-Semi dated November 19, 2019. TX and RX hardware buffer sizes
+ * are both 16 bytes.
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef LIBOPENCM3_PAC55XX_USART_H_
+#define LIBOPENCM3_PAC55XX_USART_H_
+
+#include <libopencm3/pac55xx/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/** @defgroup usart_registers Registers
+@{*/
+/** Receive Buffer Register RO, only bits 7:0 used */
+#define USART_RBR(usart_base)   MMIO32((usart_base) + 0x0000)
+/** Transmit Holding Register WO, only bits 7:0 used */
+#define USART_THR(usart_base)   MMIO32((usart_base) + 0x0004)
+/** Divisor Latch Register RW, default 0000 0001h, only bits 15:0 used.*/
+#define USART_DLR(usart_base)   MMIO32((usart_base) + 0x0008)
+/** Interrupt Enable Register RW, default 0000 0000h */
+#define USART_IER(usart_base)   MMIO32((usart_base) + 0x000C)
+/** Interrupt Identification Register RO, default 0000 0001h */
+#define USART_IIR(usart_base)   MMIO32((usart_base) + 0x0010)
+/** FIFO Control Register RW, default 0000 0000h */
+#define USART_FCR(usart_base)   MMIO32((usart_base) + 0x0014)
+/** Line control Register RW, default 0000 0000h */
+#define USART_LCR(usart_base)   MMIO32((usart_base) + 0x0018)
+/** Line Status Register RO, default 0000 0060h */
+#define USART_LSR(usart_base)   MMIO32((usart_base) + 0x0020)
+/** Scratch Pad Register RW, only bits 7:0 used */
+#define USART_SCR(usart_base)   MMIO32((usart_base) + 0x0028)
+/** Enhanced Mode Register RW, default 0000 000h */
+#define USART_EFR(usart_base)   MMIO32((usart_base) + 0x002C)
+/**@}*/
+
+/** @defgroup usart_ier_bits Interrupt Enable Register bits
+@{*/
+/** Enable RX line status interrupt */
+#define USART_IER_RLSIE         BIT2
+/** Enable the TX Holding Empty interrupt */
+#define USART_IER_THRIE         BIT1
+/** Enable the RX Buffer Register Interrupt */
+#define USART_IER_RBRIE         BIT0
+/**@}*/
+
+/** @defgroup usart_iir_bits Interrupt ID Register bits
+@{*/
+/** This bit is active low to indicate an interrupt is pending */
+#define USART_IIR_INTSTATUS     BIT0
+/** TX Holding Register Empty */
+#define USART_IIR_TXEMPTY       (0x02)
+/** Receive Data Available */
+#define USART_IIR_RXAVAIL       (0x04)
+/** Receive Line Status */
+#define USART_IIR_RXLINESTAT    (0x06)
+/** Receive FIFO Character Time-out */
+#define USART_IIR_RXTIMEOUT     (0x0C)
+/**@}*/
+
+/** @defgroup usart_fcr_bits FIFO Control Register bits
+@{*/
+/** Enable both UART RX and TX FIFOs, must be set before writing rest of FCR */
+#define USART_FCR_FIFOEN        BIT0
+/** RX FIFO Reset. Write 1 to clear. This bit is self-clearing. */
+#define USART_FCR_RXFIFORST     BIT1
+/** TX FIFO Reset. Write 1 to clear. This bit is self-clearing. */
+#define USART_FCR_TXFIFORST     BIT2
+#define USART_FCR_TXTL_MASK     (3)
+#define USART_FCR_TXTL_SHIFT    4
+/** TX Trigger Level */
+#define USART_FCR_TXTL(txtl)    (((txtl) & USART_FCR_TXTL_MASK) << USART_FCR_TXTL_SHIFT)
+#define USART_FCR_RXTL_MASK     (3)
+#define USART_FCR_RXTL_SHIFT    6
+/** RX Trigger Level */
+#define USART_FCR_RXTL(rxtl)    (((rxtl) & USART_FCR_RXTL_MASK) << USART_FCR_RXTL_SHIFT)
+#define USART_FIFO_TRIG_1CHAR   (0)
+#define USART_FIFO_TRIG_4CHAR   (1)
+#define USART_FIFO_TRIG_8CHAR   (2)
+#define USART_FIFO_TRIG_14CHAR  (3)
+/**@}*/
+
+/** @defgroup usart_lcr_bits Line Control Register bits
+@{*/
+/** LCR:WLS 5-bit character length */
+#define USART_DATABITS_5        (0)
+/** LCR:WLS 6-bit character length */
+#define USART_DATABITS_6        (0x01)
+/** LCR:WLS 7-bit character length */
+#define USART_DATABITS_7        (0x02)
+/** LCR:WLS 8-bit character length */
+#define USART_DATABITS_8        (0x03)
+/** LCR:PSEL & LCR:PEN Odd parity */
+#define USART_PSELPEN_ODD       (0x01)
+/** LCR:PSEL & LCR:PEN Even parity */
+#define USART_PSELPEN_EVEN      (0x03)
+/** LCR:PSEL & LCR:PEN Force 1 stick parity */
+#define USART_PSELPEN_FORCE1    (0x05)
+/** LCR:PSEL & LCR:PEN Force 0 stick parity */
+#define USART_PSELPEN_FORCE0    (0x07)
+/** LCR:PSEL & LCR:PEN Disable parity */
+#define USART_PARITY_DISABLE    (0)
+/** LCR:PSEL & LCR:PEN Odd parity */
+#define USART_PARITY_ODD        USART_PSELPEN_ODD
+/** LCR:PSEL & LCR:PEN Even parity */
+#define USART_PARITY_EVEN       USART_PSELPEN_EVEN
+/** LCR:PSEL & LCR:PEN Force 1 stick parity */
+#define USART_PARITY_FORCE1     USART_PSELPEN_FORCE1
+/** LCR:PSEL & LCR:PEN Force 0 stick parity */
+#define USART_PARITY_FORCE0     USART_PSELPEN_FORCE0
+/** LCR:SBS Use 1 stop bit */
+#define USART_STOPBITS_1        (0)
+/** LCR:SBS Use 1.5 stop bit when databits is 5 */
+#define USART_STOPBITS_1P5      USART_LCR_SBS
+/** LCR:SBS Use 2 stop bits */
+#define USART_STOPBITS_2        USART_LCR_SBS
+#define USART_LCR_WLS_MASK      (3)
+/** Word length select: 5-8 databits */
+#define USART_LCR_WLS(wls)      ((wls) & USART_LCR_WLS_MASK)
+/** Set LCR:SBS for 1.5 or 2 stop bits, Clear for 1 stop bit */
+#define USART_LCR_SBS           BIT2
+/** Enable parity checking */
+#define USART_LCR_PEN           BIT3
+#define USART_LCR_PSELPEN_MASK  (7)
+#define USART_LCR_PSELPEN_SHIFT 3
+/** LCR:PSEL and LCR:PEN control parity */
+#define USART_LCR_PSELPEN(psel) (((psel) & USART_LCR_PSELPEN_MASK) << USART_LCR_PSELPEN_SHIFT)
+/** Break Control: Enabling this bit forces TX to logic 0 */
+#define USART_LCR_BCON          BIT6
+/**@}*/
+
+/** @defgroup usart_lsr_bits Line Status Register bits
+@{*/
+/** Receiver Data Ready */
+#define USART_LSR_RDR           BIT0
+/** Overrun Error */
+#define USART_LSR_OE            BIT1
+/** Parity Error */
+#define USART_LSR_PE            BIT2
+/** Framing Error */
+#define USART_LSR_FE            BIT3
+/** Break Interrupt */
+#define USART_LSR_BI            BIT4
+/** Transmitter Holding Register Empty */
+#define USART_LSR_THRE          BIT5
+/** Transmitter Empty */
+#define USART_LSR_TEMT          BIT6
+/** Error in RX FIFO */
+#define USART_LSR_RXFE          BIT7
+/**@}*/
+
+/** TX FIFO depth */
+#define USART_TX_FIFO_DEPTH     (16)
+/** RX FIFO depth */
+#define USART_RX_FIFO_DETPH     (16)
+
+/** Enable Enhanced Mode to use TX and RX FIFO trigger level interrupts */
+#define USART_EFR_ENMODE        BIT4
+
+/**@}*/
+
+BEGIN_DECLS
+
+uint32_t usart_set_baudrate(uint32_t usart, uint32_t baud);
+void usart_configure_lcr(uint32_t usart, uint8_t data_bits, uint8_t stop_bits,
+				uint8_t parity);
+void usart_break_enable(uint32_t usart);
+void usart_break_disable(uint32_t usart);
+void usart_enhanced_enable(uint32_t usart);
+void usart_enhanced_disable(uint32_t usart);
+void usart_set_fifo_depth(uint32_t usart, uint8_t tx_depth, uint8_t rx_depth);
+void usart_send(uint32_t usart, uint8_t data);
+uint8_t usart_recv(uint32_t usart);
+void usart_enable_rx_interrupt(uint32_t usart);
+void usart_disable_rx_interrupt(uint32_t usart);
+void usart_enable_tx_interrupt(uint32_t usart);
+void usart_disable_tx_interrupt(uint32_t usart);
+void usart_enable_rls_interrupt(uint32_t usart);
+void usart_disable_rls_interrupt(uint32_t usart);
+void usart_fifo_enable(uint32_t usart);
+void usart_fifo_disable(uint32_t usart);
+void usart_clear_tx_fifo(uint32_t usart);
+void usart_clear_rx_fifo(uint32_t usart);
+
+END_DECLS
+
+#endif /* LIBOPENCM3_PAC55XX_USART_H_ */

include/libopencm3/sam/d/doc-samd.h

@@ -0,0 +1,8 @@
+/** @defgroup peripheral_apis Peripheral APIs
+ * APIs for device peripherals
+ */
+
+/** @defgroup SAMD_defines SAMD Defines
+ * Defined Constants and Types for the SAMD series.
+ * @copyright SPDX: LGPL-3.0-or-later
+ */

include/libopencm3/sam/d/port.h

@@ -1,68 +1,256 @@
-/*
+/** @defgroup port_defines IO Port Definitions
- * This file is part of the libopencm3 project.
  *
- * Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
+ * @ingroup SAMD_defines
  *
- * This library is free software: you can redistribute it and/or modify
+ * @brief Defined Constants and Types for the SAMD Port controller
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
  *
- * This library is distributed in the hope that it will be useful,
+ * @copyright SPDX: LGPL-3.0-or-later
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * @author 2016 Karl Palsson <karlp@tweak.net.au>
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * @author 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #pragma once
 
+/**@{*/
+
 #include <libopencm3/cm3/common.h>
+#include <libopencm3/sam/d/memorymap.h>
 
 /* --- Convenience macros ------------------------------------------------ */
 
+/**@defgroup port_reg_base Port Base registers
+ * @{
+ */
 #define PORTA				(PORT_BASE + 0)
 #define PORTB				(PORT_BASE + 0x80)
+/**@}*/
 
-/* --- PORT registers ----------------------------------------------------- */
+/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@{*/
+#define GPIO0			(1 << 0)
+#define GPIO1			(1 << 1)
+#define GPIO2			(1 << 2)
+#define GPIO3			(1 << 3)
+#define GPIO4			(1 << 4)
+#define GPIO5			(1 << 5)
+#define GPIO6			(1 << 6)
+#define GPIO7			(1 << 7)
+#define GPIO8			(1 << 8)
+#define GPIO9			(1 << 9)
+#define GPIO10			(1 << 10)
+#define GPIO11			(1 << 11)
+#define GPIO12			(1 << 12)
+#define GPIO13			(1 << 13)
+#define GPIO14			(1 << 14)
+#define GPIO15			(1 << 15)
+#define GPIO16			(1 << 16)
+#define GPIO17			(1 << 17)
+#define GPIO18			(1 << 18)
+#define GPIO19			(1 << 19)
+#define GPIO20			(1 << 20)
+#define GPIO21			(1 << 21)
+#define GPIO22			(1 << 22)
+#define GPIO23			(1 << 23)
+#define GPIO24			(1 << 24)
+#define GPIO25			(1 << 25)
+#define GPIO26			(1 << 26)
+#define GPIO27			(1 << 27)
+#define GPIO28			(1 << 28)
+#define GPIO29			(1 << 29)
+#define GPIO30			(1 << 30)
+#define GPIO31			(1 << 31)
+#define GPIO_ALL		0xffff
+/**@}*/
 
-/* Direction register */
+/* GPIO mux definitions (for convenience) */
+/** @defgroup gpio_mux GPIO mux configuration
+@{*/
+enum port_mux {
+	PORT_PMUX_FUN_A = 0,
+	PORT_PMUX_FUN_B,
+	PORT_PMUX_FUN_C,
+	PORT_PMUX_FUN_D,
+	PORT_PMUX_FUN_E,
+	PORT_PMUX_FUN_F,
+	PORT_PMUX_FUN_G,
+	PORT_PMUX_FUN_H,
+	PORT_PMUX_FUN_I
+};
+/**@}*/
+
+/** @defgroup port_registers PORT Registers
+ * @{
+ */
+/** Direction register */
 #define PORT_DIR(port)			MMIO32((port) + 0x0000)
 
-/* Direction clear register */
+/** Direction clear register */
 #define PORT_DIRCLR(port)		MMIO32((port) + 0x0004)
 
-/* Direction set register */
+/** Direction set register */
 #define PORT_DIRSET(port)		MMIO32((port) + 0x0008)
 
-/* Direction toggle register */
+/** Direction toggle register */
 #define PORT_DIRTGL(port)		MMIO32((port) + 0x000c)
 
-/* output register */
+/** output register */
 #define PORT_OUT(port)			MMIO32((port) + 0x0010)
 
-/* output clear register */
+/** output clear register */
 #define PORT_OUTCLR(port)		MMIO32((port) + 0x0014)
 
-/* output set register */
+/** output set register */
 #define PORT_OUTSET(port)		MMIO32((port) + 0x0018)
 
-/* output toggle register */
+/** output toggle register */
 #define PORT_OUTTGL(port)		MMIO32((port) + 0x001c)
 
-/* input register */
+/** input register */
 #define PORT_IN(port)			MMIO32((port) + 0x0020)
 
-/* Control register */
+/** Control register */
 #define PORT_CTRL(port)			MMIO32((port) + 0x0024)
 
-/* Write configuration register */
+/** Write configuration register */
 #define PORT_WRCONFIG(port)		MMIO32((port) + 0x0028)
 
-/* Peripheral multiplexing registers */
+/** Peripheral multiplexing registers */
 #define PORT_PMUX(port, n)		MMIO8((port) + 0x0030 + (n))
 
-/* Pin configuration registers */
+/** Pin configuration registers */
 #define PORT_PINCFG(port, n)		MMIO8((port) + 0x0040 + (n))
+/**@}*/
+
+/* --- PORTx_DIR values ---------------------------------------------------- */
+
+/* PORTx_DIR[31:0]: DIRy[31:0]: Port x set bit y direction [y=0..31] */
+
+/* --- PORTx_DIRCLR values ------------------------------------------------- */
+
+/* PORTx_DIRCLR[31:0]: DIRCLRy[31:0]: Port x set bit y as input [y=0..31] */
+
+/* --- PORTx_DIRSET values ------------------------------------------------- */
+
+/* PORTx_DIRSET[31:0]: DIRSETy[31:0]: Port x set bit y as output [y=0..31] */
+
+/* --- PORTx_DIRTGL values ------------------------------------------------- */
+
+/* PORTx_DIRTGL[31:0]: DIRTGLy[31:0]: Port x toggle bit y direction [y=0..31] */
+
+/* --- PORTx_OUT values ---------------------------------------------------- */
+
+/* PORTx_OUT[31:0]: OUTy[31:0]: Port output data [y=0..31] */
+
+/* --- PORTx_OUTCLR values ------------------------------------------------- */
+
+/* PORTx_OUTCLR[31:0]: OUTCLRy[31:0]: Port x reset bit y [y=0..31] */
+
+/* --- PORTx_OUTSET values ------------------------------------------------- */
+
+/* PORTx_OUTSET[31:0]: OUTSETy[31:0]: Port x set bit y [y=0..31] */
+
+/* --- PORTx_OUTTGL values ------------------------------------------------- */
+
+/* PORTx_OUTTGL[31:0]: OUTTGLy[31:0]: Port x toggle bit y [y=0..31] */
+
+/* --- PORTx_IN values ----------------------------------------------------- */
+
+/* PORTx_IN[31:0]: INy[31:0]: Port input data [y=0..31] */
+
+/* --- PORTx_CTRL values --------------------------------------------------- */
+
+/* PORTx_CTRL[31:0]: CTRLy[31:0]: Port input sampling mode [y=0..31] */
+
+/**@defgroup port_wrconfig_values PortX WRCONFIG Values
+ * @{
+ */
+/** HWSEL: Half word select: 0 [15:0], 1 [31:16] */
+#define PORT_WRCONFIG_HWSEL         (1 << 31)
+
+/** WRPINCFG: Write PINCFG: 1 to update pins for selected by PINMASK */
+#define PORT_WRCONFIG_WRPINCFG      (1 << 30)
+
+/** WRPMUX: Write PMUX: 1 to update pins pmux for selected by PINMASK */
+#define PORT_WRCONFIG_WRPMUX        (1 << 28)
+
+/** PMUX: Peripheral Multiplexing: determine pmux for pins selected by PINMASK */
+#define PORT_WRCONFIG_PMUX(mux)     ((0xf & (mux)) << 24)
+
+/** DRVSTR: Output Driver Strength Selection: determine strength for pins in PINMASK */
+#define PORT_WRCONFIG_DRVSTR        (1 << 22)
+
+/** PULLEN: Pull Enable: enable PINCFGy.PULLEN for pins in PINMASK */
+#define PORT_WRCONFIG_PULLEN        (1 << 18)
+
+/** INEN: Input Enable: enable PINCFGy.INEN for pins in PINMASK */
+#define PORT_WRCONFIG_INEN          (1 << 17)
+
+/** PMUXEN: Peripheral Multiplexer Enable: enable PINCFGy.PMUXEN for pins in PINMASK */
+#define PORT_WRCONFIG_PMUXEN        (1 << 16)
+
+/** PINMASK: Pin Mask for Multiple Pin Configuration: select pins to be configured
+ *          [31:16] if HWSET=1, [15:0] if HWSET=0
+ */
+#define PORT_WRCONFIG_PINMASK(pins) ((0xffff & (pins)) << 0)
+/**@}*/
+
+/* --- PORTx_PMUX values --------------------------------------------------- */
+
+/** PMUXO: Peripheral Multiplexing for Odd-Numbered Pin: 2*x+1 pin multiplexing */
+#define PORT_PMUX_PMUXO(mux)        ((0xf & (mux)) << 4)
+
+/** PMUXE: Peripheral Multiplexing for Even-Numbered Pin: 2*x pin multiplexing */
+#define PORT_PMUX_PMUXE(mux)        ((0xf & (mux)) << 0)
+
+/* --- PORTx_PINCFGy values ------------------------------------------------ */
+
+/* Bit 7: Reserved */
+
+/** DRVSTR: Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (1 << 6)
+
+/** PULLEN: Pull Enable */
+#define PORT_PINCFG_PULLEN (1 << 2)
+
+/** INEN: Input Enable */
+#define PORT_PINCFG_INEN   (1 << 1)
+
+/** PMUXEN: Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (1 << 0)
+
+/* --- Convenience enums --------------------------------------------------- */
+
+/** @defgroup gpio_direction GPIO Pin direction
+@{*/
+#define GPIO_MODE_INPUT		0x00
+#define GPIO_MODE_OUTPUT	0x01
+#define GPIO_MODE_INOUT		0x02
+/**@}*/
+
+/** @defgroup gpio_cnf GPIO mode configuration
+@li Float
+@li PullDown
+@li PullUp
+@li Alternate Function
+@{*/
+#define GPIO_CNF_FLOAT		0x00
+#define GPIO_CNF_PULLDOWN	0x01
+#define GPIO_CNF_PULLUP		0x02
+#define GPIO_CNF_AF			0x03
+/**@}*/
+
+BEGIN_DECLS
+
+void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint32_t gpios);
+void gpio_set_af(uint32_t gpioport, uint8_t af, uint32_t gpios);
+void gpio_set(uint32_t gpioport, uint32_t gpios);
+void gpio_clear(uint32_t gpioport, uint32_t gpios);
+uint32_t gpio_get(uint32_t gpioport, uint32_t gpios);
+void gpio_toggle(uint32_t gpioport, uint32_t gpios);
+uint32_t port_read(uint32_t port);
+void port_write(uint32_t port, uint32_t data);
+
+END_DECLS
+
+/**@}*/

include/libopencm3/stm32/adc.h

@@ -38,6 +38,8 @@
 #       include <libopencm3/stm32/l4/adc.h>
 #elif defined(STM32G0)
 #       include <libopencm3/stm32/g0/adc.h>
+#elif defined(STM32G4)
+#       include <libopencm3/stm32/g4/adc.h>
 #else
 #       error "stm32 family not defined."
 #endif

include/libopencm3/stm32/common/adc_common_v2.h

@@ -150,9 +150,6 @@ specific memorymap.h header before including this header file.*/
 #define ADC_CFGR1_EXTEN_BOTH_EDGES	(0x3 << 10)
 /**@}*/
 
-/** ALIGN: Data alignment */
-#define ADC_CFGR1_ALIGN		(1 << 5)
-
 #define ADC_CFGR1_RES_MASK	(0x3 << 3)
 /** @defgroup adc_cfgr1_res RES: Data resolution
 @{*/

include/libopencm3/stm32/common/adc_common_v2_multi.h

@@ -58,7 +58,7 @@ specific memorymap.h header before including this header file.*/
 #define ADC_SQR4(adc)		MMIO32((adc) + 0x3C)
 
 /* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */
-#define ADC_JSQR(adc)		MMIO32((adc) + 0x30)
+#define ADC_JSQR(adc)		MMIO32((adc) + 0x4c)
 
 /* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */
 #define ADC_OFR1(adc)		MMIO32((adc) + 0x60)
@@ -143,11 +143,6 @@ specific memorymap.h header before including this header file.*/
 #define ADC_CFGR1_DISCNUM_MASK  (0x7 << ADC_CFGR1_DISCNUM_SHIFT)
 #define ADC_CFGR1_DISCNUM_VAL(x)	(((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)
 
-/* EXTSEL[3:0]: External trigger selection for regular group */
-#define ADC_CFGR1_EXTSEL_SHIFT		6
-#define ADC_CFGR1_EXTSEL_MASK		(0xf << ADC_CFGR1_EXTSEL_SHIFT)
-#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
-
 /* ADC_SQRx Values: Regular Sequence ordering------------------------------- */
 
 #define ADC_SQR1_L_SHIFT		0

include/libopencm3/stm32/common/adc_common_v2_single.h

@@ -58,11 +58,6 @@ specific memorymap.h header before including this header file.*/
 /** Auto off mode */
 #define ADC_CFGR1_AUTOFF		(1 << 15)
 
-#define ADC_CFGR1_EXTSEL_SHIFT		6
-#define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
-/** EXTSEL[2:0]: External trigger selection for regular group */
-#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
-
 /** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */
 #define ADC_CFGR1_SCANDIR		(1 << 2)
 /**@}*/

include/libopencm3/stm32/common/cordic_common_v1.h

@@ -0,0 +1,169 @@
+/** @addtogroup cordic_defines
+
+@author @htmlonly &copy; @endhtmlonly 2022 Oskar H. Maier <ohma@posteo.de>
+
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2022 Oskar H. Maier <ohma@posteo.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CORDIC.H
+The order of header inclusion is important. cordic.h includes the device
+specific memorymap.h header before including this header file.*/
+
+/** @cond */
+#ifdef LIBOPENCM3_CORDIC_H
+/** @endcond */
+#ifndef LIBOPENCM3_CORDIC_COMMON_V1_H
+#define LIBOPENCM3_CORDIC_COMMON_V1_H
+
+/** @defgroup cordic_registers CORDIC registers
+@{*/
+/* ----- CORDIC registers ----- */
+/** CORDIC control/status register */
+#define CORDIC_CSR                      MMIO32(CORDIC_BASE + 0x00)
+/** CORDIC argument register */
+#define CORDIC_WDATA                    MMIO32(CORDIC_BASE + 0x04)
+/** CORDIC result register */
+#define CORDIC_RDATA                    MMIO32(CORDIC_BASE + 0x08)
+/**@}*/
+
+/* ----- Register values ----- */
+
+/* ----- CORDIC_CSR Values ----- */
+/** @defgroup cordic_csr CSR CORDIC control/status register
+@{*/
+/** RRDY: result ready flag */
+#define CORDIC_CSR_RRDY                 (0x1 << 31)
+/** ARGSIZE: Width of input data */
+#define CORDIC_CSR_ARGSIZE              (0x1 << 22)
+/** RESSIZE: Width of result data */
+#define CORDIC_CSR_RESSIZE              (0x1 << 21)
+/** NARGS: Number of input data writes */
+#define CORDIC_CSR_NARGS                (0x1 << 20)
+/** NRES: Number of result data reads */
+#define CORDIC_CSR_NRES                 (0x1 << 19)
+/** DMAWEN: DMA write enable */
+#define CORDIC_CSR_DMAWEN               (0x1 << 18)
+/** DMAREN: DMA write enable */
+#define CORDIC_CSR_DMAREN               (0x1 << 17)
+/** DMAREN: Interrupt enable */
+#define CORDIC_CSR_IEN                  (0x1 << 16)
+
+/** @defgroup cordic_csr_scale SCALE: Scaling factor
+@{*/
+#define CORDIC_CSR_SCALE_1              (0x0)
+#define CORDIC_CSR_SCALE_2              (0x1)
+#define CORDIC_CSR_SCALE_4              (0x2)
+#define CORDIC_CSR_SCALE_8              (0x3)
+#define CORDIC_CSR_SCALE_16             (0x4)
+#define CORDIC_CSR_SCALE_32             (0x5)
+#define CORDIC_CSR_SCALE_64             (0x6)
+#define CORDIC_CSR_SCALE_128            (0x7)
+/**@}*/
+#define CORDIC_CSR_SCALE_SHIFT          (8)
+#define CORDIC_CSR_SCALE_MASK           (0x7 << CORDIC_CSR_SCALE_SHIFT)
+
+/** @defgroup cordic_csr_precision PRECISION: Precision of CORDIC operation (number of iterations)
+@{*/
+#define CORDIC_CSR_PRECISION_ITER_04    (0x1)
+#define CORDIC_CSR_PRECISION_ITER_08    (0x2)
+#define CORDIC_CSR_PRECISION_ITER_12    (0x3)
+#define CORDIC_CSR_PRECISION_ITER_16    (0x4)
+#define CORDIC_CSR_PRECISION_ITER_20    (0x5)
+#define CORDIC_CSR_PRECISION_ITER_24    (0x6)
+#define CORDIC_CSR_PRECISION_ITER_28    (0x7)
+#define CORDIC_CSR_PRECISION_ITER_32    (0x8)
+#define CORDIC_CSR_PRECISION_ITER_36    (0x9)
+#define CORDIC_CSR_PRECISION_ITER_40    (0xA)
+#define CORDIC_CSR_PRECISION_ITER_44    (0xB)
+#define CORDIC_CSR_PRECISION_ITER_48    (0xC)
+#define CORDIC_CSR_PRECISION_ITER_52    (0xD)
+#define CORDIC_CSR_PRECISION_ITER_56    (0xE)
+#define CORDIC_CSR_PRECISION_ITER_60    (0xF)
+/**@}*/
+#define CORDIC_CSR_PRECISION_SHIFT      (4)
+#define CORDIC_CSR_PRECISION_MASK       (0xF << CORDIC_CSR_PRECISION_SHIFT)
+
+/** @defgroup cordic_csr_function FUNCTION: CORDIC operation to be performed
+@{*/
+#define CORDIC_CSR_FUNC_COS             (0x0)
+#define CORDIC_CSR_FUNC_SIN             (0x1)
+#define CORDIC_CSR_FUNC_PHASE           (0x2)
+#define CORDIC_CSR_FUNC_MODULUS         (0x3)
+#define CORDIC_CSR_FUNC_ATAN            (0x4)
+#define CORDIC_CSR_FUNC_COSH            (0x5)
+#define CORDIC_CSR_FUNC_SINH            (0x6)
+#define CORDIC_CSR_FUNC_ATANH           (0x7)
+#define CORDIC_CSR_FUNC_COSINE          (0x8)
+#define CORDIC_CSR_FUNC_SQRT            (0x9)
+/**@}*/
+#define CORDIC_CSR_FUNC_SHIFT           (0)
+#define CORDIC_CSR_FUNC_MASK            (0xF << CORDIC_CSR_FUNC_SHIFT)
+
+/**@}*/
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+bool cordic_is_result_ready(void);
+void cordic_set_argument_width_32bit(void);
+void cordic_set_argument_width_16bit(void);
+void cordic_set_result_width_32bit(void);
+void cordic_set_result_width_16bit(void);
+void cordic_set_number_of_arguments_1(void);
+void cordic_set_number_of_arguments_2(void);
+void cordic_set_number_of_results_1(void);
+void cordic_set_number_of_results_2(void);
+void cordic_enable_dma_write(void);
+void cordic_disable_dma_write(void);
+void cordic_enable_dma_read(void);
+void cordic_disable_dma_read(void);
+void cordic_enable_interrupt(void);
+void cordic_set_scaling_factor(uint8_t n);
+void cordic_set_precision(uint8_t precision);
+void cordic_set_function(uint8_t function);
+void cordic_write_16bit_argument(uint16_t argument);
+void cordic_write_16bit_arguments(uint16_t argument1, uint16_t argument2);
+void cordic_write_32bit_argument(uint32_t argument);
+uint16_t cordic_read_16bit_result(void);
+void cordic_read_16bit_results(uint16_t *result1, uint16_t *result2);
+uint32_t cordic_read_32bit_result(void);
+void cordic_configure_for_cos_16bit(void);
+void cordic_configure_for_cos_32bit(void);
+void cordic_configure_for_sin_16bit(void);
+void cordic_configure_for_sin_32bit(void);
+int16_t cordic_cos_16bit(int16_t x);
+int32_t cordic_cos_32bit(int32_t x);
+int16_t cordic_sin_16bit(int16_t x);
+int32_t cordic_sin_32bit(int32_t x);
+void cordic_cos_16bit_async(int16_t x);
+void cordic_cos_32bit_async(int32_t x);
+void cordic_sin_16bit_async(int16_t x);
+void cordic_sin_32bit_async(int32_t x);
+END_DECLS
+
+#endif
+/** @cond */
+#endif
+/** @endcond */
+/**@}*/

include/libopencm3/stm32/common/crc_common_all.h

@@ -27,12 +27,7 @@
 The order of header inclusion is important. crc.h includes the device
 specific memorymap.h header before including this header file.*/
 
-/** @cond */
+#pragma once
-#ifdef LIBOPENCM3_CRC_H
-/** @endcond */
-#ifndef LIBOPENCM3_CRC_COMMON_ALL_H
-#define LIBOPENCM3_CRC_COMMON_ALL_H
-
 /**@{*/
 
 /*****************************************************************************/
@@ -53,7 +48,7 @@ specific memorymap.h header before including this header file.*/
 
 /** CRC_CR Control register */
 #define CRC_CR				MMIO32(CRC_BASE + 0x08)
-/*@}*/
+/**@}*/
 
 /*****************************************************************************/
 /* Register values                                                           */
@@ -76,17 +71,8 @@ specific memorymap.h header before including this header file.*/
 #define CRC_CR_RESET			(1 << 0)
 /**@}*/
 
-/*****************************************************************************/
-/* API definitions                                                           */
-/*****************************************************************************/
-
-/*****************************************************************************/
-/* API Functions                                                             */
-/*****************************************************************************/
-
 BEGIN_DECLS
 
-/* TODO */
 
 /**
  * Reset the CRC calculator to initial values.
@@ -115,11 +101,3 @@ uint32_t crc_calculate_block(uint32_t *datap, int size);
 END_DECLS
 
 /**@}*/
-
-#endif
-/** @cond */
-#else
-#warning "crc_common_all.h should not be included explicitly, only via crc.h"
-#endif
-/** @endcond */
-

include/libopencm3/stm32/common/crs_common_all.h

@@ -1,10 +1,4 @@
-/** @defgroup CRS_defines CRS Defines
+/** @addtogroup crs_defines
- *
- * @brief <b>STM32 Clock Recovery System: Defined Constants and Types</b>
- *
- * @ingroup STM32_defines
- *
- * @version 1.0.0
  *
  * @date 5 Feb 2014
  *

include/libopencm3/stm32/common/dac_common_all.h

@@ -2,6 +2,8 @@
 
 @author @htmlonly © @endhtmlonly 2012
 Felix Held <felix-libopencm3@felixheld.de>
+@author @htmlonly &copy; @endhtmlonly 2020
+Ben Brewer <ben.brewer@codethink.co.uk>
 
 */
 
@@ -9,6 +11,7 @@ Felix Held <felix-libopencm3@felixheld.de>
  * This file is part of the libopencm3 project.
  *
  * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ * Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
  *
  * This library is free software: you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
@@ -36,391 +39,236 @@ specific memorymap.h header before including this header file.*/
 #ifndef LIBOPENCM3_DAC_COMMON_ALL_H
 #define LIBOPENCM3_DAC_COMMON_ALL_H
 
-/* --- DAC registers ------------------------------------------------------- */
+/**@defgroup dac_registers DAC Registers
+ @{*/
 
-/* DAC control register (DAC_CR) */
+/** DAC control register (DAC_CR) */
-#define DAC_CR				MMIO32(DAC_BASE + 0x00)
+#define DAC_CR(dac)			MMIO32((dac) + 0x00)
 
-/* DAC software trigger register (DAC_SWTRIGR) */
+/** DAC software trigger register (DAC_SWTRIGR) */
-#define DAC_SWTRIGR			MMIO32(DAC_BASE + 0x04)
+#define DAC_SWTRIGR(dac)		MMIO32((dac) + 0x04)
 
-/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
+/** DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
-#define DAC_DHR12R1			MMIO32(DAC_BASE + 0x08)
+#define DAC_DHR12R1(dac)		MMIO32((dac) + 0x08)
 
-/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
+/** DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
-#define DAC_DHR12L1			MMIO32(DAC_BASE + 0x0C)
+#define DAC_DHR12L1(dac)		MMIO32((dac) + 0x0C)
 
-/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
+/** DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
-#define DAC_DHR8R1			MMIO32(DAC_BASE + 0x10)
+#define DAC_DHR8R1(dac)			MMIO32((dac) + 0x10)
 
-/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
+/** DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
-#define DAC_DHR12R2			MMIO32(DAC_BASE + 0x14)
+#define DAC_DHR12R2(dac)		MMIO32((dac) + 0x14)
 
-/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
+/** DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
-#define DAC_DHR12L2			MMIO32(DAC_BASE + 0x18)
+#define DAC_DHR12L2(dac)		MMIO32((dac) + 0x18)
 
-/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
+/** DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
-#define DAC_DHR8R2			MMIO32(DAC_BASE + 0x1C)
+#define DAC_DHR8R2(dac)			MMIO32((dac) + 0x1C)
 
-/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
+/** Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
-#define DAC_DHR12RD			MMIO32(DAC_BASE + 0x20)
+#define DAC_DHR12RD(dac)		MMIO32((dac) + 0x20)
 
-/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
+/** DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
-#define DAC_DHR12LD			MMIO32(DAC_BASE + 0x24)
+#define DAC_DHR12LD(dac)		MMIO32((dac) + 0x24)
 
-/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
+/** DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
-#define DAC_DHR8RD			MMIO32(DAC_BASE + 0x28)
+#define DAC_DHR8RD(dac)			MMIO32((dac) + 0x28)
 
-/* DAC channel1 data output register (DAC_DOR1) */
+/** DAC channel1 data output register (DAC_DOR1) */
-#define DAC_DOR1			MMIO32(DAC_BASE + 0x2C)
+#define DAC_DOR1(dac)			MMIO32((dac) + 0x2C)
 
-/* DAC channel2 data output register (DAC_DOR2) */
+/** DAC channel2 data output register (DAC_DOR2) */
-#define DAC_DOR2			MMIO32(DAC_BASE + 0x30)
+#define DAC_DOR2(dac)			MMIO32((dac) + 0x30)
 
 /** DAC status register.
  * @note not available on F1
  */
-#define DAC_SR				MMIO32(DAC_BASE + 0x34)
+#define DAC_SR(dac)			MMIO32((dac) + 0x34)
 
-/* --- DAC_CR values ------------------------------------------------------- */
+/**@}*/
 
-/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
+/** @defgroup dac_cr_values DAC_CR values
-/* doesn't exist in most members of the STM32F1 family */
+ * @{
+ */
+
+/** DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
+ * @note doesn't exist in most members of the STM32F1 family
+ */
 #define DAC_CR_DMAUDRIE2		(1 << 29)
 
-/* DMAEN2: DAC channel2 DMA enable */
+/** DMAEN2: DAC channel2 DMA enable */
 #define DAC_CR_DMAEN2			(1 << 28)
 
-/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
+/** MAMP2[3:0]: DAC channel2 mask/amplitude selector field position */
-/* DAC_CR_MAMP2_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
 #define DAC_CR_MAMP2_SHIFT		24
-/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude
-values
-@ingroup dac_defines
 
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
+/** Wave generation mode mask size */
-@{*/
+#define DAC_CR_WAVEx_MASK		0x3
-#define DAC_CR_MAMP2_1			(0x0 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_2			(0x1 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_3			(0x2 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_4			(0x3 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_5			(0x4 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_6			(0x5 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_7			(0x6 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_8			(0x7 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_9			(0x8 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_10			(0x9 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_11			(0xA << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_12			(0xB << DAC_CR_MAMP2_SHIFT)
-/**@}*/
 
-/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
+/** WAVE2[1:0]: DAC channel2 wave generation mode*/
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- */
 #define DAC_CR_WAVE2_SHIFT		22
-#define DAC_CR_WAVE2_DIS		(0x3 << DAC_CR_WAVE2_SHIFT)
-/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
-@ingroup dac_defines
 
-@li NOISE: Noise wave generation enabled
+/** EN2: DAC channel2 enable */
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE2_NOISE		(0x1 << DAC_CR_WAVE2_SHIFT)
-#define DAC_CR_WAVE2_TRI		(0x2 << DAC_CR_WAVE2_SHIFT)
-/**@}*/
-
-/* TSEL2[2:0]: DAC channel2 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event
- * T8: Timer 8 TRGO event
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL2_SHIFT		19
-/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
-@ingroup dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
-@{*/
-#define DAC_CR_TSEL2_T6			(0x0 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T3			(0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T8			(0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T7			(0x2 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T5			(0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T15		(0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T2			(0x4 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_SW			(0x7 << DAC_CR_TSEL2_SHIFT)
-/**@}*/
-
-/* TEN2: DAC channel2 trigger enable */
-#define DAC_CR_TEN2			(1 << 18)
-
-/* BOFF2: DAC channel2 output buffer disable */
-#define DAC_CR_BOFF2			(1 << 17)
-
-/* EN2: DAC channel2 enable */
 #define DAC_CR_EN2			(1 << 16)
 
-/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
+/** DMAUDRIE1: DAC channel1 DMA underrun interrupt enable
-/* doesn't exist in most members of the STM32F1 family */
+ * @note doesn't exist in most members of the STM32F1 family
+ */
 #define DAC_CR_DMAUDRIE1		(1 << 13)
 
-/* DMAEN1: DAC channel1 DMA enable */
+/** DMAEN1: DAC channel1 DMA enable */
 #define DAC_CR_DMAEN1			(1 << 12)
 
-/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
+/** MAMP1[3:0]: DAC channel1 mask/amplitude selector field position */
-/* DAC_CR_MAMP1_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
 #define DAC_CR_MAMP1_SHIFT		8
-/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude
+/** MAMP Mask/Amplitude selector field size */
-values
+#define DAC_CR_MAMPx_MASK		0xf
-@ingroup dac_defines
 
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
+/** WAVE1[1:0]: DAC channel1 wave generation mode */
-@{*/
-#define DAC_CR_MAMP1_1			(0x0 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_2			(0x1 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_3			(0x2 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_4			(0x3 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_5			(0x4 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_6			(0x5 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_7			(0x6 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_8			(0x7 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_9			(0x8 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_10			(0x9 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_11			(0xA << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_12			(0xB << DAC_CR_MAMP1_SHIFT)
-/**@}*/
-
-/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- */
 #define DAC_CR_WAVE1_SHIFT		6
-#define DAC_CR_WAVE1_DIS		(0x3 << DAC_CR_WAVE1_SHIFT)
-/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
-@ingroup dac_defines
 
-@li DIS: wave generation disabled
+/** EN1: DAC channel1 enable */
-@li NOISE: Noise wave generation enabled
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE1_NOISE		(0x1 << DAC_CR_WAVE1_SHIFT)
-#define DAC_CR_WAVE1_TRI		(0x2 << DAC_CR_WAVE1_SHIFT)
-/**@}*/
-
-/* TSEL1[2:0]: DAC channel1 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event in connectivity line devices
- * T8: Timer 8 TRGO event in high-density and XL-density devices
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL1_SHIFT		3
-/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
-@ingroup dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line 9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
-@{*/
-#define DAC_CR_TSEL1_T6			(0x0 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T3			(0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T8			(0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T7			(0x2 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T5			(0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T15		(0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T2			(0x4 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_SW			(0x7 << DAC_CR_TSEL1_SHIFT)
-/**@}*/
-
-/* TEN1: DAC channel1 trigger enable */
-#define DAC_CR_TEN1			(1 << 2)
-
-/* BOFF1: DAC channel1 output buffer disable */
-#define DAC_CR_BOFF1			(1 << 1)
-
-/* EN1: DAC channel1 enable */
 #define DAC_CR_EN1			(1 << 0)
+/**@}*/
 
-
+/**@defgroup dac_swtrigr_values DAC_SWTRIGR Values
-/* --- DAC_SWTRIGR values -------------------------------------------------- */
+ * @{
-
+ */
-/* SWTRIG2: DAC channel2 software trigger */
+/** SWTRIG2: DAC channel2 software trigger */
 #define DAC_SWTRIGR_SWTRIG2		(1 << 1)
 
-/* SWTRIG1: DAC channel1 software trigger */
+/** SWTRIG1: DAC channel1 software trigger */
 #define DAC_SWTRIGR_SWTRIG1		(1 << 0)
+/**@}*/
 
 
+/**@defgroup dac_dhrxxx_values DAC_DHRxxx Values
+ * @{
+ */
 /* --- DAC_DHR12R1 values -------------------------------------------------- */
-#define DAC_DHR12R1_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12R1_DACC1DHR_SHIFT	0
-#define DAC_DHR12R1_DACC1DHR_MSK	(0x0FFF << 0)
+#define DAC_DHR12R1_DACC1DHR_MASK	0xFFF
 
 
 /* --- DAC_DHR12L1 values -------------------------------------------------- */
-#define DAC_DHR12L1_DACC1DHR_LSB	(1 << 4)
+#define DAC_DHR12L1_DACC1DHR_SHIFT	4
-#define DAC_DHR12L1_DACC1DHR_MSK	(0x0FFF << 4)
+#define DAC_DHR12L1_DACC1DHR_MASK	0xFFF
 
 
 /* --- DAC_DHR8R1 values --------------------------------------------------- */
-#define DAC_DHR8R1_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8R1_DACC1DHR_SHIFT	0
-#define DAC_DHR8R1_DACC1DHR_MSK		(0x00FF << 0)
+#define DAC_DHR8R1_DACC1DHR_MASK	0xFF
 
 
 /* --- DAC_DHR12R2 values -------------------------------------------------- */
-#define DAC_DHR12R2_DACC2DHR_LSB	(1 << 0)
+#define DAC_DHR12R2_DACC2DHR_SHIFT	0
-#define DAC_DHR12R2_DACC2DHR_MSK	(0x00FFF << 0)
+#define DAC_DHR12R2_DACC2DHR_MASK	0xFFF
 
 
 /* --- DAC_DHR12L2 values -------------------------------------------------- */
-#define DAC_DHR12L2_DACC2DHR_LSB	(1 << 4)
+#define DAC_DHR12L2_DACC2DHR_SHIFT	4
-#define DAC_DHR12L2_DACC2DHR_MSK	(0x0FFF << 4)
+#define DAC_DHR12L2_DACC2DHR_MASK	0xFFF
 
 
 /* --- DAC_DHR8R2 values --------------------------------------------------- */
-#define DAC_DHR8R2_DACC2DHR_LSB		(1 << 0)
+#define DAC_DHR8R2_DACC2DHR_SHIFT	0
-#define DAC_DHR8R2_DACC2DHR_MSK		(0x00FF << 0)
+#define DAC_DHR8R2_DACC2DHR_MASK	0xFF
 
 
 /* --- DAC_DHR12RD values -------------------------------------------------- */
-#define DAC_DHR12RD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12RD_DACC2DHR_SHIFT	16
-#define DAC_DHR12RD_DACC2DHR_MSK	(0x0FFF << 16)
+#define DAC_DHR12RD_DACC2DHR_MASK	0xFFF
-#define DAC_DHR12RD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12RD_DACC1DHR_SHIFT	0
-#define DAC_DHR12RD_DACC1DHR_MSK	(0x0FFF << 0)
+#define DAC_DHR12RD_DACC1DHR_MSK	0xFFF
 
 
 /* --- DAC_DHR12LD values -------------------------------------------------- */
-#define DAC_DHR12LD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12LD_DACC2DHR_SHIFT	16
-#define DAC_DHR12LD_DACC2DHR_MSK	(0x0FFF << 20)
+#define DAC_DHR12LD_DACC2DHR_MSK	0xFFF
-#define DAC_DHR12LD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12LD_DACC1DHR_SHIFT	0
-#define DAC_DHR12LD_DACC1DHR_MSK	(0x0FFF << 4)
+#define DAC_DHR12LD_DACC1DHR_MSK	0xFFF
 
 
 /* --- DAC_DHR8RD values --------------------------------------------------- */
-#define DAC_DHR8RD_DACC2DHR_LSB		(1 << 8)
+#define DAC_DHR8RD_DACC2DHR_SHIFT	8
-#define DAC_DHR8RD_DACC2DHR_MSK		(0x00FF << 8)
+#define DAC_DHR8RD_DACC2DHR_MSK		0xFF
-#define DAC_DHR8RD_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8RD_DACC1DHR_SHIFT	0
-#define DAC_DHR8RD_DACC1DHR_MSK		(0x00FF << 0)
+#define DAC_DHR8RD_DACC1DHR_MSK		0xFF
+/**@}*/
 
 
+/**@defgroup dac_dorx_values DAC_DORx Values
+ * @{
+ */
 /* --- DAC_DOR1 values ----------------------------------------------------- */
-#define DAC_DOR1_DACC1DOR_LSB		(1 << 0)
+#define DAC_DOR1_DACC1DOR_SHIFT		0
-#define DAC_DOR1_DACC1DOR_MSK		(0x0FFF << 0)
+#define DAC_DOR1_DACC1DOR_MSK		0xFFF
 
 
 /* --- DAC_DOR2 values ----------------------------------------------------- */
-#define DAC_DOR2_DACC2DOR_LSB		(1 << 0)
+#define DAC_DOR2_DACC2DOR_SHIFT		0
-#define DAC_DOR2_DACC2DOR_MSK		(0x0FFF << 0)
+#define DAC_DOR2_DACC2DOR_MSK		0xFFF
+
+/**@}*/
 
 /**@defgroup dac_sr_values DAC_SR Values
-@{*/
+ * @{
+ */
 /** DAC channel 1 DMA underrun flag */
 #define DAC_SR_DMAUDR1			(1 << 13)
 
 /** DAC channel 2 DMA underrun flag */
 #define DAC_SR_DMAUDR2			(1 << 29)
-/*@}*/
+/**@}*/
-
-/** DAC channel identifier */
-typedef enum {
-	CHANNEL_1, CHANNEL_2, CHANNEL_D
-} data_channel;
-
-/** DAC data size (8/12 bits), alignment (right/left) */
-typedef enum {
-	RIGHT8, RIGHT12, LEFT12
-} data_align;
 
 /* --- Function prototypes ------------------------------------------------- */
 
+/** @defgroup dac_channel_id DAC Channel Identifier
+ * @note Not all parts have two channels, notably, some of the smaller F0's
+ * @{
+ */
+#define DAC_CHANNEL1		(1 << 0)
+#define DAC_CHANNEL2		(1 << 1)
+#define DAC_CHANNEL_BOTH	(DAC_CHANNEL1 | DAC_CHANNEL2)
+/**@}*/
+
+/** DAC data size (8/12 bits), alignment (right/left) */
+enum dac_align {
+	DAC_ALIGN_RIGHT8,
+	DAC_ALIGN_RIGHT12,
+	DAC_ALIGN_LEFT12,
+};
+
+/** DAC waveform generation options.
+ * Not all wave shapes are available on all parts.
+ */
+enum dac_wave {
+	DAC_WAVE_DISABLE  = 0,
+	DAC_WAVE_NOISE    = 1,
+	DAC_WAVE_TRIANGLE = 2,
+	DAC_WAVE_SAWTOOTH = 3,
+};
+
 BEGIN_DECLS
 
-void dac_enable(data_channel dac_channel);
+void dac_enable(uint32_t dac, int channel);
-void dac_disable(data_channel dac_channel);
+void dac_disable(uint32_t dac, int channel);
-void dac_buffer_enable(data_channel dac_channel);
+void dac_buffer_enable(uint32_t dac, int channel);
-void dac_buffer_disable(data_channel dac_channel);
+void dac_buffer_disable(uint32_t dac, int channel);
-void dac_dma_enable(data_channel dac_channel);
+void dac_dma_enable(uint32_t dac, int channel);
-void dac_dma_disable(data_channel dac_channel);
+void dac_dma_disable(uint32_t dac, int channel);
-void dac_trigger_enable(data_channel dac_channel);
+void dac_trigger_enable(uint32_t dac, int channel);
-void dac_trigger_disable(data_channel dac_channel);
+void dac_trigger_disable(uint32_t dac, int channel);
-void dac_set_trigger_source(uint32_t dac_trig_src);
+void dac_set_trigger_source(uint32_t dac, uint32_t source);
-void dac_set_waveform_generation(uint32_t dac_wave_ens);
+void dac_set_waveform_generation(uint32_t dac, int channel, enum dac_wave wave);
-void dac_disable_waveform_generation(data_channel dac_channel);
+void dac_disable_waveform_generation(uint32_t dac, int channel);
-void dac_set_waveform_characteristics(uint32_t dac_mamp);
+void dac_set_waveform_characteristics(uint32_t dac, int channel, int mamp);
-void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
+void dac_load_data_buffer_single(uint32_t dac, uint16_t data,
-				 data_channel dac_channel);
+                                 enum dac_align align, int channel);
-void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
+void dac_load_data_buffer_dual(uint32_t dac, uint16_t data1, uint16_t data2,
-			       data_align dac_data_format);
+			       enum dac_align align);
-void dac_software_trigger(data_channel dac_channel);
+void dac_software_trigger(uint32_t dac, int channel);
 
 END_DECLS
 

include/libopencm3/stm32/common/dac_common_v1.h

@@ -0,0 +1,139 @@
+/** @addtogroup dac_defines
+
+@author @htmlonly © @endhtmlonly 2020
+Ben Brewer <ben.brewer@codethink.co.uk>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
+The order of header inclusion is important. dac.h includes the device
+specific memorymap.h header before including this header file.*/
+
+/** @cond */
+#ifdef LIBOPENCM3_DAC_H
+/** @endcond */
+#ifndef LIBOPENCM3_DAC_COMMON_V1_H
+#define LIBOPENCM3_DAC_COMMON_V1_H
+
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+/**@addtogroup dac_cr_values
+ * @{
+ */
+
+/** TSEL2[2:0]: DAC channel2 trigger selection */
+#define DAC_CR_TSEL2_SHIFT		19
+/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
+@ingroup dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
+@{*/
+#define DAC_CR_TSEL2_T6			(0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7			(0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T5			(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15		(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2			(0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_SW			(0x7 << DAC_CR_TSEL2_SHIFT)
+/**@}*/
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2			(1 << 18)
+
+/* BOFF2: DAC channel2 output buffer disable */
+#define DAC_CR_BOFF2			(1 << 17)
+
+/* TSEL1[2:0]: DAC channel1 trigger selection */
+#define DAC_CR_TSEL1_SHIFT		3
+/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
+@ingroup dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line 9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN1 is set (DAC channel 1 trigger enabled).
+@{*/
+#define DAC_CR_TSEL1_T6			(0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7			(0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T5			(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15		(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2			(0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_SW			(0x7 << DAC_CR_TSEL1_SHIFT)
+/**@}*/
+
+/* TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1			(1 << 2)
+
+/* BOFF1: DAC channel1 output buffer disable */
+#define DAC_CR_BOFF1			(1 << 1)
+
+/**@}*/
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+END_DECLS
+
+#endif
+/** @cond */
+#else
+#warning "dac_common_v1.h should not be included explicitly, only via dac.h"
+#endif
+/** @endcond */
+
+/**@}*/
+

include/libopencm3/stm32/common/dac_common_v2.h

@@ -0,0 +1,589 @@
+/** @addtogroup dac_defines
+
+@author @htmlonly © @endhtmlonly 2020
+Ben Brewer <ben.brewer@codethink.co.uk>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
+The order of header inclusion is important. dac.h includes the device
+specific memorymap.h header before including this header file.*/
+
+/** @cond */
+#ifdef LIBOPENCM3_DAC_H
+/** @endcond */
+#ifndef LIBOPENCM3_DAC_COMMON_V2_H
+#define LIBOPENCM3_DAC_COMMON_V2_H
+
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+/**@addtogroup dac_registers
+ @{*/
+
+/** DAC calibration control register (DAC_CCR) */
+#define DAC_CCR(dac)			MMIO32((dac) + 0x38)
+
+/** DAC mode control register (DAC_MCR) */
+#define DAC_MCR(dac)			MMIO32((dac) + 0x3C)
+
+/** DAC channel1 sample and hold sample time register (DAC_SHSR1) */
+#define DAC_SHSR1(dac)			MMIO32((dac) + 0x40)
+
+/** DAC channel2 sample and hold sample time register (DAC_SHSR2) */
+#define DAC_SHSR2(dac)			MMIO32((dac) + 0x44)
+
+/** DAC sample and hold time register (DAC_SHHR) */
+#define DAC_SHHR(dac)			MMIO32((dac) + 0x48)
+
+/** DAC sample and hold refresh time register (DAC_SHRR) */
+#define DAC_SHRR(dac)			MMIO32((dac) + 0x4C)
+
+/** DAC channel1 sawtooth register (DAC_STR1) */
+#define DAC_STR1(dac)			MMIO32((dac) + 0x58)
+
+/** DAC channel2 sawtooth register (DAC_STR2) */
+#define DAC_STR2(dac)			MMIO32((dac) + 0x5C)
+
+/** DAC sawtooth mode register (DAC_STMODR) */
+#define DAC_STMODR(dac)			MMIO32((dac) + 0x60)
+/**@}*/
+
+/**@addtogroup dac_cr_values
+ * @{
+ */
+
+/** CEN2: DAC channel2 calibration enable */
+#define DAC_CR_CEN2			(1 << 30)
+
+/* TSEL2[3:0]: DAC channel2 trigger selection */
+#define DAC_CR_TSEL2_SHIFT		18
+/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
+@ingroup dac_defines
+
+@li SW: Software trigger
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line 9
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li HRR1: hrtim_dac_reset_trg1
+@li HRR2: hrtim_dac_reset_trg2
+@li HRR3: hrtim_dac_reset_trg3
+@li HRR4: hrtim_dac_reset_trg4
+@li HRR5: hrtim_dac_reset_trg5
+@li HRR6: hrtim_dac_reset_trg6
+@li HR2: hrtim_dac_trg2
+
+@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
+@{*/
+#define DAC_CR_TSEL2_SW			(0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7			(0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15		(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2			(0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T6			(0x7 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3			(0x8 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR1		(0x9 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR2		(0xA << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR3		(0xB << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR4		(0xC << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR5		(0xD << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HRR6		(0xE << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_HR2		(0xF << DAC_CR_TSEL2_SHIFT)
+/**@}*/
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2			(1 << 17)
+
+/* CEN1: DAC channel1 calibration enable */
+#define DAC_CR_CEN1			(1 << 14)
+
+/* TSEL1[3:0]: DAC channel1 trigger selection */
+#define DAC_CR_TSEL1_SHIFT		2
+/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
+@ingroup dac_defines
+
+@li CK: ck_lsi or ck_lse (selected in the RCC)
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event in connectivity line devices
+@li T15: Timer 15 TRGO event in high-density and XL-density devices
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line9
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li HRR1: hrtim_dac_reset_trg1
+@li HRR2: hrtim_dac_reset_trg2
+@li HRR3: hrtim_dac_reset_trg3
+@li HRR4: hrtim_dac_reset_trg4
+@li HRR5: hrtim_dac_reset_trg5
+@li HRR6: hrtim_dac_reset_trg6
+@li HR2: hrtim_dac_trg2
+
+@note: only used if bit TEN1 is set (DAC channel 1 trigger enabled).
+@{*/
+#define DAC_CR_TSEL1_CK			(0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7			(0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15		(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2			(0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T6			(0x7 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3			(0x8 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR1		(0x9 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR2		(0xA << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR3		(0xB << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR4		(0xC << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR5		(0xD << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HRR6		(0xE << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_HR3		(0xF << DAC_CR_TSEL1_SHIFT)
+/**@}*/
+
+/** TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1			(1 << 1)
+/**@}*/
+
+
+/** @addtogroup dac_swtrigr_values
+ * @{
+ */
+/** SWTRIG2: DAC channel2 software trigger B */
+#define DAC_SWTRIGR_SWTRIGB2		(1 << 17)
+
+/** SWTRIG1: DAC channel1 software trigger B */
+#define DAC_SWTRIGR_SWTRIGB1		(1 << 16)
+/**@}*/
+
+/** @addtogroup dac_dorx_values
+ * @{
+ */
+/* --- DAC_DOR1 values ----------------------------------------------------- */
+#define DAC_DOR1_DACC1DORB_SHIFT	16
+#define DAC_DOR1_DACC1DORB_MASK		0xFFF
+
+
+/* --- DAC_DOR2 values ----------------------------------------------------- */
+#define DAC_DOR2_DACC2DORB_SHIFT	16
+#define DAC_DOR2_DACC2DORB_MASK		0xFFF
+/**@}*/
+
+/** @addtogroup dac_sr_values
+ * @{
+ */
+/** DAC channel2 busy writing sample time flag */
+#define DAC_SR_BWST2			(1 << 31)
+
+/** DAC channel2 calibration offset status */
+#define DAC_SR_CAL_FLAG2		(1 << 30)
+
+/** DAC channel2 DMA underrun flag */
+#define DAC_SR_DMAUDR2			(1 << 29)
+
+/** DAC channel2 output register status bit */
+#define DAC_SR_DORSTAT2			(1 << 28)
+
+/** DAC channel2 ready status bit */
+#define DAC_SR_DAC2RDY			(1 << 27)
+
+/** DAC channel1 busy writing sample time flag */
+#define DAC_SR_BWST1			(1 << 15)
+
+/** DAC channel1 calibration offset status */
+#define DAC_SR_CAL_FLAG1		(1 << 14)
+
+/** DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR1			(1 << 13)
+
+/** DAC channel1 output register status bit */
+#define DAC_SR_DORSTAT1			(1 << 12)
+
+/** DAC channel1 ready status bit */
+#define DAC_SR_DAC1RDY			(1 << 11)
+/**@}*/
+
+
+/**@defgroup dac_ccr_values DAC_CCR values
+ * @{
+ */
+/* DAC channel2 offset trimming value */
+#define DAC_CCR_OTRIM2_SHIFT		16
+#define DAC_CCR_OTRIM2_MASK		0x1F
+
+/* DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM1_SHIFT		0
+#define DAC_CCR_OTRIM1_MASK		0x1F
+/**@}*/
+
+/* --- DAC_MCR values ----------------------------------------------------- */
+
+/**@defgroup dac_mcr_values DAC_MCR values
+ * @{
+ */
+/** Enable signed format for DAC channel2 */
+#define DAC_MCR_SINFORMAT2		(1 << 25)
+
+/** DAC channel2 DMA double data mode */
+#define DAC_MCR_DMADOUBLE2		(1 << 24)
+
+/** MODE2[2:0]: DAC channel2 mode */
+#define DAC_MCR_MODE2_SHIFT		16
+/** @defgroup dac_mode2_sel DAC Channel 2 Mode Selection
+@ingroup dac_defines
+
+@li E_BUFF: External pin with buffer enabled
+@li EP_BUFF: External pin and on-chip peripherals with buffer
+@li E: External pin without buffer
+@li EP: External pin and on-chip peripherals without buffer
+@li SH_E_BUFF: Sample & Hold, External pin with buffer enabled
+@li SH_EP_BUFF: Sample & Hold, External pin and on-chip peripherals with buffer
+@li SH_E: Sample & Hold, External pin without buffer
+@li SH_EP: Sample & Hold, External pin and on-chip peripherals without buffer
+@{*/
+#define DAC_MCR_MODE2_E_BUFF		(0x0 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_EP_BUFF		(0x1 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_E			(0x2 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_EP		(0x3 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_SH_E_BUFF		(0x4 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_SH_EP_BUFF	(0x5 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_SH_E		(0x6 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_SH_EP		(0x7 << DAC_MCR_MODE2_SHIFT)
+/**@}*/
+
+#define DAC_MCR_MODE2_PERIPHERAL	(0x1 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_UNBUFFERED	(0x2 << DAC_MCR_MODE2_SHIFT)
+#define DAC_MCR_MODE2_SAMPLEHOLD	(0x4 << DAC_MCR_MODE2_SHIFT)
+
+/* HFSEL[1:0]: High frequency interface mode selection */
+#define DAC_MCR_HFSEL_SHIFT		14
+#define DAC_MCR_HFSEL_MASK		0x3
+/** @defgroup dac_hfsel High frequency interface mode selection
+@ingroup dac_defines
+
+@li DIS: High frequency mode disabled
+@li AHB80: High frequency interface mode compatible to AHB>80MHz enabled
+@li AHB160: High frequency interface mode compatible to AHB>160MHz enabled
+@{*/
+#define DAC_MCR_HFSEL_DIS		(0x0 << DAC_MCR_HFSEL_SHIFT)
+#define DAC_MCR_HFSEL_AHB80		(0x1 << DAC_MCR_HFSEL_SHIFT)
+#define DAC_MCR_HFSEL_AHB160		(0x2 << DAC_MCR_HFSEL_SHIFT)
+/**@}*/
+
+/** Enable signed format for DAC channel1 */
+#define DAC_MCR_SINFORMAT1		(1 << 9)
+
+/** DAC channel1 DMA double data mode */
+#define DAC_MCR_DMADOUBLE1		(1 << 8)
+
+/* MODE1[2:0]: DAC channel1 mode */
+#define DAC_MCR_MODE1_SHIFT		0
+/** @defgroup dac_mode1_sel DAC Channel 1 Mode Selection
+@ingroup dac_defines
+
+@li E_BUFF: External pin with buffer enabled
+@li EP_BUFF: External pin and on-chip peripherals with buffer
+@li E: External pin without buffer
+@li EP: External pin and on-chip peripherals without buffer
+@li SH_E_BUFF: Sample & Hold, External pin with buffer enabled
+@li SH_EP_BUFF: Sample & Hold, External pin and on-chip peripherals with buffer
+@li SH_E: Sample & Hold, External pin without buffer
+@li SH_EP: Sample & Hold , External pin and on-chip peripherals without buffer
+@{*/
+#define DAC_MCR_MODE1_E_BUFF		(0x0 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_EP_BUFF		(0x1 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_E			(0x2 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_EP		(0x3 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_SH_E_BUFF		(0x4 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_SH_EP_BUFF	(0x5 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_SH_E		(0x6 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_SH_EP		(0x7 << DAC_MCR_MODE1_SHIFT)
+/**@}*/
+
+#define DAC_MCR_MODE1_PERIPHERAL	(0x1 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_UNBUFFERED	(0x2 << DAC_MCR_MODE1_SHIFT)
+#define DAC_MCR_MODE1_SAMPLEHOLD	(0x4 << DAC_MCR_MODE1_SHIFT)
+/**@}*/
+
+/* --- DAC_SHSR1 values ----------------------------------------------------- */
+
+/* DAC channel1 sample time (only valid in Sample and hold mode) */
+#define DAC_SHSR1_TSAMPLE1_SHIFT	0
+#define DAC_SHSR1_TSAMPLE1_MASK		0x1FF
+
+/* --- DAC_SHSR2 values ----------------------------------------------------- */
+
+/* DAC channel2 sample time (only valid in Sample and hold mode) */
+#define DAC_SHSR2_TSAMPLE2_SHIFT	0
+#define DAC_SHSR2_TSAMPLE2_MASK		0x1FF
+
+/* --- DAC_SHHR values ----------------------------------------------------- */
+
+/* DAC channel2 hold time (only valid in Sample and hold mode) */
+#define DAC_SHHSR_THOLD2_SHIFT		16
+#define DAC_SHHSR_THOLD2_MASK		0x1FF
+
+/* DAC channel1 hold time (only valid in Sample and hold mode) */
+#define DAC_SHHSR_THOLD1_SHIFT		0
+#define DAC_SHHSR_THOLD1_MASK		0x1FF
+
+/* --- DAC_STR1 values ----------------------------------------------------- */
+
+/* DAC channel1 sawtooth increment value (12.4 bit format) */
+#define DAC_STR1_STINCDATA1_SHIFT	16
+#define DAC_STR1_STINCDATA1_MASK	0xFFFF
+
+/* STDIR1: DAC channel1 sawtooth direction setting */
+#define DAC_STR1_STDIR1_SHIFT		12
+/** @defgroup dac_stdir1 DAC Channel 1 Sawtooth Direction Setting
+@ingroup dac_defines
+
+@li DEC: Decrement
+@li INC: Increment
+@{*/
+#define DAC_STR1_STDIR1_DEC		(0x0 << DAC_STR_STDIR1_SHIFT)
+#define DAC_STR1_STDIR1_INC		(0x1 << DAC_STR_STDIR1_SHIFT)
+/**@}*/
+
+/* DAC channel1 sawtooth reset value */
+#define DAC_STR1_STRSTDATA1_SHIFT	0
+#define DAC_STR1_STRSTDATA1_MASK	0xFFF
+
+/* --- DAC_STR2 values ----------------------------------------------------- */
+
+/* DAC channel2 sawtooth increment value (12.4 bit format) */
+#define DAC_STR2_STINCDATA2_SHIFT	16
+#define DAC_STR2_STINCDATA2_MASK	0xFFFF
+
+/* STDIR1: DAC channel2 sawtooth direction setting */
+#define DAC_STR2_STDIR2_SHIFT		12
+/** @defgroup dac_stdir2 DAC Channel 2 Sawtooth Direction Setting
+@ingroup dac_defines
+
+@li DEC: Decrement
+@li INC: Increment
+@{*/
+#define DAC_STR2_STDIR2_DEC		(0x0 << DAC_STR_STDIR2_SHIFT)
+#define DAC_STR2_STDIR2_INC		(0x1 << DAC_STR_STDIR2_SHIFT)
+/**@}*/
+
+/* DAC channel1 sawtooth reset value */
+#define DAC_STR2_STRSTDATA2_SHIFT	0
+#define DAC_STR2_STRSTDATA2_MASK	0xFFF
+
+/* --- DAC_STMODR values ----------------------------------------------------- */
+
+/* STINCTRIGSEL2[3:0]: DAC channel2 sawtooth increment trigger selection */
+#define DAC_STMODR_STINCTRIGSEL2_SHIFT	24
+/** @defgroup dac_sawtooth2_inc DAC Channel 2 Sawtooth Increment Trigger
+@ingroup dac_defines
+
+@li SW: SWTRIGB2
+@li T1: dac_inc_ch2_trg1
+@li T2: dac_inc_ch2_trg2
+@li T3: dac_inc_ch2_trg3
+@li T4: dac_inc_ch2_trg4
+@li T5: dac_inc_ch2_trg5
+@li T6: dac_inc_ch2_trg6
+@li T7: dac_inc_ch2_trg7
+@li T8: dac_inc_ch2_trg8
+@li T9: dac_inc_ch2_trg9
+@li T10: dac_inc_ch2_trg10
+@li T11: dac_inc_ch2_trg11
+@li T12: dac_inc_ch2_trg12
+@li T13: dac_inc_ch2_trg13
+@li T14: dac_inc_ch2_trg14
+@li T15: dac_inc_ch2_trg15
+
+@note: These bits are only available only on dual-channel DACs.
+@{*/
+#define DAC_STMODR_STINCTRIGSEL2_SW	(0x0 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T1	(0x1 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T2	(0x2 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T3	(0x3 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T4	(0x4 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T5	(0x5 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T6	(0x6 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T7	(0x7 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T8	(0x8 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T9	(0x9 << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T10	(0xA << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T11	(0xB << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T12	(0xC << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T13	(0xD << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T14	(0xE << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL2_T15	(0xF << DAC_STMODR_STINCTRIGSEL2_SHIFT)
+/**@}*/
+
+/* STRSTTRIGSEL2[3:0]: DAC channel2 sawtooth reset trigger selection */
+#define DAC_STMODR_STRSTTRIGSEL2_SHIFT	16
+/** @defgroup dac_sawtooth2_rst DAC Channel 2 Sawtooth Reset Trigger
+@ingroup dac_defines
+
+@li SW: SWTRIGB2
+@li T1: dac_ch2_trg1
+@li T2: dac_ch2_trg2
+@li T3: dac_ch2_trg3
+@li T4: dac_ch2_trg4
+@li T5: dac_ch2_trg5
+@li T6: dac_ch2_trg6
+@li T7: dac_ch2_trg7
+@li T8: dac_ch2_trg8
+@li T9: dac_ch2_trg9
+@li T10: dac_ch2_trg10
+@li T11: dac_ch2_trg11
+@li T12: dac_ch2_trg12
+@li T13: dac_ch2_trg13
+@li T14: dac_ch2_trg14
+@li T15: dac_ch2_trg15
+
+@note: These bits are only available only on dual-channel DACs.
+@{*/
+#define DAC_STMODR_STRSTTRIGSEL2_SW	(0x0 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T1	(0x1 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T2	(0x2 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T3	(0x3 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T4	(0x4 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T5	(0x5 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T6	(0x6 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T7	(0x7 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T8	(0x8 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T9	(0x9 << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T10	(0xA << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T11	(0xB << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T12	(0xC << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T13	(0xD << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T14	(0xE << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL2_T15	(0xF << DAC_STMODR_STRSTTRIGSEL2_SHIFT)
+/**@}*/
+
+
+/* STINCTRIGSEL1[3:0]: DAC channel1 sawtooth increment trigger selection */
+#define DAC_STMODR_STINCTRIGSEL1_SHIFT	8
+/** @defgroup dac_sawtooth1_inc DAC Channel 1 Sawtooth Increment Trigger
+@ingroup dac_defines
+
+@li SW: SWTRIGB2
+@li T1: dac_inc_ch1_trg1
+@li T2: dac_inc_ch1_trg2
+@li T3: dac_inc_ch1_trg3
+@li T4: dac_inc_ch1_trg4
+@li T5: dac_inc_ch1_trg5
+@li T6: dac_inc_ch1_trg6
+@li T7: dac_inc_ch1_trg7
+@li T8: dac_inc_ch1_trg8
+@li T9: dac_inc_ch1_trg9
+@li T10: dac_inc_ch1_trg10
+@li T11: dac_inc_ch1_trg11
+@li T12: dac_inc_ch1_trg12
+@li T13: dac_inc_ch1_trg13
+@li T14: dac_inc_ch1_trg14
+@li T15: dac_inc_ch1_trg15
+
+@note: These bits are only available only on dual-channel DACs.
+@{*/
+#define DAC_STMODR_STINCTRIGSEL1_SW	(0x0 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T1	(0x1 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T2	(0x2 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T3	(0x3 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T4	(0x4 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T5	(0x5 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T6	(0x6 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T7	(0x7 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T8	(0x8 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T9	(0x9 << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T10	(0xA << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T11	(0xB << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T12	(0xC << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T13	(0xD << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T14	(0xE << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+#define DAC_STMODR_STINCTRIGSEL1_T15	(0xF << DAC_STMODR_STINCTRIGSEL1_SHIFT)
+/**@}*/
+
+/* STRSTTRIGSEL1[3:0]: DAC channel1 sawtooth reset trigger selection */
+#define DAC_STMODR_STRSTTRIGSEL1_SHIFT	0
+/** @defgroup dac_sawtooth1_rst DAC Channel 1 Sawtooth Reset Trigger
+@ingroup dac_defines
+
+@li SW: SWTRIGB2
+@li T1: dac_ch1_trg1
+@li T2: dac_ch1_trg2
+@li T3: dac_ch1_trg3
+@li T4: dac_ch1_trg4
+@li T5: dac_ch1_trg5
+@li T6: dac_ch1_trg6
+@li T7: dac_ch1_trg7
+@li T8: dac_ch1_trg8
+@li T9: dac_ch1_trg9
+@li T10: dac_ch1_trg10
+@li T11: dac_ch1_trg11
+@li T12: dac_ch1_trg12
+@li T13: dac_ch1_trg13
+@li T14: dac_ch1_trg14
+@li T15: dac_ch1_trg15
+
+@note: These bits are only available only on dual-channel DACs.
+@{*/
+#define DAC_STMODR_STRSTTRIGSEL1_SW	(0x0 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T1	(0x1 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T2	(0x2 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T3	(0x3 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T4	(0x4 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T5	(0x5 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T6	(0x6 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T7	(0x7 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T8	(0x8 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T9	(0x9 << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T10	(0xA << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T11	(0xB << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T12	(0xC << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T13	(0xD << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T14	(0xE << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+#define DAC_STMODR_STRSTTRIGSEL1_T15	(0xF << DAC_STMODR_STRSTTRIGSEL1_SHIFT)
+/**@}*/
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dac_set_mode(uint32_t dac, uint32_t mode);
+bool dac_is_ready(uint32_t dac, int channel);
+void dac_wait_on_ready(uint32_t dac, int channel);
+void dac_set_high_frequency_mode(uint32_t dac, uint32_t hfsel);
+
+END_DECLS
+
+#endif
+/** @cond */
+#else
+#warning "dac_common_v2.h should not be included explicitly, only via dac.h"
+#endif
+/** @endcond */
+
+/**@}*/
+

include/libopencm3/stm32/common/dcmi_common_f47.h

@@ -0,0 +1,229 @@
+/** @addtogroup dcmi_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2020
+ * Smolyaninov Nikolay <smolin35@gmail.com>
+ * @author @htmlonly &copy; @endhtmlonly 2017
+ * Marek Koza <qyx@krtko.org>
+ *
+ * @date 15 May 2020
+ *
+ * This library supports the  Digital camera interface (DCMI) in the STM32F4xx
+ * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2020, Smolyaninov Nikolay <smolin35@gmail.com>
+ * Copyright (C) 2017, Marek Koza <qyx@krtko.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/memorymap.h>
+
+/**@{*/
+
+/**
+ * DCMI control register 1
+ */
+#define DCMI_CR				MMIO32(DCMI_BASE + 0x0U)
+/**
+ * @defgroup dcmi_cr_values DCMI_CR Values
+ * @{
+ */
+#define DCMI_CR_EN			(1 << 14)
+#define DCMI_CR_EDM1			(1 << 11)
+#define DCMI_CR_EDM0			(1 << 10)
+#define DCMI_CR_FCRC1			(1 << 9)
+#define DCMI_CR_FCRC0			(1 << 8)
+#define DCMI_CR_VSPOL			(1 << 7)
+#define DCMI_CR_HSPOL			(1 << 6)
+#define DCMI_CR_PCKPOL			(1 << 5)
+#define DCMI_CR_ESS			(1 << 4)
+#define DCMI_CR_JPEG			(1 << 3)
+#define DCMI_CR_CROP			(1 << 2)
+#define DCMI_CR_CM			(1 << 1)
+#define DCMI_CR_CAPTURE			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI status register
+ */
+#define DCMI_SR				MMIO32(DCMI_BASE + 0x04U)
+/**
+ * @defgroup dcmi_sr_values DCMI_SR Values
+ * @{
+ */
+#define DCMI_SR_FNE			(1 << 2)
+#define DCMI_SR_VSYNCK			(1 << 1)
+#define DCMI_SR_HSYNCK			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI raw interrupt status register
+ *
+ * DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
+ * register returns the status of the corresponding interrupt before masking with the DCMI_IER
+ * register value.
+ */
+#define DCMI_RIS			MMIO32(DCMI_BASE + 0x08U)
+/**
+ * @defgroup dcmi_ris_values DCMI_RIS Values
+ * @{
+ */
+#define DCMI_RIS_LINE			(1 << 4)
+#define DCMI_RIS_VSYNC			(1 << 3)
+#define DCMI_RIS_ERR			(1 << 2)
+#define DCMI_RIS_OVR			(1 << 1)
+#define DCMI_RIS_FRAME			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI interrupt enable register
+ *
+ * The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set,
+ * the corresponding interrupt is enabled. This register is accessible in both read and write.
+ */
+#define DCMI_IER			MMIO32(DCMI_BASE + 0x0CU)
+/**
+ * @defgroup dcmi_ier_values DCMI_IER Values
+ * @{
+ */
+#define DCMI_IER_LINE			(1 << 4)
+#define DCMI_IER_VSYNC			(1 << 3)
+#define DCMI_IER_ERR			(1 << 2)
+#define DCMI_IER_OVR			(1 << 1)
+#define DCMI_IER_FRAME			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI masked interrupt status register
+ *
+ * This DCMI_MIS register is a read-only register. When read, it returns the current masked
+ * status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in
+ * this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding
+ * bit in DCMI_RIS is set.
+ */
+#define DCMI_MIS			MMIO32(DCMI_BASE + 0x10U)
+/**
+ * @defgroup dcmi_mis_values DCMI_MIS Values
+ * @{
+ */
+#define DCMI_MIS_LINE			(1 << 4)
+#define DCMI_MIS_VSYNC			(1 << 3)
+#define DCMI_MIS_ERR			(1 << 2)
+#define DCMI_MIS_OVR			(1 << 1)
+#define DCMI_MIS_FRAME			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI interrupt clear register
+ *
+ * The DCMI_ICR register is write-only. Writing a ‘1’ into a bit of this register clears the
+ * corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
+ */
+#define DCMI_ICR			MMIO32(DCMI_BASE + 0x14U)
+/**
+ * @defgroup dcmi_icr_values DCMI_ICR Values
+ * @{
+ */
+#define DCMI_ICR_LINE			(1 << 4)
+#define DCMI_ICR_VSYNC			(1 << 3)
+#define DCMI_ICR_ERR			(1 << 2)
+#define DCMI_ICR_OVR			(1 << 1)
+#define DCMI_ICR_FRAME			(1 << 0)
+/**@}*/
+
+/**
+ * DCMI embedded synchronization code register
+ */
+#define DCMI_ESCR			MMIO32(DCMI_BASE + 0x18U)
+/**
+ * @defgroup dcmi_escr_values DCMI_ESCR Values
+ * @{
+ */
+#define DCMI_ESCR_FEC_SHIFT		24
+#define DCMI_ESCR_FEC_MASK		0xff
+#define DCMI_ESCR_LEC_SHIFT		16
+#define DCMI_ESCR_LEC_MASK		0xff
+#define DCMI_ESCR_LSC_SHIFT		8
+#define DCMI_ESCR_LSC_MASK		0xff
+#define DCMI_ESCR_FSC_SHIFT		0
+#define DCMI_ESCR_FSC_MASK		0xff
+/**@}*/
+
+
+/**
+ * DCMI embedded synchronization unmask register
+ */
+#define DCMI_ESUR			MMIO32(DCMI_BASE + 0x1CU)
+/**
+ * @defgroup dcmi_esur_values DCMI_ESUR Values
+ * @{
+ */
+#define DCMI_ESUR_FEU_SHIFT		24
+#define DCMI_ESUR_FEU_MASK		0xff
+#define DCMI_ESUR_LEU_SHIFT		16
+#define DCMI_ESUR_LEU_MASK		0xff
+#define DCMI_ESUR_LSU_SHIFT		8
+#define DCMI_ESUR_LSU_MASK		0xff
+#define DCMI_ESUR_FSU_SHIFT		0
+#define DCMI_ESUR_FSU_MASK		0xff
+/**@}*/
+
+/**
+ * DCMI crop window start
+ */
+#define DCMI_CWSTRT			MMIO32(DCMI_BASE + 0x20U)
+/**
+ * @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values
+ * @{
+ */
+#define DCMI_CWSTRT_VST_SHIFT		16
+#define DCMI_CWSTRT_VST_MASK		0x1fff
+#define DCMI_CWSTRT_HOFFCNT_SHIFT	0
+#define DCMI_CWSTRT_HOFFCNT_MASK	0x3fff
+/**@}*/
+
+/**
+ * DCMI crop window size
+ */
+#define DCMI_CWSIZE			MMIO32(DCMI_BASE + 0x24U)
+/**
+ * @defgroup dcmi_cwsize_values DCMI_CWSIZE Values
+ * @{
+ */
+#define DCMI_CWSIZE_VLINE_SHIFT		16
+#define DCMI_CWSIZE_VLINE_MASK		0x3fff
+#define DCMI_CWSIZE_CAPCNT_SHIFT	0
+#define DCMI_CWSIZE_CAPCNT_MASK		0x3fff
+/**@}*/
+
+/**
+ * DCMI data register
+ *
+ * The digital camera Interface packages all the received data in 32-bit format before
+ * requesting a DMA transfer. A 4-word deep FIFO is available to leave enough time for DMA
+ * transfers and avoid DMA overrun conditions.
+ */
+#define DCMI_DR				MMIO32(DCMI_BASE + 0x28U)
+
+/**@}*/

include/libopencm3/stm32/common/dmamux_common_all.h

@@ -25,11 +25,7 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/** @cond */
+#pragma once
-#if defined(LIBOPENCM3_DMAMUX_H)
-/** @endcond */
-#ifndef LIBOPENCM3_DMAMUX_COMMON_ALL_H
-#define LIBOPENCM3_DMAMUX_COMMON_ALL_H
 
 /**@{*/
 
@@ -38,24 +34,24 @@
 #define DMAMUX2_CxCR(dma_channel)		DMAMUX_CxCR(DMAMUX2, (dma_channel))
 
 #define DMAMUX_CSR(dmamux_base)			MMIO32((dmamux_base) + 0x80)
-#define DMAMUX1_CSR(dmamux_base)			DMAMUX_CSR(DMAMUX1)
+#define DMAMUX1_CSR				DMAMUX_CSR(DMAMUX1)
-#define DMAMUX2_CSR(dmamux_base)			DMAMUX_CSR(DMAMUX2)
+#define DMAMUX2_CSR				DMAMUX_CSR(DMAMUX2)
 
 #define DMAMUX_CFR(dmamux_base)			MMIO32((dmamux_base) + 0x84)
-#define DMAMUX1_CFR(dmamux_base)			DMAMUX_CFR(DMAMUX1)
+#define DMAMUX1_CFR				DMAMUX_CFR(DMAMUX1)
-#define DMAMUX2_CFR(dmamux_base)			DMAMUX_CFR(DMAMUX2)
+#define DMAMUX2_CFR				DMAMUX_CFR(DMAMUX2)
 
 #define DMAMUX_RGxCR(dmamux_base, rg_channel)	MMIO32((dmamux_base) + 0x100 + 0x04 * ((rg_channel) - 1))
-#define DMAMUX1_RGxCR(dmamux_base, rg_channel)	DMAMUX_RGxCR(DMAMUX1, (rg_channel))
+#define DMAMUX1_RGxCR(rg_channel)		DMAMUX_RGxCR(DMAMUX1, (rg_channel))
-#define DMAMUX2_RGxCR(dmamux_base, rg_channel)	DMAMUX_RGxCR(DMAMUX2, (rg_channel))
+#define DMAMUX2_RGxCR(rg_channel)		DMAMUX_RGxCR(DMAMUX2, (rg_channel))
 
 #define DMAMUX_RGSR(dmamux_base)		MMIO32((dmamux_base) + 0x140)
-#define DMAMUX1_RGSR(dmamux_base)			DMAMUX_RSGR(DMAMUX1)
+#define DMAMUX1_RGSR				DMAMUX_RSGR(DMAMUX1)
-#define DMAMUX2_RGSR(dmamux_base)			DMAMUX_RSGR(DMAMUX2)
+#define DMAMUX2_RGSR				DMAMUX_RSGR(DMAMUX2)
 
 #define DMAMUX_RGCFR(dmamux_base)		MMIO32((dmamux_base) + 0x144)
-#define DMAMUX1_RGCFR(dmamux_base)			DMAMUX_RGCFR(DMAMUX1)
+#define DMAMUX1_RGCFR				DMAMUX_RGCFR(DMAMUX1)
-#define DMAMUX2_RGCFR(dmamux_base)			DMAMUX_RGCFR(DMAMUX2)
+#define DMAMUX2_RGCFR				DMAMUX_RGCFR(DMAMUX2)
 
 /** @defgroup dmamux_cxcr CxCR DMA request line multiplexer channel x control register
 @{*/
@@ -205,10 +201,3 @@ void dmamux_clear_request_generator_trigger_overrun_interrupt(uint32_t dmamux, u
 END_DECLS
 
 /**@}*/
-
-#endif
-/** @cond */
-#else
-#warning "dmamux_common_all.h should not be included explicitly, only via dmamux.h"
-#endif
-/** @endcond */

include/libopencm3/stm32/common/flash_common_all.h

@@ -25,14 +25,18 @@
 BEGIN_DECLS
 
 /**
- * This buffer is used for instruction fetches and is enabled by default after
+ * This buffer is used for instruction fetches and may or may not be
- * reset.
+ * enabled by default, depending on platform. (F1: yes, most others: no)
  * 
  * Note carefully the clock restrictions under which the prefetch buffer may be
  * enabled or disabled. Changes are normally made while the clock is running in
  * the power-on low frequency mode before being set to a higher speed mode.
  *
- * See the reference manual for details.
+ * Note carefully that prefetch may also results in increased consumption
+ * and can only improve performance on "mostly linear" workloads where there
+ * is at least one flash wait state.
+ *
+ * See the reference manual for your particular target for more details.
  */
 void flash_prefetch_enable(void);
 

include/libopencm3/stm32/common/flash_common_f24.h

@@ -59,7 +59,7 @@
 #define FLASH_OPTCR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
 /** Flash Option Control register 1 (bank 2) */
 #define FLASH_OPTCR1			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
-/*@}*/
+/**@}*/
 
 /** @defgroup flash_latency FLASH Wait States
 @ingroup flash_defines
@@ -73,7 +73,7 @@
 #define FLASH_ACR_LATENCY_5WS          0x05
 #define FLASH_ACR_LATENCY_6WS          0x06
 #define FLASH_ACR_LATENCY_7WS          0x07
-/*@}*/
+/**@}*/
 #define FLASH_ACR_LATENCY_SHIFT		0
 #define FLASH_ACR_LATENCY_MASK		0x0f
 

include/libopencm3/stm32/common/flash_common_l01.h

@@ -120,6 +120,19 @@ void flash_unlock_progmem(void);
 void flash_lock_progmem(void);
 void flash_lock_option_bytes(void);
 void flash_unlock_acr(void);
+/** Erase a page in flash.
+ * @param page_address For L1, must be first word in page, L0 doesn't care
+ * Takes 1 tprog. Flash must already be unlocked!
+ */
+void flash_erase_page(uint32_t page_address);
+
+/**
+ * Write a half page from buf to dst.
+ * This function _must_ be in ram! (See the Ref Man for more details)
+ * @param dst where to write to, expected to be aligned and erased.
+ * @param buf the half page to write, size required depends on target
+ */
+void flash_program_half_page(uint32_t *dst, void *buf);
 
 void eeprom_program_word(uint32_t address, uint32_t data);
 void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words);

include/libopencm3/stm32/common/i2c_common_v1.h

@@ -181,55 +181,50 @@ specific memorymap.h header before including this header file.*/
 
 /* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
 
-/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz, 2-42 MHz for
+enum i2c_cr2_freq_values  {
- * STM32F4 respectively) */
+	I2C_CR2_FREQ_2MHZ __attribute__ ((deprecated("Replace with 2 directly"))) = 2,
-/****************************************************************************/
+	I2C_CR2_FREQ_3MHZ __attribute__ ((deprecated("Replace with 3 directly"))),
-/** @defgroup i2c_clock I2C clock frequency settings
+	I2C_CR2_FREQ_4MHZ __attribute__ ((deprecated("Replace with 4 directly"))),
-@ingroup i2c_defines
+	I2C_CR2_FREQ_5MHZ __attribute__ ((deprecated("Replace with 5 directly"))),
+	I2C_CR2_FREQ_6MHZ __attribute__ ((deprecated("Replace with 6 directly"))),
+	I2C_CR2_FREQ_7MHZ __attribute__ ((deprecated("Replace with 7 directly"))),
+	I2C_CR2_FREQ_8MHZ __attribute__ ((deprecated("Replace with 8 directly"))),
+	I2C_CR2_FREQ_9MHZ __attribute__ ((deprecated("Replace with 9 directly"))),
+	I2C_CR2_FREQ_10MHZ __attribute__ ((deprecated("Replace with 10 directly"))),
+	I2C_CR2_FREQ_11MHZ __attribute__ ((deprecated("Replace with 11 directly"))),
+	I2C_CR2_FREQ_12MHZ __attribute__ ((deprecated("Replace with 12 directly"))),
+	I2C_CR2_FREQ_13MHZ __attribute__ ((deprecated("Replace with 13 directly"))),
+	I2C_CR2_FREQ_14MHZ __attribute__ ((deprecated("Replace with 14 directly"))),
+	I2C_CR2_FREQ_15MHZ __attribute__ ((deprecated("Replace with 15 directly"))),
+	I2C_CR2_FREQ_16MHZ __attribute__ ((deprecated("Replace with 16 directly"))),
+	I2C_CR2_FREQ_17MHZ __attribute__ ((deprecated("Replace with 17 directly"))),
+	I2C_CR2_FREQ_18MHZ __attribute__ ((deprecated("Replace with 18 directly"))),
+	I2C_CR2_FREQ_19MHZ __attribute__ ((deprecated("Replace with 19 directly"))),
+	I2C_CR2_FREQ_20MHZ __attribute__ ((deprecated("Replace with 20 directly"))),
+	I2C_CR2_FREQ_21MHZ __attribute__ ((deprecated("Replace with 21 directly"))),
+	I2C_CR2_FREQ_22MHZ __attribute__ ((deprecated("Replace with 22 directly"))),
+	I2C_CR2_FREQ_23MHZ __attribute__ ((deprecated("Replace with 23 directly"))),
+	I2C_CR2_FREQ_24MHZ __attribute__ ((deprecated("Replace with 24 directly"))),
+	I2C_CR2_FREQ_25MHZ __attribute__ ((deprecated("Replace with 25 directly"))),
+	I2C_CR2_FREQ_26MHZ __attribute__ ((deprecated("Replace with 26 directly"))),
+	I2C_CR2_FREQ_27MHZ __attribute__ ((deprecated("Replace with 27 directly"))),
+	I2C_CR2_FREQ_28MHZ __attribute__ ((deprecated("Replace with 28 directly"))),
+	I2C_CR2_FREQ_29MHZ __attribute__ ((deprecated("Replace with 29 directly"))),
+	I2C_CR2_FREQ_30MHZ __attribute__ ((deprecated("Replace with 30 directly"))),
+	I2C_CR2_FREQ_31MHZ __attribute__ ((deprecated("Replace with 31 directly"))),
+	I2C_CR2_FREQ_32MHZ __attribute__ ((deprecated("Replace with 32 directly"))),
+	I2C_CR2_FREQ_33MHZ __attribute__ ((deprecated("Replace with 33 directly"))),
+	I2C_CR2_FREQ_34MHZ __attribute__ ((deprecated("Replace with 34 directly"))),
+	I2C_CR2_FREQ_35MHZ __attribute__ ((deprecated("Replace with 35 directly"))),
+	I2C_CR2_FREQ_36MHZ __attribute__ ((deprecated("Replace with 36 directly"))),
+	I2C_CR2_FREQ_37MHZ __attribute__ ((deprecated("Replace with 37 directly"))),
+	I2C_CR2_FREQ_38MHZ __attribute__ ((deprecated("Replace with 38 directly"))),
+	I2C_CR2_FREQ_39MHZ __attribute__ ((deprecated("Replace with 39 directly"))),
+	I2C_CR2_FREQ_40MHZ __attribute__ ((deprecated("Replace with 40 directly"))),
+	I2C_CR2_FREQ_41MHZ __attribute__ ((deprecated("Replace with 41 directly"))),
+	I2C_CR2_FREQ_42MHZ __attribute__ ((deprecated("Replace with 42 directly"))),
+} __attribute__ ((deprecated("Replace _nMHZ with n directly")));
 
-@{*/
-#define I2C_CR2_FREQ_2MHZ		0x02
-#define I2C_CR2_FREQ_3MHZ		0x03
-#define I2C_CR2_FREQ_4MHZ		0x04
-#define I2C_CR2_FREQ_5MHZ		0x05
-#define I2C_CR2_FREQ_6MHZ		0x06
-#define I2C_CR2_FREQ_7MHZ		0x07
-#define I2C_CR2_FREQ_8MHZ		0x08
-#define I2C_CR2_FREQ_9MHZ		0x09
-#define I2C_CR2_FREQ_10MHZ		0x0a
-#define I2C_CR2_FREQ_11MHZ		0x0b
-#define I2C_CR2_FREQ_12MHZ		0x0c
-#define I2C_CR2_FREQ_13MHZ		0x0d
-#define I2C_CR2_FREQ_14MHZ		0x0e
-#define I2C_CR2_FREQ_15MHZ		0x0f
-#define I2C_CR2_FREQ_16MHZ		0x10
-#define I2C_CR2_FREQ_17MHZ		0x11
-#define I2C_CR2_FREQ_18MHZ		0x12
-#define I2C_CR2_FREQ_19MHZ		0x13
-#define I2C_CR2_FREQ_20MHZ		0x14
-#define I2C_CR2_FREQ_21MHZ		0x15
-#define I2C_CR2_FREQ_22MHZ		0x16
-#define I2C_CR2_FREQ_23MHZ		0x17
-#define I2C_CR2_FREQ_24MHZ		0x18
-#define I2C_CR2_FREQ_25MHZ		0x19
-#define I2C_CR2_FREQ_26MHZ		0x1a
-#define I2C_CR2_FREQ_27MHZ		0x1b
-#define I2C_CR2_FREQ_28MHZ		0x1c
-#define I2C_CR2_FREQ_29MHZ		0x1d
-#define I2C_CR2_FREQ_30MHZ		0x1e
-#define I2C_CR2_FREQ_31MHZ		0x1f
-#define I2C_CR2_FREQ_32MHZ		0x20
-#define I2C_CR2_FREQ_33MHZ		0x21
-#define I2C_CR2_FREQ_34MHZ		0x22
-#define I2C_CR2_FREQ_35MHZ		0x23
-#define I2C_CR2_FREQ_36MHZ		0x24
-#define I2C_CR2_FREQ_37MHZ		0x25
-#define I2C_CR2_FREQ_38MHZ		0x26
-#define I2C_CR2_FREQ_39MHZ		0x27
-#define I2C_CR2_FREQ_40MHZ		0x28
-#define I2C_CR2_FREQ_41MHZ		0x29
-#define I2C_CR2_FREQ_42MHZ		0x2a
-/**@}*/
 
 /* --- I2Cx_OAR1 values ---------------------------------------------------- */
 
@@ -390,7 +385,6 @@ enum i2c_speeds {
 
 BEGIN_DECLS
 
-void i2c_reset(uint32_t i2c);
 void i2c_peripheral_enable(uint32_t i2c);
 void i2c_peripheral_disable(uint32_t i2c);
 void i2c_send_start(uint32_t i2c);
@@ -420,7 +414,7 @@ void i2c_enable_dma(uint32_t i2c);
 void i2c_disable_dma(uint32_t i2c);
 void i2c_set_dma_last_transfer(uint32_t i2c);
 void i2c_clear_dma_last_transfer(uint32_t i2c);
-void i2c_transfer7(uint32_t i2c, uint8_t addr, uint8_t *w, size_t wn, uint8_t *r, size_t rn);
+void i2c_transfer7(uint32_t i2c, uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn);
 void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz);
 
 END_DECLS

include/libopencm3/stm32/common/i2c_common_v2.h

@@ -402,7 +402,6 @@ enum i2c_speeds {
 
 BEGIN_DECLS
 
-void i2c_reset(uint32_t i2c);
 void i2c_peripheral_enable(uint32_t i2c);
 void i2c_peripheral_disable(uint32_t i2c);
 void i2c_send_start(uint32_t i2c);
@@ -444,7 +443,7 @@ void i2c_enable_rxdma(uint32_t i2c);
 void i2c_disable_rxdma(uint32_t i2c);
 void i2c_enable_txdma(uint32_t i2c);
 void i2c_disable_txdma(uint32_t i2c);
-void i2c_transfer7(uint32_t i2c, uint8_t addr, uint8_t *w, size_t wn, uint8_t *r, size_t rn);
+void i2c_transfer7(uint32_t i2c, uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn);
 void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz);
 
 END_DECLS

include/libopencm3/stm32/common/iwdg_common_all.h

@@ -97,7 +97,7 @@ specific memorymap.h header before including this header file.*/
 
 /** PVU: Watchdog prescaler value update */
 #define IWDG_SR_PVU			(1 << 0)
-/*@}*/
+/**@}*/
 
 /* --- IWDG function prototypes---------------------------------------------- */
 

include/libopencm3/stm32/common/ltdc_common_f47.h

@@ -109,9 +109,15 @@
 #define LTDC_L1CLUTWR              LTDC_LxCLUTWR(LTDC_LAYER_1)
 #define LTDC_L2CLUTWR              LTDC_LxCLUTWR(LTDC_LAYER_2)
 
+/* LTDC layer base addresses (for API parameters) */
+/** @defgroup ltdc_layer_num LTDC Layer Number
+@ingroup STM32F4xx_ltdc_defines
 
+@{*/
 #define LTDC_LAYER_1 1
 #define LTDC_LAYER_2 2
+/**@}*/
+
 
 /* --- LTDC_SSCR values ---------------------------------------------------- */
 
@@ -500,7 +506,8 @@ void ltdc_set_tft_sync_timings(
 void ltdc_setup_windowing(
 		uint8_t  layer_number,
 		uint16_t h_back_porch,  uint16_t v_back_porch,
-		uint16_t active_width,  uint16_t active_height
+		uint16_t h_sync, uint16_t v_sync,
+		uint16_t width,  uint16_t height
 );
 
 

include/libopencm3/stm32/common/opamp_common_all.h

@@ -0,0 +1,99 @@
+/** @addtogroup opamp_defines
+ *
+ * @date 10 Dec 2020
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @cond */
+#if defined(LIBOPENCM3_OPAMP_H)
+/** @endcond */
+#ifndef LIBOPENCM3_OPAMP_COMMON_ALL_H
+#define LIBOPENCM3_OPAMP_COMMON_ALL_H
+/**@{*/
+
+/* OpAmp registers */
+
+/* Control and status register (OPAMPx_CSR) */
+#define OPAMP_CSR(opamp_base)		MMIO32((opamp_base) + 0x00)
+
+/* OPAMPx_CSR values */
+
+#define OPAMP_CSR_LOCK			(0x1 << 31)
+
+#define OPAMP_CSR_TSTREF		(0x1 << 29)
+
+#define OPAMP_CSR_TRIMOFFSETN_MASK	(0x1f)
+#define OPAMP_CSR_TRIMOFFSETN_SHIFT	(24)
+
+#define OPAMP_CSR_TRIMOFFSETP_MASK	(0x1f)
+#define OPAMP_CSR_TRIMOFFSETP_SHIFT	(19)
+
+#define OPAMP_CSR_CALSEL_MASK		(0x3)
+#define OPAMP_CSR_CALSEL_SHIFT		(12)
+#define OPAMP_CSR_CALSEL_3P3_PERCENT	(0x0)
+#define OPAMP_CSR_CALSEL_10_PERCENT	(0x1)
+#define OPAMP_CSR_CALSEL_50_PERCENT	(0x2)
+#define OPAMP_CSR_CALSEL_90_PERCENT	(0x3)
+
+#define OPAMP_CSR_CALON			(0x1 << 11)
+
+#define OPAMP_CSR_VM_SEL_MASK		(0x3)
+#define OPAMP_CSR_VM_SEL_SHIFT		(5)
+
+#define OPAMP_CSR_VP_SEL_MASK		(0x3)
+#define OPAMP_CSR_VP_SEL_SHIFT		(2)
+
+#define OPAMP_CSR_FORCE_VP		(0x1 << 1)
+#define OPAMP_CSR_EN			(0x1 << 0)
+
+
+BEGIN_DECLS
+
+void opamp_enable(uint32_t base);
+void opamp_disable(uint32_t base);
+void opamp_lock(uint32_t base);
+
+void opamp_set_calsel(uint32_t base, uint32_t calsel);
+void opamp_tstref_enable(uint32_t base);
+void opamp_tstref_disable(uint32_t base);
+void opamp_force_vp_enable(uint32_t base);
+void opamp_force_vp_disable(uint32_t base);
+void opamp_cal_enable(uint32_t base);
+void opamp_cal_disable(uint32_t base);
+
+void opamp_trimoffsetn_set(uint32_t base, uint32_t trim);
+void opamp_trimoffsetp_set(uint32_t base, uint32_t trim);
+void opamp_user_trim_enable(uint32_t base);
+void opamp_user_trim_disable(uint32_t base);
+
+void opamp_pga_gain_select(uint32_t base, uint32_t gain);
+
+void opamp_vp_select(uint32_t base, uint32_t vp);
+void opamp_vm_select(uint32_t base, uint32_t vm);
+
+END_DECLS
+/**@}*/
+
+#endif
+/** @cond */
+#else
+#warning "opamp_common_all.h should not be included directly, only via opamp.h"
+#endif
+/** @endcond */

include/libopencm3/stm32/common/opamp_common_v1.h

@@ -0,0 +1,86 @@
+/** @addtogroup opamp_defines
+ *
+ * @date 10 Dec 2020
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @cond */
+#if defined(LIBOPENCM3_OPAMP_H)
+/** @endcond */
+#ifndef LIBOPENCM3_OPAMP_COMMON_V1_H
+#define LIBOPENCM3_OPAMP_COMMON_V1_H
+/**@{*/
+
+#include <libopencm3/stm32/common/opamp_common_all.h>
+
+/* OPAMPx_CSR values */
+
+#define OPAMP_CSR_OUTCAL_MASK		(0x1)
+#define OPAMP_CSR_OUTCAL_SHIFT		(30)
+#define OPAMP_CSR_OUTCAL_NON_LO_INV	(0x0)
+#define OPAMP_CSR_OUTCAL_NON_HI_INV	(0x1)
+
+#define OPAMP_CSR_USER_TRIM		(0x1 << 18)
+
+#define OPAMP_CSR_PGA_GAIN_MASK		(0xf)
+#define OPAMP_CSR_PGA_GAIN_SHIFT	(14)
+#define OPAMP_CSR_PGA_GAIN_2		(0x0)
+#define OPAMP_CSR_PGA_GAIN_4		(0x1)
+#define OPAMP_CSR_PGA_GAIN_8		(0x2)
+#define OPAMP_CSR_PGA_GAIN_16		(0x3)
+#define OPAMP_CSR_PGA_GAIN_2_MINUS_VM0	(0x8)
+#define OPAMP_CSR_PGA_GAIN_4_MINUS_VM0	(0x9)
+#define OPAMP_CSR_PGA_GAIN_8_MINUS_VM0	(0xa)
+#define OPAMP_CSR_PGA_GAIN_16_MINUS_VM0	(0xb)
+#define OPAMP_CSR_PGA_GAIN_2_MINUS_VM1	(0xc)
+#define OPAMP_CSR_PGA_GAIN_4_MINUS_VM1	(0xd)
+#define OPAMP_CSR_PGA_GAIN_8_MINUS_VM1	(0xe)
+#define OPAMP_CSR_PGA_GAIN_16_MINUS_VM1	(0xf)
+
+#define OPAMP_CSR_VPS_SEL_MASK		(0x3)
+#define OPAMP_CSR_VPS_SEL_SHIFT		(9)
+
+#define OPAMP_CSR_VMS_SEL_MASK		(0x1)
+#define OPAMP_CSR_VMS_SEL_SHIFT		(8)
+
+#define OPAMP_CSR_TCM_EN		(0x1 << 7)
+
+#define OPAMP_CSR_VM_SEL_PGA_MODE	(0x2)
+#define OPAMP_CSR_VM_SEL_FOLLOWER_MODE	(0x3)
+
+
+BEGIN_DECLS
+
+bool opamp_read_outcal(uint32_t base);
+
+void opamp_vps_select(uint32_t base, uint32_t vps);
+void opamp_vms_select(uint32_t base, uint32_t vms);
+void opamp_tcm_enable(uint32_t base);
+void opamp_tcm_disable(uint32_t base);
+
+END_DECLS
+/**@}*/
+
+#endif
+/** @cond */
+#else
+#warning "opamp_common_v1.h should not be included directly, only via opamp.h"
+#endif
+/** @endcond */

include/libopencm3/stm32/common/opamp_common_v2.h

@@ -0,0 +1,111 @@
+/** @addtogroup opamp_defines
+ *
+ * @date 10 Dec 2020
+ *
+ *LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @cond */
+#if defined(LIBOPENCM3_OPAMP_H)
+/** @endcond */
+#ifndef LIBOPENCM3_OPAMP_COMMON_V2_H
+#define LIBOPENCM3_OPAMP_COMMON_V2_H
+/**@{*/
+
+#include <libopencm3/stm32/common/opamp_common_all.h>
+
+/* OpAmp registers */
+
+/* Timer controlled mode register (OPAMPx_TMCR) */
+#define OPAMP_TCMR(opamp_base)		MMIO32((opamp_base) + 0x18)
+
+/* OPAMPx_CSR values */
+
+#define OPAMP_CSR_CALOUT_MASK		(0x1)
+#define OPAMP_CSR_CALOUT_SHIFT		(30)
+#define OPAMP_CSR_CALOUT_UNSUCC		(0x0)
+#define OPAMP_CSR_CALOUT_SUCC		(0x1)
+
+#define OPAMP_CSR_PGA_GAIN_MASK		(0x1f)
+#define OPAMP_CSR_PGA_GAIN_SHIFT	(14)
+
+/* Non-inverting gain*/
+#define OPAMP_CSR_PGA_GAIN_2					(0x00)
+#define OPAMP_CSR_PGA_GAIN_4					(0x01)
+#define OPAMP_CSR_PGA_GAIN_8					(0x02)
+#define OPAMP_CSR_PGA_GAIN_16					(0x03)
+#define OPAMP_CSR_PGA_GAIN_32					(0x04)
+#define OPAMP_CSR_PGA_GAIN_64					(0x05)
+/* Inverting gain -n/non-inverting gain y with VINM0 pin for input bias */
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_1_GAIN_2_VM0		(0x08)
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_3_GAIN_4_VM0		(0x09)
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_7_GAIN_8_VM0		(0x0A)
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_15_GAIN_16_VM0		(0x0B)
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_31_GAIN_32_VM0		(0x0C)
+#define OPAMP_CSR_PGA_INV_GAIN_MINUS_63_GAIN_64_VM0		(0x0D)
+/* Non-inverting gain with filtering on VINM0 */
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_2				(0x10)
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_4				(0x11)
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_8				(0x12)
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_16				(0x13)
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_32				(0x14)
+#define OPAMP_CSR_PGA_FILT_VM0_GAIN_64				(0x15)
+/* Inverting gain -x/non-inverting gain y with VINM0 pin for input bias
+ * VINM1 for filtering*/
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_1_GAIN_2_VM0	(0x18)
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_3_GAIN_4_VM0	(0x19)
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_7_GAIN_8_VM0	(0x1a)
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_15_GAIN_16_VM0	(0x1B)
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_31_GAIN_32_VM0	(0x1c)
+#define OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_63_GAIN_64_VM0	(0x1d)
+
+#define OPAMP_CSR_OPAINTOEN		(0x1 << 8)
+
+#define OPAMP_CSR_OPAHSM		(0x1 << 7)
+
+#define OPAMP_CSR_VM_SEL_VINM0_IN	(0x0)
+#define OPAMP_CSR_VM_SEL_VINM1_IN	(0x1)
+#define OPAMP_CSR_VM_SEL_PGA_MODE	(0x2)
+#define OPAMP_CSR_VM_SEL_OUT_IN		(0x3)
+
+#define OPAMP_CSR_USER_TRIM		(0x1 << 4)
+
+#define OPAMP_CSR_VP_SEL_VINP0		(0x0)
+#define OPAMP_CSR_VP_SEL_VINP1		(0x1)
+#define OPAMP_CSR_VP_SEL_VINP2		(0x2)
+
+BEGIN_DECLS
+
+bool opamp_read_calout(uint32_t base);
+
+void opamp_high_speed_mode_enable(uint32_t base);
+void opamp_high_speed_mode_disable(uint32_t base);
+
+void opamp_output_set_internal(uint32_t base);
+void opamp_output_set_external(uint32_t base);
+
+END_DECLS
+/**@}*/
+
+#endif
+/** @cond */
+#else
+#warning "opamp_common_v2.h should not be included directly, only via opamp.h"
+#endif
+/** @endcond */

include/libopencm3/stm32/common/quadspi_common_v1.h

@@ -0,0 +1,175 @@
+/** @addtogroup quadspi_defines
+ * @author Chuck McManis <cmcmanis@mcmanis.com> 2016
+ * @copyright SPDX: LGPL-3.0-or-later
+ * @{
+ */
+
+#pragma once
+
+/** @addtogroup quadspi_registers QuadSPI Registers
+ * @{
+ */
+/** QUADSPI Control register */
+#define QUADSPI_CR      MMIO32(QUADSPI_BASE + 0x0U)
+
+/** QUADSPI Device Configuration */
+#define QUADSPI_DCR     MMIO32(QUADSPI_BASE + 0x4U)
+
+/** QUADSPI Status Register */
+#define QUADSPI_SR      MMIO32(QUADSPI_BASE + 0x8U)
+
+/** QUADSPI Flag Clear Register */
+#define QUADSPI_FCR     MMIO32(QUADSPI_BASE + 0xCU)
+
+/** QUADSPI Data Length Register */
+#define QUADSPI_DLR     MMIO32(QUADSPI_BASE + 0x10U)
+
+/** QUADSPI Communication Configuration Register */
+#define QUADSPI_CCR     MMIO32(QUADSPI_BASE + 0x14U)
+
+/** QUADSPI address register */
+#define QUADSPI_AR      MMIO32(QUADSPI_BASE + 0x18U)
+
+/** QUADSPI alternate bytes register */
+#define QUADSPI_ABR     MMIO32(QUADSPI_BASE + 0x1CU)
+
+/** QUADSPI data register */
+#define QUADSPI_DR      MMIO32(QUADSPI_BASE + 0x20U)
+/** BYTE addressable version for fetching bytes from the interface */
+#define QUADSPI_BYTE_DR     MMIO8(QUADSPI_BASE + 0x20U)
+
+/** QUADSPI polling status */
+#define QUADSPI_PSMKR     MMIO32(QUADSPI_BASE + 0x24U)
+
+/** QUADSPI polling status match */
+#define QUADSPI_PSMAR     MMIO32(QUADSPI_BASE + 0x28U)
+
+/** QUADSPI polling interval register */
+#define QUADSPI_PIR     MMIO32(QUADSPI_BASE + 0x2CU)
+
+/** QUADSPI low power timeout */
+#define QUADSPI_LPTR      MMIO32(QUADSPI_BASE + 0x30U
+/**@}*/
+
+#define QUADSPI_CR_PRESCALE_MASK  0xff
+#define QUADSPI_CR_PRESCALE_SHIFT 24
+#define QUADSPI_CR_PMM      (1 << 23)
+#define QUADSPI_CR_APMS     (1 << 22)
+/* bit 21 is reserved */
+#define QUADSPI_CR_TOIE     (1 << 20)
+#define QUADSPI_CR_SMIE     (1 << 19)
+#define QUADSPI_CR_FTIE     (1 << 18)
+#define QUADSPI_CR_TCIE     (1 << 17)
+#define QUADSPI_CR_TEIE     (1 << 16)
+
+/* bits 15:13 reserved */
+#define QUADSPI_CR_FTHRES_MASK    0x1f
+#define QUADSPI_CR_FTHRES_SHIFT   8
+#define QUADSPI_CR_FSEL     (1 << 7)
+#define QUADSPI_CR_DFM      (1 << 6)
+/* bit 5 reserved */
+#define QUADSPI_CR_SSHIFT   (1 << 4)
+#define QUADSPI_CR_TCEN     (1 << 3)
+/* bit 2 reserved on h7, DMAEN on f4 */
+#define QUADSPI_CR_ABORT    (1 << 1)
+#define QUADSPI_CR_EN     (1 << 0)
+
+/* bits 31:21 reserved */
+#define QUADSPI_DCR_FSIZE_MASK    0x1f
+#define QUADSPI_DCR_FSIZE_SHIFT   16
+/* bits 15:11 reserved */
+#define QUADSPI_DCR_CSHT_MASK   0x7
+#define QUADSPI_DCR_CSHT_SHIFT    8
+/* bits 7:1 reserved */
+#define QUADSPI_DCR_CKMODE    (1 << 0)
+
+/* bits 31:14 reserved */
+#define QUADSPI_SR_FLEVEL_MASK    0x3f
+#define QUADSPI_SR_FLEVEL_SHIFT   8
+
+/* bits 7:6 reserved */
+#define QUADSPI_SR_BUSY     (1 << 5)
+#define QUADSPI_SR_TOF      (1 << 4)
+#define QUADSPI_SR_SMF      (1 << 3)
+#define QUADSPI_SR_FTF      (1 << 2)
+#define QUADSPI_SR_TCF      (1 << 1)
+#define QUADSPI_SR_TEF      (1 << 0)
+
+/* bits 31:5 reserved */
+#define QUADSPI_FCR_CTOF    (1 << 4)
+#define QUADSPI_FCR_CSMF    (1 << 3)
+/* bit 2 reserved */
+#define QUADSPI_FCR_CTCF    (1 << 1)
+#define QUADSPI_FCR_CTEF    (1 << 0)
+
+#define QUADSPI_CCR_DDRM    (1 << 31)
+#define QUADSPI_CCR_DHHC    (1 << 30)
+/* bit 29 reserved on F4, FRCM on H7 */
+#define QUADSPI_CCR_SIOO    (1 << 28)
+#define QUADSPI_CCR_FMODE_MASK    0x3
+#define QUADSPI_CCR_FMODE_SHIFT   26
+#define QUADSPI_CCR_DMODE_MASK    0x3
+#define QUADSPI_CCR_DMODE_SHIFT   24
+/* bit 23 reserved */
+#define QUADSPI_CCR_DCYC_MASK   0x1f
+#define QUADSPI_CCR_DCYC_SHIFT    18
+
+#define QUADSPI_CCR_ABSIZE_MASK   0x3
+#define QUADSPI_CCR_ABSIZE_SHIFT  16
+
+#define QUADSPI_CCR_ABMODE_MASK   0x3
+#define QUADSPI_CCR_ABMODE_SHIFT  14
+
+#define QUADSPI_CCR_ADSIZE_MASK   0x3
+#define QUADSPI_CCR_ADSIZE_SHIFT  12
+
+#define QUADSPI_CCR_ADMODE_MASK   0x3
+#define QUADSPI_CCR_ADMODE_SHIFT  10
+
+#define QUADSPI_CCR_IMODE_MASK    0x3
+#define QUADSPI_CCR_IMODE_SHIFT   8
+
+#define QUADSPI_CCR_INST_MASK   0xff
+#define QUADSPI_CCR_INST_SHIFT    0
+
+/* MODE values */
+#define QUADSPI_CCR_MODE_NONE   0
+#define QUADSPI_CCR_MODE_1LINE    1
+#define QUADSPI_CCR_MODE_2LINE    2
+#define QUADSPI_CCR_MODE_4LINE    3
+
+/* FMODE values */
+#define QUADSPI_CCR_FMODE_IWRITE  0
+#define QUADSPI_CCR_FMODE_IREAD   1
+#define QUADSPI_CCR_FMODE_APOLL   2
+#define QUADSPI_CCR_FMODE_MEMMAP  3
+
+/**@}*/
+
+
+/**
+ * @defgroup quadspi_file QuadSPI peripheral API
+ * @brief APIs for the specialized SPI Flash peripheral
+ * @ingroup peripheral_apis
+ * @copyright SPDX: LGPL-3.0-or-later
+ *
+ * The QUADSPI is a specialized communication interface targeting single,
+ * dual or quad SPI Flash memories
+ * @{
+ */
+
+BEGIN_DECLS
+
+/**
+ * Enable the quadspi peripheral.
+ */
+void quadspi_enable(void);
+
+/**
+ * Disable the quadspi peripheral.
+ */
+void quadspi_disable(void);
+
+END_DECLS
+
+/**@}*/

include/libopencm3/stm32/common/rcc_common_all.h

@@ -67,6 +67,13 @@ bool rcc_is_osc_ready(enum rcc_osc osc);
  */
 void rcc_wait_for_osc_ready(enum rcc_osc osc);
 
+/**
+ * This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a
+ * 4-bit value, typically used for hpre and other prescalers.
+ * @param div_val  Masked and shifted divider value from register (e.g. RCC_CFGR)
+ */
+uint16_t rcc_get_div_from_hpre(uint8_t div_val);
+
 END_DECLS
 /**@}*/