diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
deleted file mode 100644
index af8265cc7..000000000
--- a/.codespell/exclude-file.txt
+++ /dev/null
@@ -1 +0,0 @@
- return USB0.INTSTS1.BIT.ATTCH ? true : false;
diff --git a/.codespellrc b/.codespellrc
index 8c32ed706..1f06e0c5c 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -2,9 +2,9 @@
[codespell]
# In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line).
# Or copy & paste the whole problematic line to 'exclude-file.txt'
-ignore-words = .codespell/ignore-words.txt
-exclude-file = .codespell/exclude-file.txt
+ignore-words = tools/codespell/ignore-words.txt
+exclude-file = tools/codespell/exclude-file.txt
check-filenames =
check-hidden =
count =
-skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/unit-test/vendor,./tests_obsolete,./tools/uf2
+skip = *.rb,.cproject,.git,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./tests_obsolete
diff --git a/.gitattributes b/.gitattributes
index 2342decc3..140ae8929 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -1,10 +1,10 @@
# Set the default behavior, in case people don't have core.autocrlf set.
* text=auto
-*.c text
-*.cpp text
+*.c text
+*.cpp text
*.h text
-*.icf text
+*.icf text
*.js text
*.json text
*.ld text
diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 8c39b95e1..d00ee78bd 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -54,21 +54,21 @@ body:
Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well.
1. Go to '...'
2. Click on '....'
- 3. See error
+ 3. See error
validations:
required: true
- type: textarea
attributes:
- label: Debug Log as txt file
+ label: Debug Log as txt file (LOG/CFG_TUSB_DEBUG=2)
placeholder: |
Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
-
+
Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability.
- Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h.
+ Note2: To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h.
More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
validations:
- required: false
+ required: true
- type: textarea
attributes:
diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 800a54380..6ac7ad015 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -1,6 +1,7 @@
name: Build AArch64
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -42,9 +43,6 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-
- name: Checkout hathach/linkermap
uses: actions/checkout@v3
with:
@@ -72,7 +70,7 @@ jobs:
run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- name: Get Dependencies
- run: python3 tools/get_dependencies.py ${{ matrix.family }}
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 96c337462..171c1fec3 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -1,6 +1,7 @@
name: Build ARM
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -33,29 +34,14 @@ jobs:
family:
# Alphabetical order
- 'broadcom_32bit'
- - 'imxrt'
- - 'lpc15'
- - 'lpc18'
- - 'lpc54'
- - 'lpc55'
- - 'mm32'
- - 'msp432e4'
- - 'nrf'
- - 'rp2040'
- - 'samd11'
- - 'samd21'
- - 'samd51'
- - 'saml2x'
- - 'stm32f0'
- - 'stm32f1'
- - 'stm32f4'
- - 'stm32f7'
- - 'stm32g4'
- - 'stm32h7'
- - 'stm32l4'
- - 'stm32wb'
- - 'tm4c123'
- - 'xmc4000'
+ - 'kinetis_k32l2'
+ - 'lpc11 lpc13 lpc15 lpc17'
+ - 'lpc51'
+ - 'mm32 msp432e4'
+ - 'samd11 same5x saml2x'
+ - 'stm32f2 stm32f3'
+ - 'stm32l0 stm32wb'
+ - 'tm4c123 xmc4000'
steps:
- name: Setup Python
uses: actions/setup-python@v4
@@ -70,23 +56,14 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-
- name: Checkout hathach/linkermap
uses: actions/checkout@v3
with:
repository: hathach/linkermap
path: linkermap
- - name: Checkout pico-sdk for rp2040
- if: matrix.family == 'rp2040'
- run: |
- git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
- echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-
- name: Get Dependencies
- run: python3 tools/get_dependencies.py ${{ matrix.family }}
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
run: python3 tools/build_family.py ${{ matrix.family }}
@@ -99,193 +76,3 @@ jobs:
do
find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
done
-
- # Upload binaries for rp2040 hardware test with self-hosted
- - name: Prepare rp2040 Artifacts
- if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
- run: find examples/ -name "*.elf" -exec mv {} . \;
-
- - name: Upload rp2040 Artifacts
- if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
- uses: actions/upload-artifact@v3
- with:
- name: ${{ matrix.family }}
- path: |
- *.elf
-
- # Upload binaries for stm32l412nucleo hardware test with self-hosted
- - name: Prepare stm32l412nucleo Artifacts
- if: matrix.family == 'stm32l4'
- run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
-
- - name: Upload stm32l412nucleo Artifacts
- if: matrix.family == 'stm32l4'
- uses: actions/upload-artifact@v3
- with:
- name: stm32l412nucleo
- path: |
- *.elf
-
- # ---------------------------------------
- # Build all no-family (orphaned) boards
- # disable this workflow since it is often failed randomly
- # ---------------------------------------
- build-board:
- runs-on: ubuntu-latest
- if: false
- strategy:
- fail-fast: false
- matrix:
- example:
- # Alphabetical order, a group of 4
- - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc'
- - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos'
- - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun'
- - 'device/net_lwip_webserver'
- - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid'
-
- steps:
- - name: Setup Python
- uses: actions/setup-python@v4
- with:
- python-version: '3.x'
-
- - name: Install ARM GCC
- uses: carlosperate/arm-none-eabi-gcc-action@v1
- with:
- release: '11.2-2022.02'
-
- - name: Checkout TinyUSB
- uses: actions/checkout@v3
-
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
- - name: Build
- run: python3 tools/build_board.py ${{ matrix.example }}
-
- # ---------------------------------------
- # Hardware in the loop (HIL)
- # Current self-hosted instance is running on an RPI4 with
- # - pico + pico-probe connected via USB
- # - pico-probe is /dev/ttyACM0
- # ---------------------------------------
- hw-rp2040-test:
- # run only with hathach's commit due to limited resource on RPI4
- if: github.repository_owner == 'hathach'
- needs: build-arm
- runs-on: [self-hosted, Linux, ARM64, rp2040]
-
- steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
-
- - name: Download rp2040 Artifacts
- uses: actions/download-artifact@v3
- with:
- name: rp2040
-
- - name: Create flash.sh
- run: |
- #echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
- echo > flash.sh 'pyocd flash -t rp2040 $1'
- echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
- chmod +x flash.sh
-
- - name: Test cdc_dual_ports
- run: |
- ./flash.sh cdc_dual_ports.elf
- while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
- test -e /dev/ttyACM1 && echo "ttyACM1 exists"
- test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
- - name: Test cdc_msc
- run: |
- ./flash.sh cdc_msc.elf
- readme='/media/pi/TinyUSB MSC/README.TXT'
- while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
- test -e /dev/ttyACM1 && echo "ttyACM1 exists"
- test -f "$readme" && echo "$readme exists"
- cat "$readme"
-
- - name: Test dfu
- run: |
- ./flash.sh dfu.elf
- while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
- dfu-util -d cafe -a 0 -U dfu0
- dfu-util -d cafe -a 1 -U dfu1
- grep "TinyUSB DFU! - Partition 0" dfu0
- grep "TinyUSB DFU! - Partition 1" dfu1
-
- - name: Test dfu_runtime
- run: |
- ./flash.sh dfu_runtime.elf
- while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
-
- # ---------------------------------------
- # Hardware in the loop (HIL)
- # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
- # - STM32L412 Nucleo with on-board jlink as ttyACM0
- # ---------------------------------------
- hw-stm32l412nucleo-test:
- needs: build-arm
- runs-on: [self-hosted, Linux, X64, hifiphile]
-
- steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
-
- - name: Download stm32l4 Artifacts
- uses: actions/download-artifact@v3
- with:
- name: stm32l412nucleo
-
- - name: Create flash.sh
- run: |
- echo > flash.sh 'echo halt > flash.jlink'
- echo >> flash.sh 'echo r >> flash.jlink'
- echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
- echo >> flash.sh 'echo r >> flash.jlink'
- echo >> flash.sh 'echo go >> flash.jlink'
- echo >> flash.sh 'echo exit >> flash.jlink'
- echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
- echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
- chmod +x flash.sh
-
- - name: Test cdc_dual_ports
- run: |
- ./flash.sh cdc_dual_ports.elf
- while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
- test -e /dev/ttyACM1 && echo "ttyACM1 exists"
- test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
- # Debian does not auto mount usb drive. skip this test for now
- - name: Test cdc_msc
- if: false
- run: |
- ./flash.sh cdc_msc.elf
- readme='/media/pi/TinyUSB MSC/README.TXT'
- while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
- test -e /dev/ttyACM1 && echo "ttyACM1 exists"
- test -f "$readme" && echo "$readme exists"
- cat "$readme"
-
- - name: Test dfu
- run: |
- ./flash.sh dfu.elf
- while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
- dfu-util -d cafe -a 0 -U dfu0
- dfu-util -d cafe -a 1 -U dfu1
- grep "TinyUSB DFU! - Partition 0" dfu0
- grep "TinyUSB DFU! - Partition 1" dfu1
-
- - name: Test dfu_runtime
- run: |
- ./flash.sh dfu_runtime.elf
- while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index dbc51a60f..897616f09 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -1,6 +1,7 @@
name: Build ESP
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -28,12 +29,10 @@ jobs:
fail-fast: false
matrix:
board:
- # Alphabetical order
# ESP32-S2
- - 'espressif_saola_1'
+ - 'espressif_kaluga_1'
# ESP32-S3
- #- 'espressif_s3_devkitm'
- # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
+ - 'espressif_s3_devkitm'
steps:
- name: Setup Python
@@ -47,20 +46,5 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout hathach/linkermap
- uses: actions/checkout@v3
- with:
- repository: hathach/linkermap
- path: linkermap
-
- name: Build
- run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32sx.py ${{ matrix.board }}
-
- - name: Linker Map
- run: |
- pip install linkermap/
- # find -quit to only print linkermap of 1 board per example
- for ex in `ls -d examples/device/*/`
- do
- find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
- done
+ run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }}
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 33e77c3dc..1eacf90c9 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -1,6 +1,7 @@
name: Build IAR
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -22,36 +23,32 @@ concurrency:
cancel-in-progress: true
jobs:
- build-arm:
+ cmake:
runs-on: [self-hosted, Linux, X64, hifiphile]
strategy:
fail-fast: false
matrix:
family:
- # Alphabetical order
- # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
- # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
- - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4'
+ # Alphabetical order
+ # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
+ # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
+ - 'lpc43 stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
steps:
- - name: Clean workspace
- run: |
- echo "Cleaning up previous run"
- rm -rf "${{ github.workspace }}"
- mkdir -p "${{ github.workspace }}"
+ - name: Clean workspace
+ run: |
+ echo "Cleaning up previous run"
+ rm -rf "${{ github.workspace }}"
+ mkdir -p "${{ github.workspace }}"
- - name: Checkout TinyUSB
- uses: actions/checkout@v3
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v3
- - name: Checkout submodules and dependencies
- run: |
- git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
- python3 tools/get_dependencies.py ${{ matrix.family }}
+ - name: Get Dependencies
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- #- name: Checkout pico-sdk for rp2040
- # if: matrix.family == 'rp2040'
- # run: |
- # git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
- # echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
+ - name: Build
+ run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar -DCMAKE_BUILD_TYPE=MinSizeRel
- - name: Build
- run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
+ - name: Test on actual hardware (hardware in the loop)
+ run: |
+ python3 test/hil/hil_test.py hil_hfp.json
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 2c7785806..c62056940 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -1,6 +1,7 @@
name: Build MSP430
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -21,7 +22,7 @@ concurrency:
group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
cancel-in-progress: true
-jobs:
+jobs:
build-msp430:
runs-on: ubuntu-latest
strategy:
@@ -40,9 +41,6 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
- name: Checkout hathach/linkermap
uses: actions/checkout@v3
with:
@@ -70,7 +68,7 @@ jobs:
run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- name: Get Dependencies
- run: python3 tools/get_dependencies.py ${{ matrix.family }}
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 3a961d327..66b98a71b 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -1,6 +1,7 @@
name: Build Renesas
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -39,9 +40,6 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
- name: Checkout hathach/linkermap
uses: actions/checkout@v3
with:
@@ -70,7 +68,7 @@ jobs:
run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- name: Get Dependencies
- run: python3 tools/get_dependencies.py ${{ matrix.family }}
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index fb4d4d28c..8ec549072 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -1,6 +1,7 @@
name: Build RISC-V
on:
+ workflow_dispatch:
push:
paths:
- 'src/**'
@@ -41,9 +42,6 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Checkout common submodules in lib
- run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
- name: Checkout hathach/linkermap
uses: actions/checkout@v3
with:
@@ -71,7 +69,7 @@ jobs:
run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
- name: Get Dependencies
- run: python3 tools/get_dependencies.py ${{ matrix.family }}
+ run: python3 tools/get_deps.py ${{ matrix.family }}
- name: Build
run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
new file mode 100644
index 000000000..cb879a705
--- /dev/null
+++ b/.github/workflows/build_win_mac.yml
@@ -0,0 +1,54 @@
+name: Build Windows/MacOS
+
+on:
+ workflow_dispatch:
+ push:
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - '.github/workflows/build_win_mac.yml'
+ pull_request:
+ branches: [ master ]
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - '.github/workflows/build_win_mac.yml'
+
+concurrency:
+ group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+ cancel-in-progress: true
+
+jobs:
+ # ---------------------------------------
+ # Build ARM family
+ # ---------------------------------------
+ build-arm:
+ strategy:
+ fail-fast: false
+ matrix:
+ os: [windows-latest, macos-latest]
+ runs-on: ${{ matrix.os }}
+
+ steps:
+ - name: Setup Python
+ uses: actions/setup-python@v4
+ with:
+ python-version: '3.x'
+
+ - name: Install ARM GCC
+ uses: carlosperate/arm-none-eabi-gcc-action@v1
+ with:
+ release: '10.3-2021.10'
+
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v3
+
+ - name: Get Dependencies
+ run: python3 tools/get_deps.py stm32f4
+
+ - name: Build
+ run: python3 tools/build_family.py stm32f4 stm32f411disco
diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml
index 7314fd9e6..4c4b12a6b 100644
--- a/.github/workflows/cifuzz.yml
+++ b/.github/workflows/cifuzz.yml
@@ -1,5 +1,6 @@
name: CIFuzz
on:
+ workflow_dispatch:
pull_request:
branches:
- master
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
new file mode 100644
index 000000000..e57c297d7
--- /dev/null
+++ b/.github/workflows/cmake_arm.yml
@@ -0,0 +1,164 @@
+name: CMake ARM
+
+on:
+ workflow_dispatch:
+ push:
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - '.github/workflows/cmake_arm.yml'
+ pull_request:
+ branches: [ master ]
+ paths:
+ - 'src/**'
+ - 'examples/**'
+ - 'lib/**'
+ - 'hw/**'
+ - '.github/workflows/cmake_arm.yml'
+
+concurrency:
+ group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+ cancel-in-progress: true
+
+jobs:
+ # ---------------------------------------
+ # Build ARM family
+ # ---------------------------------------
+ build-arm:
+ runs-on: ubuntu-latest
+ strategy:
+ fail-fast: false
+ matrix:
+ family:
+ # Alphabetical order
+ - 'imxrt'
+ - 'kinetis_kl'
+ - 'lpc18 lpc40 lpc43'
+ - 'lpc54 lpc55'
+ - 'mcx'
+ - 'nrf'
+ - 'ra'
+ - 'rp2040'
+ - 'samd21'
+ - 'samd51'
+ - 'stm32f0'
+ - 'stm32f1'
+ - 'stm32f4'
+ - 'stm32f7'
+ - 'stm32g0'
+ - 'stm32g4'
+ - 'stm32h7'
+ - 'stm32l4'
+ - 'stm32u5'
+ steps:
+ - name: Setup Python
+ uses: actions/setup-python@v4
+ with:
+ python-version: '3.x'
+
+ - name: Install ARM GCC
+ uses: carlosperate/arm-none-eabi-gcc-action@v1
+ with:
+ release: '11.2-2022.02'
+
+ - name: Install Ninja
+ run: sudo apt install -y ninja-build
+
+ - name: Checkout TinyUSB
+ uses: actions/checkout@v3
+
+ - name: Checkout pico-sdk for rp2040
+ if: matrix.family == 'rp2040'
+ uses: actions/checkout@v3
+ with:
+ repository: raspberrypi/pico-sdk
+ ref: develop
+ path: pico-sdk
+
+ - name: Get Dependencies
+ run: python3 tools/get_deps.py ${{ matrix.family }}
+
+ - name: Build
+ run: python tools/build_cmake.py ${{ matrix.family }} -DCMAKE_BUILD_TYPE=MinSizeRel
+ env:
+ # for rp2040, there is no harm if defined for other families
+ PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
+
+ # Upload binaries for hardware test with self-hosted
+ - name: Prepare rp2040 Artifacts
+ if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
+ working-directory: ${{github.workspace}}/cmake-build/cmake-build-raspberry_pi_pico
+ run: |
+ find device/ -name "*.elf" -exec mv {} ../../ \;
+ # find host/ -name "*.elf" -exec mv {} ../../ \;
+ # find dual/ -name "*.elf" -exec mv {} ../../ \;
+
+ - name: Upload Artifacts for rp2040
+ if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'
+ uses: actions/upload-artifact@v3
+ with:
+ name: rp2040
+ path: |
+ *.elf
+
+ # ---------------------------------------
+ # Hardware in the loop (HIL)
+ # Current self-hosted instance is running on an RPI4 with
+ # - pico + pico-probe connected via USB
+ # - pico-probe is /dev/ttyACM0
+ # ---------------------------------------
+ hw-rp2040-test:
+ # run only with hathach's commit due to limited resource on RPI4
+ if: github.repository_owner == 'hathach'
+ needs: build-arm
+ runs-on: [self-hosted, Linux, ARM64, rp2040]
+
+ steps:
+ - name: Clean workspace
+ run: |
+ echo "Cleaning up previous run"
+ rm -rf "${{ github.workspace }}"
+ mkdir -p "${{ github.workspace }}"
+
+ - name: Download rp2040 Artifacts
+ uses: actions/download-artifact@v3
+ with:
+ name: rp2040
+
+ - name: Create flash.sh
+ run: |
+ echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")'
+ echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+ chmod +x flash.sh
+
+ - name: Test cdc_dual_ports
+ run: |
+ ./flash.sh cdc_dual_ports.elf
+ while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
+ test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+ test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+ - name: Test cdc_msc
+ run: |
+ ./flash.sh cdc_msc.elf
+ readme='/media/pi/TinyUSB MSC/README.TXT'
+ while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
+ test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+ test -f "$readme" && echo "$readme exists"
+ cat "$readme"
+
+ - name: Test dfu
+ run: |
+ ./flash.sh dfu.elf
+ while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
+ dfu-util -d cafe -a 0 -U dfu0
+ dfu-util -d cafe -a 1 -U dfu1
+ grep "TinyUSB DFU! - Partition 0" dfu0
+ grep "TinyUSB DFU! - Partition 1" dfu1
+
+ - name: Test dfu_runtime
+ run: |
+ ./flash.sh dfu_runtime.elf
+ while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index d2150d13f..f984954d9 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -1,6 +1,7 @@
name: pre-commit
on:
+ workflow_dispatch:
push:
pull_request:
branches: [ master ]
@@ -26,15 +27,14 @@ jobs:
- name: Checkout TinyUSB
uses: actions/checkout@v3
- - name: Run codespell
- uses: codespell-project/actions-codespell@master
-
- - name: Run Unit Tests
+ - name: Get Dependencies
run: |
- # Install Ceedling
gem install ceedling
- cd test/unit-test
- ceedling test:all
+ #cd test/unit-test
+ #ceedling test:all
+
+ - name: Run pre-commit
+ uses: pre-commit/action@v3.0.0
- name: Build Fuzzer
run: |
diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index e434ca238..33e3db859 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -1,6 +1,7 @@
name: Trigger Repos
on:
+ workflow_dispatch:
push:
branches: master
release:
@@ -43,7 +44,7 @@ jobs:
if [ -n "$(git status --porcelain)" ]; then
git add .
git commit --message "Update from https://github.com/$GITHUB_REPOSITORY/commit/$GITHUB_SHA"
- git push
+ git push
fi
- name: Create tinyusb_src Release
@@ -53,8 +54,7 @@ jobs:
cd tinyusb_src
git tag ${{ github.event.release.tag_name }}
git push origin ${{ github.event.release.tag_name }}
-
+
# Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release
- bb={{ github.event.release.body }}
- bb=${bb//\n/\\\n}
+ bb="For release note, please checkout https://github.com/hathach/tinyusb/releases/tag/${{ github.event.release.tag_name }}"
curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases
diff --git a/.gitignore b/.gitignore
index 87a5faa80..c665d6c73 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,7 +12,7 @@ latex
*.ind
.env
.settings/
-.idea/
+.vscode/
.gdb_history
/examples/*/*/build*
test_old/
@@ -21,10 +21,68 @@ _build
/examples/*/*/ses
/examples/*/*/ozone
/examples/obsolete
+hw/bsp/**/cubemx/*/
+.mxproject
# coverity intermediate files
cov-int
# cppcheck build directories
*-build-dir
/_bin/
__pycache__
+cmake-build-*
+sdkconfig
+# submodules
+hw/mcu/allwinner
+hw/mcu/bridgetek/ft9xx/ft90x-sdk
+hw/mcu/broadcom
+hw/mcu/gd/nuclei-sdk
+hw/mcu/infineon/mtb-xmclib-cat3
+hw/mcu/microchip
+hw/mcu/mindmotion/mm32sdk
+hw/mcu/nordic/nrfx
+hw/mcu/nuvoton
+hw/mcu/nxp/lpcopen
+hw/mcu/nxp/mcux-sdk
+hw/mcu/nxp/nxp_sdk
+hw/mcu/raspberry_pi/Pico-PIO-USB
+hw/mcu/renesas/rx
+hw/mcu/silabs/cmsis-dfp-efm32gg12b
+hw/mcu/sony/cxd56/spresense-exported-sdk
+hw/mcu/st/cmsis_device_f0
+hw/mcu/st/cmsis_device_f1
+hw/mcu/st/cmsis_device_f2
+hw/mcu/st/cmsis_device_f3
+hw/mcu/st/cmsis_device_f4
+hw/mcu/st/cmsis_device_f7
+hw/mcu/st/cmsis_device_g0
+hw/mcu/st/cmsis_device_g4
+hw/mcu/st/cmsis_device_h7
+hw/mcu/st/cmsis_device_l0
+hw/mcu/st/cmsis_device_l1
+hw/mcu/st/cmsis_device_l4
+hw/mcu/st/cmsis_device_l5
+hw/mcu/st/cmsis_device_u5
+hw/mcu/st/cmsis_device_wb
+hw/mcu/st/stm32f0xx_hal_driver
+hw/mcu/st/stm32f1xx_hal_driver
+hw/mcu/st/stm32f2xx_hal_driver
+hw/mcu/st/stm32f3xx_hal_driver
+hw/mcu/st/stm32f4xx_hal_driver
+hw/mcu/st/stm32f7xx_hal_driver
+hw/mcu/st/stm32g0xx_hal_driver
+hw/mcu/st/stm32g4xx_hal_driver
+hw/mcu/st/stm32h7xx_hal_driver
+hw/mcu/st/stm32l0xx_hal_driver
+hw/mcu/st/stm32l1xx_hal_driver
+hw/mcu/st/stm32l4xx_hal_driver
+hw/mcu/st/stm32l5xx_hal_driver
+hw/mcu/st/stm32u5xx_hal_driver
+hw/mcu/st/stm32wbxx_hal_driver
+hw/mcu/ti
+hw/mcu/wch/ch32v307
+lib/CMSIS_5
+lib/FreeRTOS-Kernel
+lib/lwip
+lib/sct_neopixel
+tools/uf2
diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index 14f47746b..000000000
--- a/.gitmodules
+++ /dev/null
@@ -1,160 +0,0 @@
-[submodule "hw/mcu/nordic/nrfx"]
- path = hw/mcu/nordic/nrfx
- url = https://github.com/NordicSemiconductor/nrfx.git
-[submodule "tools/uf2"]
- path = tools/uf2
- url = https://github.com/microsoft/uf2.git
-[submodule "hw/mcu/sony/cxd56/spresense-exported-sdk"]
- path = hw/mcu/sony/cxd56/spresense-exported-sdk
- url = https://github.com/sonydevworld/spresense-exported-sdk.git
-[submodule "hw/mcu/ti"]
- path = hw/mcu/ti
- url = https://github.com/hathach/ti_driver.git
-[submodule "hw/mcu/microchip"]
- path = hw/mcu/microchip
- url = https://github.com/hathach/microchip_driver.git
-[submodule "hw/mcu/nuvoton"]
- path = hw/mcu/nuvoton
- url = https://github.com/majbthrd/nuc_driver.git
-[submodule "lib/lwip"]
- path = lib/lwip
- url = https://github.com/lwip-tcpip/lwip.git
-[submodule "hw/mcu/st/cmsis_device_f4"]
- path = hw/mcu/st/cmsis_device_f4
- url = https://github.com/STMicroelectronics/cmsis_device_f4.git
-[submodule "hw/mcu/st/stm32f4xx_hal_driver"]
- path = hw/mcu/st/stm32f4xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f0"]
- path = hw/mcu/st/cmsis_device_f0
- url = https://github.com/STMicroelectronics/cmsis_device_f0.git
-[submodule "hw/mcu/st/stm32f0xx_hal_driver"]
- path = hw/mcu/st/stm32f0xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f1"]
- path = hw/mcu/st/cmsis_device_f1
- url = https://github.com/STMicroelectronics/cmsis_device_f1.git
-[submodule "hw/mcu/st/stm32f1xx_hal_driver"]
- path = hw/mcu/st/stm32f1xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f2"]
- path = hw/mcu/st/cmsis_device_f2
- url = https://github.com/STMicroelectronics/cmsis_device_f2.git
-[submodule "hw/mcu/st/stm32f2xx_hal_driver"]
- path = hw/mcu/st/stm32f2xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f3"]
- path = hw/mcu/st/cmsis_device_f3
- url = https://github.com/STMicroelectronics/cmsis_device_f3.git
-[submodule "hw/mcu/st/stm32f3xx_hal_driver"]
- path = hw/mcu/st/stm32f3xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f7"]
- path = hw/mcu/st/cmsis_device_f7
- url = https://github.com/STMicroelectronics/cmsis_device_f7.git
-[submodule "hw/mcu/st/stm32f7xx_hal_driver"]
- path = hw/mcu/st/stm32f7xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_h7"]
- path = hw/mcu/st/cmsis_device_h7
- url = https://github.com/STMicroelectronics/cmsis_device_h7.git
-[submodule "hw/mcu/st/stm32h7xx_hal_driver"]
- path = hw/mcu/st/stm32h7xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l0"]
- path = hw/mcu/st/cmsis_device_l0
- url = https://github.com/STMicroelectronics/cmsis_device_l0.git
-[submodule "hw/mcu/st/stm32l0xx_hal_driver"]
- path = hw/mcu/st/stm32l0xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l1"]
- path = hw/mcu/st/cmsis_device_l1
- url = https://github.com/STMicroelectronics/cmsis_device_l1.git
-[submodule "hw/mcu/st/stm32l1xx_hal_driver"]
- path = hw/mcu/st/stm32l1xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l4"]
- path = hw/mcu/st/cmsis_device_l4
- url = https://github.com/STMicroelectronics/cmsis_device_l4.git
-[submodule "hw/mcu/st/stm32l4xx_hal_driver"]
- path = hw/mcu/st/stm32l4xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g0"]
- path = hw/mcu/st/cmsis_device_g0
- url = https://github.com/STMicroelectronics/cmsis_device_g0.git
-[submodule "hw/mcu/st/stm32g0xx_hal_driver"]
- path = hw/mcu/st/stm32g0xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g4"]
- path = hw/mcu/st/cmsis_device_g4
- url = https://github.com/STMicroelectronics/cmsis_device_g4.git
-[submodule "hw/mcu/st/stm32g4xx_hal_driver"]
- path = hw/mcu/st/stm32g4xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l5"]
- path = hw/mcu/st/cmsis_device_l5
- url = https://github.com/STMicroelectronics/cmsis_device_l5.git
-[submodule "hw/mcu/st/stm32l5xx_hal_driver"]
- path = hw/mcu/st/stm32l5xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_wb"]
- path = hw/mcu/st/cmsis_device_wb
- url = https://github.com/STMicroelectronics/cmsis_device_wb.git
-[submodule "hw/mcu/st/stm32wbxx_hal_driver"]
- path = hw/mcu/st/stm32wbxx_hal_driver
- url = https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git
-[submodule "lib/sct_neopixel"]
- path = lib/sct_neopixel
- url = https://github.com/gsteiert/sct_neopixel
-[submodule "lib/FreeRTOS-Kernel"]
- path = lib/FreeRTOS-Kernel
- url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "lib/CMSIS_5"]
- path = lib/CMSIS_5
- url = https://github.com/ARM-software/CMSIS_5.git
-[submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
- path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
- url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
-[submodule "hw/mcu/renesas/rx"]
- path = hw/mcu/renesas/rx
- url = https://github.com/kkitayam/rx_device.git
-[submodule "hw/mcu/nxp/lpcopen"]
- path = hw/mcu/nxp/lpcopen
- url = https://github.com/hathach/nxp_lpcopen.git
-[submodule "hw/mcu/nxp/mcux-sdk"]
- path = hw/mcu/nxp/mcux-sdk
- url = https://github.com/NXPmicro/mcux-sdk.git
-[submodule "hw/mcu/nxp/nxp_sdk"]
- path = hw/mcu/nxp/nxp_sdk
- url = https://github.com/hathach/nxp_sdk.git
-[submodule "hw/mcu/gd/nuclei-sdk"]
- path = hw/mcu/gd/nuclei-sdk
- url = https://github.com/Nuclei-Software/nuclei-sdk.git
-[submodule "hw/mcu/bridgetek/ft9xx/ft90x-sdk"]
- path = hw/mcu/bridgetek/ft9xx/ft90x-sdk
- url = https://github.com/BRTSG-FOSS/ft90x-sdk
-[submodule "hw/mcu/mindmotion/mm32sdk"]
- path = hw/mcu/mindmotion/mm32sdk
- url = https://github.com/hathach/mm32sdk.git
-[submodule "hw/mcu/broadcom"]
- path = hw/mcu/broadcom
- url = https://github.com/adafruit/broadcom-peripherals.git
- branch = main-build
-[submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
- path = hw/mcu/infineon/mtb-xmclib-cat3
- url = https://github.com/Infineon/mtb-xmclib-cat3.git
-[submodule "hw/mcu/allwinner"]
- path = hw/mcu/allwinner
- url = https://github.com/hathach/allwinner_driver.git
-[submodule "hw/mcu/wch/ch32v307"]
- path = hw/mcu/wch/ch32v307
- url = https://github.com/openwch/ch32v307.git
-[submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
- path = hw/mcu/raspberry_pi/Pico-PIO-USB
- url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
-[submodule "hw/mcu/st/cmsis_device_u5"]
- path = hw/mcu/st/cmsis_device_u5
- url = https://github.com/STMicroelectronics/cmsis_device_u5
-[submodule "hw/mcu/st/stm32u5xx_hal_driver"]
- path = hw/mcu/st/stm32u5xx_hal_driver
- url = https://github.com/STMicroelectronics/stm32u5xx_hal_driver
diff --git a/.idea/.gitignore b/.idea/.gitignore
new file mode 100644
index 000000000..73f69e095
--- /dev/null
+++ b/.idea/.gitignore
@@ -0,0 +1,8 @@
+# Default ignored files
+/shelf/
+/workspace.xml
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml
+# Editor-based HTTP Client requests
+/httpRequests/
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
new file mode 100644
index 000000000..88e0e27ad
--- /dev/null
+++ b/.idea/cmake.xml
@@ -0,0 +1,70 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
new file mode 100644
index 000000000..66f8ea684
--- /dev/null
+++ b/.idea/runConfigurations/kl25.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
new file mode 100644
index 000000000..f7d4ba402
--- /dev/null
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc4088.xml b/.idea/runConfigurations/lpc4088.xml
new file mode 100644
index 000000000..911876903
--- /dev/null
+++ b/.idea/runConfigurations/lpc4088.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc54628.xml b/.idea/runConfigurations/lpc54628.xml
new file mode 100644
index 000000000..e0047f187
--- /dev/null
+++ b/.idea/runConfigurations/lpc54628.xml
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc55s69.xml b/.idea/runConfigurations/lpc55s69.xml
new file mode 100644
index 000000000..d5e9b117a
--- /dev/null
+++ b/.idea/runConfigurations/lpc55s69.xml
@@ -0,0 +1,10 @@
+
+
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+
+
+
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+
+
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
new file mode 100644
index 000000000..31e5c27dd
--- /dev/null
+++ b/.idea/runConfigurations/mcx947.xml
@@ -0,0 +1,10 @@
+
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+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
new file mode 100644
index 000000000..3ffa16385
--- /dev/null
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -0,0 +1,10 @@
+
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+
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diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml
new file mode 100644
index 000000000..2f8009444
--- /dev/null
+++ b/.idea/runConfigurations/nrf5340.xml
@@ -0,0 +1,10 @@
+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
new file mode 100644
index 000000000..6135e5cf3
--- /dev/null
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -0,0 +1,10 @@
+
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diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
new file mode 100644
index 000000000..0833d43b3
--- /dev/null
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -0,0 +1,10 @@
+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
new file mode 100644
index 000000000..606e04e52
--- /dev/null
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -0,0 +1,10 @@
+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
new file mode 100644
index 000000000..51ae689be
--- /dev/null
+++ b/.idea/runConfigurations/rp2040.xml
@@ -0,0 +1,10 @@
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\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
new file mode 100644
index 000000000..f4f48181c
--- /dev/null
+++ b/.idea/runConfigurations/rt1010.xml
@@ -0,0 +1,10 @@
+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
new file mode 100644
index 000000000..3d740edeb
--- /dev/null
+++ b/.idea/runConfigurations/rt1060.xml
@@ -0,0 +1,10 @@
+
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\ No newline at end of file
diff --git a/.idea/runConfigurations/samd21g18.xml b/.idea/runConfigurations/samd21g18.xml
new file mode 100644
index 000000000..9a1e65563
--- /dev/null
+++ b/.idea/runConfigurations/samd21g18.xml
@@ -0,0 +1,10 @@
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\ No newline at end of file
diff --git a/.idea/runConfigurations/samd51j19.xml b/.idea/runConfigurations/samd51j19.xml
new file mode 100644
index 000000000..74d0e3649
--- /dev/null
+++ b/.idea/runConfigurations/samd51j19.xml
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\ No newline at end of file
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
new file mode 100644
index 000000000..b29b63f1a
--- /dev/null
+++ b/.idea/runConfigurations/stlink.xml
@@ -0,0 +1,10 @@
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diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
new file mode 100644
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--- /dev/null
+++ b/.idea/runConfigurations/stm32g474.xml
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diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
new file mode 100644
index 000000000..9cd142de0
--- /dev/null
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -0,0 +1,10 @@
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diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml
new file mode 100644
index 000000000..75eb3df4d
--- /dev/null
+++ b/.idea/runConfigurations/uno_r4.xml
@@ -0,0 +1,10 @@
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diff --git a/.idea/vcs.xml b/.idea/vcs.xml
new file mode 100644
index 000000000..94a25f7f4
--- /dev/null
+++ b/.idea/vcs.xml
@@ -0,0 +1,6 @@
+
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\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
new file mode 100644
index 000000000..4071ec326
--- /dev/null
+++ b/.pre-commit-config.yaml
@@ -0,0 +1,42 @@
+# SPDX-FileCopyrightText: 2020 Diego Elio Pettenò
+#
+# SPDX-License-Identifier: Unlicense
+
+repos:
+- repo: https://github.com/pre-commit/pre-commit-hooks
+ rev: v4.4.0
+ hooks:
+ - id: check-yaml
+ - id: trailing-whitespace
+ exclude: |
+ (?x)^(
+ hw/bsp/mcx/sdk/
+ )
+ - id: end-of-file-fixer
+ exclude: |
+ (?x)^(
+ .idea/|
+ hw/bsp/mcx/sdk/
+ )
+ - id: forbid-submodules
+
+- repo: https://github.com/codespell-project/codespell
+ rev: v2.2.4
+ hooks:
+ - id: codespell
+ args: [-w]
+ exclude: |
+ (?x)^(
+ lib/|
+ hw/bsp/mcx/sdk/
+ )
+
+- repo: local
+ hooks:
+ - id: unit-test
+ name: unit-test
+ files: ^(src/|test/unit-test/)
+ entry: sh -c "cd test/unit-test && ceedling test:all"
+ pass_filenames: false
+ types_or: [c, header]
+ language: system
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index e83cd90fd..e26b1f475 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -4,15 +4,21 @@
version: 2
+# Set the version of Python and other tools you might need
+build:
+ os: ubuntu-22.04
+ tools:
+ python: "3.11"
+
+# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: docs/conf.py
+# Optionally declare the Python requirements required to build your docs
python:
- version: 3.8
install:
- requirements: docs/requirements.txt
submodules:
include: []
recursive: false
-
\ No newline at end of file
diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 5726169f8..085f8082a 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -119,6 +119,7 @@ Notable contributors
- Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board
- Rewrite documentation in rst and setup for readthedocs
+- Generalize Renesas driver and support RA family with EK-RA4M3 board
`Raspberry Pi Team `__
@@ -199,6 +200,8 @@ Notable contributors
- Add new DCD port for Microchip SAMx7x
- Add IAR compiler support
- Improve UAC2, CDC, DFU class driver
+- Improve stm32_fsdev, chipidea_ci_hs, lpc_ip3511 DCD
+- Host IAR Build CI & hardware in the loop (HITL) test
`Full contributors list `__
diff --git a/README.rst b/README.rst
index 7825a1b0a..aef310b98 100644
--- a/README.rst
+++ b/README.rst
@@ -20,8 +20,8 @@ Please take a look at the online `documentation `__.
├── docs # Documentation
├── examples # Sample with Makefile build support
├── hw
- │ ├── bsp # Supported boards source files
- │ └── mcu # Low level mcu core & peripheral drivers
+ │ ├── bsp # Supported boards source files
+ │ └── mcu # Low level mcu core & peripheral drivers
├── lib # Sources from 3rd party such as freeRTOS, fatfs ...
├── src # All sources files for TinyUSB stack itself.
├── test # Unit tests for the stack
@@ -33,6 +33,7 @@ Supported MCUs
The stack supports the following MCUs:
- **Allwinner:** F1C100s/F1C200s
+- **Analog:** MAX3421e (aka Arduino usb host shield)
- **Broadcom:** BCM2837, BCM2711
- **Dialog:** DA1469x
- **Espressif:** ESP32-S2, ESP32-S3
@@ -46,12 +47,17 @@ The stack supports the following MCUs:
- iMX RT Series: RT10xx, RT11xx
- Kinetis: KL25, K32L2
- LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
+ - MCX: N9x
- **Raspberry Pi:** RP2040
-- **Renesas:** RX63N, RX65N, RX72N
+- **Renesas:**
+
+ - RX Series: 63n, 65n, 72n
+ - RA Series: 4m1, 4m3, 6m1, 6m5
+
- **Silabs:** EFM32GG
- **Sony:** CXD56
-- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+, WB
+- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G0, G4, L0, L1, L4, L4+, WB
- **TI:** MSP430, MSP432E4, TM4C123
- **ValentyUSB:** eptri
- **WCH:** CH32V307
@@ -83,8 +89,19 @@ Host Stack
- Human Interface Device (HID): Keyboard, Mouse, Generic
- Mass Storage Class (MSC)
+- Communication Device Class: CDC-ACM
+- Vendor serial over USB: FTDI, CP210x
- Hub with multiple-level support
+Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
+
+TypeC PD Stack
+==============
+
+- Power Delivery 3.0 (PD3.0) with USB Type-C support (WIP)
+- Super early stage, only for testing purpose
+- Only support STM32 G4
+
OS Abstraction layer
====================
@@ -108,6 +125,7 @@ Docs
- `Supported Devices`_
- `Getting Started`_
+ - `Dependencies`_
- `Concurrency`_
- `Contributing`_
@@ -126,7 +144,7 @@ Please make sure you understand all the license term for files you use
in your project.
-.. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
+.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg
:target: https://github.com/hathach/tinyusb/actions
.. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
:target: https://docs.tinyusb.org/en/latest/?badge=latest
@@ -142,6 +160,7 @@ in your project.
.. _Reference: docs/reference/index.rst
.. _Supported Devices: docs/reference/supported.rst
.. _Getting Started: docs/reference/getting_started.rst
+.. _Dependencies: docs/reference/dependencies.rst
.. _Concurrency: docs/reference/concurrency.rst
.. _Contributing: docs/contributing/index.rst
.. _Code of Conduct: CODE_OF_CONDUCT.rst
diff --git a/docs/assets/stack.svg b/docs/assets/stack.svg
index 85fe35e96..ed46c8649 100644
--- a/docs/assets/stack.svg
+++ b/docs/assets/stack.svg
@@ -1 +1 @@
-
\ No newline at end of file
+
diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
index 710af51c3..f81d98782 100644
--- a/docs/contributing/porting.rst
+++ b/docs/contributing/porting.rst
@@ -62,9 +62,9 @@ Feel free to skip this until you want to verify your demo code is running. To im
OS Abstraction Layer (OSAL)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
-The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts.
+The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts. The code is almost entirely agnostic of MCU and lives in ``src/osal``.
-The code is almost entirely agnostic of MCU and lives in ``src/osal``.
+In RTOS configurations, tud_task()/tuh_task() blocks behind a synchronization structure when the event queue is empty, so that the scheduler may give the CPU to a different task. To take advantage of the library's capability to yield the CPU when there are no actionable USB device events, ensure that the `CFG_TUSB_OS` symbol is defined, e.g `OPT_OS_FREERTOS` enables the FreeRTOS scheduler to schedule other threads than that which calls `tud_task()/tuh_task()`.
Device API
^^^^^^^^^^
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 451e3dace..c6c02d181 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -15,7 +15,7 @@ Changelog
- Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths)
- Better support for IAR (ARM) with ci build check for stm32 mcus.
- Fix Windows build for some mingw gnu make situations
-
+
Controller Driver (DCD & HCD)
-----------------------------
@@ -27,7 +27,7 @@ Controller Driver (DCD & HCD)
- Fix endpoint internal state when closed
- Fix reception of large ISO packets
-- [rp2040]
+- [rp2040]
- [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80%
- [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times
@@ -51,7 +51,7 @@ Device Stack
- Support port name strings
- fix MS Header wTotalLength computation
-
+
- [HID]
- Add FIDO descriptor template
@@ -60,7 +60,7 @@ Device Stack
- [CDC]
- Fix autoflush for FIFO < MPS
- - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data
+ - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data
- [USBTMC] Fix packet size with highspeed
@@ -93,21 +93,21 @@ Controller Driver (DCD & HCD)
- CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE
- tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void)
-- Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific)
+- Add dcd/hcd port specific defines `TUP_` (stand for tinyusb port-specific)
- [dwc2]
- Update to support stm32 h72x, h73x with only 1 otg controller
- Fix overwrite with grstctl when disable endpoint
- [EHCI] Fix an issue with EHCI driver
- [msp430] Fix for possible bug in msp430-elf-gcc 9.3.0
-- [nrf5x] Fix DMA access race condition using atomic function
+- [nrf5x] Fix DMA access race condition using atomic function
- [pic32] Fix PIC32 santiy
- [rp2040]
- Add PICO-PIO-USB as controller (device/host) support for rp2040
- Use shared IRQ handlers, so user can also hook the USB IRQ
- Fix resumed signal not reported to device stack
-- [stm32fsdev] Add support for stm32wb55
+- [stm32fsdev] Add support for stm32wb55
Device Stack
------------
@@ -159,7 +159,7 @@ Controller Driver (DCD & HCD)
- [F1C100s] Add new DCD for Allwinner F1C100s family
- [PIC32MZ] Add new DCD for PIC32MZ
- [nRF] Fix/Enhance various race condition with: EASY DMA, request HFXO, EPOUT
-- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed,
+- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed,
- [RP2040] various update/fix for hcd/dcd
- [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices
- [DA1469X] Fix resume
@@ -246,7 +246,7 @@ RP2040
^^^^^^
- Add RP2040 suspend & resume support
-- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet
+- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet
Device Stack
------------
@@ -267,7 +267,7 @@ DFU
^^^
- Enhance DFU implementation to support multiple alternate interface and better support bwPollTimeout
-- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU
+- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU
HID
^^^
@@ -287,7 +287,7 @@ UAC2
^^^^
- Fix bug and enhance of UAC2
-
+
Vendor
^^^^^^
@@ -479,7 +479,7 @@ Host Controller Driver (HCD)
- Move echi/ohci files to portable/
- Rename hcd_lpc18_43 to hcd_transdimension
- Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
-
+
- Update NXP transdimention hcd_init() to reset controller to host mode
- Ported hcd to rt10xx
@@ -529,13 +529,13 @@ Device Controller Driver
- ESP32-S2:
- Add bus suspend and wakeup support
-
+
- SAMD21:
- Fix (walkaround) samd21 setup_packet overflow by USB DMA
-
+
- STM32 Synopsys:
- Rework USB FIFO allocation scheme and allow RX FIFO size reduction
-
+
- Sony CXD56
- Update Update Spresense SDK to 2.0.2
- Fix dcd issues with setup packets
@@ -554,17 +554,17 @@ USB Device
- CDC
- Allow to transmit data, even if the host does not support control line states i.e set DTR
-
+
- HID
- change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
-
+
- MIDI
- Fix midi sysex sending bug
-
+
- MSC
- Invoke only scsi complete callback after status transaction is complete.
- Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
-
+
- USBTMC
- Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
@@ -614,20 +614,20 @@ Device Controller Driver
- Fix FIFO flush during stall
- Implement dcd_edpt_close() API
- Support F105, F107
-
+
- Enhance STM32 fsdev
- Improve dcd fifo allocation
- Fix ISTR race condition
- Support remap USB IRQ on supported MCUs
- Implement dcd_edpt_close() API
-
+
- Enhance NUC 505: enhance set configure behavior
- Enhance SAMD
- Fix race condition with setup packet
- Add SAMD11 option `OPT_MCU_SAMD11`
- Add SAME5x option `OPT_MCU_SAME5X`
-
+
- Fix SAMG control data toggle and stall race condition
- Enhance nRF
@@ -659,7 +659,7 @@ USB Device
- `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
- Add application implemented class driver via `usbd_app_driver_get_cb()`
- IAD is handled to assign driver id
-
+
- Added `tud_descriptor_device_qualifier_cb()` callback
- Optimize `tu_fifo` bulk write/read transfer
- Forward non-std control request to class driver
@@ -675,12 +675,12 @@ USB Device
- Send zero length packet for end of data when needed
- Add `tud_cdc_tx_complete_cb()` callback
- Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
-
+
- MIDI:
- Add packet interface
- Add multiple jack descriptors
- Fix MIDI driver for sysex
-
+
- DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
- Rename some configure macro to make it clear that those are used directly for endpoint transfer
@@ -688,7 +688,7 @@ USB Device
- CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
- CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
- CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
-
+
- HID:
- Fix gamepad template descriptor
- Add multiple HID interface API
@@ -700,7 +700,7 @@ USB Host
- Rework USB host stack (still work in progress)
- Fix compile error with pipehandle
- Rework usbh control and enumeration as non-blocking
-
+
- Improve Hub, MSC, HID host driver
Examples
@@ -713,7 +713,7 @@ Examples
- Enhance `net_lwip_webserver` example
- Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
- Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
-
+
- Added new Audio example: audio_test uac2_headsest
New Boards
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
new file mode 100644
index 000000000..130527e2c
--- /dev/null
+++ b/docs/reference/dependencies.rst
@@ -0,0 +1,64 @@
+************
+Dependencies
+************
+
+MCU low-level peripheral driver and external libraries for building TinyUSB examples
+
+======================================== ============================================================== ========================================
+Path Project Commit
+======================================== ============================================================== ========================================
+hw/mcu/allwinner https://github.com/hathach/allwinner_driver.git 8e5e89e8e132c0fd90e72d5422e5d3d68232b756
+hw/mcu/bridgetek/ft9xx/ft90x-sdk https://github.com/BRTSG-FOSS/ft90x-sdk.git 91060164afe239fcb394122e8bf9eb24d3194eb1
+hw/mcu/broadcom https://github.com/adafruit/broadcom-peripherals.git 08370086080759ed54ac1136d62d2ad24c6fa267
+hw/mcu/gd/nuclei-sdk https://github.com/Nuclei-Software/nuclei-sdk.git 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7
+hw/mcu/infineon/mtb-xmclib-cat3 https://github.com/Infineon/mtb-xmclib-cat3.git daf5500d03cba23e68c2f241c30af79cd9d63880
+hw/mcu/microchip https://github.com/hathach/microchip_driver.git 9e8b37e307d8404033bb881623a113931e1edf27
+hw/mcu/mindmotion/mm32sdk https://github.com/hathach/mm32sdk.git 0b79559eb411149d36e073c1635c620e576308d4
+hw/mcu/nordic/nrfx https://github.com/NordicSemiconductor/nrfx.git 281cc2e178fd9a470d844b3afdea9eb322a0b0e8
+hw/mcu/nuvoton https://github.com/majbthrd/nuc_driver.git 2204191ec76283371419fbcec207da02e1bc22fa
+hw/mcu/nxp/lpcopen https://github.com/hathach/nxp_lpcopen.git 43c45c85405a5dd114fff0ea95cca62837740c13
+hw/mcu/nxp/mcux-sdk https://github.com/NXPmicro/mcux-sdk.git ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294
+hw/mcu/nxp/nxp_sdk https://github.com/hathach/nxp_sdk.git 845c8fc49b6fb660f06a5c45225494eacb06f00c
+hw/mcu/raspberry_pi/Pico-PIO-USB https://github.com/sekigon-gonnoc/Pico-PIO-USB.git c3715ce94b6f6391856de56081d4d9b3e98fa93d
+hw/mcu/renesas/fsp https://github.com/renesas/fsp.git 8dc14709f2a6518b43f71efad70d900b7718d9f1
+hw/mcu/renesas/rx https://github.com/kkitayam/rx_device.git 706b4e0cf485605c32351e2f90f5698267996023
+hw/mcu/silabs/cmsis-dfp-efm32gg12b https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git f1c31b7887669cb230b3ea63f9b56769078960bc
+hw/mcu/sony/cxd56/spresense-exported-sdk https://github.com/sonydevworld/spresense-exported-sdk.git 2ec2a1538362696118dc3fdf56f33dacaf8f4067
+hw/mcu/st/cmsis_device_f0 https://github.com/STMicroelectronics/cmsis_device_f0.git 2fc25ee22264bc27034358be0bd400b893ef837e
+hw/mcu/st/cmsis_device_f1 https://github.com/STMicroelectronics/cmsis_device_f1.git 6601104a6397299b7304fd5bcd9a491f56cb23a6
+hw/mcu/st/cmsis_device_f2 https://github.com/STMicroelectronics/cmsis_device_f2.git 182fcb3681ce116816feb41b7764f1b019ce796f
+hw/mcu/st/cmsis_device_f3 https://github.com/STMicroelectronics/cmsis_device_f3.git 5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b
+hw/mcu/st/cmsis_device_f4 https://github.com/STMicroelectronics/cmsis_device_f4.git 2615e866fa48fe1ff1af9e31c348813f2b19e7ec
+hw/mcu/st/cmsis_device_f7 https://github.com/STMicroelectronics/cmsis_device_f7.git fc676ef1ad177eb874eaa06444d3d75395fc51f4
+hw/mcu/st/cmsis_device_g0 https://github.com/STMicroelectronics/cmsis_device_g0.git 08258b28ee95f50cb9624d152a1cbf084be1f9a5
+hw/mcu/st/cmsis_device_g4 https://github.com/STMicroelectronics/cmsis_device_g4.git ce822adb1dc552b3aedd13621edbc7fdae124878
+hw/mcu/st/cmsis_device_h7 https://github.com/STMicroelectronics/cmsis_device_h7.git 60dc2c913203dc8629dc233d4384dcc41c91e77f
+hw/mcu/st/cmsis_device_l0 https://github.com/STMicroelectronics/cmsis_device_l0.git 06748ca1f93827befdb8b794402320d94d02004f
+hw/mcu/st/cmsis_device_l1 https://github.com/STMicroelectronics/cmsis_device_l1.git 7f16ec0a1c4c063f84160b4cc6bf88ad554a823e
+hw/mcu/st/cmsis_device_l4 https://github.com/STMicroelectronics/cmsis_device_l4.git 6ca7312fa6a5a460b5a5a63d66da527fdd8359a6
+hw/mcu/st/cmsis_device_l5 https://github.com/STMicroelectronics/cmsis_device_l5.git d922865fc0326a102c26211c44b8e42f52c1e53d
+hw/mcu/st/cmsis_device_u5 https://github.com/STMicroelectronics/cmsis_device_u5.git bc00f3c9d8a4e25220f84c26d414902cc6bdf566
+hw/mcu/st/cmsis_device_wb https://github.com/STMicroelectronics/cmsis_device_wb.git 9c5d1920dd9fabbe2548e10561d63db829bb744f
+hw/mcu/st/stm32f0xx_hal_driver https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git 0e95cd88657030f640a11e690a8a5186c7712ea5
+hw/mcu/st/stm32f1xx_hal_driver https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git 1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29
+hw/mcu/st/stm32f2xx_hal_driver https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git c75ace9b908a9aca631193ebf2466963b8ea33d0
+hw/mcu/st/stm32f3xx_hal_driver https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git 1761b6207318ede021706e75aae78f452d72b6fa
+hw/mcu/st/stm32f4xx_hal_driver https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git 04e99fbdabd00ab8f370f377c66b0a4570365b58
+hw/mcu/st/stm32f7xx_hal_driver https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git f7ffdf6bf72110e58b42c632b0a051df5997e4ee
+hw/mcu/st/stm32g0xx_hal_driver https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git 5b53e6cee664a82b16c86491aa0060e2110c00cb
+hw/mcu/st/stm32g4xx_hal_driver https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git 8b4518417706d42eef5c14e56a650005abf478a8
+hw/mcu/st/stm32h7xx_hal_driver https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04
+hw/mcu/st/stm32l0xx_hal_driver https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b
+hw/mcu/st/stm32l1xx_hal_driver https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git 44efc446fa69ed8344e7fd966e68ed11043b35d9
+hw/mcu/st/stm32l4xx_hal_driver https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git aee3d5bf283ae5df87532b781bdd01b7caf256fc
+hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git 675c32a75df37f39d50d61f51cb0dcf53f07e1cb
+hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 2e1d4cdb386e33391cb261dfff4fefa92e4aa35a
+hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8
+hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5
+hw/mcu/wch/ch32v307 https://github.com/openwch/ch32v307.git 17761f5cf9dbbf2dcf665b7c04934188add20082
+lib/CMSIS_5 https://github.com/ARM-software/CMSIS_5.git 20285262657d1b482d132d20d755c8c330d55c1f
+lib/FreeRTOS-Kernel https://github.com/FreeRTOS/FreeRTOS-Kernel.git def7d2df2b0506d3d249334974f51e427c17a41c
+lib/lwip https://github.com/lwip-tcpip/lwip.git 159e31b689577dbf69cf0683bbaffbd71fa5ee10
+lib/sct_neopixel https://github.com/gsteiert/sct_neopixel.git e73e04ca63495672d955f9268e003cffe168fcd8
+tools/uf2 https://github.com/microsoft/uf2.git 19615407727073e36d81bf239c52108ba92e7660
+======================================== ============================================================== ========================================
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index e328757ba..1f41cb888 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -44,40 +44,36 @@ For your convenience, TinyUSB contains a handful of examples for both host and d
$ git clone https://github.com/hathach/tinyusb tinyusb
$ cd tinyusb
-Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them
-
-.. code-block::
-
- $ git submodule update --init lib
-
-Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide.
+Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide.
Build
^^^^^
-To build example, first change directory to an example folder.
+To build example, first change directory to an example folder.
.. code-block::
$ cd examples/device/cdc_msc
-Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu
+Before building, we firstly need to download dependencies such as: MCU low-level peripheral driver and external libraries e.g FreeRTOS (required by some examples). Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu. Check out `complete list of dependencies and their designated path here `_
.. code-block::
- $ make BOARD=feather_nrf52840_express get-deps
-
-
-Some modules (e.g. RP2040 and ESP32s2) require the project makefiles to be customized using CMake. If necessary apply any setup steps for the platform's SDK.
+ $ make BOARD=raspberry_pi_pico get-deps
Then compile with ``make BOARD=[board_name] all``\ , for example
.. code-block::
- $ make BOARD=feather_nrf52840_express all
+ $ make BOARD=raspberry_pi_pico all
Note: ``BOARD`` can be found as directory name in ``hw/bsp``\ , either in its family/boards or directly under bsp (no family).
-Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
+Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``99-tinyusb.rules`` and reload your udev is good to go
+
+.. code-block::
+
+ $ cp examples/device/99-tinyusb.rules /etc/udev/rules.d/
+ $ sudo udevadm control --reload-rules && sudo udevadm trigger
Port Selection
~~~~~~~~~~~~~~
@@ -118,7 +114,7 @@ To compile for debugging add ``DEBUG=1``\ , for example
Log
~~~
-Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet.
+Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet.
.. code-block::
@@ -127,7 +123,7 @@ Should you have an issue running example and/or submitting an bug report. You co
Logger
~~~~~~
-By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols:
+By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols:
* `LOGGER=rtt`: use `Segger RTT protocol `_
@@ -178,12 +174,12 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj
* Take example of STM32F0:
-
+
- You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`.
- `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs.
-* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects)
+* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects)
Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack,
for example `C:\\tinyusb`
diff --git a/docs/reference/index.rst b/docs/reference/index.rst
index 292fb1a93..a9663ee7d 100644
--- a/docs/reference/index.rst
+++ b/docs/reference/index.rst
@@ -56,4 +56,5 @@ Index
supported
getting_started
+ dependencies
concurrency
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7ec568ede..aed64782c 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -61,9 +61,11 @@ Supported MCUs
| | | 55 | ✔ | | ✔ | lpc_ip3511 | |
+--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
| Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040, pio_usb | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Renesas | RX 63N, 65N, 72N | ✔ | ✔ | ✖ | usba | |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
+| Renesas | RX | 63N, 65N, 72N | ✔ | ✔ | ✖ | rusb2 | |
+| +-----+-----------------+--------+------+-----------+-------------------+--------------+
+| | RA | XXX | ✔ | ✔ | | rusb2 | |
++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
| Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | |
+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | |
@@ -173,7 +175,7 @@ SAMD11 & SAMD21
- `Adafruit Feather M0 Express `__
- `Adafruit ItsyBitsy M0 Express `__
- `Adafruit Metro M0 Express `__
-- `Great Scott Gadgets LUNA `__
+- `Great Scott Gadgets Cynthion `__
- `Microchip SAMD11 Xplained Pro `__
- `Microchip SAMD21 Xplained Pro `__
- `Seeeduino Xiao `__
@@ -251,6 +253,7 @@ Kinetis
^^^^^^^
- `Freedom FRDM-KL25Z `__
+- `Freedom FRDM-K32L2A4S `__
- `Freedom FRDM-K32L2B3 `__
- `KUIIC `__
@@ -295,8 +298,17 @@ LPC55
- `LPCXpresso 55s69 EVK `__
- `MCU-Link `__
-Renesas RX
-----------
+Renesas
+-------
+
+RA
+^^
+
+- `Evaluation Kit for RA4M1 `__
+- `Evaluation Kit for RA4M3 `__
+
+RX
+^^
- `GR-CITRUS `__
- `Renesas RX65N Target Board `__
diff --git a/docs/requirements.txt b/docs/requirements.txt
index 15022e147..ad5c89922 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,4 +1,4 @@
-sphinx~=3.0
+sphinx>=5.0
furo>=2020.12.30.b24
sphinx-autodoc-typehints>=1.10
-jinja2==3.0.3
+jinja2>=3.0.3
diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
new file mode 100644
index 000000000..c603d0c22
--- /dev/null
+++ b/examples/CMakeLists.txt
@@ -0,0 +1,11 @@
+cmake_minimum_required(VERSION 3.17)
+
+#set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
+
+project(tinyusb_examples C CXX ASM)
+
+add_subdirectory(device)
+add_subdirectory(dual)
+add_subdirectory(host)
+add_subdirectory(typec)
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index edf5ab805..0a2e49ef0 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -1,20 +1,23 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
-project(tinyusb_device_examples)
+project(tinyusb_device_examples C CXX ASM)
family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
# family_add_subdirectory will filter what to actually add based on selected FAMILY
family_add_subdirectory(audio_4_channel_mic)
family_add_subdirectory(audio_test)
+family_add_subdirectory(audio_test_multi_rate)
family_add_subdirectory(board_test)
family_add_subdirectory(cdc_dual_ports)
family_add_subdirectory(cdc_msc)
family_add_subdirectory(cdc_msc_freertos)
+family_add_subdirectory(cdc_uac2)
family_add_subdirectory(dfu)
family_add_subdirectory(dfu_runtime)
family_add_subdirectory(dynamic_configuration)
+family_add_subdirectory(hid_boot_interface)
family_add_subdirectory(hid_composite)
family_add_subdirectory(hid_composite_freertos)
family_add_subdirectory(hid_generic_inout)
diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index f6e10e2ea..0f5d36193 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -1,28 +1,38 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Add libm for GCC
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_libraries(${PROJECT} PUBLIC m)
+endif()
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 5a455078e..8ee6a01ec 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -6,7 +5,10 @@ INC += \
$(TOP)/hw \
# Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+ src/main.c \
+ src/usb_descriptors.c \
+
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
include ../../rules.mk
diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt
index ae9b57f1f..3c42a96d9 100644
--- a/examples/device/audio_4_channel_mic/skip.txt
+++ b/examples/device/audio_4_channel_mic/skip.txt
@@ -1,3 +1,4 @@
mcu:SAMD11
mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
+family:broadcom_64bit
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index a6af5fd19..9c37315c8 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Reinhard Panhuber
@@ -34,17 +34,16 @@
#include
#include
#include
+#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
+#include "tusb_config.h"
//--------------------------------------------------------------------+
// MACRO CONSTANT TYPEDEF PROTYPES
//--------------------------------------------------------------------+
-
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE 48000
-#endif
+#define AUDIO_SAMPLE_RATE CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE
/* Blink pattern
* - 250 ms : device not mounted
@@ -70,8 +69,13 @@ uint8_t clkValid;
audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
-// Audio test data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2]; // Ensure half word aligned
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN]; // Ensure half word aligned
+#endif
void led_blinking_task(void);
void audio_task(void);
@@ -84,6 +88,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
// Init values
sampFreq = AUDIO_SAMPLE_RATE;
clkValid = 1;
@@ -93,15 +101,51 @@ int main(void)
sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
sampleFreqRng.subrange[0].bRes = 0;
+ // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+ uint16_t * p_buff = i2s_dummy_buffer[0];
+ uint16_t dataVal = 1;
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH0 saw wave
+ *p_buff++ = dataVal;
+ // CH1 inverted saw wave
+ *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+ dataVal++;
+ }
+ p_buff = i2s_dummy_buffer[1];
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH3 square wave
+ *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+ // CH4 sinus wave
+ float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+ *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
+ }
+#else
+ uint16_t * p_buff = i2s_dummy_buffer;
+ uint16_t dataVal = 1;
+ for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+ {
+ // CH0 saw wave
+ *p_buff++ = dataVal;
+ // CH1 inverted saw wave
+ *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+ dataVal++;
+ // CH3 square wave
+ *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+ // CH4 sinus wave
+ float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+ *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
+ }
+#endif
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
audio_task();
}
-
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -132,7 +176,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
@@ -290,7 +334,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
// Those are dummy values for now
ret.bNrChannels = 1;
- ret.bmChannelConfig = 0;
+ ret.bmChannelConfig = (audio_channel_config_t) 0;
ret.iChannelNames = 0;
TU_LOG2(" Get terminal connector\r\n");
@@ -363,7 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
{
case AUDIO_CS_REQ_CUR:
TU_LOG2(" Get Sample Freq.\r\n");
- return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+ // Buffered control transfer is needed for IN flow control to work
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
case AUDIO_CS_REQ_RANGE:
TU_LOG2(" Get Sample Freq. range\r\n");
@@ -399,11 +444,24 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
(void) ep_in;
(void) cur_alt_setting;
- for (uint8_t cnt=0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
+
+ // In read world application data flow is driven by I2S clock,
+ // both tud_audio_tx_done_pre_load_cb() & tud_audio_tx_done_post_load_cb() are hardly used.
+ // For example in your I2S receive callback:
+ // void I2S_Rx_Callback(int channel, const void* data, uint16_t samples)
+ // {
+ // tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
+ // }
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+ // Write I2S buffer into FIFO
+ for (uint8_t cnt=0; cnt < 2; cnt++)
{
tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
}
-
+#else
+ tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
return true;
}
@@ -415,22 +473,6 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
(void) ep_in;
(void) cur_alt_setting;
- uint16_t dataVal;
-
- // Generate dummy data
- for (uint16_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
- {
- uint16_t * p_buff = i2s_dummy_buffer[cnt]; // 2 bytes per sample
- dataVal = 1;
- for (uint16_t cnt2 = 0; cnt2 < AUDIO_SAMPLE_RATE/1000; cnt2++)
- {
- for (uint8_t cnt3 = 0; cnt3 < CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX; cnt3++)
- {
- *p_buff++ = dataVal;
- }
- dataVal++;
- }
- }
return true;
}
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
index 9ab15135d..d17a908b6 100644
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -10,11 +10,11 @@ if __name__ == '__main__':
# print(sd.query_devices())
fs = 48000 # Sample rate
- duration = 100e-3 # Duration of recording
+ duration = 1 # Duration of recording
if platform.system() == 'Windows':
# WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
- device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+ device = 'Microphone (MicNode_4_Ch), Windows WASAPI'
elif platform.system() == 'Darwin':
device = 'MicNode_4_Ch'
else:
@@ -25,10 +25,13 @@ if __name__ == '__main__':
sd.wait() # Wait until recording is finished
print('Done!')
+
time = np.arange(0, duration, 1 / fs) # time vector
+ # strip starting zero
+
plt.plot(time, myrecording)
plt.xlabel('Time [s]')
plt.ylabel('Amplitude')
plt.title('MicNode 4 Channel')
+ plt.legend(['CH-1', 'CH-2', 'CH-3','CH-4'])
plt.show()
-
\ No newline at end of file
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 5cf6d07c3..cf44918e2 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -103,6 +103,7 @@ extern "C" {
//--------------------------------------------------------------------
// Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE 48000
#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
@@ -112,15 +113,27 @@ extern "C" {
#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
-#define CFG_TUD_AUDIO_EP_SZ_IN (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - the Windows driver always needs an extra sample per channel of space more, otherwise it complains... found by trial and error
+#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_ENABLE_ENCODING 1
#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1
#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ 4 * CFG_TUD_AUDIO_EP_SZ_IN // Minimum 4*EP size is needed for flow control
+
+#endif
#ifdef __cplusplus
}
diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 8929f3057..728a5f9ce 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -44,7 +45,7 @@ tusb_desc_device_t const desc_device =
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
- // Use Interface Association Descriptor (IAD) for CDC
+ // Use Interface Association Descriptor (IAD) for Audio
// As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
.bDeviceClass = TUSB_CLASS_MISC,
.bDeviceSubClass = MISC_SUBCLASS_COMMON,
@@ -96,7 +97,7 @@ enum
uint8_t const desc_configuration[] =
{
- // Interface count, string index, total length, attribute, power in mA
+ // Config number, interface count, string index, total length, attribute, power in mA
TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
// Interface number, string index, EP Out & EP In address, EP size
@@ -116,50 +117,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
- (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
- "PaniRCorp", // 1: Manufacturer
- "MicNode_4_Ch", // 2: Product
- "123458", // 3: Serials, should use chip ID
- "UAC2", // 4: Audio Interface
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
};
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const* string_desc_arr [] = {
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "PaniRCorp", // 1: Manufacturer
+ "MicNode_4_Ch", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2", // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Convert ASCII string into UTF-16
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index cb321f9a8..f61e1b640 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test/Makefile b/examples/device/audio_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/audio_test/Makefile
+++ b/examples/device/audio_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/audio_test/skip.txt b/examples/device/audio_test/skip.txt
index ae9b57f1f..1ee86a485 100644
--- a/examples/device/audio_test/skip.txt
+++ b/examples/device/audio_test/skip.txt
@@ -1,3 +1,3 @@
mcu:SAMD11
mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index d0849c7ac..06783ccfb 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Reinhard Panhuber
@@ -35,7 +35,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -71,7 +71,7 @@ audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1];
audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
// Audio test data
-uint16_t test_buffer_audio[CFG_TUD_AUDIO_EP_SZ_IN/2];
+uint16_t test_buffer_audio[(CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2];
uint16_t startVal = 0;
void led_blinking_task(void);
@@ -85,6 +85,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
// Init values
sampFreq = AUDIO_SAMPLE_RATE;
clkValid = 1;
@@ -100,9 +104,6 @@ int main(void)
led_blinking_task();
audio_task();
}
-
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -133,7 +134,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
@@ -291,7 +292,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
// Those are dummy values for now
ret.bNrChannels = 1;
- ret.bmChannelConfig = 0;
+ ret.bmChannelConfig = (audio_channel_config_t) 0;
ret.iChannelNames = 0;
TU_LOG2(" Get terminal connector\r\n");
@@ -400,7 +401,7 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
(void) ep_in;
(void) cur_alt_setting;
- tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN);
+ tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN - 2);
return true;
}
@@ -413,7 +414,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
(void) ep_in;
(void) cur_alt_setting;
- for (size_t cnt = 0; cnt < CFG_TUD_AUDIO_EP_SZ_IN/2; cnt++)
+ for (size_t cnt = 0; cnt < (CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2; cnt++)
{
test_buffer_audio[cnt] = startVal++;
}
diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py
index 6e3c4978e..1504684a6 100644
--- a/examples/device/audio_test/src/plot_audio_samples.py
+++ b/examples/device/audio_test/src/plot_audio_samples.py
@@ -2,6 +2,7 @@ import sounddevice as sd
import matplotlib.pyplot as plt
import numpy as np
import platform
+import csv
if __name__ == '__main__':
@@ -31,4 +32,6 @@ if __name__ == '__main__':
plt.ylabel('Amplitude')
plt.title('MicNode')
plt.show()
-
\ No newline at end of file
+
+ samples = np.array(myrecording)
+ np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 355ed1011..9f38612a9 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -114,7 +114,7 @@ extern "C" {
#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX 2 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 1 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
-#define CFG_TUD_AUDIO_EP_SZ_IN 48 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX // 48 Samples (48 kHz) x 2 Bytes/Sample x 1 Channel
+#define CFG_TUD_AUDIO_EP_SZ_IN (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - One extra sample is needed for asynchronous transfer adjustment, see feedback EP
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN // Maximum EP IN size for all AS alternate settings used
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN + 1
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index da3e203d7..9864377f6 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -44,7 +45,7 @@ tusb_desc_device_t const desc_device =
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
- // Use Interface Association Descriptor (IAD) for CDC
+ // Use Interface Association Descriptor (IAD) for Audio
// As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
.bDeviceClass = TUSB_CLASS_MISC,
.bDeviceSubClass = MISC_SUBCLASS_COMMON,
@@ -96,7 +97,7 @@ enum
uint8_t const desc_configuration[] =
{
- // Interface count, string index, total length, attribute, power in mA
+ // Config number, interface count, string index, total length, attribute, power in mA
TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
// Interface number, string index, EP Out & EP In address, EP size
@@ -116,50 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
char const* string_desc_arr [] =
{
- (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
- "PaniRCorp", // 1: Manufacturer
- "MicNode", // 2: Product
- "123456", // 3: Serials, should use chip ID
- "UAC2", // 4: Audio Interface
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "PaniRCorp", // 1: Manufacturer
+ "MicNode", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2", // 4: Audio Interface
+
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Convert ASCII string into UTF-16
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
new file mode 100644
index 000000000..f61e1b640
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -0,0 +1,33 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test_multi_rate/Makefile b/examples/device/audio_test_multi_rate/Makefile
new file mode 100644
index 000000000..2a3d854fb
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/Makefile
@@ -0,0 +1,11 @@
+include ../../make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/audio_test_multi_rate/skip.txt b/examples/device/audio_test_multi_rate/skip.txt
new file mode 100644
index 000000000..1ee86a485
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/skip.txt
@@ -0,0 +1,3 @@
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
new file mode 100644
index 000000000..3e7f40dac
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -0,0 +1,525 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Reinhard Panhuber
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* plot_audio_samples.py requires following modules:
+ * $ sudo apt install libportaudio
+ * $ pip3 install sounddevice matplotlib
+ *
+ * Then run
+ * $ python3 plot_audio_samples.py
+ */
+
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+uint32_t sampFreq;
+uint8_t bytesPerSample;
+uint8_t clkValid;
+
+// Range states
+// List of supported sample rates
+static const uint32_t sampleRatesList[] =
+{
+ 32000, 48000, 96000
+};
+
+#define N_sampleRates TU_ARRAY_SIZE(sampleRatesList)
+
+// Bytes per format of every Alt settings
+static const uint8_t bytesPerSampleAltList[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] =
+{
+ CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX,
+ CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX,
+};
+
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
+
+
+// Audio test data
+CFG_TUSB_MEM_ALIGN uint8_t test_buffer_audio[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+uint16_t startVal = 0;
+
+void led_blinking_task(void);
+void audio_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+ board_init();
+
+ // init device stack on configured roothub port
+ tud_init(BOARD_TUD_RHPORT);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ // Init values
+ sampFreq = sampleRatesList[0];
+ clkValid = 1;
+
+ while (1)
+ {
+ tud_task(); // tinyusb device task
+ led_blinking_task();
+ audio_task();
+ }
+
+
+ return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+ (void) remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+ // Yet to be filled - e.g. put meas data into TX FIFOs etc.
+ // asm("nop");
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when set interface is called, typically on start/stop streaming or format change
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void)rhport;
+ //uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+ uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+ // Clear buffer when streaming format is changed
+ if(alt != 0)
+ {
+ bytesPerSample = bytesPerSampleAltList[alt-1];
+ }
+ return true;
+}
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+ (void) pBuff;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ (void) itf;
+
+ // We do not support any set range requests here, only current value requests
+ TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+ // If request is for our feature unit
+ if ( entityID == UAC2_ENTITY_FEATURE_UNIT )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Request uses format layout 1
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+ mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+ return true;
+
+ case AUDIO_FU_CTRL_VOLUME:
+ // Request uses format layout 2
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+ volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
+
+ TU_LOG2(" Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+ return true;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Clock Source unit
+ if ( entityID == UAC2_ENTITY_CLOCK )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_CS_CTRL_SAM_FREQ:
+ TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_4_t));
+
+ sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur;
+
+ TU_LOG2("Clock set current freq: %lu\r\n", sampFreq);
+
+ return true;
+ break;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) ep;
+
+ // return tud_control_xfer(rhport, p_request, &tmp, 1);
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+ (void) channelNum; (void) ctrlSel; (void) itf;
+
+ return false; // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+
+ // Page 91 in UAC2 specification
+ uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+ uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+ // uint8_t itf = TU_U16_LOW(p_request->wIndex); // Since we have only one audio function implemented, we do not need the itf value
+ uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+ // Input terminal (Microphone input)
+ if (entityID == UAC2_ENTITY_INPUT_TERMINAL)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_TE_CTRL_CONNECTOR:
+ {
+ // The terminal connector control only has a get request with only the CUR attribute.
+ audio_desc_channel_cluster_t ret;
+
+ // Those are dummy values for now
+ ret.bNrChannels = 1;
+ ret.bmChannelConfig = 0;
+ ret.iChannelNames = 0;
+
+ TU_LOG2(" Get terminal connector\r\n");
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+ }
+ break;
+
+ // Unknown/Unsupported control selector
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Feature unit
+ if (entityID == UAC2_ENTITY_FEATURE_UNIT)
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_FU_CTRL_MUTE:
+ // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+ // There does not exist a range parameter block for mute
+ TU_LOG2(" Get Mute of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+ case AUDIO_FU_CTRL_VOLUME:
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Volume of channel: %u\r\n", channelNum);
+ return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+ case AUDIO_CS_REQ_RANGE:
+ TU_LOG2(" Get Volume range of channel: %u\r\n", channelNum);
+
+ // Copy values - only for testing - better is version below
+ audio_control_range_2_n_t(1)
+ ret;
+
+ ret.wNumSubRanges = 1;
+ ret.subrange[0].bMin = -90; // -90 dB
+ ret.subrange[0].bMax = 30; // +30 dB
+ ret.subrange[0].bRes = 1; // 1 dB steps
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ // Clock Source unit
+ if ( entityID == UAC2_ENTITY_CLOCK )
+ {
+ switch ( ctrlSel )
+ {
+ case AUDIO_CS_CTRL_SAM_FREQ:
+ // channelNum is always zero in this case
+ switch ( p_request->bRequest )
+ {
+ case AUDIO_CS_REQ_CUR:
+ TU_LOG2(" Get Sample Freq.\r\n");
+ return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+ case AUDIO_CS_REQ_RANGE:
+ {
+ TU_LOG2(" Get Sample Freq. range\r\n");
+ audio_control_range_4_n_t(N_sampleRates) rangef =
+ {
+ .wNumSubRanges = tu_htole16(N_sampleRates)
+ };
+ TU_LOG1("Clock get %d freq ranges\r\n", N_sampleRates);
+ for(uint8_t i = 0; i < N_sampleRates; i++)
+ {
+ rangef.subrange[i].bMin = (int32_t)sampleRatesList[i];
+ rangef.subrange[i].bMax = (int32_t)sampleRatesList[i];
+ rangef.subrange[i].bRes = 0;
+ TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+ }
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &rangef, sizeof(rangef));
+ }
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ break;
+
+ case AUDIO_CS_CTRL_CLK_VALID:
+ // Only cur attribute exists for this request
+ TU_LOG2(" Get Sample Freq. valid\r\n");
+ return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+ // Unknown/Unsupported control
+ default:
+ TU_BREAKPOINT();
+ return false;
+ }
+ }
+
+ TU_LOG2(" Unsupported entity: %d\r\n", entityID);
+ return false; // Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+ tud_audio_write((uint8_t *)test_buffer_audio, (uint16_t)(sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000) * bytesPerSample));
+
+ return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void) rhport;
+ (void) n_bytes_copied;
+ (void) itf;
+ (void) ep_in;
+ (void) cur_alt_setting;
+
+ // 16bit
+ if(bytesPerSample == 2)
+ {
+ uint16_t* pData_16 = (uint16_t*)((void*)test_buffer_audio);
+ for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+ {
+ pData_16[cnt] = startVal++;
+ }
+ }
+ // 24bit in 32bit slot
+ else if(bytesPerSample == 4)
+ {
+ uint32_t* pData_32 = (uint32_t*)((void*)test_buffer_audio);
+ for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+ {
+ pData_32[cnt] = (uint32_t)startVal++ << 16U;
+ }
+ }
+
+ return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void) rhport;
+ (void) p_request;
+ startVal = 0;
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
new file mode 100644
index 000000000..c92e49957
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
@@ -0,0 +1,37 @@
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+import csv
+
+if __name__ == '__main__':
+
+ # If you got "ValueError: No input device matching", that is because your PC name example device
+ # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+ # print(sd.query_devices())
+
+ fs = 96000 # Sample rate
+ duration = 100e-3 # Duration of recording
+
+ if platform.system() == 'Windows':
+ # MME is needed since there are more than one MicNode device APIs (at least in Windows)
+ device = 'Microphone (MicNode) MME'
+ elif platform.system() == 'Darwin':
+ device = 'MicNode'
+ else:
+ device ='default'
+
+ myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=1, dtype='int16', device=device)
+ print('Waiting...')
+ sd.wait() # Wait until recording is finished
+ print('Done!')
+
+ time = np.arange(0, duration, 1 / fs) # time vector
+ plt.plot(time, myrecording)
+ plt.xlabel('Time [s]')
+ plt.ylabel('Amplitude')
+ plt.title('MicNode')
+ plt.show()
+
+ samples = np.array(myrecording)
+ np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
diff --git a/examples/device/audio_test_multi_rate/src/tusb_config.h b/examples/device/audio_test_multi_rate/src/tusb_config.h
new file mode 100644
index 000000000..1c8288bce
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/tusb_config.h
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG 0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO 1
+#define CFG_TUD_CDC 0
+#define CFG_TUD_MSC 0
+#define CFG_TUD_HID 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_VENDOR 0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE 96000
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS 2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX 2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX 16
+
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX 4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX 24
+
+// Have a look into audio_device.h for all configurations
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 1 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ 64 // Size of control request buffer
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 1 // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
new file mode 100644
index 000000000..f50e70a25
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -0,0 +1,185 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0200,
+
+ // Use Interface Association Descriptor (IAD) for Audio
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = 0xCafe,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+ return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+ ITF_NUM_AUDIO_CONTROL = 0,
+ ITF_NUM_AUDIO_STREAMING,
+ ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+ #define EPNUM_AUDIO 0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+ // nRF5x ISO can only be endpoint 8
+ #define EPNUM_AUDIO 0x08
+
+#else
+ #define EPNUM_AUDIO 0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_epin*/ 0x80 | EPNUM_AUDIO)
+};
+
+TU_VERIFY_STATIC(sizeof(desc_configuration) == CONFIG_TOTAL_LEN, "Incorrect size");
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+ (void) index; // for multiple configurations
+ return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "PaniRCorp", // 1: Manufacturer
+ "MicNode", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "UAC2", // 4: Audio Interface
+
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+ const char *str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
new file mode 100644
index 000000000..8381e31f5
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
@@ -0,0 +1,102 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK 0x04
+#define UAC2_ENTITY_INPUT_TERMINAL 0x01
+#define UAC2_ENTITY_OUTPUT_TERMINAL 0x03
+#define UAC2_ENTITY_FEATURE_UNIT 0x02
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\
+ /* Interface 1, Alternate 0 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ /* Interface 1, Alternate 1 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ /* Interface 1, Alternate 2 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(_itfnum, _stridx, _epin) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_PRO_CLK, /*_ctrl*/ AUDIO_CTRL_RW << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS | AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_VAL_POS, /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ UAC2_ENTITY_INPUT_TERMINAL, /*_srcid*/ UAC2_ENTITY_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ UAC2_ENTITY_FEATURE_UNIT, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+ /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN, /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+
+#endif
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 37113578e..012eff095 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,42 +1,32 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
- # use BOARD-Directory name for project id
- get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
- set(PROJECT ${BOARD}-${PROJECT})
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
- # TOP is absolute path to root directory of TinyUSB git repo
- set(TOP "../../..")
- get_filename_component(TOP "${TOP}" REALPATH)
+project(${PROJECT} C CXX ASM)
- project(${PROJECT})
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-else()
-
- # gets PROJECT name for the example (e.g. -)
- family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-
- project(${PROJECT})
-
- # Checks this example is valid for the family and initializes the project
- family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-
- add_executable(${PROJECT})
-
- # Example source
- target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- )
-
- # Example include
- target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
-
- # Configure compilation flags and libraries for the example... see the corresponding function
- # in hw/bsp/FAMILY/family.cmake for details.
- family_configure_device_example(${PROJECT})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/board_test/Makefile b/examples/device/board_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/board_test/Makefile
+++ b/examples/device/board_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt
index e4e1f4e9a..8d85dcafd 100644
--- a/examples/device/board_test/src/CMakeLists.txt
+++ b/examples/device/board_test/src/CMakeLists.txt
@@ -1,17 +1,3 @@
-# FAMILY = esp32sx
idf_component_register(SRCS "main.c"
INCLUDE_DIRS "."
- REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
- include(${board_cmake})
-endif()
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
- "${FREERTOS_ORIG_INCLUDE_PATH}"
- "${TOP}/hw"
- "${TOP}/src"
-)
+ REQUIRES boards tinyusb_src)
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 0289ca15f..0a134a2e6 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,10 +27,10 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
//--------------------------------------------------------------------+
/* Blink pattern
@@ -74,8 +74,6 @@ int main(void)
board_uart_write(&ch, 1);
}
}
-
- return 0;
}
#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index abc4d91da..f61e1b640 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_dual_ports/Makefile b/examples/device/cdc_dual_ports/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/cdc_dual_ports/Makefile
+++ b/examples/device/cdc_dual_ports/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 0264f0566..98f3ab923 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -28,7 +28,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//------------- prototypes -------------//
@@ -42,13 +42,15 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
cdc_task();
}
-
- return 0;
}
// echo to either Serial0 or Serial1
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 4eb8c7c27..de2505c07 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,13 +23,14 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
* Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
*
* Auto ProductID layout's Bitmap:
- * [MSB] MIDI | HID | MSC | CDC [LSB]
+ * [MSB] HID | MSC | CDC [LSB]
*/
#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -213,52 +214,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB CDC", // 4: CDC Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index fa6e83b7e..9415f8c68 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,29 +1,35 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
+set_property(GLOBAL PROPERTY USE_FOLDERS ON)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
# Configure compilation flags and libraries for the example... see the corresponding function
# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile
index 69b633fea..429959e70 100644
--- a/examples/device/cdc_msc/Makefile
+++ b/examples/device/cdc_msc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -6,7 +5,11 @@ INC += \
$(TOP)/hw \
# Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+ src/main.c \
+ src/msc_disk.c \
+ src/usb_descriptors.c \
+
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
include ../../rules.mk
diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt
index d844feae8..eadb6e74a 100644
--- a/examples/device/cdc_msc/skip.txt
+++ b/examples/device/cdc_msc/skip.txt
@@ -1 +1 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index c83299e59..172f48ae0 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -58,6 +58,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -65,8 +69,6 @@ int main(void)
cdc_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -97,7 +99,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index e67e381ce..d2f8628f1 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#if CFG_TUD_MSC
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 6b59ed50f..2afa24903 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -41,35 +42,33 @@
//--------------------------------------------------------------------+
// Device Descriptors
//--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
- .bLength = sizeof(tusb_desc_device_t),
- .bDescriptorType = TUSB_DESC_DEVICE,
- .bcdUSB = USB_BCD,
+tusb_desc_device_t const desc_device = {
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = USB_BCD,
- // Use Interface Association Descriptor (IAD) for CDC
- // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
- .bDeviceClass = TUSB_CLASS_MISC,
- .bDeviceSubClass = MISC_SUBCLASS_COMMON,
- .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ // Use Interface Association Descriptor (IAD) for CDC
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
- .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
- .idVendor = USB_VID,
- .idProduct = USB_PID,
- .bcdDevice = 0x0100,
+ .idVendor = USB_VID,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
- .iManufacturer = 0x01,
- .iProduct = 0x02,
- .iSerialNumber = 0x03,
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
- .bNumConfigurations = 0x01
+ .bNumConfigurations = 0x01
};
// Invoked when received GET DEVICE DESCRIPTOR
// Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const *tud_descriptor_device_cb(void) {
return (uint8_t const *) &desc_device;
}
@@ -77,8 +76,7 @@ uint8_t const * tud_descriptor_device_cb(void)
// Configuration Descriptor
//--------------------------------------------------------------------+
-enum
-{
+enum {
ITF_NUM_CDC = 0,
ITF_NUM_CDC_DATA,
ITF_NUM_MSC,
@@ -95,7 +93,7 @@ enum
#define EPNUM_MSC_OUT 0x05
#define EPNUM_MSC_IN 0x85
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
// SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
// e.g EP1 OUT & EP1 IN cannot exist together
#define EPNUM_CDC_NOTIF 0x81
@@ -140,67 +138,62 @@ enum
#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
// full speed configuration
-uint8_t const desc_fs_configuration[] =
-{
- // Config number, interface count, string index, total length, attribute, power in mA
- TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_fs_configuration[] = {
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
- // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
- TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+ // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
- // Interface number, string index, EP Out & EP In address, EP size
- TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
};
#if TUD_OPT_HIGH_SPEED
// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
// high speed configuration
-uint8_t const desc_hs_configuration[] =
-{
- // Config number, interface count, string index, total length, attribute, power in mA
- TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_hs_configuration[] = {
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
- // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
- TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+ // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
- // Interface number, string index, EP Out & EP In address, EP size
- TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
};
// other speed configuration
uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
- .bLength = sizeof(tusb_desc_device_qualifier_t),
- .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
- .bcdUSB = USB_BCD,
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+ .bLength = sizeof(tusb_desc_device_qualifier_t),
+ .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+ .bcdUSB = USB_BCD,
- .bDeviceClass = TUSB_CLASS_MISC,
- .bDeviceSubClass = MISC_SUBCLASS_COMMON,
- .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
- .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
- .bNumConfigurations = 0x01,
- .bReserved = 0x00
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+ .bNumConfigurations = 0x01,
+ .bReserved = 0x00
};
// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
// device_qualifier descriptor describes information about a high-speed capable device that would
// change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
- return (uint8_t const*) &desc_device_qualifier;
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+ return (uint8_t const *) &desc_device_qualifier;
}
// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
(void) index; // for multiple configurations
// if link speed is high return fullspeed config, and vice versa
@@ -220,13 +213,12 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
// Invoked when received GET CONFIGURATION DESCRIPTOR
// Application return pointer to descriptor
// Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
(void) index; // for multiple configurations
#if TUD_OPT_HIGH_SPEED
// Although we are highspeed, host may be fullspeed.
- return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
+ return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
#else
return desc_fs_configuration;
#endif
@@ -236,53 +228,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
- (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
- "TinyUSB", // 1: Manufacturer
- "TinyUSB Device", // 2: Product
- "123456789012", // 3: Serials, should use chip ID
- "TinyUSB CDC", // 4: CDC Interface
- "TinyUSB MSC", // 5: MSC Interface
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
};
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "TinyUSB", // 1: Manufacturer
+ "TinyUSB Device", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "TinyUSB CDC", // 4: CDC Interface
+ "TinyUSB MSC", // 5: MSC Interface
+};
+
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index cbd75efd6..33c7a1ec0 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,22 +1,35 @@
-cmake_minimum_required(VERSION 3.5)
-
-# TOP is absolute path to root directory of TinyUSB git repo
-# needed for esp32sx build. TODO could be removed later on
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-else()
- message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 4ee816880..84c833fb5 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,18 +1,15 @@
-DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-
-include ../../../tools/top.mk
include ../../make.mk
FREERTOS_SRC = lib/FreeRTOS-Kernel
-FREERTOS_PORTABLE_SRC= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)/$(FREERTOS_PORT)
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
INC += \
src \
src/FreeRTOSConfig \
$(TOP)/hw \
$(TOP)/$(FREERTOS_SRC)/include \
- $(TOP)/$(FREERTOS_PORTABLE_SRC)
-
+ $(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
# Example source
EXAMPLE_SOURCE = \
src/freertos_hook.c \
@@ -28,22 +25,22 @@ SRC_C += \
$(FREERTOS_SRC)/queue.c \
$(FREERTOS_SRC)/tasks.c \
$(FREERTOS_SRC)/timers.c \
- $(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.c))
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
SRC_S += \
- $(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.s))
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
# CFLAGS += -Wno-error=sign-compare
# Suppress FreeRTOSConfig.h warnings
-GCC_CFLAGS += -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=redundant-decls
# Suppress FreeRTOS source warnings
-GCC_CFLAGS += -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=cast-qual
# FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
include ../../rules.mk
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
mcu:SAMD11
mcu:SAMX7X
mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
family:broadcom_32bit
family:broadcom_64bit
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 9216e2b49..fee264363 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -1,35 +1,4 @@
+# This file is for ESP-IDF only
idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
INCLUDE_DIRS "."
- REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
- include(${board_cmake})
-endif()
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
- "${TOP}/hw"
- "${TOP}/src"
-)
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
- ESP_PLATFORM
-)
-
-target_sources(${COMPONENT_TARGET} PUBLIC
- "${TOP}/src/tusb.c"
- "${TOP}/src/common/tusb_fifo.c"
- "${TOP}/src/device/usbd.c"
- "${TOP}/src/device/usbd_control.c"
- "${TOP}/src/class/cdc/cdc_device.c"
- "${TOP}/src/class/dfu/dfu_rt_device.c"
- "${TOP}/src/class/hid/hid_device.c"
- "${TOP}/src/class/midi/midi_device.c"
- "${TOP}/src/class/msc/msc_device.c"
- "${TOP}/src/class/net/ecm_rndis_device.c"
- "${TOP}/src/class/net/ncm_device.c"
- "${TOP}/src/class/usbtmc/usbtmc_device.c"
- "${TOP}/src/class/vendor/vendor_device.c"
- "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
+ REQUIRES boards tinyusb_src)
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
-#define configQUEUE_REGISTRY_SIZE 2
+#define configQUEUE_REGISTRY_SIZE 4
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 0
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index cfb14aa2b..1dadc4513 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
@@ -41,6 +41,7 @@
#define USBD_STACK_SIZE 4096
#else
+
#include "FreeRTOS.h"
#include "semphr.h"
#include "queue.h"
@@ -54,7 +55,7 @@
#define CDC_STACK_SZIE configMINIMAL_STACK_SIZE
//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
//--------------------------------------------------------------------+
/* Blink pattern
@@ -62,7 +63,7 @@
* - 1000 ms : device mounted
* - 2500 ms : device is suspended
*/
-enum {
+enum {
BLINK_NOT_MOUNTED = 250,
BLINK_MOUNTED = 1000,
BLINK_SUSPENDED = 2500,
@@ -81,16 +82,15 @@ StaticTask_t cdc_taskdef;
TimerHandle_t blinky_tm;
-void led_blinky_cb(TimerHandle_t xTimer);
-void usb_device_task(void* param);
-void cdc_task(void* params);
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_device_task(void *param);
+void cdc_task(void *params);
//--------------------------------------------------------------------+
// Main
//--------------------------------------------------------------------+
-int main(void)
-{
+int main(void) {
board_init();
#if configSUPPORT_STATIC_ALLOCATION
@@ -104,8 +104,8 @@ int main(void)
xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
#else
blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
- xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
- xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+ xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+ xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
#endif
xTimerStart(blinky_tm, 0);
@@ -119,16 +119,14 @@ int main(void)
}
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-void app_main(void)
-{
+void app_main(void) {
main();
}
#endif
// USB Device Driver task
// This top level thread process all usb events and invoke callbacks
-void usb_device_task(void* param)
-{
+static void usb_device_task(void *param) {
(void) param;
// init device stack on configured roothub port
@@ -136,9 +134,12 @@ void usb_device_task(void* param)
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
// RTOS forever loop
- while (1)
- {
+ while (1) {
// put this thread to waiting state until there is new events
tud_task();
@@ -152,49 +153,46 @@ void usb_device_task(void* param)
//--------------------------------------------------------------------+
// Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
}
// Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
}
// Invoked when usb bus is suspended
// remote_wakeup_en : if host allow us to perform remote wakeup
// Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
(void) remote_wakeup_en;
xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
}
// Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
- xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+void tud_resume_cb(void) {
+ if (tud_mounted()) {
+ xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+ } else {
+ xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+ }
}
//--------------------------------------------------------------------+
// USB CDC
//--------------------------------------------------------------------+
-void cdc_task(void* params)
-{
+void cdc_task(void *params) {
(void) params;
// RTOS forever loop
- while ( 1 )
- {
+ while (1) {
// connected() check for DTR bit
// Most but not all terminal client set this when making connection
// if ( tud_cdc_connected() )
{
// There are data available
- while ( tud_cdc_available() )
- {
+ while (tud_cdc_available()) {
uint8_t buf[64];
// read and echo back
@@ -217,32 +215,27 @@ void cdc_task(void* params)
}
// Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
(void) itf;
(void) rts;
// TODO set some indicator
- if ( dtr )
- {
+ if (dtr) {
// Terminal connected
- }else
- {
+ } else {
// Terminal disconnected
}
}
// Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
(void) itf;
}
//--------------------------------------------------------------------+
// BLINKING TASK
//--------------------------------------------------------------------+
-void led_blinky_cb(TimerHandle_t xTimer)
-{
+static void led_blinky_cb(TimerHandle_t xTimer) {
(void) xTimer;
static bool led_state = false;
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index a895f4738..9520dfec1 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#if CFG_TUD_MSC
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 0ec8896b9..91efe7d40 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -54,7 +54,9 @@
#endif
// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_FREERTOS
+#endif
// Espressif IDF requires "freertos/" prefix in include path
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 30a712275..9c29701c7 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -212,53 +213,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456789012", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB CDC", // 4: CDC Interface
"TinyUSB MSC", // 5: MSC Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/cdc_uac2/CMakeLists.txt b/examples/device/cdc_uac2/CMakeLists.txt
new file mode 100644
index 000000000..64e4374e9
--- /dev/null
+++ b/examples/device/cdc_uac2/CMakeLists.txt
@@ -0,0 +1,38 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/uac2_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
+
+# Uncomment me to enable UART based debugging
+# pico_enable_stdio_uart(${PROJECT} 1)
diff --git a/examples/device/cdc_uac2/Makefile b/examples/device/cdc_uac2/Makefile
new file mode 100644
index 000000000..b7a8302ce
--- /dev/null
+++ b/examples/device/cdc_uac2/Makefile
@@ -0,0 +1,16 @@
+include ../../make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+ src/cdc_app.c \
+ src/main.c \
+ src/uac2_app.c \
+ src/usb_descriptors.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/cdc_uac2/README.md b/examples/device/cdc_uac2/README.md
new file mode 100644
index 000000000..5d120be7d
--- /dev/null
+++ b/examples/device/cdc_uac2/README.md
@@ -0,0 +1,52 @@
+#### Composite CDC + UAC2 on Pico
+
+This example provides a composite CDC + UAC2 device on top of a Raspberry Pi
+Pico board.
+
+
+#### Use Cases
+
+- The CDC + UAC2 composite device happens to be important, especially in the
+ amateur radio community.
+
+ Modern radios (`rigs`) like Icom IC-7300 + IC-705 expose a sound card and a
+ serial device (`composite device`) to the computer over a single USB cable.
+ This allows for Audio I/O and CAT control over a single USB cable which is
+ very convenient.
+
+ By including and maintaining this example in TinyUSB repository, we enable
+ the amateur radio community to build (`homebrew`) radios with similar
+ functionality as the (expensive) commercial rigs.
+
+ This PR is important in bridging this specific gap between the commercial
+ rigs and homebrew equipment.
+
+- https://digirig.net/digirig-mobile-rev-1-9/ is a digital interface for
+ interfacing radios (that lack an inbuilt digital interface) with computers.
+ Digirig Mobile works brilliantly (is OSS!) and is a big improvement over
+ traditional digital interfaces (like the SignaLink USB Interface). By using a
+ Raspberry Pi Pico powered CDC + UAC2 composite device, we can simplify the
+ Digirig Mobile schematic, drastically reduce the manufacturing cost, and
+ (again) enable the homebrewers community to homebrew a modern digital interface
+ with ease themselves.
+
+
+#### Build Steps
+
+```
+cd examples/device/cdc_uac2
+
+export PICO_SDK_PATH=$HOME/pico-sdk
+
+cmake -DFAMILY=rp2040 pico .
+
+cmake -DFAMILY=rp2040 -DCMAKE_BUILD_TYPE=Debug # use this for debugging
+
+make BOARD=raspberry_pi_pico all
+```
+
+
+#### Development Notes
+
+Please try to keep this code synchronized with the `uac2_headset` example
+included in this repository.
diff --git a/examples/device/cdc_uac2/src/cdc_app.c b/examples/device/cdc_uac2/src/cdc_app.c
new file mode 100644
index 000000000..2166c1d6b
--- /dev/null
+++ b/examples/device/cdc_uac2/src/cdc_app.c
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "common.h"
+
+// Invoked when cdc when line state changed e.g connected/disconnected
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
+{
+ (void) itf;
+ (void) rts;
+
+ if (dtr)
+ {
+ // Terminal connected
+ }
+ else
+ {
+ // Terminal disconnected
+ }
+}
+
+// Invoked when CDC interface received data from host
+void tud_cdc_rx_cb(uint8_t itf)
+{
+ uint8_t buf[64];
+ uint32_t count;
+
+ // connected() check for DTR bit
+ // Most but not all terminal client set this when making connection
+ if (tud_cdc_connected())
+ {
+ if (tud_cdc_available()) // data is available
+ {
+ count = tud_cdc_n_read(itf, buf, sizeof(buf));
+ (void) count;
+
+ tud_cdc_n_write(itf, buf, count);
+ tud_cdc_n_write_flush(itf);
+ // dummy code to check that cdc serial is responding
+ board_led_write(0);
+ board_delay(50);
+ board_led_write(1);
+ board_delay(50);
+ board_led_write(0);
+ }
+ }
+}
diff --git a/examples/device/cdc_uac2/src/common.h b/examples/device/cdc_uac2/src/common.h
new file mode 100644
index 000000000..f281024c7
--- /dev/null
+++ b/examples/device/cdc_uac2/src/common.h
@@ -0,0 +1,34 @@
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+/* Blink pattern
+ * - 25 ms : streaming data
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum
+{
+ BLINK_STREAMING = 25,
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+enum
+{
+ VOLUME_CTRL_0_DB = 0,
+ VOLUME_CTRL_10_DB = 2560,
+ VOLUME_CTRL_20_DB = 5120,
+ VOLUME_CTRL_30_DB = 7680,
+ VOLUME_CTRL_40_DB = 10240,
+ VOLUME_CTRL_50_DB = 12800,
+ VOLUME_CTRL_60_DB = 15360,
+ VOLUME_CTRL_70_DB = 17920,
+ VOLUME_CTRL_80_DB = 20480,
+ VOLUME_CTRL_90_DB = 23040,
+ VOLUME_CTRL_100_DB = 25600,
+ VOLUME_CTRL_SILENCE = 0x8000,
+};
+
+#endif
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
new file mode 100644
index 000000000..7afa96c1a
--- /dev/null
+++ b/examples/device/cdc_uac2/src/main.c
@@ -0,0 +1,99 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina
+ * Copyright (c) 2023 Dhiru Kholia
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "common.h"
+
+extern uint32_t blink_interval_ms;
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+#include "pico/stdlib.h"
+#endif
+
+void led_blinking_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+ board_init();
+
+ // init device stack on configured roothub port
+ tud_init(BOARD_TUD_RHPORT);
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+ stdio_init_all();
+#endif
+
+ TU_LOG1("CDC UAC2 example running\r\n");
+
+ while (1)
+ {
+ tud_task(); // TinyUSB device task
+ led_blinking_task();
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+ // printf("Hello, world!\n");
+#endif
+ }
+
+ return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+ blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+ blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+ (void)remote_wakeup_en;
+ blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+ blink_interval_ms = BLINK_MOUNTED;
+}
diff --git a/examples/device/cdc_uac2/src/tusb_config.h b/examples/device/cdc_uac2/src/tusb_config.h
new file mode 100644
index 000000000..373f0b01f
--- /dev/null
+++ b/examples/device/cdc_uac2/src/tusb_config.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC 1
+#define CFG_TUD_MSC 0
+#define CFG_TUD_HID 0
+#define CFG_TUD_MIDI 0
+#define CFG_TUD_AUDIO 1
+#define CFG_TUD_VENDOR 0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN TUD_AUDIO_HEADSET_STEREO_DESC_LEN
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS 2
+
+// Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE 48000 // 16bit/48kHz is the best quality for Renesas RX
+#else
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE 96000 // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#endif
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX 1 // Changed
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX 2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX 16
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX 2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX 16
+
+#if defined(__RX__)
+// 8bit in 8bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX 1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX 8
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX 1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX 8
+#else
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX 4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX 24
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX 4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX 24
+#endif
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_IN 1
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_OUT 1
+
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT)
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
+
+// Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 2
+
+// Size of control request buffer
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ 64
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE 64
+#define CFG_TUD_CDC_TX_BUFSIZE 64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
new file mode 100644
index 000000000..98659ea68
--- /dev/null
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -0,0 +1,316 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// List of supported sample rates
+const uint32_t sample_rates[] = {44100, 48000};
+uint32_t current_sample_rate = 44100;
+
+#define N_SAMPLE_RATES TU_ARRAY_SIZE(sample_rates)
+
+uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
+
+// Buffer for microphone data
+int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
+// Buffer for speaker data
+int32_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ / 4];
+// Speaker data size received in the last frame
+int spk_data_size;
+// Resolution per format
+const uint8_t resolutions_per_format[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] = {CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX};
+// Current resolution, update on format change
+uint8_t current_resolution;
+
+// Helper for clock get requests
+static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+
+ if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+ {
+ if (request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+
+ audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
+ }
+ else if (request->bRequest == AUDIO_CS_REQ_RANGE)
+ {
+ audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
+ {
+ .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
+ };
+ TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+ for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+ {
+ rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+ rangef.subrange[i].bMax = (int32_t) sample_rates[i];
+ rangef.subrange[i].bRes = 0;
+ TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+ }
+
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
+ }
+ }
+ else if (request->bControlSelector == AUDIO_CS_CTRL_CLK_VALID &&
+ request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_1_t cur_valid = { .bCur = 1 };
+ TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
+ }
+ TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+}
+
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+ (void)rhport;
+
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+ TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+ if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+ current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
+
+ TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+
+ return true;
+ }
+ else
+ {
+ TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+ }
+}
+
+// Helper for feature unit get requests
+static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+
+ if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
+ TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
+ }
+ else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ {
+ if (request->bRequest == AUDIO_CS_REQ_RANGE)
+ {
+ audio_control_range_2_n_t(1) range_vol = {
+ .wNumSubRanges = tu_htole16(1),
+ .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
+ };
+ TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+ range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
+ }
+ else if (request->bRequest == AUDIO_CS_REQ_CUR)
+ {
+ audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
+ TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
+ return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
+ }
+ }
+ TU_LOG1("Feature unit get request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+
+ return false;
+}
+
+// Helper for feature unit set requests
+static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+ (void)rhport;
+
+ TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+ TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+ if (request->bControlSelector == AUDIO_FU_CTRL_MUTE)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
+
+ mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
+
+ TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+
+ return true;
+ }
+ else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+ {
+ TU_VERIFY(request->wLength == sizeof(audio_control_cur_2_t));
+
+ volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
+
+ TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+
+ return true;
+ }
+ else
+ {
+ TU_LOG1("Feature unit set request not supported, entity = %u, selector = %u, request = %u\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ return false;
+ }
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
+{
+ audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+ if (request->bEntityID == UAC2_ENTITY_CLOCK)
+ return tud_audio_clock_get_request(rhport, request);
+ if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+ return tud_audio_feature_unit_get_request(rhport, request);
+ else
+ {
+ TU_LOG1("Get request not handled, entity = %d, selector = %d, request = %d\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+ }
+ return false;
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *buf)
+{
+ audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+ if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+ return tud_audio_feature_unit_set_request(rhport, request, buf);
+ if (request->bEntityID == UAC2_ENTITY_CLOCK)
+ return tud_audio_clock_set_request(rhport, request, buf);
+ TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
+ request->bEntityID, request->bControlSelector, request->bRequest);
+
+ return false;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void)rhport;
+
+ uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+ uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+ if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt == 0) {
+ // Audio streaming stop
+ blink_interval_ms = BLINK_MOUNTED;
+ }
+
+ return true;
+}
+
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ (void)rhport;
+ uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+ uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+ TU_LOG2("Set interface %d alt %d\r\n", itf, alt);
+ if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0) {
+ // Audio streaming start
+ blink_interval_ms = BLINK_STREAMING;
+ }
+
+ // Clear buffer when streaming format is changed
+ spk_data_size = 0;
+ if(alt != 0)
+ {
+ current_resolution = resolutions_per_format[alt-1];
+ }
+
+ return true;
+}
+
+bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
+{
+ (void)rhport;
+ (void)func_id;
+ (void)ep_out;
+ (void)cur_alt_setting;
+
+ spk_data_size = tud_audio_read(spk_buf, n_bytes_received);
+ tud_audio_write(spk_buf, n_bytes_received);
+
+ return true;
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+ (void)rhport;
+ (void)itf;
+ (void)ep_in;
+ (void)cur_alt_setting;
+
+ // This callback could be used to fill microphone data separately
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if (board_millis() - start_ms < blink_interval_ms) return;
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
new file mode 100644
index 000000000..72a695622
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -0,0 +1,216 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ * [MSB] AUDIO | MIDI | HID | MSC | CDC [LSB]
+ */
+#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
+#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+ _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0200,
+
+ // Use Interface Association Descriptor (IAD)
+ // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+ .idVendor = 0xCafe,
+ .idProduct = USB_PID,
+ .bcdDevice = 0x0100,
+
+ .iManufacturer = 0x01,
+ .iProduct = 0x02,
+ .iSerialNumber = 0x03,
+
+ .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+ return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_HEADSET_STEREO_DESC_LEN + CFG_TUD_CDC * TUD_CDC_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+ // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+ // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+ #define EPNUM_AUDIO_IN 0x03
+ #define EPNUM_AUDIO_OUT 0x03
+
+ #define EPNUM_CDC_NOTIF 0x84
+ #define EPNUM_CDC_OUT 0x05
+ #define EPNUM_CDC_IN 0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+ // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+ #define EPNUM_AUDIO_IN 0x08
+ #define EPNUM_AUDIO_OUT 0x08
+
+ #define EPNUM_CDC_NOTIF 0x81
+ #define EPNUM_CDC_OUT 0x02
+ #define EPNUM_CDC_IN 0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
+ // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_AUDIO_IN 0x01
+ #define EPNUM_AUDIO_OUT 0x02
+
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x04
+ #define EPNUM_CDC_IN 0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+ // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+ // e.g EP1 OUT & EP1 IN cannot exist together
+ #define EPNUM_AUDIO_IN 0x01
+ #define EPNUM_AUDIO_OUT 0x02
+
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x04
+ #define EPNUM_CDC_IN 0x85
+
+#else
+ #define EPNUM_AUDIO_IN 0x01
+ #define EPNUM_AUDIO_OUT 0x01
+
+ #define EPNUM_CDC_NOTIF 0x83
+ #define EPNUM_CDC_OUT 0x04
+ #define EPNUM_CDC_IN 0x84
+#endif
+
+uint8_t const desc_configuration[] =
+{
+ // Config number, interface count, string index, total length, attribute, power in mA
+ TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+ // Interface number, string index, EP Out & EP In address, EP size
+ TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80),
+
+ // CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+ TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 6, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+ (void)index; // for multiple configurations
+ return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] =
+{
+ (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+ "TinyUSB", // 1: Manufacturer
+ "TinyUSB headset", // 2: Product
+ NULL, // 3: Serials will use unique ID if possible
+ "TinyUSB Speakers", // 4: Audio Interface
+ "TinyUSB Microphone", // 5: Audio Interface
+ "TinyUSB CDC", // 6: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
+
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
+
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
+
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+
+ const char *str = string_desc_arr[index];
+
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
+ }
+
+ // first byte is length (including header), second byte is string type
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+ return _desc_str;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.h b/examples/device/cdc_uac2/src/usb_descriptors.h
new file mode 100644
index 000000000..736feeefe
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.h
@@ -0,0 +1,158 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenbreg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK 0x04
+// Speaker path
+#define UAC2_ENTITY_SPK_INPUT_TERMINAL 0x01
+#define UAC2_ENTITY_SPK_FEATURE_UNIT 0x02
+#define UAC2_ENTITY_SPK_OUTPUT_TERMINAL 0x03
+// Microphone path
+#define UAC2_ENTITY_MIC_INPUT_TERMINAL 0x11
+#define UAC2_ENTITY_MIC_OUTPUT_TERMINAL 0x13
+
+enum
+{
+ ITF_NUM_AUDIO_CONTROL = 0,
+ ITF_NUM_AUDIO_STREAMING_SPK,
+ ITF_NUM_AUDIO_STREAMING_MIC,
+ ITF_NUM_CDC,
+ ITF_NUM_CDC_DATA,
+ ITF_NUM_TOTAL
+};
+
+#define TUD_AUDIO_HEADSET_STEREO_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ /* Interface 1, Alternate 0 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ /* Interface 1, Alternate 0 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ /* Interface 1, Alternate 2 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ /* Interface 2, Alternate 0 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ /* Interface 2, Alternate 1 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ /* Interface 2, Alternate 2 */\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 7, /*_assocTerm*/ 0x00, /*_stridx*/ 0x00), \
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_srcid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrlch0master*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch2*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_HEADPHONES, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x05),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+ /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 2, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x04),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 2, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+ /* Interface 2, Alternate 2 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+#endif
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index acaa54198..a01eb3456 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dfu/Makefile b/examples/device/dfu/Makefile
index 5148ed55a..b3f2cc588 100644
--- a/examples/device/dfu/Makefile
+++ b/examples/device/dfu/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 6bb183819..81fc0a62c 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -42,7 +42,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -77,13 +77,15 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -114,7 +116,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 51a0d09f5..fd469aaf2 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "class/dfu/dfu_device.h"
@@ -116,56 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"FLASH", // 4: DFU Partition 1
"EEPROM", // 5: DFU Partition 2
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
-
size_t chr_count;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }
- else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- const char* str = string_desc_arr[index];
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) {
- chr_count = 31;
- }
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index abc4d91da..a01eb3456 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dfu_runtime/Makefile b/examples/device/dfu_runtime/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/dfu_runtime/Makefile
+++ b/examples/device/dfu_runtime/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index bd9a91c27..170dde932 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -40,7 +40,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -72,13 +72,15 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -109,7 +111,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
// Invoked on DFU_DETACH request to reboot to the bootloader
diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c
index 1b0a60551..7ac53d255 100644
--- a/examples/device/dfu_runtime/src/usb_descriptors.c
+++ b/examples/device/dfu_runtime/src/usb_descriptors.c
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "class/dfu/dfu_rt_device.h"
@@ -112,55 +113,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB DFU runtime", // 4: DFU runtime
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
-
size_t chr_count;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }
- else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- const char* str = string_desc_arr[index];
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) {
- chr_count = 31;
- }
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index fa6e83b7e..2b20d2234 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -24,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dynamic_configuration/Makefile b/examples/device/dynamic_configuration/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/dynamic_configuration/Makefile
+++ b/examples/device/dynamic_configuration/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt
index d844feae8..eadb6e74a 100644
--- a/examples/device/dynamic_configuration/skip.txt
+++ b/examples/device/dynamic_configuration/skip.txt
@@ -1 +1 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 33a603343..b6409c8e1 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -59,6 +59,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -66,8 +70,6 @@ int main(void)
cdc_task();
midi_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -98,7 +100,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index e8cb03fdd..10c3ac6fe 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#if CFG_TUD_MSC
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 092229b99..7f35b4b22 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,8 +23,8 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
-#include "bsp/board.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
* Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
@@ -183,7 +183,7 @@ uint8_t const desc_configuration_0[] =
};
-uint8_t const desc_configuraiton_1[] =
+uint8_t const desc_configuration_1[] =
{
// Config number, interface count, string index, total length, attribute, power in mA
TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, 0x00, 100),
@@ -199,58 +199,70 @@ uint8_t const desc_configuraiton_1[] =
uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
{
(void) index; // for multiple configurations
- return mode ? desc_configuraiton_1 : desc_configuration_0;
+ return mode ? desc_configuration_1 : desc_configuration_0;
}
//--------------------------------------------------------------------+
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index abc4d91da..a01eb3456 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index c6a9c5b21..b3f2cc588 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -9,7 +8,7 @@ INC += \
EXAMPLE_SOURCE = \
src/main.c \
src/usb_descriptors.c
-
+
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
include ../../rules.mk
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index b13428041..7ad5c53c2 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -59,6 +59,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -98,7 +102,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
index a0d7e9f15..d68ef16d9 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.c
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -130,51 +131,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.h b/examples/device/hid_boot_interface/src/usb_descriptors.h
index 57cf0e2c0..6fee9e223 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.h
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index abc4d91da..a01eb3456 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_composite/Makefile b/examples/device/hid_composite/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_composite/Makefile
+++ b/examples/device/hid_composite/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 05315f266..dcf13079f 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -60,6 +60,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -67,8 +71,6 @@ int main(void)
hid_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -99,7 +101,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index 2988baee2..e174db46d 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -177,51 +178,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/hid_composite/src/usb_descriptors.h b/examples/device/hid_composite/src/usb_descriptors.h
index ca8925ad9..e733d31dd 100644
--- a/examples/device/hid_composite/src/usb_descriptors.h
+++ b/examples/device/hid_composite/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index ed734b954..eb22014fb 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -1,17 +1,34 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
-# use BOARD-Directory name for project id
-get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-set(PROJECT ${BOARD}-${PROJECT})
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
-# TOP is absolute path to root directory of TinyUSB git repo
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
- include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
- project(${PROJECT})
-else()
- message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index a354a90b6..a892e7d1d 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -1,10 +1,9 @@
DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-include ../../../tools/top.mk
include ../../make.mk
FREERTOS_SRC = lib/FreeRTOS-Kernel
-FREERTOS_PORTABLE_SRC= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)/$(FREERTOS_PORT)
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
INC += \
src \
@@ -18,7 +17,7 @@ EXAMPLE_SOURCE = \
src/freertos_hook.c \
src/main.c \
src/usb_descriptors.c
-
+
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
# FreeRTOS source, all files in port folder
@@ -27,22 +26,22 @@ SRC_C += \
$(FREERTOS_SRC)/queue.c \
$(FREERTOS_SRC)/tasks.c \
$(FREERTOS_SRC)/timers.c \
- $(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.c))
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
SRC_S += \
- $(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.s))
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
# CFLAGS += -Wno-error=sign-compare
# Suppress FreeRTOSConfig.h warnings
-GCC_CFLAGS += -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=redundant-decls
# Suppress FreeRTOS source warnings
-GCC_CFLAGS += -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=cast-qual
# FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
include ../../rules.mk
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
mcu:SAMD11
mcu:SAMX7X
mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
family:broadcom_32bit
family:broadcom_64bit
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 25da8fcd7..6d912854f 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -1,35 +1,3 @@
idf_component_register(SRCS "main.c" "usb_descriptors.c"
INCLUDE_DIRS "."
- REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
- include(${board_cmake})
-endif()
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
- "${TOP}/hw"
- "${TOP}/src"
-)
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
- ESP_PLATFORM
-)
-
-target_sources(${COMPONENT_TARGET} PUBLIC
- "${TOP}/src/tusb.c"
- "${TOP}/src/common/tusb_fifo.c"
- "${TOP}/src/device/usbd.c"
- "${TOP}/src/device/usbd_control.c"
- "${TOP}/src/class/cdc/cdc_device.c"
- "${TOP}/src/class/dfu/dfu_rt_device.c"
- "${TOP}/src/class/hid/hid_device.c"
- "${TOP}/src/class/midi/midi_device.c"
- "${TOP}/src/class/msc/msc_device.c"
- "${TOP}/src/class/net/ecm_rndis_device.c"
- "${TOP}/src/class/net/ncm_device.c"
- "${TOP}/src/class/usbtmc/usbtmc_device.c"
- "${TOP}/src/class/vendor/vendor_device.c"
- "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
+ REQUIRES boards tinyusb_src)
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
-#define configQUEUE_REGISTRY_SIZE 2
+#define configQUEUE_REGISTRY_SIZE 4
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 0
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 7c9619c4b..ff2cb635e 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -138,6 +138,10 @@ void usb_device_task(void* param)
// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
// RTOS forever loop
while (1)
{
@@ -176,7 +180,14 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+ if (tud_mounted())
+ {
+ xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+ }
+ else
+ {
+ xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+ }
}
//--------------------------------------------------------------------+
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 935ae9453..3ba9bf311 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -54,7 +54,9 @@
#endif
// This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_FREERTOS
+#endif
// Espressif IDF requires "freertos/" prefix in include path
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 4df12d3db..85820de55 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -175,51 +176,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.h b/examples/device/hid_composite_freertos/src/usb_descriptors.h
index ca8925ad9..e733d31dd 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.h
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index abc4d91da..a01eb3456 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_generic_inout/Makefile b/examples/device/hid_generic_inout/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_generic_inout/Makefile
+++ b/examples/device/hid_generic_inout/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/hid_generic_inout/hid_test.js b/examples/device/hid_generic_inout/hid_test.js
index daa958fd5..16bc723e2 100644
--- a/examples/device/hid_generic_inout/hid_test.js
+++ b/examples/device/hid_generic_inout/hid_test.js
@@ -48,7 +48,7 @@ if( deviceInfo ) {
function anySupportedBoard(d) {
-
+
for (var key in boards) {
if (boards.hasOwnProperty(key)) {
if (isDevice(boards[key],d)) {
@@ -65,4 +65,3 @@ function isDevice(board,d){
// product id 0xff is matches all
return d.vendorId==board[0] && (d.productId==board[1] || board[1] == 0xFFFF);
}
-
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5b7daf118..cfa9f6283 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
/* This example demonstrate HID Generic raw Input & Output.
@@ -83,13 +83,15 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -120,7 +122,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index cd4838407..64f6d17ae 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -120,51 +121,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index abc4d91da..a01eb3456 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
@@ -23,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_multiple_interface/Makefile b/examples/device/hid_multiple_interface/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_multiple_interface/Makefile
+++ b/examples/device/hid_multiple_interface/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 29ba74398..30b4ae055 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -64,6 +64,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -71,8 +75,6 @@ int main(void)
hid_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -103,7 +105,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/hid_multiple_interface/src/usb_descriptors.c b/examples/device/hid_multiple_interface/src/usb_descriptors.c
index 42471a961..86f567e8e 100644
--- a/examples/device/hid_multiple_interface/src/usb_descriptors.c
+++ b/examples/device/hid_multiple_interface/src/usb_descriptors.c
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -136,53 +137,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"Keyboard Interface", // 4: Interface 1 String
"Mouse Interface", // 5: Interface 2 String
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index abc4d91da..e51f14c02 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -1,17 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
add_executable(${PROJECT})
-
# Example source
target_sources(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
@@ -23,6 +26,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/midi_test/Makefile b/examples/device/midi_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/midi_test/Makefile
+++ b/examples/device/midi_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 3310348bd..b1d51598f 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
/* This MIDI example send sequence of note (on/off) repeatedly. To test on PC, you need to install
@@ -65,15 +65,16 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
midi_task();
}
-
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -104,7 +105,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index c84a873b1..9781d3d6f 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,13 +23,14 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
* Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
*
* Auto ProductID layout's Bitmap:
- * [MSB] MIDI | HID | MSC | CDC [LSB]
+ * [MSB] HID | MSC | CDC [LSB]
*/
#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) )
#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -133,51 +134,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 9e834ae21..e69fead35 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -1,29 +1,34 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/msc_dual_lun/Makefile b/examples/device/msc_dual_lun/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/msc_dual_lun/Makefile
+++ b/examples/device/msc_dual_lun/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/msc_dual_lun/skip.txt b/examples/device/msc_dual_lun/skip.txt
index 3549c702a..47e561cf0 100644
--- a/examples/device/msc_dual_lun/skip.txt
+++ b/examples/device/msc_dual_lun/skip.txt
@@ -1,2 +1,2 @@
mcu:SAMD11
-mcu:MKL25ZXX
\ No newline at end of file
+mcu:MKL25ZXX
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 96790d20c..de402d3da 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -57,13 +57,15 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -94,7 +96,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 2b773b43b..4f0f6410f 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#if CFG_TUD_MSC
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index d8dbb5ce3..c0610945f 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -141,51 +142,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456789012", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 9fe1a325e..a16b8bd71 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -1,83 +1,93 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake)
-if (EXISTS ${TOP}/lib/lwip/src)
- include(${TOP}/hw/bsp/family_support.cmake)
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
- # gets PROJECT name for the example (e.g. -)
- family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+set(LWIP ${TOP}/lib/lwip)
+if (NOT EXISTS ${LWIP}/src)
+ family_example_missing_dependency(${PROJECT} "lib/lwip")
+ return()
+endif()
- project(${PROJECT})
+project(${PROJECT} C CXX ASM)
- # Checks this example is valid for the family and initializes the project
- family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
- add_executable(${PROJECT})
+add_executable(${PROJECT})
- # Example source
- target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
- )
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/src/main.c
+ ${CMAKE_CURRENT_LIST_DIR}/src/usb_descriptors.c
+ )
- # Example include
- target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- ${TOP}/lib/lwip/src/include
- ${TOP}/lib/lwip/src/include/ipv4
- ${TOP}/lib/lwip/src/include/lwip/apps
- ${TOP}/lib/networking
- )
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/src
+ ${LWIP}/src/include
+ ${LWIP}/src/include/ipv4
+ ${LWIP}/src/include/lwip/apps
+ ${TOP}/lib/networking
+ )
- target_sources(${PROJECT} PUBLIC
- ${TOP}/lib/lwip/src/core/altcp.c
- ${TOP}/lib/lwip/src/core/altcp_alloc.c
- ${TOP}/lib/lwip/src/core/altcp_tcp.c
- ${TOP}/lib/lwip/src/core/def.c
- ${TOP}/lib/lwip/src/core/dns.c
- ${TOP}/lib/lwip/src/core/inet_chksum.c
- ${TOP}/lib/lwip/src/core/init.c
- ${TOP}/lib/lwip/src/core/ip.c
- ${TOP}/lib/lwip/src/core/mem.c
- ${TOP}/lib/lwip/src/core/memp.c
- ${TOP}/lib/lwip/src/core/netif.c
- ${TOP}/lib/lwip/src/core/pbuf.c
- ${TOP}/lib/lwip/src/core/raw.c
- ${TOP}/lib/lwip/src/core/stats.c
- ${TOP}/lib/lwip/src/core/sys.c
- ${TOP}/lib/lwip/src/core/tcp.c
- ${TOP}/lib/lwip/src/core/tcp_in.c
- ${TOP}/lib/lwip/src/core/tcp_out.c
- ${TOP}/lib/lwip/src/core/timeouts.c
- ${TOP}/lib/lwip/src/core/udp.c
- ${TOP}/lib/lwip/src/core/ipv4/autoip.c
- ${TOP}/lib/lwip/src/core/ipv4/dhcp.c
- ${TOP}/lib/lwip/src/core/ipv4/etharp.c
- ${TOP}/lib/lwip/src/core/ipv4/icmp.c
- ${TOP}/lib/lwip/src/core/ipv4/igmp.c
- ${TOP}/lib/lwip/src/core/ipv4/ip4.c
- ${TOP}/lib/lwip/src/core/ipv4/ip4_addr.c
- ${TOP}/lib/lwip/src/core/ipv4/ip4_frag.c
- ${TOP}/lib/lwip/src/netif/ethernet.c
- ${TOP}/lib/lwip/src/netif/slipif.c
- ${TOP}/lib/lwip/src/apps/http/httpd.c
- ${TOP}/lib/lwip/src/apps/http/fs.c
- ${TOP}/lib/networking/dhserver.c
- ${TOP}/lib/networking/dnserver.c
- ${TOP}/lib/networking/rndis_reports.c
- )
+# lib/networking sources
+target_sources(${PROJECT} PUBLIC
+ ${TOP}/lib/networking/dhserver.c
+ ${TOP}/lib/networking/dnserver.c
+ ${TOP}/lib/networking/rndis_reports.c
+ )
- # due to warnings from other net source, we need to prevent error from some of the warnings options
- target_compile_options(${PROJECT} PUBLIC
- -Wno-error=null-dereference
- -Wno-error=conversion
- -Wno-error=sign-conversion
- -Wno-error=sign-compare
- )
+# lwip sources
+target_sources(${PROJECT} PUBLIC
+ ${LWIP}/src/core/altcp.c
+ ${LWIP}/src/core/altcp_alloc.c
+ ${LWIP}/src/core/altcp_tcp.c
+ ${LWIP}/src/core/def.c
+ ${LWIP}/src/core/dns.c
+ ${LWIP}/src/core/inet_chksum.c
+ ${LWIP}/src/core/init.c
+ ${LWIP}/src/core/ip.c
+ ${LWIP}/src/core/mem.c
+ ${LWIP}/src/core/memp.c
+ ${LWIP}/src/core/netif.c
+ ${LWIP}/src/core/pbuf.c
+ ${LWIP}/src/core/raw.c
+ ${LWIP}/src/core/stats.c
+ ${LWIP}/src/core/sys.c
+ ${LWIP}/src/core/tcp.c
+ ${LWIP}/src/core/tcp_in.c
+ ${LWIP}/src/core/tcp_out.c
+ ${LWIP}/src/core/timeouts.c
+ ${LWIP}/src/core/udp.c
+ ${LWIP}/src/core/ipv4/autoip.c
+ ${LWIP}/src/core/ipv4/dhcp.c
+ ${LWIP}/src/core/ipv4/etharp.c
+ ${LWIP}/src/core/ipv4/icmp.c
+ ${LWIP}/src/core/ipv4/igmp.c
+ ${LWIP}/src/core/ipv4/ip4.c
+ ${LWIP}/src/core/ipv4/ip4_addr.c
+ ${LWIP}/src/core/ipv4/ip4_frag.c
+ ${LWIP}/src/netif/ethernet.c
+ ${LWIP}/src/netif/slipif.c
+ ${LWIP}/src/apps/http/httpd.c
+ ${LWIP}/src/apps/http/fs.c
+ )
- # Configure compilation flags and libraries for the example... see the corresponding function
- # in hw/bsp/FAMILY/family.cmake for details.
- family_configure_device_example(${PROJECT})
-endif()
\ No newline at end of file
+# due to warnings from other net source, we need to prevent error from some of the warnings options
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_compile_options(${PROJECT} PUBLIC
+ -Wno-error=null-dereference
+ -Wno-error=conversion
+ -Wno-error=sign-conversion
+ -Wno-error=sign-compare
+ )
+elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+
+endif ()
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 55bd820bd..90b429d00 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -1,10 +1,9 @@
DEPS_SUBMODULES += lib/lwip
-include ../../../tools/top.mk
include ../../make.mk
# suppress warning caused by lwip
-GCC_CFLAGS += \
+CFLAGS_GCC += \
-Wno-error=null-dereference \
-Wno-error=unused-parameter \
-Wno-error=unused-variable
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 68761b058..e3a726a2b 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -4,7 +4,8 @@ mcu:MSP430x5xx
mcu:NUC121
mcu:SAMD11
mcu:STM32L0
-mcu:MKL25ZXX
+mcu:KINETIS_KL
family:broadcom_64bit
family:broadcom_32bit
-board:curiosity_nano
\ No newline at end of file
+board:curiosity_nano
+board:frdm_kl25z
diff --git a/examples/device/net_lwip_webserver/src/arch/cc.h b/examples/device/net_lwip_webserver/src/arch/cc.h
index 56a0cacf7..9f30b91cb 100644
--- a/examples/device/net_lwip_webserver/src/arch/cc.h
+++ b/examples/device/net_lwip_webserver/src/arch/cc.h
@@ -1,8 +1,8 @@
/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * derived from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
- *
+ *
* Author: Adam Dunkels
*
*/
@@ -42,7 +42,7 @@ typedef int sys_prot_t;
#if defined (__ICCARM__)
#define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#define PACK_STRUCT_USE_INCLUDES
@@ -50,7 +50,7 @@ typedef int sys_prot_t;
#elif defined (__CC_ARM)
#define PACK_STRUCT_BEGIN __packed
-#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index a215017c7..336c9243d 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -1,8 +1,8 @@
/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
+ * derived from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
- *
+ *
* Author: Simon Goldschmidt
*
*/
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 33b4d38b6..7d98aacbc 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Peter Lawrence
@@ -39,11 +39,11 @@ and likely their manufacturer has not tested such functionality. Some code work
The smartphone may only have an ECM driver, but refuse to automatically pick ECM (unlike the OSes above);
try modifying ./examples/devices/net_lwip_webserver/usb_descriptors.c so that CONFIG_ID_ECM is default.
-The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens,
+The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens,
try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 (clearing bit 1).
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "dhserver.h"
@@ -64,7 +64,7 @@ static struct pbuf *received_frame;
/* this is used by this code, ./class/net/net_driver.c, and usb_descriptors.c */
/* ideally speaking, this should be generated from the hardware's unique ID (if available) */
/* it is suggested that the first byte is 0x02 to indicate a link-local address */
-const uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
+uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
/* network parameters of this MCU */
static const ip4_addr_t ipaddr = INIT_IP4(192, 168, 7, 1);
@@ -170,7 +170,7 @@ bool dns_query_proc(const char *name, ip4_addr_t *addr)
bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
{
- /* this shouldn't happen, but if we get another packet before
+ /* this shouldn't happen, but if we get another packet before
parsing the previous, we must signal our inability to accept it */
if (received_frame) return false;
@@ -232,6 +232,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
/* initialize lwip, dhcp-server, dns-server, and http */
init_lwip();
while (!netif_is_up(&netif_data));
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index bee51790a..da628c8be 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -77,7 +78,7 @@ tusb_desc_device_t const desc_device =
.bDeviceClass = TUSB_CLASS_MISC,
.bDeviceSubClass = MISC_SUBCLASS_COMMON,
.bDeviceProtocol = MISC_PROTOCOL_IAD,
-
+
.bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
.idVendor = 0xCafe,
@@ -190,55 +191,56 @@ static char const* string_desc_arr [] =
[STRID_LANGID] = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409)
[STRID_MANUFACTURER] = "TinyUSB", // Manufacturer
[STRID_PRODUCT] = "TinyUSB Device", // Product
- [STRID_SERIAL] = "123456", // Serial
+ [STRID_SERIAL] = NULL, // Serials will use unique ID if possible
[STRID_INTERFACE] = "TinyUSB Network Interface" // Interface Description
// STRID_MAC index is handled separately
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
-
unsigned int chr_count = 0;
- if (STRID_LANGID == index)
- {
- memcpy(&_desc_str[1], string_desc_arr[STRID_LANGID], 2);
- chr_count = 1;
- }
- else if (STRID_MAC == index)
- {
- // Convert MAC address into UTF-16
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- for (unsigned i=0; i> 4) & 0xf];
- _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
- }
- }
- else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ case STRID_MAC:
+ // Convert MAC address into UTF-16
+ for (unsigned i=0; i> 4) & 0xf];
+ _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
+ }
+ break;
- const char* str = string_desc_arr[index];
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > (TU_ARRAY_SIZE(_desc_str) - 1)) chr_count = TU_ARRAY_SIZE(_desc_str) - 1;
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Convert ASCII string into UTF-16
- for (unsigned int i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index abc4d91da..e92a57148 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
@@ -23,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/uac2_headset/Makefile b/examples/device/uac2_headset/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/uac2_headset/Makefile
+++ b/examples/device/uac2_headset/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 003dc2a74..0ab72b2f3 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Jerzy Kasenberg
@@ -26,7 +26,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -79,8 +79,8 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
// Audio controls
// Current states
-int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
-int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1]; // +1 for master channel 0
// Buffer for microphone data
int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
@@ -105,6 +105,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
TU_LOG1("Headset running\r\n");
while (1)
@@ -113,8 +117,6 @@ int main(void)
audio_task();
led_blinking_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -145,7 +147,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
// Helper for clock get requests
@@ -176,7 +178,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
rangef.subrange[i].bRes = 0;
TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
}
-
+
return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
}
}
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 07c86b903..6d1e6a23f 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Ha Thach (tinyusb.org)
@@ -24,6 +24,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -46,7 +47,7 @@ tusb_desc_device_t const desc_device =
.bDescriptorType = TUSB_DESC_DEVICE,
.bcdUSB = 0x0200,
- // Use Interface Association Descriptor (IAD) for CDC
+ // Use Interface Association Descriptor (IAD) for Audio
// As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
.bDeviceClass = TUSB_CLASS_MISC,
.bDeviceSubClass = MISC_SUBCLASS_COMMON,
@@ -106,7 +107,7 @@ uint8_t const * tud_descriptor_device_cb(void)
uint8_t const desc_configuration[] =
{
- // Interface count, string index, total length, attribute, power in mA
+ // Config number, interface count, string index, total length, attribute, power in mA
TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
// Interface number, string index, EP Out & EP In address, EP size
@@ -126,52 +127,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB headset", // 2: Product
- "000001", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB Speakers", // 4: Audio Interface
"TinyUSB Microphone", // 5: Audio Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
- (void)langid;
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+ (void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if (index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }
- else
- {
- // Convert ASCII string into UTF-16
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if (chr_count > 31) chr_count = 31;
+ const char *str = string_desc_arr[index];
- for (uint8_t i = 0; i < chr_count; i++)
- {
- _desc_str[1 + i] = str[i];
- }
+ // Cap at max char
+ chr_count = strlen(str);
+ size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+ if ( chr_count > max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 342b4fac1..d7e170162 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Jerzy Kasenbreg
@@ -57,7 +57,7 @@ enum
+ TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
/* Interface 1, Alternate 0 */\
+ TUD_AUDIO_DESC_STD_AS_INT_LEN\
- /* Interface 1, Alternate 0 */\
+ /* Interface 1, Alternate 1 */\
+ TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
@@ -86,7 +86,7 @@ enum
#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
/* Standard Interface Association Descriptor (IAD) */\
- TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+ TUD_AUDIO_DESC_IAD(/*_firstitf*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
/* Standard AC Interface Descriptor(4.7.1) */\
TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
/* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -114,7 +114,7 @@ enum
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
/* Interface 1, Alternate 2 - alternate interface for data streaming */\
@@ -124,7 +124,7 @@ enum
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
/* Standard AS Interface Descriptor(4.9.1) */\
@@ -138,7 +138,7 @@ enum
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
/* Interface 2, Alternate 2 - alternate interface for data streaming */\
@@ -148,7 +148,7 @@ enum
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
- TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index c49603c26..a63ca2d81 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
@@ -24,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/usbtmc/Makefile b/examples/device/usbtmc/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/usbtmc/Makefile
+++ b/examples/device/usbtmc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 6945d8743..9d8f0783d 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usbtmc_app.h"
//--------------------------------------------------------------------+
@@ -57,14 +57,16 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
led_blinking_task();
usbtmc_app_task_iter();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -95,7 +97,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index ff682ff97..54948291e 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "class/usbtmc/usbtmc.h"
#include "class/usbtmc/usbtmc_device.h"
@@ -188,55 +189,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB USBTMC", // 4: USBTMC
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
-
size_t chr_count;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }
- else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- const char* str = string_desc_arr[index];
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) {
- chr_count = 31;
- }
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 503ee3071..fb25982c7 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -26,7 +26,7 @@
#include
#include /* atoi */
#include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "main.h"
#if (CFG_TUD_USBTMC_ENABLE_488)
@@ -88,14 +88,6 @@ static size_t buffer_tx_ix; // for transmitting using multiple transfers
static uint8_t buffer[225]; // A few packets long should be enough.
-static usbtmc_msg_dev_dep_msg_in_header_t rspMsg = {
- .bmTransferAttributes =
- {
- .EOM = 1,
- .UsingTermChar = 0
- }
-};
-
void tud_usbtmc_open_cb(uint8_t interface_id)
{
(void)interface_id;
@@ -148,12 +140,14 @@ bool tud_usbtmc_msg_data_cb(void *data, size_t len, bool transfer_complete)
queryState = transfer_complete;
idnQuery = 0;
- if ( transfer_complete && (len >= 4) && (!strncmp("*idn?", data, 4) || !strncmp("*IDN?", data, 4)) )
+ if ( transfer_complete && (len >= 4) &&
+ (!strncmp("*idn?", data, 4) || !strncmp("*IDN?", data, 4)) )
{
idnQuery = 1;
}
- if ( transfer_complete && (!strncmp("delay ", data, 5) || !strncmp("DELAY ", data, 5)) )
+ if ( transfer_complete &&
+ (!strncmp("delay ", data, 5) || !strncmp("DELAY ", data, 5)) )
{
queryState = 0;
int d = atoi((char*)data + 5);
@@ -185,9 +179,6 @@ static unsigned int msgReqLen;
bool tud_usbtmc_msgBulkIn_request_cb(usbtmc_msg_request_dev_dep_in const * request)
{
- rspMsg.header.MsgID = request->header.MsgID,
- rspMsg.header.bTag = request->header.bTag,
- rspMsg.header.bTagInverse = request->header.bTagInverse;
msgReqLen = request->TransferSize;
#ifdef xDEBUG
@@ -251,7 +242,6 @@ void usbtmc_app_task_iter(void) {
break;
default:
TU_ASSERT(false,);
- return;
}
}
diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
index c4e5ad2b9..ca65daf97 100644
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -36,8 +36,8 @@ def test_trig():
time.sleep(0.3) # SRQ may have some delay
assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
assert (inst.read_stb() == 0)
-
-
+
+
def test_mav():
inst.write("delay 50")
inst.read_stb() # clear STB
@@ -45,15 +45,15 @@ def test_mav():
inst.write("123")
time.sleep(0.3)
assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
-
+
rsp = inst.read()
assert(rsp == "123\r\n")
-
-
+
+
def test_srq():
assert (inst.read_stb() == 0)
inst.write("123")
-
+
#inst.enable_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
#waitrsp = inst.wait_on_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, 5000)
#inst.discard_events(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
@@ -64,7 +64,7 @@ def test_srq():
assert (stb == 0x50),msg
assert (inst.read_stb() == 0x10), "SRQ set at second read!"
-
+
rsp = inst.read()
assert(rsp == "123\r\n")
@@ -110,7 +110,7 @@ def test_abort_in():
inst.timeout = 800
y = inst.read()
assert(y == "xxx\r\n")
-
+
def test_indicate():
# perform indicator pulse
usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
@@ -120,8 +120,8 @@ def test_indicate():
assert(retv == b'\x01')
else:
assert((retv[1] == pyvisa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
-
-
+
+
def test_multi_read():
old_chunk_size = inst.chunk_size
longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
@@ -133,7 +133,7 @@ def test_multi_read():
y = inst.read()
assert (x + "\r\n" == y)
#inst.chunk_size = old_chunk_size
-
+
def test_stall_ep0():
usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
inst.read_stb()
@@ -143,7 +143,7 @@ def test_stall_ep0():
assert(False)
except pyvisa.VisaIOError:
pass
-
+
assert (inst.read_stb() == 0)
@@ -153,7 +153,7 @@ print(reslist)
if (len(reslist) == 0):
sys.exit()
-
+
inst = rm.open_resource(reslist[0]);
inst.timeout = 3000
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index b92a2b804..80dc39ca5 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
if (FORCE_READONLY)
@@ -29,6 +34,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index fda66bcc1..90d174c32 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
ifeq ($(DISABLE_MJPEG),1)
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 3ceebe821..c653761c1 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -59,6 +59,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -66,8 +70,6 @@ int main(void)
video_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
@@ -98,7 +100,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index e567ba669..274bf2b9c 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -100,6 +100,9 @@
// video streaming endpoint size
#define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256
+// use bulk endpoint for streaming interface
+#define CFG_TUD_VIDEO_STREAMING_BULK 0
+
#ifdef __cplusplus
}
#endif
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 0cf772010..292d86cd9 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -76,15 +77,27 @@ uint8_t const * tud_descriptor_device_cb(void)
//--------------------------------------------------------------------+
#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+# define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN)
+# else
+# define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
+# endif
#else
-#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+# define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN)
+# else
+# define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
+# endif
#endif
#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+#if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+ #define EPNUM_VIDEO_IN 0x82
+#else
#define EPNUM_VIDEO_IN 0x83
+#endif
#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
// nRF5x ISO can only be endpoint 8
@@ -102,13 +115,25 @@ uint8_t const desc_fs_configuration[] =
// IAD for Video Control
#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+ TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(4, EPNUM_VIDEO_IN,
+ FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+ 64)
+# else
TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+# endif
#else
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+ TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
+ FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+ 64)
+# else
TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+# endif
#endif
};
@@ -126,52 +151,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB UVC", // 4: UVC Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index f1ed3c8e9..b924c8dbe 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Jerzy Kasenbreg
@@ -79,6 +79,38 @@ enum {
+ 7/* Endpoint */\
)
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN (\
+ TUD_VIDEO_DESC_IAD_LEN\
+ /* control */\
+ + TUD_VIDEO_DESC_STD_VC_LEN\
+ + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+ + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+ /* Interface 1, Alternate 0 */\
+ + TUD_VIDEO_DESC_STD_VS_LEN\
+ + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+ + 7/* Endpoint */\
+ )
+
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN (\
+ TUD_VIDEO_DESC_IAD_LEN\
+ /* control */\
+ + TUD_VIDEO_DESC_STD_VC_LEN\
+ + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+ + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+ /* Interface 1, Alternate 0 */\
+ + TUD_VIDEO_DESC_STD_VS_LEN\
+ + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+ + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+ + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+ + 7/* Endpoint */\
+ )
+
/* Windows support YUY2 and NV12
* https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
@@ -165,4 +197,75 @@ enum {
/* EP */ \
TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+ /* Video control 0 */ \
+ TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+ TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+ /* wTotalLength - bLength */ \
+ TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+ UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+ TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+ /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+ /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+ /* Video stream alt. 0 */ \
+ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+ /* Video stream header for without still image capture */ \
+ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+ /*wTotalLength - bLength */\
+ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+ /*bmaControls(1)*/0), \
+ /* Video stream format */ \
+ TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+ /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+ /* Video stream frame format */ \
+ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+ _width * _height * 16, _width * _height * 16 * _fps, \
+ _width * _height * 16, \
+ (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+ TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+ /* Video control 0 */ \
+ TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+ TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+ /* wTotalLength - bLength */ \
+ TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+ UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+ TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+ /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+ /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+ /* Video stream alt. 0 */ \
+ TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+ /* Video stream header for without still image capture */ \
+ TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+ /*wTotalLength - bLength */\
+ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+ + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+ /*bmaControls(1)*/0), \
+ /* Video stream format */ \
+ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+ /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+ /* Video stream frame format */ \
+ TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
+ _width * _height * 16, _width * _height * 16 * _fps, \
+ _width * _height * 16 / 8, \
+ (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+ /* EP */ \
+ TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+
#endif
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index abc4d91da..e92a57148 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
@@ -23,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/webusb_serial/Makefile b/examples/device/webusb_serial/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/webusb_serial/Makefile
+++ b/examples/device/webusb_serial/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 604d30a83..800d435b8 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -47,7 +47,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -96,6 +96,10 @@ int main(void)
// init device stack on configured roothub port
tud_init(BOARD_TUD_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -103,8 +107,6 @@ int main(void)
webserial_task();
led_blinking_task();
}
-
- return 0;
}
// send characters to both CDC and WebUSB
@@ -114,7 +116,7 @@ void echo_all(uint8_t buf[], uint32_t count)
if ( web_serial_connected )
{
tud_vendor_write(buf, count);
- tud_vendor_flush();
+ tud_vendor_write_flush();
}
// echo to cdc
@@ -158,7 +160,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
//--------------------------------------------------------------------+
@@ -213,7 +215,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
blink_interval_ms = BLINK_ALWAYS_ON;
tud_vendor_write_str("\r\nWebUSB interface connected\r\n");
- tud_vendor_flush();
+ tud_vendor_write_flush();
}else
{
blink_interval_ms = BLINK_MOUNTED;
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index 99f5caaf9..b01fae8e3 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
#include "usb_descriptors.h"
@@ -207,53 +208,65 @@ TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size");
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB CDC", // 4: CDC Interface
"TinyUSB WebUSB" // 5: Vendor Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/device/webusb_serial/src/usb_descriptors.h b/examples/device/webusb_serial/src/usb_descriptors.h
index 19f1ff3f3..a1c4a2cf1 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.h
+++ b/examples/device/webusb_serial/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index d2f9a42f0..15081cf26 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -1,12 +1,13 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
-project(tinyusb_dual_examples)
+project(tinyusb_dual_examples C CXX ASM)
family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR})
+
if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
- message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
-else()
- # family_add_subdirectory will filter what to actually add based on selected FAMILY
- family_add_subdirectory(host_hid_to_device_cdc)
-endif()
+ message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
+else ()
+ # family_add_subdirectory will filter what to actually add based on selected FAMILY
+ family_add_subdirectory(host_hid_to_device_cdc)
+endif ()
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 724d1e119..a6557c2d0 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
@@ -14,27 +14,27 @@ add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_dual_usb_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT} noos)
# due to warnings from Pico-PIO-USB
target_compile_options(${PROJECT} PUBLIC
- -Wno-error=shadow
- -Wno-error=cast-align
- -Wno-error=cast-qual
- -Wno-error=redundant-decls
- -Wno-error=sign-conversion
- -Wno-error=conversion
- -Wno-error=sign-compare
- -Wno-error=unused-function
- )
+ -Wno-error=shadow
+ -Wno-error=cast-align
+ -Wno-error=cast-qual
+ -Wno-error=redundant-decls
+ -Wno-error=sign-conversion
+ -Wno-error=conversion
+ -Wno-error=sign-compare
+ -Wno-error=unused-function
+ )
diff --git a/examples/dual/host_hid_to_device_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile
index 3fe9b0888..95c88e7e8 100644
--- a/examples/dual/host_hid_to_device_cdc/Makefile
+++ b/examples/dual/host_hid_to_device_cdc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index 6ee8e3fde..cfc87eb4e 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -1,3 +1,6 @@
board:mimxrt1060_evk
board:mimxrt1064_evk
+board:mcb1800
mcu:RP2040
+mcu:ra6m5
+mcu:MAX3421
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index bd7870274..96a2beff5 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -30,7 +30,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -83,6 +83,10 @@ int main(void)
tud_init(BOARD_TUD_RHPORT);
tuh_init(BOARD_TUH_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
tud_task(); // tinyusb device task
@@ -121,7 +125,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
// Invoked when usb bus is resumed
void tud_resume_cb(void)
{
- blink_interval_ms = BLINK_MOUNTED;
+ blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
}
// Invoked when CDC interface received data from host
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index f749bd712..8133ed418 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -84,10 +84,6 @@
#define CFG_TUH_RPI_PIO_USB 1
#endif
-
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG 0
-
/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
* Tinyusb use follows macros to declare transferring memory so that they can be put
* into those specific section.
@@ -95,12 +91,12 @@
* - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
#endif
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN __attribute__ ((aligned(4)))
#endif
//--------------------------------------------------------------------
@@ -128,11 +124,19 @@
// Size of buffer to hold descriptors and other data used for enumeration
#define CFG_TUH_ENUMERATION_BUFSIZE 256
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
#define CFG_TUH_HUB 1
// max device support (excluding hub device)
#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
-#define CFG_TUH_HID 4
+#define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX)
#define CFG_TUH_HID_EPIN_BUFSIZE 64
#define CFG_TUH_HID_EPOUT_BUFSIZE 64
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index 6b0a89127..293620042 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,6 +23,7 @@
*
*/
+#include "bsp/board_api.h"
#include "tusb.h"
/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -214,52 +215,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
// String Descriptors
//--------------------------------------------------------------------+
+// String Descriptor Index
+enum {
+ STRID_LANGID = 0,
+ STRID_MANUFACTURER,
+ STRID_PRODUCT,
+ STRID_SERIAL,
+};
+
// array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
{
(const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
"TinyUSB", // 1: Manufacturer
"TinyUSB Device", // 2: Product
- "123456789012", // 3: Serials, should use chip ID
+ NULL, // 3: Serials will use unique ID if possible
"TinyUSB CDC", // 4: CDC Interface
};
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
// Invoked when received GET STRING DESCRIPTOR request
// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
(void) langid;
+ size_t chr_count;
- uint8_t chr_count;
+ switch ( index ) {
+ case STRID_LANGID:
+ memcpy(&_desc_str[1], string_desc_arr[0], 2);
+ chr_count = 1;
+ break;
- if ( index == 0)
- {
- memcpy(&_desc_str[1], string_desc_arr[0], 2);
- chr_count = 1;
- }else
- {
- // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
- // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+ case STRID_SERIAL:
+ chr_count = board_usb_get_serial(_desc_str + 1, 32);
+ break;
- if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+ default:
+ // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+ // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
- const char* str = string_desc_arr[index];
+ if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
- // Cap at max char
- chr_count = (uint8_t) strlen(str);
- if ( chr_count > 31 ) chr_count = 31;
+ const char *str = string_desc_arr[index];
- // Convert ASCII string into UTF-16
- for(uint8_t i=0; i max_count ) chr_count = max_count;
+
+ // Convert ASCII string into UTF-16
+ for ( size_t i = 0; i < chr_count; i++ ) {
+ _desc_str[1 + i] = str[i];
+ }
+ break;
}
// first byte is length (including header), second byte is string type
- _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+ _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
return _desc_str;
}
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 758973ab2..bedd2220b 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -1,8 +1,8 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
-project(tinyusb_host_examples)
+project(tinyusb_host_examples C CXX ASM)
family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
# family_add_subdirectory will filter what to actually add based on selected FAMILY
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 4879613b4..76182d6fa 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
@@ -22,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
${CMAKE_CURRENT_SOURCE_DIR}/src
)
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 84555a889..161f8c774 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -11,14 +10,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-# TinyUSB Host Stack source
-SRC_C += \
- src/class/cdc/cdc_host.c \
- src/class/hid/hid_host.c \
- src/class/msc/msc_host.c \
- src/host/hub.c \
- src/host/usbh.c \
- src/portable/ohci/ohci.c \
- src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
include ../../rules.mk
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index fa9c14857..fee10f9e2 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -1,11 +1,14 @@
+mcu:KINETIS_KL
mcu:LPC175X_6X
mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
mcu:MIMXRT10XX
mcu:MIMXRT11XX
mcu:RP2040
mcu:MSP432E4
mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 51cab2de0..14725996d 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -32,7 +32,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
// English
@@ -67,6 +67,10 @@ int main(void)
// init host stack on configured roothub port
tuh_init(BOARD_TUH_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
// tinyusb host task
@@ -410,6 +414,7 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
}
static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
+ if ((temp_buf[0] & 0xff) == 0) return; // empty
size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
_convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 701aa6d90..ede9618d3 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -80,12 +80,12 @@
* - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
#endif
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
#endif
//--------------------------------------------------------------------
@@ -100,7 +100,7 @@
// max device support (excluding hub device)
// 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1)
+#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1)
// Max endpoint per device
#define CFG_TUH_ENDPOINT_MAX 8
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index dbba6bf44..a7c372a34 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -1,30 +1,35 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 9adccfa3a..15b8a5b31 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -14,14 +13,4 @@ EXAMPLE_SOURCE = \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-# TinyUSB Host Stack source
-SRC_C += \
- src/class/cdc/cdc_host.c \
- src/class/hid/hid_host.c \
- src/class/msc/msc_host.c \
- src/host/hub.c \
- src/host/usbh.c \
- src/portable/ohci/ohci.c \
- src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index fa9c14857..fee10f9e2 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -1,11 +1,14 @@
+mcu:KINETIS_KL
mcu:LPC175X_6X
mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
mcu:MIMXRT10XX
mcu:MIMXRT11XX
mcu:RP2040
mcu:MSP432E4
mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index b1b137e0e..a1b26e49c 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -25,7 +25,7 @@
*/
#include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
@@ -87,10 +87,10 @@ void tuh_cdc_rx_cb(uint8_t idx)
void tuh_cdc_mount_cb(uint8_t idx)
{
- tuh_cdc_itf_info_t itf_info = { 0 };
+ tuh_itf_info_t itf_info = { 0 };
tuh_cdc_itf_get_info(idx, &itf_info);
- printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+ printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
// CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
@@ -106,8 +106,8 @@ void tuh_cdc_mount_cb(uint8_t idx)
void tuh_cdc_umount_cb(uint8_t idx)
{
- tuh_cdc_itf_info_t itf_info = { 0 };
+ tuh_itf_info_t itf_info = { 0 };
tuh_cdc_itf_get_info(idx, &itf_info);
- printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+ printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
}
diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index ed53c502d..f0d42a08f 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -160,7 +160,9 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
putchar(ch);
if ( ch == '\r' ) putchar('\n'); // added new line for enter key
+ #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
fflush(stdout); // flush right away, else nanolib will wait for newline
+ #endif
}
}
// TODO example skips key released
@@ -263,7 +265,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c
if (!rpt_info)
{
- printf("Couldn't find the report info for this report !\r\n");
+ printf("Couldn't find report info !\r\n");
return;
}
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index b34810252..405bf8c06 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -27,7 +27,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -48,6 +48,10 @@ int main(void)
// init host stack on configured roothub port
tuh_init(BOARD_TUH_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
// tinyusb host task
@@ -57,8 +61,6 @@ int main(void)
cdc_app_task();
hid_app_task();
}
-
- return 0;
}
//--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 797d55f8a..e9c9676b8 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -68,4 +68,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
(void) dev_addr;
printf("A MassStorage device is unmounted\r\n");
}
-
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 139a921d1..c8e9138e3 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -35,9 +35,9 @@
//--------------------------------------------------------------------+
#if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB 0
-#define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB
+ // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+ #define CFG_TUH_RPI_PIO_USB 0
+ #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB
#endif
// RHPort number used for host can be defined by board.mk, default to port 0
@@ -80,12 +80,12 @@
* - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
#endif
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
#endif
//--------------------------------------------------------------------
@@ -96,13 +96,15 @@
#define CFG_TUH_ENUMERATION_BUFSIZE 256
#define CFG_TUH_HUB 1 // number of supported hubs
-#define CFG_TUH_CDC 1
-#define CFG_TUH_HID 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_CDC 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
#define CFG_TUH_MSC 1
#define CFG_TUH_VENDOR 0
-// max device support (excluding hub device)
-#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1)
//------------- HID -------------//
#define CFG_TUH_HID_EPIN_BUFSIZE 64
diff --git a/examples/host/cdc_msc_hid_freertos/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
new file mode 100644
index 000000000..2e95a18e0
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
@@ -0,0 +1,36 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} freertos)
diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
new file mode 100644
index 000000000..a9670b4f2
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -0,0 +1,34 @@
+include ../../make.mk
+
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
+
+INC += \
+ src \
+ src/FreeRTOSConfig \
+ $(TOP)/hw \
+ $(TOP)/$(FREERTOS_SRC)/include \
+ $(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
+# Example source
+EXAMPLE_SOURCE = \
+ src/cdc_app.c \
+ src/freertos_hook.c \
+ src/hid_app.c \
+ src/main.c \
+ src/msc_app.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# FreeRTOS source, all files in port folder
+SRC_C += \
+ $(FREERTOS_SRC)/list.c \
+ $(FREERTOS_SRC)/queue.c \
+ $(FREERTOS_SRC)/tasks.c \
+ $(FREERTOS_SRC)/timers.c \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+ $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+
+include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
new file mode 100644
index 000000000..3837ac8a2
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -0,0 +1,13 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..6f057c106
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -0,0 +1,6 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "cdc_app.c" "hid_app.c" "main.c" "msc_app.c"
+ INCLUDE_DIRS "."
+ REQUIRES boards tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..a1fc8bb09
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+// Include MCU header
+#include "bsp/board_mcu.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+ #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+// TODO fix later
+// FIXME cause redundant-decls warnings
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+ extern u32 SystemCoreClock;
+#else
+ extern uint32_t SystemCoreClock;
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
+#define vTickISR INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY 1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+ // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+ // RISC-V Bumblebee core from nuclei
+ #define configPRIO_BITS __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+ // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+ // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+ // IAR user must update this to correct value of the target MCU
+ #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+ #define configPRIO_BITS 2
+
+#else
+ #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< cdc interfaces
+ tuh_cdc_write(idx, buf, count);
+ tuh_cdc_write_flush(idx);
+ }
+ }
+ }
+
+ vTaskDelay(1);
+ }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx) {
+ uint8_t buf[64 + 1]; // +1 for extra null character
+ uint32_t const bufsize = sizeof(buf) - 1;
+
+ // forward cdc interfaces -> console
+ uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+ buf[count] = 0;
+
+ printf((char *) buf);
+}
+
+void tuh_cdc_mount_cb(uint8_t idx) {
+ tuh_itf_info_t itf_info = { 0 };
+ tuh_cdc_itf_get_info(idx, &itf_info);
+
+ printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+ // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
+ // otherwise you need to call tuh_cdc_set_line_coding() first
+ cdc_line_coding_t line_coding = { 0 };
+ if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
+ printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+ printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
+ }
+#endif
+}
+
+void tuh_cdc_umount_cb(uint8_t idx) {
+ tuh_itf_info_t itf_info = { 0 };
+ tuh_cdc_itf_get_info(idx, &itf_info);
+
+ printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
new file mode 100644
index 000000000..07d159fd5
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "common/tusb_common.h"
+
+void vApplicationMallocFailedHook(void) {
+ taskDISABLE_INTERRUPTS();
+ TU_ASSERT(false,);
+}
+
+void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) {
+ (void) pxTask;
+ (void) pcTaskName;
+
+ taskDISABLE_INTERRUPTS();
+ TU_ASSERT(false,);
+}
+
+/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer,
+ uint32_t *pulIdleTaskStackSize) {
+ /* If the buffers to be provided to the Idle task are declared inside this
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
+ static StaticTask_t xIdleTaskTCB;
+ static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+ state will be stored. */
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+ /* Pass out the array that will be used as the Idle task's stack. */
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer,
+ uint32_t *pulTimerTaskStackSize) {
+ /* If the buffers to be provided to the Timer task are declared inside this
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
+ static StaticTask_t xTimerTaskTCB;
+ static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer
+ task's state will be stored. */
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+ /* Pass out the array that will be used as the Timer task's stack. */
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+ Note that, as the array is necessarily of type StackType_t,
+ configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void)
+{
+ /* Enable CMT0 */
+ SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+ MSTP(CMT0) = 0;
+ SYSTEM.PRCR.WORD = (0xA5u<<8);
+
+ CMT0.CMCNT = 0;
+ CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+ CMT0.CMCR.WORD = TU_BIT(6) | 2;
+ IR(CMT0, CMI0) = 0;
+ IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+ IEN(CMT0, CMI0) = 1;
+ CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
new file mode 100644
index 000000000..9ea5c1be0
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -0,0 +1,267 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// If your host terminal support ansi escape code such as TeraTerm
+// it can be use to simulate mouse cursor movement within terminal
+#define USE_ANSI_ESCAPE 0
+
+#define MAX_REPORT 4
+
+static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
+
+// Each HID instance can has multiple reports
+static struct {
+ uint8_t report_count;
+ tuh_hid_report_info_t report_info[MAX_REPORT];
+} hid_info[CFG_TUH_HID];
+
+static void process_kbd_report(hid_keyboard_report_t const *report);
+static void process_mouse_report(hid_mouse_report_t const *report);
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
+
+void hid_app_init(void) {
+ // nothing to do
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_report, uint16_t desc_len) {
+ printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+
+ // Interface protocol (hid_interface_protocol_enum_t)
+ const char *protocol_str[] = { "None", "Keyboard", "Mouse" };
+ uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+ printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]);
+
+ // By default host stack will use activate boot protocol on supported interface.
+ // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser)
+ if (itf_protocol == HID_ITF_PROTOCOL_NONE) {
+ hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT,
+ desc_report, desc_len);
+ printf("HID has %u reports \r\n", hid_info[instance].report_count);
+ }
+
+ // request to receive report
+ // tuh_hid_report_received_cb() will be invoked when report is available
+ if (!tuh_hid_receive_report(dev_addr, instance)) {
+ printf("Error: cannot request to receive report\r\n");
+ }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
+ printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+ uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+ switch (itf_protocol) {
+ case HID_ITF_PROTOCOL_KEYBOARD:
+ TU_LOG2("HID receive boot keyboard report\r\n");
+ process_kbd_report((hid_keyboard_report_t const *) report);
+ break;
+
+ case HID_ITF_PROTOCOL_MOUSE:
+ TU_LOG2("HID receive boot mouse report\r\n");
+ process_mouse_report((hid_mouse_report_t const *) report);
+ break;
+
+ default:
+ // Generic report requires matching ReportID and contents with previous parsed report info
+ process_generic_report(dev_addr, instance, report, len);
+ break;
+ }
+
+ // continue to request to receive report
+ if (!tuh_hid_receive_report(dev_addr, instance)) {
+ printf("Error: cannot request to receive report\r\n");
+ }
+}
+
+//--------------------------------------------------------------------+
+// Keyboard
+//--------------------------------------------------------------------+
+
+// look up new key in previous keys
+static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) {
+ for (uint8_t i = 0; i < 6; i++) {
+ if (report->keycode[i] == keycode) return true;
+ }
+
+ return false;
+}
+
+static void process_kbd_report(hid_keyboard_report_t const *report) {
+ static hid_keyboard_report_t prev_report = { 0, 0, { 0 } }; // previous report to check key released
+
+ //------------- example code ignore control (non-printable) key affects -------------//
+ for (uint8_t i = 0; i < 6; i++) {
+ if (report->keycode[i]) {
+ if (find_key_in_report(&prev_report, report->keycode[i])) {
+ // exist in previous report means the current key is holding
+ } else {
+ // not existed in previous report means the current key is pressed
+ bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+ uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0];
+ putchar(ch);
+ if (ch == '\r') putchar('\n'); // added new line for enter key
+
+ #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
+ fflush(stdout); // flush right away, else nanolib will wait for newline
+ #endif
+ }
+ }
+ // TODO example skips key released
+ }
+
+ prev_report = *report;
+}
+
+//--------------------------------------------------------------------+
+// Mouse
+//--------------------------------------------------------------------+
+
+void cursor_movement(int8_t x, int8_t y, int8_t wheel) {
+#if USE_ANSI_ESCAPE
+ // Move X using ansi escape
+ if ( x < 0) {
+ printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left
+ }else if ( x > 0) {
+ printf(ANSI_CURSOR_FORWARD(%d), x); // move right
+ }
+
+ // Move Y using ansi escape
+ if ( y < 0) {
+ printf(ANSI_CURSOR_UP(%d), (-y)); // move up
+ }else if ( y > 0) {
+ printf(ANSI_CURSOR_DOWN(%d), y); // move down
+ }
+
+ // Scroll using ansi escape
+ if (wheel < 0) {
+ printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up
+ }else if (wheel > 0) {
+ printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down
+ }
+
+ printf("\r\n");
+#else
+ printf("(%d %d %d)\r\n", x, y, wheel);
+#endif
+}
+
+static void process_mouse_report(hid_mouse_report_t const *report) {
+ static hid_mouse_report_t prev_report = { 0 };
+
+ //------------- button state -------------//
+ uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
+ if (button_changed_mask & report->buttons) {
+ printf(" %c%c%c ",
+ report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-',
+ report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-',
+ report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-');
+ }
+
+ //------------- cursor movement -------------//
+ cursor_movement(report->x, report->y, report->wheel);
+}
+
+//--------------------------------------------------------------------+
+// Generic Report
+//--------------------------------------------------------------------+
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+ (void) dev_addr;
+
+ uint8_t const rpt_count = hid_info[instance].report_count;
+ tuh_hid_report_info_t *rpt_info_arr = hid_info[instance].report_info;
+ tuh_hid_report_info_t *rpt_info = NULL;
+
+ if (rpt_count == 1 && rpt_info_arr[0].report_id == 0) {
+ // Simple report without report ID as 1st byte
+ rpt_info = &rpt_info_arr[0];
+ } else {
+ // Composite report, 1st byte is report ID, data starts from 2nd byte
+ uint8_t const rpt_id = report[0];
+
+ // Find report id in the array
+ for (uint8_t i = 0; i < rpt_count; i++) {
+ if (rpt_id == rpt_info_arr[i].report_id) {
+ rpt_info = &rpt_info_arr[i];
+ break;
+ }
+ }
+
+ report++;
+ len--;
+ }
+
+ if (!rpt_info) {
+ printf("Couldn't find report info !\r\n");
+ return;
+ }
+
+ // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+ // - Keyboard : Desktop, Keyboard
+ // - Mouse : Desktop, Mouse
+ // - Gamepad : Desktop, Gamepad
+ // - Consumer Control (Media Key) : Consumer, Consumer Control
+ // - System Control (Power key) : Desktop, System Control
+ // - Generic (vendor) : 0xFFxx, xx
+ if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) {
+ switch (rpt_info->usage) {
+ case HID_USAGE_DESKTOP_KEYBOARD:
+ TU_LOG1("HID receive keyboard report\r\n");
+ // Assume keyboard follow boot report layout
+ process_kbd_report((hid_keyboard_report_t const *) report);
+ break;
+
+ case HID_USAGE_DESKTOP_MOUSE:
+ TU_LOG1("HID receive mouse report\r\n");
+ // Assume mouse follow boot report layout
+ process_mouse_report((hid_mouse_report_t const *) report);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
new file mode 100644
index 000000000..691ff3e29
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -0,0 +1,165 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ // ESP-IDF need "freertos/" prefix in include path.
+ // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+ #include "freertos/FreeRTOS.h"
+ #include "freertos/semphr.h"
+ #include "freertos/queue.h"
+ #include "freertos/task.h"
+ #include "freertos/timers.h"
+
+ #define USBH_STACK_SIZE 4096
+#else
+ #include "FreeRTOS.h"
+ #include "semphr.h"
+ #include "queue.h"
+ #include "task.h"
+ #include "timers.h"
+
+ // Increase stack size when debug log is enabled
+ #define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+/* Blink pattern
+ * - 250 ms : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum {
+ BLINK_NOT_MOUNTED = 250,
+ BLINK_MOUNTED = 1000,
+ BLINK_SUSPENDED = 2500,
+};
+
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
+StaticTimer_t blinky_tmdef;
+
+StackType_t usb_host_stack[USBH_STACK_SIZE];
+StaticTask_t usb_host_taskdef;
+#endif
+
+TimerHandle_t blinky_tm;
+
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_host_task(void* param);
+
+extern void cdc_app_init(void);
+extern void hid_app_init(void);
+extern void msc_app_init(void);
+
+/*------------- MAIN -------------*/
+int main(void) {
+ board_init();
+
+ printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
+
+ // Create soft timer for blinky, task for tinyusb stack
+#if configSUPPORT_STATIC_ALLOCATION
+ blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+ xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
+#else
+ blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+ xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+#endif
+
+ xTimerStart(blinky_tm, 0);
+
+ // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ vTaskStartScheduler();
+#endif
+
+ return 0;
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+void app_main(void) {
+ main();
+}
+#endif
+
+// USB Host task
+// This top level thread process all usb events and invoke callbacks
+static void usb_host_task(void *param) {
+ (void) param;
+
+ // init host stack on configured roothub port
+ tuh_init(BOARD_TUH_RHPORT);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
+ cdc_app_init();
+ hid_app_init();
+ msc_app_init();
+
+ // RTOS forever loop
+ while (1) {
+ // put this thread to waiting state until there is new events
+ tuh_task();
+
+ // following code only run if tuh_task() process at least 1 event
+ }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+void tuh_mount_cb(uint8_t dev_addr) {
+ // application set-up
+ printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr) {
+ // application tear-down
+ printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+static void led_blinky_cb(TimerHandle_t xTimer) {
+ (void) xTimer;
+ static bool led_state = false;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
new file mode 100644
index 000000000..ee02ba917
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -0,0 +1,67 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+static scsi_inquiry_resp_t inquiry_resp;
+
+void msc_app_init(void) {
+ // nothing to do
+}
+
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
+ msc_cbw_t const *cbw = cb_data->cbw;
+ msc_csw_t const *csw = cb_data->csw;
+
+ if (csw->status != 0) {
+ printf("Inquiry failed\r\n");
+ return false;
+ }
+
+ // Print out Vendor ID, Product ID and Rev
+ printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
+
+ // Get capacity of device
+ uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+ uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+
+ printf("Disk Size: %lu MB\r\n", block_count / ((1024 * 1024) / block_size));
+ printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+
+ return true;
+}
+
+//------------- IMPLEMENTATION -------------//
+void tuh_msc_mount_cb(uint8_t dev_addr) {
+ printf("A MassStorage device is mounted\r\n");
+
+ uint8_t const lun = 0;
+ tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
+}
+
+void tuh_msc_umount_cb(uint8_t dev_addr) {
+ (void) dev_addr;
+ printf("A MassStorage device is unmounted\r\n");
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
new file mode 100644
index 000000000..1bed9a9b3
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -0,0 +1,133 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+ // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+ #define CFG_TUH_RPI_PIO_USB 0
+ #define BOARD_TUH_RHPORT CFG_TUH_RPI_PIO_USB
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT 0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define CFG_TUSB_OS_INC_PATH freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG 0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED 1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB 1 // number of supported hubs
+#define CFG_TUH_CDC 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC 1
+#define CFG_TUH_VENDOR 0
+
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1)
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE 64
+#define CFG_TUH_HID_EPOUT_BUFSIZE 64
+
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index aa50b5a52..c1b500dd8 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ )
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index e7fbd741f..e7f603f25 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
INC += \
@@ -12,14 +11,4 @@ EXAMPLE_SOURCE += \
SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-# TinyUSB Host Stack source
-SRC_C += \
- src/class/cdc/cdc_host.c \
- src/class/hid/hid_host.c \
- src/class/msc/msc_host.c \
- src/host/hub.c \
- src/host/usbh.c \
- src/portable/ohci/ohci.c \
- src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
include ../../rules.mk
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index fa9c14857..fee10f9e2 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -1,11 +1,14 @@
+mcu:KINETIS_KL
mcu:LPC175X_6X
mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
mcu:MIMXRT10XX
mcu:MIMXRT11XX
mcu:RP2040
mcu:MSP432E4
mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 75c91400e..bff830ca2 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -23,7 +23,7 @@
*
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
/* From https://www.kernel.org/doc/html/latest/input/gamepad.html
@@ -91,9 +91,8 @@ typedef struct TU_ATTR_PACKED
uint8_t counter : 6; // +1 each report
};
- // comment out since not used by this example
- // uint8_t l2_trigger; // 0 released, 0xff fully pressed
- // uint8_t r2_trigger; // as above
+ uint8_t l2_trigger; // 0 released, 0xff fully pressed
+ uint8_t r2_trigger; // as above
// uint16_t timestamp;
// uint8_t battery;
@@ -105,15 +104,54 @@ typedef struct TU_ATTR_PACKED
} sony_ds4_report_t;
+typedef struct TU_ATTR_PACKED {
+ // First 16 bits set what data is pertinent in this structure (1 = set; 0 = not set)
+ uint8_t set_rumble : 1;
+ uint8_t set_led : 1;
+ uint8_t set_led_blink : 1;
+ uint8_t set_ext_write : 1;
+ uint8_t set_left_volume : 1;
+ uint8_t set_right_volume : 1;
+ uint8_t set_mic_volume : 1;
+ uint8_t set_speaker_volume : 1;
+ uint8_t set_flags2;
+
+ uint8_t reserved;
+
+ uint8_t motor_right;
+ uint8_t motor_left;
+
+ uint8_t lightbar_red;
+ uint8_t lightbar_green;
+ uint8_t lightbar_blue;
+ uint8_t lightbar_blink_on;
+ uint8_t lightbar_blink_off;
+
+ uint8_t ext_data[8];
+
+ uint8_t volume_left;
+ uint8_t volume_right;
+ uint8_t volume_mic;
+ uint8_t volume_speaker;
+
+ uint8_t other[9];
+} sony_ds4_output_report_t;
+
+static bool ds4_mounted = false;
+static uint8_t ds4_dev_addr = 0;
+static uint8_t ds4_instance = 0;
+static uint8_t motor_left = 0;
+static uint8_t motor_right = 0;
+
// check if device is Sony DualShock 4
static inline bool is_sony_ds4(uint8_t dev_addr)
{
uint16_t vid, pid;
tuh_vid_pid_get(dev_addr, &vid, &pid);
- return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4
- || (vid == 0x0f0d && pid == 0x005e) // Hori FC4
- || (vid == 0x0f0d && pid == 0x00ee) // Hori PS4 Mini (PS4-099U)
+ return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4
+ || (vid == 0x0f0d && pid == 0x005e) // Hori FC4
+ || (vid == 0x0f0d && pid == 0x00ee) // Hori PS4 Mini (PS4-099U)
|| (vid == 0x1f4f && pid == 0x1002) // ASW GG xrd controller
);
}
@@ -124,7 +162,23 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
void hid_app_task(void)
{
- // nothing to do
+ if (ds4_mounted)
+ {
+ const uint32_t interval_ms = 200;
+ static uint32_t start_ms = 0;
+
+ uint32_t current_time_ms = board_millis();
+ if ( current_time_ms - start_ms >= interval_ms)
+ {
+ start_ms = current_time_ms;
+
+ sony_ds4_output_report_t output_report = {0};
+ output_report.set_rumble = 1;
+ output_report.motor_left = motor_left;
+ output_report.motor_right = motor_right;
+ tuh_hid_send_report(ds4_dev_addr, ds4_instance, 5, &output_report, sizeof(output_report));
+ }
+ }
}
//--------------------------------------------------------------------+
@@ -149,6 +203,14 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
// Sony DualShock 4 [CUH-ZCT2x]
if ( is_sony_ds4(dev_addr) )
{
+ if (!ds4_mounted)
+ {
+ ds4_dev_addr = dev_addr;
+ ds4_instance = instance;
+ motor_left = 0;
+ motor_right = 0;
+ ds4_mounted = true;
+ }
// request to receive report
// tuh_hid_report_received_cb() will be invoked when report is available
if ( !tuh_hid_receive_report(dev_addr, instance) )
@@ -162,6 +224,10 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
{
printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+ if (ds4_mounted && ds4_dev_addr == dev_addr && ds4_instance == instance)
+ {
+ ds4_mounted = false;
+ }
}
// check if different than 2
@@ -179,8 +245,8 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
result = diff_than_2(rpt1->x, rpt2->x) || diff_than_2(rpt1->y , rpt2->y ) ||
diff_than_2(rpt1->z, rpt2->z) || diff_than_2(rpt1->rz, rpt2->rz);
- // check the reset with mem compare
- result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-4);
+ // check the rest with mem compare
+ result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-6);
return result;
}
@@ -234,6 +300,10 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
printf("\r\n");
}
+ // The left and right triggers control the intensity of the left and right rumble motors
+ motor_left = ds4_report.l2_trigger;
+ motor_right = ds4_report.r2_trigger;
+
prev_report = ds4_report;
}
}
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 299a3ff10..05a5ae176 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -32,7 +32,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -54,6 +54,10 @@ int main(void)
// init host stack on configured roothub port
tuh_init(BOARD_TUH_RHPORT);
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
while (1)
{
// tinyusb host task
@@ -68,8 +72,6 @@ int main(void)
hid_app_task();
#endif
}
-
- return 0;
}
//--------------------------------------------------------------------+
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index e6d6f873d..d37fc02d2 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -80,12 +80,12 @@
* - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
* - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
*/
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
#endif
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4)))
#endif
//--------------------------------------------------------------------
@@ -97,13 +97,12 @@
#define CFG_TUH_HUB 0
#define CFG_TUH_CDC 0
-#define CFG_TUH_HID 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
#define CFG_TUH_MSC 0
#define CFG_TUH_VENDOR 0
-// max device support (excluding hub device)
-// 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1)
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1)
//------------- HID -------------//
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 2c06eafee..1a57c7466 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -1,34 +1,47 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
# gets PROJECT name for the example (e.g. -)
family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
# Checks this example is valid for the family and initializes the project
family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
add_executable(${PROJECT})
# Example source
target_sources(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
- ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
- ${TOP}/lib/fatfs/source/ff.c
- ${TOP}/lib/fatfs/source/ffsystem.c
- ${TOP}/lib/fatfs/source/ffunicode.c
- )
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+ ${TOP}/lib/fatfs/source/ff.c
+ ${TOP}/lib/fatfs/source/ffsystem.c
+ ${TOP}/lib/fatfs/source/ffunicode.c
+ )
+
+# Suppress warnings on fatfs
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ set_source_files_properties(
+ ${TOP}/lib/fatfs/source/ff.c
+ PROPERTIES
+ COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual"
+ )
+endif ()
# Example include
target_include_directories(${PROJECT} PUBLIC
- ${CMAKE_CURRENT_SOURCE_DIR}/src
- ${TOP}/lib/fatfs/source
- ${TOP}/lib/embedded-cli
- )
-
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ ${TOP}/lib/fatfs/source
+ ${TOP}/lib/embedded-cli
+ )
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index de2f9c01c..8319d3c2b 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
include ../../make.mk
FATFS_PATH = lib/fatfs/source
@@ -25,14 +24,4 @@ SRC_C += \
# suppress warning caused by fatfs
CFLAGS += -Wno-error=cast-qual
-# TinyUSB Host Stack source
-SRC_C += \
- src/class/cdc/cdc_host.c \
- src/class/hid/hid_host.c \
- src/class/msc/msc_host.c \
- src/host/hub.c \
- src/host/usbh.c \
- src/portable/ohci/ohci.c \
- src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
include ../../rules.mk
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index fa9c14857..fee10f9e2 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -1,11 +1,14 @@
+mcu:KINETIS_KL
mcu:LPC175X_6X
mcu:LPC177X_8X
mcu:LPC18XX
mcu:LPC40XX
mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
mcu:MIMXRT10XX
mcu:MIMXRT11XX
mcu:RP2040
mcu:MSP432E4
mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index ab2cfd498..73f3e9eb5 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -23,11 +23,43 @@
*
*/
+/* Example to show how to navigate mass storage device with built-in command line.
+ * Type help for list of supported commands and syntax (mostly linux commands)
+
+ > help
+ * help
+ Print list of commands
+ * cat
+ Usage: cat [FILE]...
+ Concatenate FILE(s) to standard output..
+ * cd
+ Usage: cd [DIR]...
+ Change the current directory to DIR.
+ * cp
+ Usage: cp SOURCE DEST
+ Copy SOURCE to DEST.
+ * ls
+ Usage: ls [DIR]...
+ List information about the FILEs (the current directory by default).
+ * pwd
+ Usage: pwd
+ Print the name of the current working directory.
+ * mkdir
+ Usage: mkdir DIR...
+ Create the DIRECTORY(ies), if they do not already exist..
+ * mv
+ Usage: mv SOURCE DEST...
+ Rename SOURCE to DEST.
+ * rm
+ Usage: rm [FILE]...
+ Remove (unlink) the FILE(s).
+ */
+
#include
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "tusb.h"
//--------------------------------------------------------------------+
@@ -48,6 +80,11 @@ int main(void)
// init host stack on configured roothub port
tuh_init(BOARD_TUH_RHPORT);
+
+ if (board_init_after_tusb) {
+ board_init_after_tusb();
+ }
+
msc_app_init();
while (1)
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 5a1635015..ecea614a2 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
#include
#include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "ff.h"
#include "diskio.h"
@@ -66,7 +66,10 @@ bool msc_app_init(void)
for(size_t i=0; i $(BUILD)/$(BOARD).jlink
- @echo r > $(BUILD)/$(BOARD).jlink
- @echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
- @echo r >> $(BUILD)/$(BOARD).jlink
- @echo go >> $(BUILD)/$(BOARD).jlink
- @echo exit >> $(BUILD)/$(BOARD).jlink
- $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
+# Jlink script
+$(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex
+ @echo halt > $@
+ @echo loadfile $^ >> $@
+ @echo r >> $@
+ @echo go >> $@
+ @echo exit >> $@
+# Flash using jlink
+flash-jlink: $(BUILD)/$(BOARD).jlink
+ $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $<
+
+# --------------- stm32 cube programmer -----------------
# Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
flash-stlink: $(BUILD)/$(PROJECT).elf
STM32_Programmer_CLI --connect port=swd --write $< --go
+# --------------- xfel -----------------
$(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin
$(PYTHON) $(TOP)/tools/mksunxi.py $< $@
@@ -245,18 +123,23 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
xfel spinor write 0 $<
xfel reset
-# Flash using pyocd
+# --------------- pyocd -----------------
PYOCD_OPTION ?=
flash-pyocd: $(BUILD)/$(PROJECT).hex
pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
#pyocd reset -t $(PYOCD_TARGET)
-# Flash using openocd
+# --------------- openocd -----------------
OPENOCD_OPTION ?=
flash-openocd: $(BUILD)/$(PROJECT).elf
openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
-# flash with Black Magic Probe
+# --------------- dfu-util -----------------
+DFU_UTIL_OPTION ?= -a 0
+flash-dfu-util: $(BUILD)/$(PROJECT).bin
+ dfu-util -R $(DFU_UTIL_OPTION) -D $<
+
+# --------------- Black Magic -----------------
# This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules
BMP ?= /dev/ttyBmpGdb
@@ -270,7 +153,11 @@ debug-bmp: $(BUILD)/$(PROJECT).elf
# Create binary directory
$(BIN):
+ifeq ($(CMDEXE),1)
+ @$(MKDIR) $(subst /,\,$@)
+else
@$(MKDIR) -p $@
+endif
# Copy binaries .elf, .bin, .hex, .uf2 to BIN for upload
# due to large size of combined artifacts, only uf2 is uploaded for now
@@ -283,4 +170,4 @@ copy-artifact: $(BIN)
# Print out the value of a make variable.
# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
print-%:
- @echo $* = $($*)
\ No newline at end of file
+ @echo $* = $($*)
diff --git a/examples/typec/CMakeLists.txt b/examples/typec/CMakeLists.txt
new file mode 100644
index 000000000..c7641494e
--- /dev/null
+++ b/examples/typec/CMakeLists.txt
@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
+
+project(tinyusb_host_examples C CXX ASM)
+family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
+
+# family_add_subdirectory will filter what to actually add based on selected FAMILY
+family_add_subdirectory(power_delivery)
diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt
new file mode 100644
index 000000000..012eff095
--- /dev/null
+++ b/examples/typec/power_delivery/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. -)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+ return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+ )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+ ${CMAKE_CURRENT_SOURCE_DIR}/src
+ )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/typec/power_delivery/Makefile b/examples/typec/power_delivery/Makefile
new file mode 100644
index 000000000..2a3d854fb
--- /dev/null
+++ b/examples/typec/power_delivery/Makefile
@@ -0,0 +1,11 @@
+include ../../make.mk
+
+INC += \
+ src \
+ $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/typec/power_delivery/only.txt b/examples/typec/power_delivery/only.txt
new file mode 100644
index 000000000..657aeaac5
--- /dev/null
+++ b/examples/typec/power_delivery/only.txt
@@ -0,0 +1 @@
+mcu:STM32G4
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
new file mode 100644
index 000000000..489d01aa1
--- /dev/null
+++ b/examples/typec/power_delivery/src/main.c
@@ -0,0 +1,193 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// Voltage and current for selecting PDO
+// DANGEROUS: Please make sure your board can withstand the voltage and current
+// defined here. Otherwise, you may damage your board, smoke can come out
+#define VOLTAGE_MAX_MV 5000 // maximum voltage in mV
+#define CURRENT_MAX_MA 500 // maximum current in mA
+#define CURRENT_OPERATING_MA 100 // operating current in mA
+
+/* Blink pattern
+ * - 250 ms : button is not pressed
+ * - 1000 ms : button is pressed (and hold)
+ */
+enum {
+ BLINK_PRESSED = 250,
+ BLINK_UNPRESSED = 1000
+};
+
+static uint32_t blink_interval_ms = BLINK_UNPRESSED;
+
+void led_blinking_task(void);
+
+#define HELLO_STR "Hello from TinyUSB\r\n"
+
+int main(void)
+{
+ board_init();
+ board_led_write(true);
+
+ tuc_init(0, TUSB_TYPEC_PORT_SNK);
+
+ while (1) {
+ led_blinking_task();
+
+ // tinyusb typec task
+ tuc_task();
+ }
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+void app_main(void)
+{
+ main();
+}
+#endif
+
+//--------------------------------------------------------------------+
+// TypeC PD callbacks
+//--------------------------------------------------------------------+
+
+bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) {
+ switch (header->msg_type) {
+ case PD_DATA_SOURCE_CAP: {
+ printf("PD Source Capabilities\r\n");
+ // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
+ uint8_t selected_pos = 1;
+
+ for(size_t i=0; in_data_obj; i++) {
+ TU_VERIFY(dobj < p_end);
+ uint32_t const pdo = tu_le32toh(tu_unaligned_read32(dobj));
+
+ switch ((pdo >> 30) & 0x03ul) {
+ case PD_PDO_TYPE_FIXED: {
+ pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
+ uint32_t const voltage_mv = fixed->voltage_50mv*50;
+ uint32_t const current_ma = fixed->current_max_10ma*10;
+ printf("[Fixed] %lu mV %lu mA\r\n", voltage_mv, current_ma);
+
+ if (voltage_mv <= VOLTAGE_MAX_MV && current_ma >= CURRENT_MAX_MA) {
+ // Found a suitable PDO
+ selected_pos = i+1;
+ }
+
+ break;
+ }
+
+ case PD_PDO_TYPE_BATTERY:
+ break;
+
+ case PD_PDO_TYPE_VARIABLE:
+ break;
+
+ case PD_PDO_TYPE_APDO:
+ break;
+ }
+
+ dobj += 4;
+ }
+
+ //------------- Response with selected PDO -------------//
+ // Be careful and make sure your board can withstand the selected PDO
+ // voltage other than safe5v e.g 12v or 20v
+
+ printf("Selected PDO %u\r\n", selected_pos);
+
+ // Send request with selected PDO position as response to Source Cap
+ pd_rdo_fixed_variable_t rdo = {
+ .current_extremum_10ma = 50, // max 500mA
+ .current_operate_10ma = 30, // 300mA
+ .reserved = 0,
+ .epr_mode_capable = 0,
+ .unchunked_ext_msg_support = 0,
+ .no_usb_suspend = 0,
+ .usb_comm_capable = 1,
+ .capability_mismatch = 0,
+ .give_back_flag = 0, // exteremum is max
+ .object_position = selected_pos,
+ };
+ tuc_msg_request(rhport, &rdo);
+
+ break;
+ }
+
+ default: break;
+ }
+
+ return true;
+}
+
+bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) {
+ (void) rhport;
+ switch (header->msg_type) {
+ case PD_CTRL_ACCEPT:
+ printf("PD Request Accepted\r\n");
+ // preparing for power transition
+ break;
+
+ case PD_CTRL_REJECT:
+ printf("PD Request Rejected\r\n");
+ // try to negotiate further power
+ break;
+
+ case PD_CTRL_PS_READY:
+ printf("PD Power Ready\r\n");
+ // Source is ready to supply power
+ break;
+
+ default:
+ break;
+ }
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+ static uint32_t start_ms = 0;
+ static bool led_state = false;
+
+ // Blink every interval ms
+ if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+ start_ms += blink_interval_ms;
+
+ board_led_write(led_state);
+ led_state = 1 - led_state; // toggle
+}
diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h
new file mode 100644
index 000000000..f7cb3cc04
--- /dev/null
+++ b/examples/typec/power_delivery/src/tusb_config.h
@@ -0,0 +1,83 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+ #error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+ #define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#define CFG_TUD_ENABLED 0
+#define CFG_TUH_ENABLED 0
+
+// Enable TYPEC stack
+#define CFG_TUC_ENABLED 1
+
+
+// special example that doesn't enable device or host stack
+// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
+// to pass the compilation process
+#if CFG_TUD_ENABLED == 0
+#define tud_int_handler(x)
+#endif
+
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG 0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4)))
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/hw/bsp/ansi_escape.h b/hw/bsp/ansi_escape.h
index 6e62ee20a..15af2f3ab 100644
--- a/hw/bsp/ansi_escape.h
+++ b/hw/bsp/ansi_escape.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 14858c2b6..562792625 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@@ -23,56 +23,7 @@
*
*/
-#include "board.h"
-
-#if 0
-#define LED_PHASE_MAX 8
-
-static struct
-{
- uint32_t phase[LED_PHASE_MAX];
- uint8_t phase_count;
-
- bool led_state;
- uint8_t current_phase;
- uint32_t current_ms;
-}led_pattern;
-
-void board_led_pattern(uint32_t const phase_ms[], uint8_t count)
-{
- memcpy(led_pattern.phase, phase_ms, 4*count);
- led_pattern.phase_count = count;
-
- // reset with 1st phase is on
- led_pattern.current_ms = board_millis();
- led_pattern.current_phase = 0;
- led_pattern.led_state = true;
- board_led_on();
-}
-
-void board_led_task(void)
-{
- if ( led_pattern.phase_count == 0 ) return;
-
- uint32_t const duration = led_pattern.phase[led_pattern.current_phase];
-
- // return if not enough time
- if (board_millis() - led_pattern.current_ms < duration) return;
-
- led_pattern.led_state = !led_pattern.led_state;
- board_led_write(led_pattern.led_state);
-
- led_pattern.current_ms += duration;
- led_pattern.current_phase++;
-
- if (led_pattern.current_phase == led_pattern.phase_count)
- {
- led_pattern.current_phase = 0;
- led_pattern.led_state = true;
- board_led_on();
- }
-}
-#endif
+#include "board_api.h"
//--------------------------------------------------------------------+
// newlib read()/write() retarget
@@ -93,17 +44,16 @@ void board_led_task(void)
// If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
#if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
+
#include "SEGGER_RTT.h"
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) {
(void) fhdl;
- SEGGER_RTT_Write(0, (const char*) buf, (int) count);
+ SEGGER_RTT_Write(0, (const char *) buf, (int) count);
return count;
}
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
(void) fhdl;
int rd = (int) SEGGER_RTT_Read(0, buf, count);
return (rd > 0) ? rd : -1;
@@ -116,19 +66,18 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
#include "board_mcu.h"
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
(void) fhdl;
uint8_t const* buf8 = (uint8_t const*) buf;
- for(size_t i=0; i 0) ? rd : -1;
@@ -153,8 +100,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
#endif
-int board_getchar(void)
-{
+int board_getchar(void) {
char c;
- return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1);
+ return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
}
diff --git a/hw/bsp/board.h b/hw/bsp/board_api.h
similarity index 55%
rename from hw/bsp/board.h
rename to hw/bsp/board_api.h
index 0a10294d0..a7dcabfcc 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board_api.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,21 +24,16 @@
* This file is part of the TinyUSB stack.
*/
-/** \ingroup group_demo
- * \defgroup group_board Boards Abstraction Layer
- * @{ */
-
-#ifndef _BSP_BOARD_H_
-#define _BSP_BOARD_H_
+#ifndef _BOARD_API_H_
+#define _BOARD_API_H_
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#include
#include
-#include "ansi_escape.h"
#include "tusb.h"
// Define the default baudrate
@@ -54,6 +49,9 @@
// Initialize on-board peripherals : led, button, uart and USB
void board_init(void);
+// Init board after tinyusb is initialized
+void board_init_after_tusb(void) TU_ATTR_WEAK;
+
// Turn LED on or off
void board_led_write(bool state);
@@ -65,42 +63,39 @@ void board_led_write(bool state);
// a '1' means active (pressed), a '0' means inactive.
uint32_t board_button_read(void);
-// Get characters from UART
-// Return number of read bytes
-int board_uart_read(uint8_t* buf, int len);
+// Get board unique ID for USB serial number. Return number of bytes. Note max_len is typically 16
+TU_ATTR_WEAK size_t board_get_unique_id(uint8_t id[], size_t max_len);
-// Send characters to UART
-// Return number of sent bytes
-int board_uart_write(void const * buf, int len);
+// Get characters from UART. Return number of read bytes
+int board_uart_read(uint8_t *buf, int len);
+
+// Send characters to UART. Return number of sent bytes
+int board_uart_write(void const *buf, int len);
#if CFG_TUSB_OS == OPT_OS_NONE
- // Get current milliseconds, must be implemented when no RTOS is used
- uint32_t board_millis(void);
+// Get current milliseconds, must be implemented when no RTOS is used
+uint32_t board_millis(void);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
- static inline uint32_t board_millis(void)
- {
- return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
- }
+static inline uint32_t board_millis(void) {
+ return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
+}
#elif CFG_TUSB_OS == OPT_OS_MYNEWT
- static inline uint32_t board_millis(void)
- {
- return os_time_ticks_to_ms32( os_time_get() );
- }
+static inline uint32_t board_millis(void) {
+ return os_time_ticks_to_ms32( os_time_get() );
+}
#elif CFG_TUSB_OS == OPT_OS_PICO
- #include "pico/time.h"
- static inline uint32_t board_millis(void)
- {
- return to_ms_since_boot(get_absolute_time());
- }
+#include "pico/time.h"
+static inline uint32_t board_millis(void) {
+ return to_ms_since_boot(get_absolute_time());
+}
#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
- static inline uint32_t board_millis(void)
- {
- return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
- }
+static inline uint32_t board_millis(void) {
+ return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
+}
#else
#error "board_millis() is not implemented for this OS"
@@ -109,26 +104,58 @@ int board_uart_write(void const * buf, int len);
//--------------------------------------------------------------------+
// Helper functions
//--------------------------------------------------------------------+
-static inline void board_led_on(void)
-{
+static inline void board_led_on(void) {
board_led_write(true);
}
-static inline void board_led_off(void)
-{
+static inline void board_led_off(void) {
board_led_write(false);
}
+// Get USB Serial number string from unique ID if available. Return number of character.
+// Input is string descriptor from index 1 (index 0 is type + len)
+static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars) {
+ uint8_t uid[16] TU_ATTR_ALIGNED(4);
+ size_t uid_len;
+
+ if ( board_get_unique_id ) {
+ uid_len = board_get_unique_id(uid, sizeof(uid));
+ }else {
+ // fixed serial string is 01234567889ABCDEF
+ uint32_t* uid32 = (uint32_t*) (uintptr_t) uid;
+ uid32[0] = 0x67452301;
+ uid32[1] = 0xEFCDAB89;
+ uid_len = 8;
+ }
+
+ if ( uid_len > max_chars / 2 ) uid_len = max_chars / 2;
+
+ for ( size_t i = 0; i < uid_len; i++ ) {
+ for ( size_t j = 0; j < 2; j++ ) {
+ const char nibble_to_hex[16] = {
+ '0', '1', '2', '3', '4', '5', '6', '7',
+ '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+ };
+ uint8_t const nibble = (uid[i] >> (j * 4)) & 0xf;
+ desc_str1[i * 2 + (1 - j)] = nibble_to_hex[nibble]; // UTF-16-LE
+ }
+ }
+
+ return 2 * uid_len;
+}
+
// TODO remove
-static inline void board_delay(uint32_t ms)
-{
+static inline void board_delay(uint32_t ms) {
uint32_t start_ms = board_millis();
- while (board_millis() - start_ms < ms)
- {
- #if CFG_TUD_ENABLED
+ while ( board_millis() - start_ms < ms ) {
// take chance to run usb background
+ #if CFG_TUD_ENABLED
tud_task();
#endif
+
+ #if CFG_TUH_ENABLED
+ tuh_task();
+ #endif
}
}
@@ -136,9 +163,7 @@ static inline void board_delay(uint32_t ms)
int board_getchar(void);
#ifdef __cplusplus
- }
+}
#endif
-#endif /* _BSP_BOARD_H_ */
-
-/** @} */
+#endif
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 18f071a22..e5d2bb608 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -39,15 +39,15 @@
//--------------------------------------------------------------------+
// Include order follows OPT_MCU_ number
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || \
- CFG_TUSB_MCU == OPT_MCU_LPC15XX || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \
- CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
- CFG_TUSB_MCU == OPT_MCU_LPC40XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
+#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \
+ TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \
+ TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
#include "chip.h"
-#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
- CFG_TUSB_MCU == OPT_MCU_LPC55XX || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
- CFG_TUSB_MCU == OPT_MCU_K32L2BXX
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
+ #include "fsl_device_registers.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L)
#include "fsl_device_registers.h"
#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
@@ -101,6 +101,9 @@
#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
#include "stm32u5xx.h"
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+ #include "stm32g0xx.h"
+
#elif CFG_TUSB_MCU == OPT_MCU_CXD56
// no header needed
@@ -113,7 +116,7 @@
#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
// no header needed
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT
+#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
#include "fsl_device_registers.h"
#elif CFG_TUSB_MCU == OPT_MCU_NUC120
@@ -136,13 +139,16 @@
#elif CFG_TUSB_MCU == OPT_MCU_RP2040
#include "pico.h"
-
+
#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
#include "em_device.h"
#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
// no header needed
+#elif CFG_TUSB_MCU == OPT_MCU_RAXXX
+ #include "bsp_api.h"
+
#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
#include "gd32vf103.h"
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
index 52e9e45c4..052033230 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
@@ -1,5 +1,5 @@
-CFLAGS += -mcpu=arm1176jzf-s \
- -DBCM_VERSION=2835 \
+CPU_CORE = arm1176
+CFLAGS += -DBCM_VERSION=2835 \
-DCFG_TUSB_MCU=OPT_MCU_BCM2835
-SUFFIX =
+SUFFIX =
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index f7a11fb49..664b4dcaf 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "broadcom/cpu.h"
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
index 5706b8318..702f10137 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
@@ -1,3 +1,3 @@
-CFLAGS += -mcpu=cortex-a72 \
- -DBCM_VERSION=2711 \
+CPU_CORE = cortex-a72
+CFLAGS += -DBCM_VERSION=2711 \
-DCFG_TUSB_MCU=OPT_MCU_BCM2711
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
index 3060b0571..da3fe17bc 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
@@ -1,3 +1,3 @@
-CFLAGS += -mcpu=cortex-a53 \
- -DBCM_VERSION=2837 \
+CPU_CORE = cortex-a53
+CFLAGS += -DBCM_VERSION=2837 \
-DCFG_TUSB_MCU=OPT_MCU_BCM2837
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index f7a11fb49..664b4dcaf 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "broadcom/cpu.h"
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 3b6b03904..4d81e7d52 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright 2021 Bridgetek Pte Ltd
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include
@@ -70,7 +70,7 @@ void board_init(void)
board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
#ifdef BOARD_GPIO_LED
- gpio_function(BOARD_GPIO_LED, pad_func_0);
+ gpio_function(BOARD_GPIO_LED, pad_func_0);
gpio_idrive(BOARD_GPIO_LED, pad_drive_12mA);
gpio_dir(BOARD_GPIO_LED, pad_dir_output);
#endif
@@ -233,7 +233,7 @@ int board_uart_write(void const *buf, int len)
uint32_t board_millis(void)
{
uint32_t safe_ms;
-
+
CRITICAL_SECTION_BEGIN
safe_ms = timer_ms;
CRITICAL_SECTION_END
@@ -254,4 +254,3 @@ void chip_reboot(void)
dbg_memory_copy(0xfe, 0, 0, 255);
#endif
}
-
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 0ddf47a3a..6df0bfdfe 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -5,7 +5,7 @@ SKIP_NANOLIB = 1
# Set to use FT90X prebuilt libraries.
FT9XX_PREBUILT_LIBS = 0
ifeq ($(FT9XX_PREBUILT_LIBS),1)
-# If the FT90X toolchain is installed on Windows systems then the SDK
+# If the FT90X toolchain is installed on Windows systems then the SDK
# include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
INC += "$(FT9XX_SDK)/include"
@@ -21,7 +21,7 @@ endif
# Add include files which are within the TinyUSB directory structure.
INC += \
- $(TOP)/$(BOARD_PATH)
+ $(TOP)/$(BOARD_PATH)
# Add required C Compiler flags for FT90X.
CFLAGS += \
@@ -30,7 +30,7 @@ CFLAGS += \
-fvar-tracking-assignments \
-fmessage-length=0 \
-ffunction-sections \
- -DCFG_TUSB_MCU=OPT_MCU_FT90X
+ -DCFG_TUSB_MCU=OPT_MCU_FT90X
# Maximum USB device speed supported by the board
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
@@ -45,7 +45,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \
-Wl,-lc
# Additional Source files for FT90X.
-SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c
# Linker library.
ifneq ($(FT9XX_PREBUILT_LIBS),1)
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
similarity index 99%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
index 0eab34916..7b488096e 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
similarity index 99%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
index 45fc9e3aa..db3551ca7 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
+++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
@@ -36,7 +36,7 @@ static unsigned int tx_produce;
static volatile unsigned int tx_consume;
void USART1_IRQHandler(void) __attribute__((naked));
-void USART1_IRQHandler(void) {
+void USART1_IRQHandler(void) {
__asm volatile ("call USART1_IRQHandler_impl; mret");
}
@@ -57,7 +57,7 @@ __attribute__((used)) void USART1_IRQHandler_impl(void)
void uart_write(char c)
{
unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
-
+
NVIC_DisableIRQ(USART1_IRQn);
if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
tx_buf[tx_produce] = c;
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h
diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld
index af7c06615..55bd10cd0 100644
--- a/hw/bsp/ch32v307/ch32v307.ld
+++ b/hw/bsp/ch32v307/ch32v307.ld
@@ -41,7 +41,7 @@ SECTIONS
*(.glue_7t)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
- } >FLASH AT>FLASH
+ } >FLASH AT>FLASH
.fini :
{
@@ -50,31 +50,31 @@ SECTIONS
} >FLASH AT>FLASH
PROVIDE( _etext = . );
- PROVIDE( _eitcm = . );
+ PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH AT>FLASH
-
+ } >FLASH AT>FLASH
+
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH AT>FLASH
-
+ } >FLASH AT>FLASH
+
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH AT>FLASH
-
+ } >FLASH AT>FLASH
+
.ctors :
{
/* gcc uses crtbegin.o to find the start of
@@ -95,8 +95,8 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
- } >FLASH AT>FLASH
-
+ } >FLASH AT>FLASH
+
.dtors :
{
KEEP (*crtbegin.o(.dtors))
@@ -104,17 +104,17 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
- } >FLASH AT>FLASH
+ } >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
- } >RAM AT>FLASH
+ } >RAM AT>FLASH
.dlalign :
{
- . = ALIGN(4);
+ . = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
@@ -145,7 +145,7 @@ SECTIONS
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
- *(.gnu.linkonce.b.*)
+ *(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
@@ -156,15 +156,12 @@ SECTIONS
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
- PROVIDE( _heap_end = . );
+ PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
__freertos_irq_stack_top = .;
- } >RAM
+ } >RAM
}
-
-
-
diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h
index 399feaf68..0b86ad390 100644
--- a/hw/bsp/ch32v307/ch32v30x_conf.h
+++ b/hw/bsp/ch32v307/ch32v30x_conf.h
@@ -6,7 +6,7 @@
* Description : Library configuration file.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
+*******************************************************************************/
#ifndef __CH32V30x_CONF_H
#define __CH32V30x_CONF_H
@@ -36,8 +36,3 @@
#endif /* __CH32V30x_CONF_H */
-
-
-
-
-
diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c
index d348dd989..c329c5613 100644
--- a/hw/bsp/ch32v307/ch32v30x_it.c
+++ b/hw/bsp/ch32v307/ch32v30x_it.c
@@ -45,5 +45,3 @@ __attribute__((used)) void HardFault_Handler_impl(void)
{
}
}
-
-
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
index 42f285edf..f3977a8be 100644
--- a/hw/bsp/ch32v307/ch32v30x_it.h
+++ b/hw/bsp/ch32v307/ch32v30x_it.h
@@ -14,5 +14,3 @@
#endif /* __CH32V30x_IT_H */
-
-
diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h
index 2e94ec683..a7ce10a00 100644
--- a/hw/bsp/ch32v307/core_riscv.h
+++ b/hw/bsp/ch32v307/core_riscv.h
@@ -336,7 +336,7 @@ RV_STATIC_INLINE void NVIC_SystemReset(void)
}
-/* Core_Exported_Functions */
+/* Core_Exported_Functions */
extern uint32_t __get_FFLAGS(void);
extern void __set_FFLAGS(uint32_t value);
extern uint32_t __get_FRM(void);
@@ -377,8 +377,3 @@ extern uint32_t __get_SP(void);
#endif
-
-
-
-
-
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index d5602c7b4..245fa5674 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -28,7 +28,7 @@
#include "debug_uart.h"
#include "ch32v30x.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 15f6724a8..4b06cf429 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -34,23 +34,23 @@ SRC_C += \
$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_rcc.c \
- $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c
-
+ $(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c
+
SRC_S += \
- $(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S
+ $(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc
# For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
# wch-link is not supported yet in official openOCD yet. We need to either use
# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
# 2. compiled from modified source https://github.com/kprasadvnsi/riscv-openocd-wch
#
-# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable,
+# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable,
# therefore we need to compile it from source as follows:
# git clone https://github.com/kprasadvnsi/riscv-openocd-wch
# cd riscv-openocd-wch
diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c
index 12b18d7b8..23f783df4 100644
--- a/hw/bsp/ch32v307/system_ch32v30x.c
+++ b/hw/bsp/ch32v307/system_ch32v30x.c
@@ -8,17 +8,17 @@
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
-#include "ch32v30x.h"
+#include "ch32v30x.h"
-/*
-* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
-* If none of the define below is enabled, the HSI is used as System clock source.
+* If none of the define below is enabled, the HSI is used as System clock source.
*/
// #define SYSCLK_FREQ_HSE HSE_VALUE
-/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
//#define SYSCLK_FREQ_48MHz 48000000
-/* #define SYSCLK_FREQ_56MHz 56000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
//#define SYSCLK_FREQ_72MHz 72000000
//#define SYSCLK_FREQ_96MHz 96000000
//#define SYSCLK_FREQ_120MHz 120000000
@@ -60,7 +60,7 @@ static void SetSysClock(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
- static void SetSysClockTo56(void);
+ static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
@@ -90,7 +90,7 @@ void SystemInit (void)
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
-#endif
+#endif
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
@@ -101,8 +101,8 @@ void SystemInit (void)
RCC->INTR = 0x00FF0000;
RCC->CFGR2 = 0x00000000;
#else
- RCC->INTR = 0x009F0000;
-#endif
+ RCC->INTR = 0x009F0000;
+#endif
SetSysClock();
}
@@ -118,18 +118,18 @@ void SystemCoreClockUpdate (void)
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
tmp = RCC->CFGR0 & RCC_SWS;
-
+
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
- case 0x04:
+ case 0x04:
SystemCoreClock = HSE_VALUE;
break;
- case 0x08:
+ case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
- pllsource = RCC->CFGR0 & RCC_PLLSRC;
+ pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
#ifdef CH32V30x_D8
@@ -149,7 +149,7 @@ void SystemCoreClockUpdate (void)
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
- {
+ {
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
{
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
@@ -167,9 +167,9 @@ void SystemCoreClockUpdate (void)
SystemCoreClock = HSI_VALUE;
break;
}
-
+
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
- SystemCoreClock >>= tmp;
+ SystemCoreClock >>= tmp;
}
/*********************************************************************
@@ -188,7 +188,7 @@ static void SetSysClock(void)
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56();
+ SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#elif defined SYSCLK_FREQ_96MHz
@@ -199,9 +199,9 @@ static void SetSysClock(void)
SetSysClockTo144();
#endif
-
+
/* If none of the define above is enabled, the HSI is used as System clock
- * source (default after reset)
+ * source (default after reset)
*/
}
@@ -218,14 +218,14 @@ static void SetSysClock(void)
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
+
RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
+
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
- StartUpCounter++;
+ StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -235,20 +235,20 @@ static void SetSysClockToHSE(void)
else
{
HSEStatus = (uint32_t)0x00;
- }
+ }
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
- RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-
+
/* Select HSE as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
- RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+ RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
@@ -256,11 +256,11 @@ static void SetSysClockToHSE(void)
}
}
else
- {
+ {
/* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error
+ * configuration. User can add here some code to deal with this error
*/
- }
+ }
}
#elif defined SYSCLK_FREQ_24MHz
@@ -275,14 +275,14 @@ static void SetSysClockToHSE(void)
static void SetSysClockTo24(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
+
RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
+
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
- StartUpCounter++;
+ StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -292,13 +292,13 @@ static void SetSysClockTo24(void)
else
{
HSEStatus = (uint32_t)0x00;
- }
+ }
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
- RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
- RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
@@ -318,18 +318,18 @@ static void SetSysClockTo24(void)
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
- RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
- {
+ {
/* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error
+ * configuration. User can add here some code to deal with this error
*/
- }
+ }
}
#elif defined SYSCLK_FREQ_48MHz
@@ -344,14 +344,14 @@ static void SetSysClockTo24(void)
static void SetSysClockTo48(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-
+
+
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
- StartUpCounter++;
+ StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -361,14 +361,14 @@ static void SetSysClockTo48(void)
else
{
HSEStatus = (uint32_t)0x00;
- }
+ }
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
- RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
- RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
@@ -389,19 +389,19 @@ static void SetSysClockTo48(void)
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
- RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
- {
+ {
/*
* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error
+ * configuration. User can add here some code to deal with this error
*/
- }
+ }
}
#elif defined SYSCLK_FREQ_56MHz
@@ -416,14 +416,14 @@ static void SetSysClockTo48(void)
static void SetSysClockTo56(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
+
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
- StartUpCounter++;
+ StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -433,17 +433,17 @@ static void SetSysClockTo56(void)
else
{
HSEStatus = (uint32_t)0x00;
- }
+ }
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
- RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
+
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
@@ -462,19 +462,19 @@ static void SetSysClockTo56(void)
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
- RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
- {
+ {
/*
* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error
+ * configuration. User can add here some code to deal with this error
*/
- }
+ }
}
#elif defined SYSCLK_FREQ_72MHz
@@ -489,14 +489,14 @@ static void SetSysClockTo56(void)
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
+
RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
+
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
- StartUpCounter++;
+ StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -506,17 +506,17 @@ static void SetSysClockTo72(void)
else
{
HSEStatus = (uint32_t)0x00;
- }
+ }
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
- RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
- RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
+
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
@@ -532,20 +532,20 @@ static void SetSysClockTo72(void)
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
- }
+ }
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
- RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
- {
+ {
/*
* If HSE fails to start-up, the application will have wrong clock
- * configuration. User can add here some code to deal with this error
+ * configuration. User can add here some code to deal with this error
*/
}
}
diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h
index 0e0ef4e51..ad81058c7 100644
--- a/hw/bsp/ch32v307/system_ch32v30x.h
+++ b/hw/bsp/ch32v307/system_ch32v30x.h
@@ -7,16 +7,16 @@
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
-#ifndef __SYSTEM_CH32V30x_H
+#ifndef __SYSTEM_CH32V30x_H
#define __SYSTEM_CH32V30x_H
#ifdef __cplusplus
extern "C" {
-#endif
+#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
-/* System_Exported_Functions */
+/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
@@ -25,6 +25,3 @@ extern void SystemCoreClockUpdate(void);
#endif
#endif /*__CH32V30x_SYSTEM_H */
-
-
-
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
deleted file mode 100644
index b7796b9d8..000000000
--- a/hw/bsp/d5035_01/board.mk
+++ /dev/null
@@ -1,61 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-HWREV ?= 1
-
-CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mlong-calls \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
- -nostdlib -nostartfiles \
- -D__SAME51J19A__ \
- -DCONF_CPU_FREQUENCY=80000000 \
- -DCONF_GCLK_USB_FREQUENCY=48000000 \
- -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
- -DD5035_01=1 \
- -DBOARD_NAME="\"D5035-01\"" \
- -DSVC_Handler=SVCall_Handler \
- -DHWREV=$(HWREV)
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
-
-SRC_C += \
- src/portable/microchip/samd/dcd_samd.c \
- hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
- hw/mcu/microchip/same51/gcc/system_same51.c
-
-ifdef SYSCALLS
-ifneq ($(SYSCALLS),0)
- SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-ifdef LOG
-ifneq ($(LOG),0)
- SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-INC += \
- $(TOP)/hw/mcu/microchip/same51/ \
- $(TOP)/hw/mcu/microchip/same51/config \
- $(TOP)/hw/mcu/microchip/same51/include \
- $(TOP)/hw/mcu/microchip/same51/hal/include \
- $(TOP)/hw/mcu/microchip/same51/hal/utils/include \
- $(TOP)/hw/mcu/microchip/same51/hpl/port \
- $(TOP)/hw/mcu/microchip/same51/hri \
- $(TOP)/hw/mcu/microchip/same51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME51J19
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
index e969c79c2..1f7bc1588 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da14695_dk_usb/board.mk
@@ -31,7 +31,7 @@ INC += \
$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
# For flash-jlink target
JLINK_DEVICE = DA14695
@@ -52,4 +52,3 @@ flash-dialog: $(BUILD)/$(PROJECT).bin
@echo go >> $(BUILD)/$(BOARD).jlink
@echo exit >> $(BUILD)/$(BOARD).jlink
$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index a4d996810..667b83de3 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Jerzy Kasenberg
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include
#include
diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da14695_dk_usb/da1469x.ld
index 96507d6e7..8cc1d9d99 100644
--- a/hw/bsp/da14695_dk_usb/da1469x.ld
+++ b/hw/bsp/da14695_dk_usb/da1469x.ld
@@ -242,4 +242,3 @@ SECTIONS
/* Check that intvect is at the beginning of RAM */
ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
}
-
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
index 980fc422f..f9bf480de 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x_dk_pro/board.mk
@@ -31,7 +31,7 @@ INC += \
$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
# For flash-jlink target
JLINK_DEVICE = DA14699
@@ -52,4 +52,3 @@ flash-dialog: $(BUILD)/$(PROJECT).bin
@echo go >> $(BUILD)/$(BOARD).jlink
@echo exit >> $(BUILD)/$(BOARD).jlink
$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 13113fb95..21bd62714 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 Jerzy Kasenberg
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include
#include
diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld
index 96507d6e7..8cc1d9d99 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ b/hw/bsp/da1469x_dk_pro/da1469x.ld
@@ -242,4 +242,3 @@ SECTIONS
/* Check that intvect is at the beginning of RAM */
ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
}
-
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
deleted file mode 100644
index 6f243c6a2..000000000
--- a/hw/bsp/ea4357/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
- -nostdlib \
- -DCORE_M4 \
- -D__USE_LPCOPEN \
- -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
-
-SRC_C += \
- src/portable/chipidea/ci_hs/dcd_ci_hs.c \
- src/portable/chipidea/ci_hs/hcd_ci_hs.c \
- src/portable/ehci/ehci.c \
- $(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
- $(MCU_DIR)/src/chip_18xx_43xx.c \
- $(MCU_DIR)/src/clock_18xx_43xx.c \
- $(MCU_DIR)/src/gpio_18xx_43xx.c \
- $(MCU_DIR)/src/sysinit_18xx_43xx.c \
- $(MCU_DIR)/src/i2c_18xx_43xx.c \
- $(MCU_DIR)/src/i2cm_18xx_43xx.c \
- $(MCU_DIR)/src/uart_18xx_43xx.c \
- $(MCU_DIR)/src/fpu_init.c
-
-INC += \
- $(TOP)/$(MCU_DIR)/inc \
- $(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4357_M4
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
deleted file mode 100644
index c3c687a70..000000000
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-idf_component_register(SRCS esp32s2.c
- INCLUDE_DIRS "." "${BOARD}"
- PRIV_REQUIRES "driver"
- REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
- "${TOP}/hw"
- "${TOP}/src"
-)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
deleted file mode 100644
index d33962676..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
- message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
deleted file mode 100644
index d33962676..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
- message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
- message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
deleted file mode 100644
index a7ca82deb..000000000
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/rmt.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
- #include "esp_private/periph_ctrl.h"
-#else
- #include "driver/periph_ctrl.h"
-#endif
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
- #ifdef NEOPIXEL_POWER_PIN
- gpio_reset_pin(NEOPIXEL_POWER_PIN);
- gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
- gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
- #endif
-
- // WS2812 Neopixel driver with RMT peripheral
- rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
- config.clk_div = 2; // set counter clock to 40MHz
-
- rmt_config(&config);
- rmt_driver_install(config.channel, 0, 0);
-
- led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
- strip = led_strip_new_rmt_ws2812(&strip_config);
- strip->clear(strip, 100); // off led
-#endif
-
- // Button
- esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
- gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
- gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
- // USB Controller Hal init
- periph_module_reset(PERIPH_USB_MODULE);
- periph_module_enable(PERIPH_USB_MODULE);
-
- usb_hal_context_t hal = {
- .use_external_phy = false // use built-in PHY
- };
- usb_hal_init(&hal);
- configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
- /* usb_periph_iopins currently configures USB_OTG as USB Device.
- * Introduce additional parameters in usb_hal_context_t when adding support
- * for USB Host.
- */
- for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
- if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
- esp_rom_gpio_pad_select_gpio(iopin->pin);
- if (iopin->is_output) {
- esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
- } else {
- esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
- if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
- if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
- {
- gpio_ll_input_enable(&GPIO, iopin->pin);
- }
- }
- esp_rom_gpio_pad_unhold(iopin->pin);
- }
- }
- if (!usb->use_external_phy) {
- gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
- gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
- }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
- strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
- strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
- return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
- message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
deleted file mode 100644
index d5c17b9be..000000000
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
- message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
deleted file mode 100644
index 6d0fcbc86..000000000
--- a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
- INCLUDE_DIRS "include"
- PRIV_INCLUDE_DIRS ""
- PRIV_REQUIRES "driver"
- REQUIRES "")
-
diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake
deleted file mode 100644
index f3d41d041..000000000
--- a/hw/bsp/esp32s2/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s2)
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s3/boards/CMakeLists.txt b/hw/bsp/esp32s3/boards/CMakeLists.txt
deleted file mode 100644
index e1b921ae9..000000000
--- a/hw/bsp/esp32s3/boards/CMakeLists.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-idf_component_register(SRCS esp32s3.c
- INCLUDE_DIRS "." "${BOARD}"
- PRIV_REQUIRES "driver"
- REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
-target_include_directories(${COMPONENT_TARGET} PUBLIC
- "${FREERTOS_ORIG_INCLUDE_PATH}"
- "${TOP}/hw"
- "${TOP}/src"
-)
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
deleted file mode 100644
index a7ca82deb..000000000
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/rmt.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
- #include "esp_private/periph_ctrl.h"
-#else
- #include "driver/periph_ctrl.h"
-#endif
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
- #ifdef NEOPIXEL_POWER_PIN
- gpio_reset_pin(NEOPIXEL_POWER_PIN);
- gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
- gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
- #endif
-
- // WS2812 Neopixel driver with RMT peripheral
- rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
- config.clk_div = 2; // set counter clock to 40MHz
-
- rmt_config(&config);
- rmt_driver_install(config.channel, 0, 0);
-
- led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
- strip = led_strip_new_rmt_ws2812(&strip_config);
- strip->clear(strip, 100); // off led
-#endif
-
- // Button
- esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
- gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
- gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
- // USB Controller Hal init
- periph_module_reset(PERIPH_USB_MODULE);
- periph_module_enable(PERIPH_USB_MODULE);
-
- usb_hal_context_t hal = {
- .use_external_phy = false // use built-in PHY
- };
- usb_hal_init(&hal);
- configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
- /* usb_periph_iopins currently configures USB_OTG as USB Device.
- * Introduce additional parameters in usb_hal_context_t when adding support
- * for USB Host.
- */
- for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
- if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
- esp_rom_gpio_pad_select_gpio(iopin->pin);
- if (iopin->is_output) {
- esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
- } else {
- esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
- if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
- if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
- {
- gpio_ll_input_enable(&GPIO, iopin->pin);
- }
- }
- esp_rom_gpio_pad_unhold(iopin->pin);
- }
- }
- if (!usb->use_external_phy) {
- gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
- gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
- }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
- strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
- strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
- return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
-
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
deleted file mode 100644
index 8996ff9dc..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
- "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
- "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h b/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
deleted file mode 100644
index a9dffc325..000000000
--- a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
- /**
- * @brief Set RGB for a specific pixel
- *
- * @param strip: LED strip
- * @param index: index of pixel to set
- * @param red: red part of color
- * @param green: green part of color
- * @param blue: blue part of color
- *
- * @return
- * - ESP_OK: Set RGB for a specific pixel successfully
- * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
- * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
- */
- esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
- /**
- * @brief Refresh memory colors to LEDs
- *
- * @param strip: LED strip
- * @param timeout_ms: timeout value for refreshing task
- *
- * @return
- * - ESP_OK: Refresh successfully
- * - ESP_ERR_TIMEOUT: Refresh failed because of timeout
- * - ESP_FAIL: Refresh failed because some other error occurred
- *
- * @note:
- * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
- */
- esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
- /**
- * @brief Clear LED strip (turn off all LEDs)
- *
- * @param strip: LED strip
- * @param timeout_ms: timeout value for clearing task
- *
- * @return
- * - ESP_OK: Clear LEDs successfully
- * - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
- * - ESP_FAIL: Clear LEDs failed because some other error occurred
- */
- esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
- /**
- * @brief Free LED strip resources
- *
- * @param strip: LED strip
- *
- * @return
- * - ESP_OK: Free resources successfully
- * - ESP_FAIL: Free resources failed because error occurred
- */
- esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
- uint32_t max_leds; /*!< Maximum LEDs in a single strip */
- led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
- { \
- .max_leds = number, \
- .dev = dev_hdl, \
- }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-* LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100644
index fd1746cad..000000000
--- a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include
-#include
-#include
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...) \
- do \
- { \
- if (!(a)) \
- { \
- ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
- ret = ret_value; \
- goto goto_tag; \
- } \
- } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
- led_strip_t parent;
- rmt_channel_t rmt_channel;
- uint32_t strip_len;
- uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Convert RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
- size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
- if (src == NULL || dest == NULL) {
- *translated_size = 0;
- *item_num = 0;
- return;
- }
- const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
- const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
- size_t size = 0;
- size_t num = 0;
- uint8_t *psrc = (uint8_t *)src;
- rmt_item32_t *pdest = dest;
- while (size < src_size && num < wanted_num) {
- for (int i = 0; i < 8; i++) {
- // MSB first
- if (*psrc & (1 << (7 - i))) {
- pdest->val = bit1.val;
- } else {
- pdest->val = bit0.val;
- }
- num++;
- pdest++;
- }
- size++;
- psrc++;
- }
- *translated_size = size;
- *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
- esp_err_t ret = ESP_OK;
- ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
- STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
- uint32_t start = index * 3;
- // In thr order of GRB
- ws2812->buffer[start + 0] = green & 0xFF;
- ws2812->buffer[start + 1] = red & 0xFF;
- ws2812->buffer[start + 2] = blue & 0xFF;
- return ESP_OK;
-err:
- return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
- esp_err_t ret = ESP_OK;
- ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
- STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
- "transmit RMT samples failed", err, ESP_FAIL);
- return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
- return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
- ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
- // Write zero to turn off all leds
- memset(ws2812->buffer, 0, ws2812->strip_len * 3);
- return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
- ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
- free(ws2812);
- return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
- led_strip_t *ret = NULL;
- STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
- // 24 bits per led
- uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
- ws2812_t *ws2812 = calloc(1, ws2812_size);
- STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
- uint32_t counter_clk_hz = 0;
- STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
- "get rmt counter clock failed", err, NULL);
- // ns -> ticks
- float ratio = (float)counter_clk_hz / 1e9;
- ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
- ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
- ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
- ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
- // set ws2812 to rmt adapter
- rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
- ws2812->rmt_channel = (rmt_channel_t)config->dev;
- ws2812->strip_len = config->max_leds;
-
- ws2812->parent.set_pixel = ws2812_set_pixel;
- ws2812->parent.refresh = ws2812_refresh;
- ws2812->parent.clear = ws2812_clear;
- ws2812->parent.del = ws2812_del;
-
- return &ws2812->parent;
-err:
- return ret;
-}
diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake
deleted file mode 100644
index 511dd58bb..000000000
--- a/hw/bsp/esp32s3/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s3)
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/family.mk b/hw/bsp/esp32s3/family.mk
deleted file mode 100644
index cf153ffc2..000000000
--- a/hw/bsp/esp32s3/family.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#DEPS_SUBMODULES +=
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
- idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s3 build
-
-build: all
-
-clean:
- idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
- if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
- if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
- idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xc47e5767
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
- @echo CREATE $@
- $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
new file mode 100644
index 000000000..8209e8747
--- /dev/null
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -0,0 +1,8 @@
+set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../")
+
+idf_component_register(SRCS family.c
+ INCLUDE_DIRS "." ${BOARD} ${hw_dir}
+ PRIV_REQUIRES "driver"
+ REQUIRES led_strip src tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
similarity index 99%
rename from hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
rename to hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
index 43e00901d..1f8dc2cea 100644
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
similarity index 99%
rename from hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
rename to hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
index 16e30b685..084a7aaf2 100644
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
new file mode 100644
index 000000000..44ff11aa0
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
@@ -0,0 +1,51 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN 45
+
+#define BUTTON_PIN 0
+#define BUTTON_STATE_ACTIVE 0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN 15
+#define MAX3421_INTR_PIN 14
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.cmake b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/hw/bsp/espressif/boards/espressif_addax_1/board.h
similarity index 99%
rename from hw/bsp/esp32s3/boards/espressif_addax_1/board.h
rename to hw/bsp/espressif/boards/espressif_addax_1/board.h
index fff24ba44..d4690f732 100644
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
similarity index 87%
rename from hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
rename to hw/bsp/espressif/boards/espressif_kaluga_1/board.h
index 6bb44f76d..613e6ae0c 100644
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -37,6 +37,14 @@
#define BUTTON_PIN 0
#define BUTTON_STATE_ACTIVE 0
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN 15
+#define MAX3421_INTR_PIN 14
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
similarity index 99%
rename from hw/bsp/esp32s2/boards/espressif_saola_1/board.h
rename to hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
index f450b9a8b..e068efef9 100644
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
similarity index 99%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
rename to hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
index c7940c56e..fe33b5c43 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
new file mode 100644
index 000000000..9bac46d64
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
similarity index 87%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
rename to hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index c7940c56e..4b4151e72 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -36,6 +36,14 @@
#define BUTTON_PIN 0
#define BUTTON_STATE_ACTIVE 0
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI2_HOST
+#define MAX3421_SCK_PIN 36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN 15
+#define MAX3421_INTR_PIN 14
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.cmake b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/espressif_saola_1/board.h
similarity index 88%
rename from hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
rename to hw/bsp/espressif/boards/espressif_saola_1/board.h
index 49a2474bc..e068efef9 100644
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -31,7 +31,9 @@
extern "C" {
#endif
-#define NEOPIXEL_PIN 45
+// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
+// however earlier revision v1.1 WS2812 is connected to GPIO 17
+#define NEOPIXEL_PIN 18
#define BUTTON_PIN 0
#define BUTTON_STATE_ACTIVE 0
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
new file mode 100644
index 000000000..912ca5f35
--- /dev/null
+++ b/hw/bsp/espressif/boards/family.c
@@ -0,0 +1,299 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+#include "esp_rom_gpio.h"
+#include "hal/gpio_ll.h"
+#include "hal/usb_hal.h"
+#include "soc/usb_periph.h"
+
+#include "driver/rmt.h"
+#include "driver/uart.h"
+
+#if ESP_IDF_VERSION_MAJOR > 4
+ #include "esp_private/periph_ctrl.h"
+#else
+
+ #include "driver/periph_ctrl.h"
+
+#endif
+
+// Note; current code use UART0 can cause device to reset while monitoring
+#define USE_UART 0
+#define UART_ID UART_NUM_0
+
+#ifdef NEOPIXEL_PIN
+
+#include "led_strip.h"
+
+static led_strip_t* strip;
+#endif
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
+#include "driver/spi_master.h"
+
+static void max3421_init(void);
+
+#endif
+
+static void configure_pins(usb_hal_context_t* usb);
+
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
+
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void) {
+#if USE_UART
+ // uart init
+ uart_config_t uart_config = {
+ .baud_rate = 115200,
+ .data_bits = UART_DATA_8_BITS,
+ .parity = UART_PARITY_DISABLE,
+ .stop_bits = UART_STOP_BITS_1,
+ .flow_ctrl = UART_HW_FLOWCTRL_DISABLE
+ };
+ uart_driver_install(UART_ID, 1024, 0, 0, NULL, 0);
+ uart_param_config(UART_ID, &uart_config);
+#endif
+
+#ifdef NEOPIXEL_PIN
+ #ifdef NEOPIXEL_POWER_PIN
+ gpio_reset_pin(NEOPIXEL_POWER_PIN);
+ gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
+ gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
+ #endif
+
+ // WS2812 Neopixel driver with RMT peripheral
+ rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
+ config.clk_div = 2; // set counter clock to 40MHz
+
+ rmt_config(&config);
+ rmt_driver_install(config.channel, 0, 0);
+
+ led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
+ strip = led_strip_new_rmt_ws2812(&strip_config);
+ strip->clear(strip, 100); // off led
+#endif
+
+ // Button
+ esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
+ gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
+ gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
+
+ // USB Controller Hal init
+ periph_module_reset(PERIPH_USB_MODULE);
+ periph_module_enable(PERIPH_USB_MODULE);
+
+ usb_hal_context_t hal = {
+ .use_external_phy = false // use built-in PHY
+ };
+ usb_hal_init(&hal);
+ configure_pins(&hal);
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+ max3421_init();
+#endif
+}
+
+static void configure_pins(usb_hal_context_t* usb) {
+ /* usb_periph_iopins currently configures USB_OTG as USB Device.
+ * Introduce additional parameters in usb_hal_context_t when adding support
+ * for USB Host. */
+ for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+ if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
+ esp_rom_gpio_pad_select_gpio(iopin->pin);
+ if (iopin->is_output) {
+ esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
+ } else {
+ esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
+#if ESP_IDF_VERSION_MAJOR > 4
+ if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
+#else
+ if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
+#endif
+ {
+ gpio_ll_input_enable(&GPIO, iopin->pin);
+ }
+ }
+ esp_rom_gpio_pad_unhold(iopin->pin);
+ }
+ }
+
+ if (!usb->use_external_phy) {
+ gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
+ gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
+ }
+}
+
+// Turn LED on or off
+void board_led_write(bool state) {
+#ifdef NEOPIXEL_PIN
+ strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
+ strip->refresh(strip, 100);
+#endif
+}
+
+// Get the current state of button
+// a '1' means active (pressed), a '0' means inactive.
+uint32_t board_button_read(void) {
+ return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
+}
+
+// Get characters from UART
+int board_uart_read(uint8_t* buf, int len) {
+#if USE_UART
+ return uart_read_bytes(UART_ID, buf, len, 0);
+#else
+ return -1;
+#endif
+}
+
+// Send characters to UART
+int board_uart_write(void const* buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_getchar(void) {
+ uint8_t c = 0;
+ return board_uart_read(&c, 1) > 0 ? (int) c : (-1);
+}
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static spi_device_handle_t max3421_spi;
+SemaphoreHandle_t max3421_intr_sem;
+
+static void IRAM_ATTR max3421_isr_handler(void* arg) {
+ (void) arg; // arg is gpio num
+ gpio_set_level(13, 1);
+
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
+ if (xHigherPriorityTaskWoken) {
+ portYIELD_FROM_ISR();
+ }
+
+ gpio_set_level(13, 0);
+}
+
+static void max3421_intr_task(void* param) {
+ (void) param;
+
+ while (1) {
+ xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
+ tuh_int_handler(BOARD_TUH_RHPORT, false);
+ }
+}
+
+static void max3421_init(void) {
+ // CS pin
+ gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
+ gpio_set_level(MAX3421_CS_PIN, 1);
+
+ // SPI
+ spi_bus_config_t buscfg = {
+ .miso_io_num = MAX3421_MISO_PIN,
+ .mosi_io_num = MAX3421_MOSI_PIN,
+ .sclk_io_num = MAX3421_SCK_PIN,
+ .quadwp_io_num = -1,
+ .quadhd_io_num = -1,
+ .data4_io_num = -1,
+ .data5_io_num = -1,
+ .data6_io_num = -1,
+ .data7_io_num = -1,
+ .max_transfer_sz = 1024
+ };
+ ESP_ERROR_CHECK(spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
+
+ spi_device_interface_config_t max3421_cfg = {
+ .mode = 0,
+ .clock_speed_hz = 26000000,
+ .spics_io_num = -1, // manual control CS
+ .queue_size = 1
+ };
+ ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
+
+ // debug
+ gpio_set_direction(13, GPIO_MODE_OUTPUT);
+ gpio_set_level(13, 0);
+
+ // Interrupt pin
+ max3421_intr_sem = xSemaphoreCreateBinary();
+ xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
+
+ gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+ gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+
+ gpio_install_isr_service(0);
+ gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+}
+
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+ (void) rhport;
+ if (enabled) {
+ gpio_intr_enable(MAX3421_INTR_PIN);
+ } else {
+ gpio_intr_disable(MAX3421_INTR_PIN);
+ }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+ (void) rhport;
+ gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+ (void) rhport;
+
+ if (tx_buf == NULL) {
+ // fifo read, transmit rx_buf as dummy
+ tx_buf = rx_buf;
+ }
+
+ // length in bits
+ size_t const len_bits = xfer_bytes << 3;
+
+ spi_transaction_t xact = {
+ .length = len_bits,
+ .rxlength = rx_buf ? len_bits : 0,
+ .tx_buffer = tx_buf,
+ .rx_buffer = rx_buf
+ };
+
+ ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact));
+ return true;
+}
+
+#endif
diff --git a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
similarity index 99%
rename from hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
rename to hw/bsp/espressif/components/led_strip/CMakeLists.txt
index 6d0fcbc86..8266c5a1c 100644
--- a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
+++ b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
@@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}"
PRIV_INCLUDE_DIRS ""
PRIV_REQUIRES "driver"
REQUIRES "")
-
diff --git a/hw/bsp/esp32s2/components/led_strip/include/led_strip.h b/hw/bsp/espressif/components/led_strip/include/led_strip.h
similarity index 100%
rename from hw/bsp/esp32s2/components/led_strip/include/led_strip.h
rename to hw/bsp/espressif/components/led_strip/include/led_strip.h
diff --git a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
similarity index 100%
rename from hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
rename to hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
new file mode 100644
index 000000000..abe276910
--- /dev/null
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -0,0 +1,73 @@
+idf_build_get_property(target IDF_TARGET)
+
+set(srcs)
+set(includes_public)
+set(compile_options)
+set(tusb_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../../../src")
+
+if(target STREQUAL "esp32s3")
+ set(tusb_mcu "OPT_MCU_ESP32S3")
+elseif(target STREQUAL "esp32s2")
+ set(tusb_mcu "OPT_MCU_ESP32S2")
+else()
+ # CONFIG_TINYUSB dependency has been guaranteed by Kconfig logic,
+ # So it's not possible that cmake goes here
+ message(FATAL_ERROR "TinyUSB is not support on ${target}.")
+ return()
+endif()
+
+list(APPEND compile_definitions
+ CFG_TUSB_MCU=${tusb_mcu}
+ CFG_TUSB_OS=OPT_OS_FREERTOS
+ )
+
+list(APPEND srcs
+ # common
+ ${tusb_src}/tusb.c
+ ${tusb_src}/common/tusb_fifo.c
+ # device
+ ${tusb_src}/device/usbd.c
+ ${tusb_src}/device/usbd_control.c
+ ${tusb_src}/class/audio/audio_device.c
+ ${tusb_src}/class/cdc/cdc_device.c
+ ${tusb_src}/class/dfu/dfu_device.c
+ ${tusb_src}/class/dfu/dfu_rt_device.c
+ ${tusb_src}/class/hid/hid_device.c
+ ${tusb_src}/class/midi/midi_device.c
+ ${tusb_src}/class/msc/msc_device.c
+ ${tusb_src}/class/net/ecm_rndis_device.c
+ ${tusb_src}/class/net/ncm_device.c
+ ${tusb_src}/class/usbtmc/usbtmc_device.c
+ ${tusb_src}/class/vendor/vendor_device.c
+ ${tusb_src}/class/video/video_device.c
+ ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c
+ # host
+ ${tusb_src}/host/usbh.c
+ ${tusb_src}/host/hub.c
+ ${tusb_src}/class/cdc/cdc_host.c
+ ${tusb_src}/class/hid/hid_host.c
+ ${tusb_src}/class/msc/msc_host.c
+ ${tusb_src}/class/vendor/vendor_host.c
+ )
+
+# use max3421 as host controller
+if (MAX3421_HOST STREQUAL "1")
+ list(APPEND srcs ${tusb_src}/portable/analog/max3421/hcd_max3421.c)
+ list(APPEND compile_definitions CFG_TUH_MAX3421=1)
+endif ()
+
+if (DEFINED LOG)
+ list(APPEND compile_definitions CFG_TUSB_DEBUG=${LOG})
+ if (LOG STREQUAL "4")
+ # no inline for debug level 4
+ list(APPEND compile_definitions TU_ATTR_ALWAYS_INLINE=)
+ endif ()
+endif()
+
+idf_component_register(SRCS ${srcs}
+ INCLUDE_DIRS ${tusb_src}
+ REQUIRES src
+ )
+
+target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
new file mode 100644
index 000000000..92a9bcb04
--- /dev/null
+++ b/hw/bsp/espressif/family.cmake
@@ -0,0 +1,15 @@
+cmake_minimum_required(VERSION 3.5)
+
+# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
+include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
+
+if(IDF_TARGET STREQUAL "esp32s2")
+ set(FAMILY_MCUS ESP32S2)
+elseif(IDF_TARGET STREQUAL "esp32s3")
+ set(FAMILY_MCUS ESP32S3)
+endif()
+
+# Add example src and bsp directories
+set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/espressif/family.mk
similarity index 62%
rename from hw/bsp/esp32s2/family.mk
rename to hw/bsp/espressif/family.mk
index b95098e15..0dc21b8eb 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/espressif/family.mk
@@ -1,9 +1,21 @@
#DEPS_SUBMODULES +=
+UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
+UF2_FAMILY_ID_esp32s3 = 0xc47e5767
+
+BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
+ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
+ IDF_TARGET = esp32s2
+else
+ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
+ IDF_TARGET = esp32s3
+endif
+endif
+
.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
all:
- idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s2 build
+ idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
build: all
@@ -17,8 +29,6 @@ clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-com
uf2: $(BUILD)/$(PROJECT).uf2
-UF2_FAMILY_ID = 0xbfdd4eee
$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
@echo CREATE $@
- $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
+ $(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index 4aa1e153b..86d454f8e 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re
## TODO
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX` high speed MCU check in examples (maybe we should extract the logic?)
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
index 238ac796d..0ef9a1700 100644
--- a/hw/bsp/f1c100s/board.h
+++ b/hw/bsp/f1c100s/board.h
@@ -1 +1 @@
-// Nothing valuable here
\ No newline at end of file
+// Nothing valuable here
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
index 5fe26a9ea..9062483b0 100644
--- a/hw/bsp/f1c100s/board.mk
+++ b/hw/bsp/f1c100s/board.mk
@@ -32,7 +32,7 @@ SRC_C += \
$(MCU_DIR)/machine/sys-spi-flash.c \
$(MCU_DIR)/machine/f1c100s-intc.c \
$(MCU_DIR)/lib/malloc.c \
- $(MCU_DIR)/lib/printf.c
+ $(MCU_DIR)/lib/printf.c
SRC_S += \
$(MCU_DIR)/machine/start.S \
@@ -47,6 +47,6 @@ INC += \
flash: flash-xfel
exec: $(BUILD)/$(PROJECT).bin
- xfel ddr
+ xfel ddr
xfel write 0x80000000 $<
- xfel exec 0x80000000
\ No newline at end of file
+ xfel exec 0x80000000
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
index d45072ecb..272b756f2 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/f1c100s.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -28,7 +28,7 @@
#include
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
extern void sys_uart_putc(char c);
@@ -125,6 +125,6 @@ static void timer_init(void) {
f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
}
-#else
+#else
static void timer_init(void) { }
#endif
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 601cd54f5..9c625b58e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,142 +1,457 @@
-if (NOT TARGET _family_support_marker)
- add_library(_family_support_marker INTERFACE)
+include_guard(GLOBAL)
- if (NOT FAMILY)
- message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
+include(CMakePrintHelpers)
+
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
+get_filename_component(TOP ${TOP} ABSOLUTE)
+
+# Default to gcc
+if (NOT DEFINED TOOLCHAIN)
+ set(TOOLCHAIN gcc)
+endif ()
+
+# FAMILY not defined, try to detect it from BOARD
+if (NOT DEFINED FAMILY)
+ if (NOT DEFINED BOARD)
+ message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, espressif).
+ You can do this via -DFAMILY=xxx on the cmake command line")
+ endif ()
+
+ # Find path contains BOARD
+ file(GLOB BOARD_PATH LIST_DIRECTORIES true
+ RELATIVE ${TOP}/hw/bsp
+ ${TOP}/hw/bsp/*/boards/${BOARD}
+ )
+ if (NOT BOARD_PATH)
+ message(FATAL_ERROR "Could not detect FAMILY from BOARD=${BOARD}")
+ endif ()
+
+ # replace / with ; so that we can get the first element as FAMILY
+ string(REPLACE "/" ";" BOARD_PATH ${BOARD_PATH})
+ list(GET BOARD_PATH 0 FAMILY)
+endif ()
+
+if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+ message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+endif()
+
+if (NOT FAMILY STREQUAL rp2040)
+ # enable LTO if supported skip rp2040
+ include(CheckIPOSupported)
+ check_ipo_supported(RESULT IPO_SUPPORTED)
+ cmake_print_variables(IPO_SUPPORTED)
+ if (IPO_SUPPORTED)
+ set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+ endif()
+endif()
+
+set(WARNING_FLAGS_GNU
+ -Wall
+ -Wextra
+ -Werror
+ -Wfatal-errors
+ -Wdouble-promotion
+ -Wstrict-prototypes
+ -Wstrict-overflow
+ -Werror-implicit-function-declaration
+ -Wfloat-equal
+ -Wundef
+ -Wshadow
+ -Wwrite-strings
+ -Wsign-compare
+ -Wmissing-format-attribute
+ -Wunreachable-code
+ -Wcast-align
+ -Wcast-function-type
+ -Wcast-qual
+ -Wnull-dereference
+ -Wuninitialized
+ -Wunused
+ -Wreturn-type
+ -Wredundant-decls
+ )
+
+set(WARNINGS_FLAGS_IAR "")
+
+
+# Filter example based on only.txt and skip.txt
+function(family_filter RESULT DIR)
+ get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+
+ if (EXISTS "${DIR}/only.txt")
+ file(READ "${DIR}/only.txt" ONLYS)
+ # Replace newlines with semicolon so that it is treated as a list by CMake
+ string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
+
+ # For each mcu
+ foreach(MCU IN LISTS FAMILY_MCUS)
+ # For each line in only.txt
+ foreach(_line ${ONLYS_LINES})
+ # If mcu:xxx exists for this mcu or board:xxx then include
+ if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
+ set(${RESULT} 1 PARENT_SCOPE)
+ return()
+ endif()
+ endforeach()
+ endforeach()
+
+ # Didn't find it in only file so don't build
+ set(${RESULT} 0 PARENT_SCOPE)
+
+ elseif (EXISTS "${DIR}/skip.txt")
+ file(READ "${DIR}/skip.txt" SKIPS)
+ # Replace newlines with semicolon so that it is treated as a list by CMake
+ string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
+
+ # For each mcu
+ foreach(MCU IN LISTS FAMILY_MCUS)
+ # For each line in only.txt
+ foreach(_line ${SKIPS_LINES})
+ # If mcu:xxx exists for this mcu then skip
+ if (${_line} STREQUAL "mcu:${MCU}")
+ set(${RESULT} 0 PARENT_SCOPE)
+ return()
+ endif()
+ endforeach()
+ endforeach()
+
+ # Didn't find in skip file so build
+ set(${RESULT} 1 PARENT_SCOPE)
+ else()
+
+ # Didn't find skip or only file so build
+ set(${RESULT} 1 PARENT_SCOPE)
+ endif()
+endfunction()
+
+
+function(family_add_subdirectory DIR)
+ family_filter(SHOULD_ADD "${DIR}")
+ if (SHOULD_ADD)
+ add_subdirectory(${DIR})
+ endif()
+endfunction()
+
+
+function(family_get_project_name OUTPUT_NAME DIR)
+ get_filename_component(SHORT_NAME ${DIR} NAME)
+ set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
+endfunction()
+
+
+function(family_initialize_project PROJECT DIR)
+ # set output suffix to .elf (skip espressif and rp2040)
+ if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040")
+ set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
+ endif()
+
+ family_filter(ALLOWED "${DIR}")
+ if (NOT ALLOWED)
+ get_filename_component(SHORT_NAME ${DIR} NAME)
+ message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
+ endif()
+endfunction()
+
+
+#-------------------------------------------------------------
+# Common Target Configure
+# Most families use these settings except rp2040 and espressif
+#-------------------------------------------------------------
+
+# Add RTOS to example
+function(family_add_rtos TARGET RTOS)
+ if (RTOS STREQUAL "freertos")
+ # freertos config
+ if (NOT TARGET freertos_config)
+ add_library(freertos_config INTERFACE)
+ target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig)
+ # add board definition to freertos_config mostly for SystemCoreClock
+ target_link_libraries(freertos_config INTERFACE board_${BOARD})
endif()
- if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
- message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+ # freertos kernel
+ if (NOT TARGET freertos_kernel)
+ add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+ endif ()
+
+ target_link_libraries(${TARGET} PUBLIC freertos_kernel)
+ endif ()
+endfunction()
+
+
+# Add common configuration to example
+function(family_configure_common TARGET RTOS)
+ family_add_rtos(${TARGET} ${RTOS})
+
+ string(TOUPPER ${BOARD} BOARD_UPPER)
+ string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER})
+ target_compile_definitions(${TARGET} PUBLIC
+ BOARD_${BOARD_UPPER}
+ )
+
+ # run size after build
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${CMAKE_SIZE} $
+ )
+
+ # Add warnings flags
+ target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}})
+
+ # Generate linker map file
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map")
+ endif()
+
+ # ETM Trace option
+ if (TRACE_ETM STREQUAL "1")
+ target_compile_definitions(${TARGET} PUBLIC TRACE_ETM)
+ endif ()
+
+ # LOGGER option
+ if (DEFINED LOGGER)
+ target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
+
+ # Add segger rtt to example
+ if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+ if (NOT TARGET segger_rtt)
+ add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
+ target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+ target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
+ endif()
+ target_link_libraries(${TARGET} PUBLIC segger_rtt)
+ endif ()
+ endif ()
+endfunction()
+
+
+# Add tinyusb to example
+function(family_add_tinyusb TARGET OPT_MCU RTOS)
+ # tinyusb target is built for each example since it depends on example's tusb_config.h
+ set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+ add_library(${TARGET}-tinyusb_config INTERFACE)
+
+ # path to tusb_config.h
+ target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src)
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU})
+
+ if (DEFINED LOG)
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
+ if (LOG STREQUAL "4")
+ # no inline for debug level 4
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=)
+ endif ()
+ endif()
+
+ if (RTOS STREQUAL "freertos")
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS)
+ endif ()
+
+ # tinyusb's CMakeList.txt
+ add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+ if (RTOS STREQUAL "freertos")
+ # link tinyusb with freeRTOS kernel
+ target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel)
+ endif ()
+
+ # use max3421 as host controller
+ if (MAX3421_HOST STREQUAL "1")
+ target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUH_MAX3421=1)
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/analog/max3421/hcd_max3421.c
+ )
+ endif ()
+
+endfunction()
+
+
+# Add bin/hex output
+function(family_add_bin_hex TARGET)
+ add_custom_command(TARGET ${TARGET} POST_BUILD
+ COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin
+ COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex
+ VERBATIM)
+endfunction()
+
+
+#----------------------------------
+# Example Target Configure (Default rule)
+# These function can be redefined in FAMILY/family.cmake
+#----------------------------------
+
+function(family_configure_example TARGET RTOS)
+ # empty function, should be redefined in FAMILY/family.cmake
+endfunction()
+
+# Configure device example with RTOS
+function(family_configure_device_example TARGET RTOS)
+ family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+
+# Configure host example with RTOS
+function(family_configure_host_example TARGET RTOS)
+ family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+
+# Configure host + device example with RTOS
+function(family_configure_dual_usb_example TARGET RTOS)
+ family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+function(family_example_missing_dependency TARGET DEPENDENCY)
+ message(WARNING "${DEPENDENCY} submodule needed by ${TARGET} not found, please run 'python tools/get_deps.py ${DEPENDENCY}' to fetch it")
+endfunction()
+
+#----------------------------------
+# RPI specific: refactor later
+#----------------------------------
+function(family_add_default_example_warnings TARGET)
+ target_compile_options(${TARGET} PUBLIC
+ -Wall
+ -Wextra
+ -Werror
+ -Wfatal-errors
+ -Wdouble-promotion
+ -Wfloat-equal
+ # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468
+ #-Wshadow
+ -Wwrite-strings
+ -Wsign-compare
+ -Wmissing-format-attribute
+ -Wunreachable-code
+ -Wcast-align
+ -Wcast-qual
+ -Wnull-dereference
+ -Wuninitialized
+ -Wunused
+ -Wredundant-decls
+ #-Wstrict-prototypes
+ #-Werror-implicit-function-declaration
+ #-Wundef
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+ target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
endif()
- function(family_filter RESULT DIR)
- get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-
- if (EXISTS "${DIR}/only.txt")
- file(READ "${DIR}/only.txt" ONLYS)
- # Replace newlines with semicolon so that it is treated as a list by CMake
- string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
- # For each mcu
- foreach(MCU IN LISTS FAMILY_MCUS)
- # For each line in only.txt
- foreach(_line ${ONLYS_LINES})
- # If mcu:xxx exists for this mcu then include
- if (${_line} STREQUAL "mcu:${MCU}")
- set(${RESULT} 1 PARENT_SCOPE)
- return()
- endif()
- endforeach()
- endforeach()
-
- # Didn't find it in only file so don't build
- set(${RESULT} 0 PARENT_SCOPE)
-
- elseif (EXISTS "${DIR}/skip.txt")
- file(READ "${DIR}/skip.txt" SKIPS)
- # Replace newlines with semicolon so that it is treated as a list by CMake
- string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
- # For each mcu
- foreach(MCU IN LISTS FAMILY_MCUS)
- # For each line in only.txt
- foreach(_line ${SKIPS_LINES})
- # If mcu:xxx exists for this mcu then skip
- if (${_line} STREQUAL "mcu:${MCU}")
- set(${RESULT} 0 PARENT_SCOPE)
- return()
- endif()
- endforeach()
- endforeach()
-
- # Didn't find in skip file so build
- set(${RESULT} 1 PARENT_SCOPE)
-
- else()
-
- # Didn't find skip or only file so build
- set(${RESULT} 1 PARENT_SCOPE)
-
- endif()
-
- endfunction()
-
- function(family_add_subdirectory DIR)
- family_filter(SHOULD_ADD "${DIR}")
- if (SHOULD_ADD)
- add_subdirectory(${DIR})
- endif()
- endfunction()
-
- function(family_get_project_name OUTPUT_NAME DIR)
- get_filename_component(SHORT_NAME ${DIR} NAME)
- set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
- endfunction()
-
- function(family_initialize_project PROJECT DIR)
- family_filter(ALLOWED "${DIR}")
- if (NOT ALLOWED)
- get_filename_component(SHORT_NAME ${DIR} NAME)
- message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
- endif()
- endfunction()
-
- function(family_add_default_example_warnings TARGET)
- target_compile_options(${TARGET} PUBLIC
- -Wall
- -Wextra
- -Werror
- -Wfatal-errors
- -Wdouble-promotion
- -Wfloat-equal
- -Wshadow
- -Wwrite-strings
- -Wsign-compare
- -Wmissing-format-attribute
- -Wunreachable-code
- -Wcast-align
- -Wcast-qual
- -Wnull-dereference
- -Wuninitialized
- -Wunused
- -Wredundant-decls
- #-Wstrict-prototypes
- #-Werror-implicit-function-declaration
- #-Wundef
- )
-
- if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
- # GCC 10
- if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
- target_compile_options(${TARGET} PUBLIC -Wconversion)
- endif()
-
- # GCC 8
- if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
- target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
- endif()
-
- # GCC 6
- if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
- target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
- endif()
- endif()
- endfunction()
-
- # configure an executable target to link to tinyusb in device mode, and add the board implementation
- function(family_configure_device_example TARGET)
- # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
- endfunction()
-
- # configure an executable target to link to tinyusb in host mode, and add the board implementation
- function(family_configure_host_example TARGET)
- # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
- endfunction()
-
- include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-
- if (NOT FAMILY_MCUS)
- set(FAMILY_MCUS ${FAMILY})
+ # GCC 10
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+ target_compile_options(${TARGET} PUBLIC -Wconversion)
endif()
- # save it in case of re-inclusion
- set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
-endif()
\ No newline at end of file
+ # GCC 8
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+ target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
+ endif()
+
+ # GCC 6
+ if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
+ target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
+ endif()
+ endif()
+endfunction()
+
+#----------------------------------
+# Flashing target
+#----------------------------------
+
+# Add flash jlink target
+function(family_flash_jlink TARGET)
+ if (NOT DEFINED JLINKEXE)
+ set(JLINKEXE JLinkExe)
+ endif ()
+
+ file(GENERATE
+ OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+ CONTENT "halt
+loadfile $
+r
+go
+exit"
+ )
+
+ add_custom_target(${TARGET}-jlink
+ DEPENDS ${TARGET}
+ COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+ )
+endfunction()
+
+
+# Add flash stlink target
+function(family_flash_stlink TARGET)
+ if (NOT DEFINED STM32_PROGRAMMER_CLI)
+ set(STM32_PROGRAMMER_CLI STM32_Programmer_CLI)
+ endif ()
+
+ add_custom_target(${TARGET}-stlink
+ DEPENDS ${TARGET}
+ COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $ --go
+ )
+endfunction()
+
+
+# Add flash pycod target
+function(family_flash_pyocd TARGET)
+ if (NOT DEFINED PYOC)
+ set(PYOCD pyocd)
+ endif ()
+
+ add_custom_target(${TARGET}-pyocd
+ DEPENDS ${TARGET}
+ COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $
+ )
+endfunction()
+
+
+# Add flash using NXP's LinkServer (redserver)
+# https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+function(family_flash_nxplink TARGET)
+ if (NOT DEFINED LINKSERVER)
+ set(LINKSERVER LinkServer)
+ endif ()
+
+ # LinkServer has a bug that can only execute with full path otherwise it throws:
+ # realpath error: No such file or directory
+ execute_process(COMMAND which ${LINKSERVER} OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+
+ add_custom_target(${TARGET}-nxplink
+ DEPENDS ${TARGET}
+ COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $
+ )
+endfunction()
+
+
+function(family_flash_dfu_util TARGET OPTION)
+ if (NOT DEFINED DFU_UTIL)
+ set(DFU_UTIL dfu-util)
+ endif ()
+
+ add_custom_target(${TARGET}-dfu-util
+ DEPENDS ${TARGET}
+ COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $/${TARGET}.bin
+ VERBATIM
+ )
+endfunction()
+
+#----------------------------------
+# Family specific
+#----------------------------------
+
+# family specific: can override above functions
+include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+
+if (NOT FAMILY_MCUS)
+ set(FAMILY_MCUS ${FAMILY})
+endif()
+
+# if use max3421 as host controller, expand FAMILY_MCUS to include max3421
+if (MAX3421_HOST STREQUAL "1")
+ set(FAMILY_MCUS ${FAMILY_MCUS} MAX3421)
+endif ()
+
+# save it in case of re-inclusion
+set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
diff --git a/hw/bsp/fomu/boards/fomu/board.mk b/hw/bsp/fomu/boards/fomu/board.mk
index 8ced11412..b5545c89a 100644
--- a/hw/bsp/fomu/boards/fomu/board.mk
+++ b/hw/bsp/fomu/boards/fomu/board.mk
@@ -1 +1 @@
-# place holder
\ No newline at end of file
+# place holder
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index 165535c6b..d0b819120 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -19,12 +19,12 @@ INC += \
$(TOP)/$(FAMILY_PATH)/include
# For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
# flash using dfu-util
$(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
@echo "Create $@"
python $(TOP)/hw/bsp/$(BOARD)/dfu.py -b $^ -D 0x1209:0x5bf0 $@
-
+
flash: $(BUILD)/$(PROJECT).dfu
dfu-util -D $^
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index 33c630303..d155b743d 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -26,7 +26,7 @@
#include
#include
-#include "../board.h"
+#include "../board_api.h"
#include "csr.h"
#include "irq.h"
diff --git a/hw/bsp/fomu/include/hw/common.h b/hw/bsp/fomu/include/hw/common.h
index 6a97ca2e9..b902bc4f2 100644
--- a/hw/bsp/fomu/include/hw/common.h
+++ b/hw/bsp/fomu/include/hw/common.h
@@ -30,4 +30,4 @@ static inline uint32_t csr_readl(uint32_t addr)
{
return *(volatile uint32_t *)addr;
}
-#endif /* _HW_COMMON_H_ */
\ No newline at end of file
+#endif /* _HW_COMMON_H_ */
diff --git a/hw/bsp/fomu/include/irq.h b/hw/bsp/fomu/include/irq.h
index a82218907..dc96c228d 100644
--- a/hw/bsp/fomu/include/irq.h
+++ b/hw/bsp/fomu/include/irq.h
@@ -68,4 +68,4 @@ static inline unsigned int irq_pending(void)
}
#endif
-#endif /* __IRQ_H */
\ No newline at end of file
+#endif /* __IRQ_H */
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
deleted file mode 100644
index a737eb360..000000000
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
- -DCPU_K32L2B31VLH0A \
- -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
- src/portable/nxp/khci/dcd_khci.c \
- $(MCU_DIR)/system_K32L2B31A.c \
- $(MCU_DIR)/project_template/clock_config.c \
- $(MCU_DIR)/drivers/fsl_clock.c \
- $(SDK_DIR)/drivers/gpio/fsl_gpio.c \
- $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(SDK_DIR)/CMSIS/Include \
- $(TOP)/$(SDK_DIR)/drivers/smc \
- $(TOP)/$(SDK_DIR)/drivers/common \
- $(TOP)/$(SDK_DIR)/drivers/gpio \
- $(TOP)/$(SDK_DIR)/drivers/port \
- $(TOP)/$(SDK_DIR)/drivers/lpuart \
- $(TOP)/$(MCU_DIR) \
- $(TOP)/$(MCU_DIR)/drivers \
- $(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
deleted file mode 100644
index 6a72d516b..000000000
--- a/hw/bsp/frdm_kl25z/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/nxp_sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
- -DCPU_MKL25Z128VLK4 \
- -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
- -DCFG_EXAMPLE_VIDEO_READONLY
-
-LDFLAGS += \
- -Wl,--defsym,__stack_size__=0x400 \
- -Wl,--defsym,__heap_size__=0
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
-
-MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
-
-SRC_C += \
- src/portable/nxp/khci/dcd_khci.c \
- src/portable/nxp/khci/hcd_khci.c \
- $(MCU_DIR)/system_MKL25Z4.c \
- $(MCU_DIR)/project_template/clock_config.c \
- $(MCU_DIR)/drivers/fsl_clock.c \
- $(MCU_DIR)/drivers/fsl_gpio.c \
- $(MCU_DIR)/drivers/fsl_lpsci.c
-
-INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(SDK_DIR)/CMSIS/Include \
- $(TOP)/$(MCU_DIR) \
- $(TOP)/$(MCU_DIR)/drivers \
- $(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = mkl25zl128
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 60a326d27..27d7e87bb 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -28,7 +28,7 @@
#include "drv_usb_hw.h"
#include "drv_usb_dev.h"
-#include "../board.h"
+#include "../board_api.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
@@ -44,7 +44,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
// According to GD32VF103 user manual clock tree:
// Systick clock = AHB clock / 4.
-#define TIMER_TICKS ((SystemCoreClock / 4) / 1000)
+#define TIMER_TICKS ((SystemCoreClock / 4) / 1000)
#define BUTTON_PORT GPIOA
#define BUTTON_PIN GPIO_PIN_0
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 49bacdf1b..1725559c4 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -44,7 +44,7 @@ SRC_C += \
$(LIBC_STUBS)/isatty.c \
$(LIBC_STUBS)/fstat.c \
$(LIBC_STUBS)/lseek.c \
- $(LIBC_STUBS)/read.c
+ $(LIBC_STUBS)/read.c
SRC_S += \
$(STARTUP_ASM)/startup_gd32vf103.S \
@@ -57,7 +57,7 @@ INC += \
$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
# For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
# For flash-jlink target
JLINK_IF = jtag
diff --git a/hw/bsp/gd32vf103/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c
index c2001a980..200852abf 100644
--- a/hw/bsp/gd32vf103/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103/system_gd32vf103.c
@@ -95,7 +95,7 @@ void SystemInit(void)
/* reset the RCC clock configuration to the default reset state */
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
-
+
/* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
@@ -107,7 +107,7 @@ void SystemInit(void)
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
/* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
-
+
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
RCU_CFG1 = 0x00000000U;
@@ -141,12 +141,12 @@ void SystemCoreClockUpdate(void)
case SEL_IRC8M:
SystemCoreClock = IRC8M_VALUE;
break;
-
+
/* HXTAL is selected as CK_SYS */
case SEL_HXTAL:
SystemCoreClock = HXTAL_VALUE;
break;
-
+
/* PLL is selected as CK_SYS */
case SEL_PLL:
/* PLL clock source selection, HXTAL or IRC8M/2 */
@@ -313,7 +313,7 @@ static void system_clock_72m_hxtal(void)
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
- /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
+ /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..b65d8f1f9
--- /dev/null
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+ CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+ /* Disable ADC_ACLK_EN clock gate. */
+ CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+ /* Set ADC_ACLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+ /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+ /* Set Pll3 SW clock source to use the USB1 PLL output. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Set safe value of the AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+ /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
new file mode 100644
index 000000000..752a65629
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1010_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+ .memConfig =
+ {
+ .tag = FLEXSPI_CFG_BLK_TAG,
+ .version = FLEXSPI_CFG_BLK_VERSION,
+ .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+ .csHoldTime = 3u,
+ .csSetupTime = 3u,
+ .sflashPadType = kSerialFlash_4Pads,
+ .serialClkFreq = kFlexSpiSerialClk_100MHz,
+ .sflashA1Size = 16u * 1024u * 1024u,
+ .lookupTable =
+ {
+ // Read LUTs
+ FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
+ FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+ },
+ },
+ .pageSize = 256u,
+ .sectorSize = 4u * 1024u,
+ .blockSize = 64u * 1024u,
+ .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h
new file mode 100644
index 000000000..bb5a64448
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+
+#include
+#include
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
+ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+ FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+ kFlexSpiSerialClk_30MHz = 1,
+ kFlexSpiSerialClk_50MHz = 2,
+ kFlexSpiSerialClk_60MHz = 3,
+ kFlexSpiSerialClk_75MHz = 4,
+ kFlexSpiSerialClk_80MHz = 5,
+ kFlexSpiSerialClk_100MHz = 6,
+ kFlexSpiSerialClk_120MHz = 7,
+ kFlexSpiSerialClk_133MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+ kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+ kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+ kFlexSPIReadSampleClk_LoopbackInternally = 0,
+ kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+ kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+ kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+ kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
+ kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
+ kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
+ kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
+ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
+ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+ kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+ kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
+ kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
+ kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
+ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+ kSerialFlash_1Pad = 1,
+ kSerialFlash_2Pads = 2,
+ kSerialFlash_4Pads = 4,
+ kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+ uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+ uint8_t seqId; //!< Sequence Index, valid number: 0-15
+ uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+ kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
+ kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+ kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
+ kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
+ kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
+ kDeviceConfigCmdType_Reset, //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+ uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+ uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+ uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
+ uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+ uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
+ uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
+ uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+ //! Serial NAND, need to refer to datasheet
+ uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+ uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+ //! Generic configuration, etc.
+ uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+ //! DPI/QPI/OPI switch or reset command
+ flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+ //! sequence number, [31:16] Reserved
+ uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
+ uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+ uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+ flexspi_lut_seq_t
+ configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+ uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
+ uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+ uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
+ uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+ //! details
+ uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
+ uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+ uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+ //! Chapter for more details
+ uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+ //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+ uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
+ uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
+ uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
+ uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
+ uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
+ uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
+ uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+ uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+ uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
+ uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
+ uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
+ uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+ uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+ uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+ //! busy flag is 0 when flash device is busy
+ uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
+ flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+ uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/* */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
+#define NOR_CMD_INDEX_DUMMY 6 //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+ CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+ 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+ CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+ 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+ CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+ 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+ 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ * Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+ flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+ uint32_t pageSize; //!< Page size of Serial NOR
+ uint32_t sectorSize; //!< Sector size of Serial NOR
+ uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
+ uint8_t isUniformBlockSize; //!< Sector/Block size is the same
+ uint8_t reserved0[2]; //!< Reserved for future use
+ uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
+ uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
+ uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
+ uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
+ uint32_t blockSize; //!< Block size
+ uint32_t reserve2[11]; //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
new file mode 100644
index 000000000..960fc6891
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
@@ -0,0 +1,270 @@
+/*
+** ###################################################################
+** Processors: MIMXRT1011CAE4A
+** MIMXRT1011DAE5A
+**
+** Compiler: GNU C Compiler
+** Reference manual: IMXRT1010RM Rev.0, 09/2019
+** Version: rev. 1.0, 2019-08-01
+** Build: b210709
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2021 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00
+ m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
+
+ m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
+ m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+ m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ __NCACHE_REGION_START = ORIGIN(m_data2);
+ __NCACHE_REGION_SIZE = 0;
+
+ .flash_config :
+ {
+ . = ALIGN(4);
+ __FLASH_BASE = .;
+ KEEP(* (.boot_hdr.conf)) /* flash config section */
+ . = ALIGN(4);
+ } > m_flash_config
+
+ ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
+
+ .ivt : AT(ivt_begin)
+ {
+ . = ALIGN(4);
+ KEEP(* (.boot_hdr.ivt)) /* ivt section */
+ KEEP(* (.boot_hdr.boot_data)) /* boot section */
+ KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
+ . = ALIGN(4);
+ } > m_ivt
+
+ /* The startup code goes first into internal RAM */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal RAM */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > m_data
+
+ __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+ __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(m_usb_dma_init_data)
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+ .ram_function : AT(__ram_function_flash_start)
+ {
+ . = ALIGN(32);
+ __ram_function_start__ = .;
+ *(CodeQuickAccess)
+ . = ALIGN(128);
+ __ram_function_end__ = .;
+ } > m_qacode
+
+ __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
+ .ncache.init : AT(__NDATA_ROM)
+ {
+ __noncachedata_start__ = .; /* create a global symbol at ncache data start */
+ *(NonCacheable.init)
+ . = ALIGN(4);
+ __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
+ } > m_data
+ . = __noncachedata_init_end__;
+ .ncache :
+ {
+ *(NonCacheable)
+ . = ALIGN(4);
+ __noncachedata_end__ = .; /* define a global symbol at ncache data end */
+ } > m_data
+
+ __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(m_usb_dma_noninit_data)
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
new file mode 100644
index 000000000..606ec2cfc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
@@ -0,0 +1,692 @@
+
+
+
+ MIMXRT1011xxxxx
+ MIMXRT1011DAE5A
+ MIMXRT1010-EVK
+ A
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+ true
+
+
+
+
+ 2.5.1
+
+
+
+
+ true
+
+
+
+
+ 2.0.1
+
+
+
+
+ true
+
+
+
+
+ 2.0.3
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ 0
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
new file mode 100644
index 000000000..99681ab12
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1011)
+
+set(JLINK_DEVICE MIMXRT1011xxx5A)
+set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1011DAE5A
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
index 4f21b52fa..926f45618 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
index 17dc01cd9..488a56fdc 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1011
# For flash-jlink target
-JLINK_DEVICE = MIMXRT1011DAE5A
+JLINK_DEVICE = MIMXRT1011xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1010
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
new file mode 100644
index 000000000..6cd18c8c2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
@@ -0,0 +1,351 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include "fsl_iomuxc.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+ {
+ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+ CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+ /* Disable ADC_ACLK_EN clock gate. */
+ CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+ /* Set ADC_ACLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+ /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+ /* Set Pll3 SW clock source to use the USB1 PLL output. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Set safe value of the AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+ /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
new file mode 100644
index 000000000..606ec2cfc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
@@ -0,0 +1,692 @@
+
+
+
+ MIMXRT1011xxxxx
+ MIMXRT1011DAE5A
+ MIMXRT1010-EVK
+ A
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+ true
+
+
+
+
+ 2.5.1
+
+
+
+
+ true
+
+
+
+
+ 2.0.1
+
+
+
+
+ true
+
+
+
+
+ 2.0.3
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ 0
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
new file mode 100644
index 000000000..becad46d4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1015)
+
+set(JLINK_DEVICE MIMXRT1015DAF5A)
+set(PYOCD_TARGET mimxrt1015)
+set(NXPLINK_DEVICE MIMXRT1015xxxxx:EVK-MIMXRT1015)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1015_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1015DAF5A
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
index 932ce7fd7..10d9fad07 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
new file mode 100644
index 000000000..ae1aa7fb1
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
@@ -0,0 +1,357 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1015xxxxx
+package_id: MIMXRT1015DAF5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1015-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '2'}
+- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+ {
+ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 2);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
new file mode 100644
index 000000000..2acdb16a7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
@@ -0,0 +1,100 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
new file mode 100644
index 000000000..431a59af7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
@@ -0,0 +1,576 @@
+
+
+
+ MIMXRT1015xxxxx
+ MIMXRT1015DAF5A
+ MIMXRT1015-EVK
+ B
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ N/A
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ N/A
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
new file mode 100644
index 000000000..39c94147c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT MIMXRT1021)
+
+set(JLINK_DEVICE MIMXRT1021xxx5A)
+set(PYOCD_TARGET mimxrt1020)
+set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1020_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1021DAG5A
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
index 56ed5855b..284bb08e7 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
index b15da1b67..e269c8ac5 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A
MCU_VARIANT = MIMXRT1021
# For flash-jlink target
-JLINK_DEVICE = MIMXRT1021DAG5A
+JLINK_DEVICE = MIMXRT1021xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1020
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
new file mode 100644
index 000000000..764042928
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1020-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+ {
+ .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
+ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
+ .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
+ .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
new file mode 100644
index 000000000..4ddaaed77
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
@@ -0,0 +1,597 @@
+
+
+
+ MIMXRT1021xxxxx
+ MIMXRT1021DAG5A
+ MIMXRT1020-EVK
+ A3
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ 13.0.2
+ c_array
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
new file mode 100644
index 000000000..45487d148
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1024)
+
+set(JLINK_DEVICE MIMXRT1024xxx5A)
+set(PYOCD_TARGET mimxrt1024)
+set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1024_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1024DAG5A
+ CFG_EXAMPLE_VIDEO_READONLY
+ #-Wno-error=array-bounds
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
index 152c9ab18..9100072e2 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
index 92209992d..3c325cc93 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
@@ -5,7 +5,7 @@ MCU_VARIANT = MIMXRT1024
CFLAGS += -Wno-error=array-bounds
# For flash-jlink target
-JLINK_DEVICE = MIMXRT1024DAG5A
+JLINK_DEVICE = MIMXRT1024xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1024
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
new file mode 100644
index 000000000..ba0cadafa
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1024xxxxx
+package_id: MIMXRT1024DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1024-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+ {
+ .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
+ .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
+ .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
+ .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Enet PLL. */
+ CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
new file mode 100644
index 000000000..2aa55a604
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
@@ -0,0 +1,503 @@
+
+
+
+ MIMXRT1024xxxxx
+ MIMXRT1024DAG5A
+ MIMXRT1024-EVK
+ B1
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ 13.0.2
+ c_array
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ N/A
+
+
+
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
new file mode 100644
index 000000000..1aee75b0d
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1052)
+
+set(JLINK_DEVICE MIMXRT1052xxxxB)
+set(PYOCD_TARGET mimxrt1050)
+set(NXPLINK_DEVICE MIMXRT1052xxxxB:EVK-MIMXRT1050)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbimxrt1050_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1052DVL6B
+ BOARD_TUD_RHPORT=0
+ BOARD_TUH_RHPORT=1
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
index 0472f608c..beb69bf2b 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
index 9fd229105..60aa1e28f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
@@ -1,6 +1,8 @@
CFLAGS += -DCPU_MIMXRT1052DVL6B
MCU_VARIANT = MIMXRT1052
+JLINK_DEVICE = MIMXRT1052xxxxB
+
# For flash-pyocd target
PYOCD_TARGET = mimxrt1050
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
new file mode 100644
index 000000000..9738c6350
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
@@ -0,0 +1,495 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: IMXRT1050-EVKB
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 40, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
+#endif
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* Init Usb2 PLL. */
+ CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
new file mode 100644
index 000000000..6b4264bf2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
@@ -0,0 +1,119 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
new file mode 100644
index 000000000..c0a5b5660
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
@@ -0,0 +1,1001 @@
+
+
+
+ MIMXRT1052xxxxB
+ MIMXRT1052DVL6B
+ IMXRT1050-EVKB
+ A
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
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+ true
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
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+ true
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
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+ true
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+ 13.0.2
+
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+ true
+
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+
+ INPUT
+
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+ true
+
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+ OUTPUT
+
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+ true
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+ INPUT
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+
+ true
+
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+ OUTPUT
+
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+ true
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+ true
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+ 0.0.0
+
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+ 13.0.2
+
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+ kELCDIF_CurFrameDoneInterruptEnable
+
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+
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
new file mode 100644
index 000000000..fd335cdf5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1060_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1062DVL6A
+ BOARD_TUD_RHPORT=0
+ BOARD_TUH_RHPORT=1
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
index 7fa37e33f..0f45f72e1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
index d21063c99..0317ee452 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1062xxx6A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1060
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
# flash using pyocd
flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* Init Usb2 PLL. */
+ CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
@@ -0,0 +1,1001 @@
+
+
+
+ MIMXRT1062xxxxA
+ MIMXRT1062DVL6A
+ MIMXRT1060-EVK
+ A2
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
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+ true
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
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+ true
+
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+
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+
+
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+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
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+
+ OUTPUT
+
+
+
+
+ true
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+
+ INPUT
+
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+
+ true
+
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+
+ OUTPUT
+
+
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+ true
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+ true
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+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
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+
+ kELCDIF_CurFrameDoneInterruptEnable
+
+
+
+
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+ 0.0.0
+
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+
+
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
new file mode 100644
index 000000000..cd75c5227
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1064)
+
+set(JLINK_DEVICE MIMXRT1064xxx6A)
+set(PYOCD_TARGET mimxrt1064)
+set(NXPLINK_DEVICE MIMXRT1064xxxxA:EVK-MIMXRT1064)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1064_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1064DVL6A
+ BOARD_TUD_RHPORT=0
+ BOARD_TUH_RHPORT=1
+ )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
index 5f51e91a2..37ad94eef 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
index 00b574c52..ddde419ae 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1064xxx6A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1064
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
# flash using pyocd
flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
new file mode 100644
index 000000000..778ab02f2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
@@ -0,0 +1,511 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1064xxxxA
+package_id: MIMXRT1064DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1064-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+ /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+#endif
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* Init Usb2 PLL. */
+ CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
new file mode 100644
index 000000000..5e0fc72d3
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
@@ -0,0 +1,1006 @@
+
+
+
+ MIMXRT1064xxxxA
+ MIMXRT1064DVL6A
+ MIMXRT1064-EVK
+ 1
+ ksdk2_0
+
+
+
+
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ kCSI_HsyncActiveHigh
+ kCSI_VsyncActiveLow
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ kELCDIF_CurFrameDoneInterruptEnable
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+ 0.0.0
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.cmake b/hw/bsp/imxrt/boards/teensy_40/board.cmake
new file mode 100644
index 000000000..41fdc78f5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy40_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1062DVL6A
+ BOARD_TUD_RHPORT=0
+ BOARD_TUH_RHPORT=1
+ )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h
index b3cc0a8c5..cac773442 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.h
+++ b/hw/bsp/imxrt/boards/teensy_40/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_40/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
JLINK_DEVICE = MIMXRT1062xxx6A
# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH
+# Make sure it is in your PATH
flash: $(BUILD)/$(PROJECT).hex
teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* Init Usb2 PLL. */
+ CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40.mex b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
@@ -0,0 +1,1001 @@
+
+
+
+ MIMXRT1062xxxxA
+ MIMXRT1062DVL6A
+ MIMXRT1060-EVK
+ A2
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
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+
+
+
+
+
+
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+
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+
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+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ kELCDIF_CurFrameDoneInterruptEnable
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+ 0.0.0
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
index 7929906eb..dbedc90a0 100644
--- a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include
+#include "teensy40_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.cmake b/hw/bsp/imxrt/boards/teensy_41/board.cmake
new file mode 100644
index 000000000..0fd8d528e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy41_flexspi_nor_config.c
+ )
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_MIMXRT1062DVL6A
+ BOARD_TUD_RHPORT=0
+ BOARD_TUH_RHPORT=1
+ )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h
index b0b4931c7..72c18f540 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.h
+++ b/hw/bsp/imxrt/boards/teensy_41/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_41/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
JLINK_DEVICE = MIMXRT1062xxx6A
# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH
+# Make sure it is in your PATH
flash: $(BUILD)/$(PROJECT).hex
teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+ {
+ .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+ };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Init RTC OSC clock frequency. */
+ CLOCK_SetRtcXtalFreq(32768U);
+ /* Enable 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+ /* Use free 1MHz clock output. */
+ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+ /* Set XTAL 24MHz clock frequency. */
+ CLOCK_SetXtalFreq(24000000U);
+ /* Enable XTAL 24MHz clock source. */
+ CLOCK_InitExternalClk(0);
+ /* Enable internal RC. */
+ CLOCK_InitRcOsc24M();
+ /* Switch clock source to external OSC. */
+ CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+ /* Set Oscillator ready counter value. */
+ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+ /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+ /* Waiting for DCDC_STS_DC_OK bit is asserted */
+ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+ {
+ }
+ /* Set AHB_PODF. */
+ CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+ /* Disable IPG clock gate. */
+ CLOCK_DisableClock(kCLOCK_Adc1);
+ CLOCK_DisableClock(kCLOCK_Adc2);
+ CLOCK_DisableClock(kCLOCK_Xbar1);
+ CLOCK_DisableClock(kCLOCK_Xbar2);
+ CLOCK_DisableClock(kCLOCK_Xbar3);
+ /* Set IPG_PODF. */
+ CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+ /* Set ARM_PODF. */
+ CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+ /* Set PERIPH_CLK2_PODF. */
+ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+ /* Disable PERCLK clock gate. */
+ CLOCK_DisableClock(kCLOCK_Gpt1);
+ CLOCK_DisableClock(kCLOCK_Gpt1S);
+ CLOCK_DisableClock(kCLOCK_Gpt2);
+ CLOCK_DisableClock(kCLOCK_Gpt2S);
+ CLOCK_DisableClock(kCLOCK_Pit);
+ /* Set PERCLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ /* Disable USDHC1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc1);
+ /* Set USDHC1_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+ /* Set Usdhc1 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+ /* Disable USDHC2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Usdhc2);
+ /* Set USDHC2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+ /* Set Usdhc2 clock source. */
+ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+ /* Disable Semc clock gate. */
+ CLOCK_DisableClock(kCLOCK_Semc);
+ /* Set SEMC_PODF. */
+ CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+ /* Set Semc alt clock source. */
+ CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+ /* Set Semc clock source. */
+ CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Disable Flexspi clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi);
+ /* Set FLEXSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+ /* Set Flexspi clock source. */
+ CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+ /* Disable Flexspi2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_FlexSpi2);
+ /* Set FLEXSPI2_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+ /* Set Flexspi2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+ /* Disable CSI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Csi);
+ /* Set CSI_PODF. */
+ CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+ /* Set Csi clock source. */
+ CLOCK_SetMux(kCLOCK_CsiMux, 0);
+ /* Disable LPSPI clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpspi1);
+ CLOCK_DisableClock(kCLOCK_Lpspi2);
+ CLOCK_DisableClock(kCLOCK_Lpspi3);
+ CLOCK_DisableClock(kCLOCK_Lpspi4);
+ /* Set LPSPI_PODF. */
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ /* Set Lpspi clock source. */
+ CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ /* Disable TRACE clock gate. */
+ CLOCK_DisableClock(kCLOCK_Trace);
+ /* Set TRACE_PODF. */
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+ /* Set Trace clock source. */
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
+ /* Disable SAI1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai1);
+ /* Set SAI1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+ /* Set SAI1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+ /* Set Sai1 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+ /* Disable SAI2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai2);
+ /* Set SAI2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+ /* Set SAI2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+ /* Set Sai2 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+ /* Disable SAI3 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Sai3);
+ /* Set SAI3_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+ /* Set SAI3_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+ /* Set Sai3 clock source. */
+ CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+ /* Disable Lpi2c clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpi2c1);
+ CLOCK_DisableClock(kCLOCK_Lpi2c2);
+ CLOCK_DisableClock(kCLOCK_Lpi2c3);
+ /* Set LPI2C_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ /* Set Lpi2c clock source. */
+ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+ /* Disable CAN clock gate. */
+ CLOCK_DisableClock(kCLOCK_Can1);
+ CLOCK_DisableClock(kCLOCK_Can2);
+ CLOCK_DisableClock(kCLOCK_Can3);
+ CLOCK_DisableClock(kCLOCK_Can1S);
+ CLOCK_DisableClock(kCLOCK_Can2S);
+ CLOCK_DisableClock(kCLOCK_Can3S);
+ /* Set CAN_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+ /* Set Can clock source. */
+ CLOCK_SetMux(kCLOCK_CanMux, 2);
+ /* Disable UART clock gate. */
+ CLOCK_DisableClock(kCLOCK_Lpuart1);
+ CLOCK_DisableClock(kCLOCK_Lpuart2);
+ CLOCK_DisableClock(kCLOCK_Lpuart3);
+ CLOCK_DisableClock(kCLOCK_Lpuart4);
+ CLOCK_DisableClock(kCLOCK_Lpuart5);
+ CLOCK_DisableClock(kCLOCK_Lpuart6);
+ CLOCK_DisableClock(kCLOCK_Lpuart7);
+ CLOCK_DisableClock(kCLOCK_Lpuart8);
+ /* Set UART_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+ /* Set Uart clock source. */
+ CLOCK_SetMux(kCLOCK_UartMux, 0);
+ /* Disable LCDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_LcdPixel);
+ /* Set LCDIF_PRED. */
+ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+ /* Set LCDIF_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+ /* Set Lcdif pre clock source. */
+ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+ /* Disable SPDIF clock gate. */
+ CLOCK_DisableClock(kCLOCK_Spdif);
+ /* Set SPDIF0_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+ /* Set SPDIF0_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+ /* Set Spdif clock source. */
+ CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+ /* Disable Flexio1 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio1);
+ /* Set FLEXIO1_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+ /* Set FLEXIO1_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+ /* Set Flexio1 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+ /* Disable Flexio2 clock gate. */
+ CLOCK_DisableClock(kCLOCK_Flexio2);
+ /* Set FLEXIO2_CLK_PRED. */
+ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+ /* Set FLEXIO2_CLK_PODF. */
+ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+ /* Set Flexio2 clock source. */
+ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+ /* Set Pll3 sw clock source. */
+ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+ /* Init ARM PLL. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+ /* Init System PLL. */
+ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+ /* Init System pfd0. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+ /* Init System pfd1. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+ /* Init System pfd2. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+ /* Init System pfd3. */
+ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+ /* Init Usb1 PLL. */
+ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+ /* Init Usb1 pfd0. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+ /* Init Usb1 pfd1. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+ /* Init Usb1 pfd2. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+ /* Init Usb1 pfd3. */
+ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+ /* DeInit Audio PLL. */
+ CLOCK_DeinitAudioPll();
+ /* Bypass Audio PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+ /* Set divider for Audio PLL. */
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+ /* Enable Audio PLL output. */
+ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+ {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+ /* DeInit Enet PLL. */
+ CLOCK_DeinitEnetPll();
+ /* Bypass Enet PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+ /* Set Enet output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ /* Enable Enet output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+ /* Set Enet2 output divider. */
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+ /* Enable Enet2 output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+ /* Enable Enet25M output. */
+ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+ /* Init Usb2 PLL. */
+ CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+ /* Set preperiph clock source. */
+ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+ /* Set periph clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+ /* Set periph clock2 clock source. */
+ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+ /* Set per clock source. */
+ CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ /* Set lvds1 clock source. */
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ /* Set clock out1 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+ /* Set clock out1 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+ /* Set clock out2 divider. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+ /* Set clock out2 source. */
+ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+ /* Set clock out1 drives clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+ /* Disable clock out1. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+ /* Disable clock out2. */
+ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+ /* Set SAI1 MCLK1 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+ /* Set SAI1 MCLK2 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+ /* Set SAI1 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+ /* Set SAI2 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+ /* Set SAI3 MCLK3 clock source. */
+ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+ /* Set MQS configuration. */
+ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+ /* Set ENET Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ /* Set ENET2 Ref clock source. */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+ /* Set GPT1 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+ /* Set GPT2 High frequency reference clock source. */
+ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41.mex b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
@@ -0,0 +1,1001 @@
+
+
+
+ MIMXRT1062xxxxA
+ MIMXRT1062DVL6A
+ MIMXRT1060-EVK
+ A2
+ ksdk2_0
+
+
+
+
+
+
+ false
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Configures pin routing and optionally pin electrical features.
+
+ false
+ core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ INPUT
+
+
+
+
+ true
+
+
+
+
+ OUTPUT
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
+
+
+
+
+
+ 13.0.2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ kELCDIF_CurFrameDoneInterruptEnable
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0.0.0
+
+
+
+
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
index 2d2bf8f09..f40c72cf7 100644
--- a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include
+#include "teensy41_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
diff --git a/hw/bsp/imxrt/debug.jlinkscript b/hw/bsp/imxrt/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/imxrt/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+ JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+ return 0;
+}
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index fc6e9e266..32d89f794 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@@ -24,14 +24,25 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_clock.h"
#include "fsl_lpuart.h"
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
#include "clock_config.h"
#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
@@ -47,24 +58,56 @@
#endif
// needed by fsl_flexspi_nor_boot
+TU_ATTR_USED
const uint8_t dcd_data[] = { 0x00 };
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
+static void init_usb_phy(USBPHY_Type* usb_phy) {
+ // Enable PHY support for Low speed device + LS via FS Hub
+ usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+ // Enable all power for normal operation
+ // TODO may not be needed since it is called within CLOCK_EnableUsbhs0PhyPllClock()
+ usb_phy->PWD = 0;
+
+ // TX Timing
+ uint32_t phytx = usb_phy->TX;
+ phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+ phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+ usb_phy->TX = phytx;
+}
+
void board_init(void)
{
+ // make sure the dcache is on.
+#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
+ if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache();
+#endif
+
// Init clock
BOARD_BootClockRUN();
SystemCoreClockUpdate();
+#ifdef TRACE_ETM
+ // RT1011 ETM pins
+// IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
+// IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
+// IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
+// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
+// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
+// CLOCK_EnableClock(kCLOCK_Trace);
+#endif
+
// Enable IOCON clock
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
+
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
@@ -109,54 +152,29 @@ void board_init(void)
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
- LPUART_Init(UART_PORT, &uart_config, freq);
+ if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, freq) ) {
+ // failed to init uart, probably baudrate is not supported
+ // TU_BREAKPOINT();
+ }
- //------------- USB0 -------------//
+ //------------- USB -------------//
+ // Note: RT105x RT106x and later have dual USB controllers.
// Clock
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
- USBPHY_Type* usb_phy;
-
- // RT105x RT106x have dual USB controller.
#ifdef USBPHY1
- usb_phy = USBPHY1;
+ init_usb_phy(USBPHY1);
#else
- usb_phy = USBPHY;
+ init_usb_phy(USBPHY);
#endif
- // Enable PHY support for Low speed device + LS via FS Hub
- usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
- // Enable all power for normal operation
- usb_phy->PWD = 0;
-
- // TX Timing
- uint32_t phytx = usb_phy->TX;
- phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
- phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
- usb_phy->TX = phytx;
-
- // RT105x RT106x have dual USB controller.
#ifdef USBPHY2
// USB1
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
-
- usb_phy = USBPHY2;
-
- // Enable PHY support for Low speed device + LS via FS Hub
- usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
- // Enable all power for normal operation
- usb_phy->PWD = 0;
-
- // TX Timing
- phytx = usb_phy->TX;
- phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
- phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
- usb_phy->TX = phytx;
+ init_usb_phy(USBPHY2);
#endif
}
@@ -170,7 +188,7 @@ void USB_OTG1_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
@@ -181,7 +199,7 @@ void USB_OTG2_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1);
+ tuh_int_handler(1, true);
#endif
}
@@ -202,25 +220,42 @@ uint32_t board_button_read(void)
int board_uart_read(uint8_t* buf, int len)
{
- LPUART_ReadBlocking(UART_PORT, buf, len);
- return len;
+ int count = 0;
+
+ while( count < len )
+ {
+ uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
+ if (!rx_count)
+ {
+ // clear all error flag if any
+ uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
+ status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag);
+ LPUART_ClearStatusFlags(UART_PORT, status_flags);
+ break;
+ }
+
+ for(int i=0; iSOPT5 = ((SIM->SOPT5 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
similarity index 99%
rename from hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
index 5420ffc00..f478a99c7 100644
--- a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
@@ -214,4 +214,3 @@ SECTIONS
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}
-
diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
similarity index 99%
rename from hw/bsp/kuiic/board.h
rename to hw/bsp/kinetis_k32l2/boards/kuiic/board.h
index 78ad83a2e..1e2d4f18b 100644
--- a/hw/bsp/kuiic/board.h
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
new file mode 100644
index 000000000..fc5bdeec8
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
@@ -0,0 +1,18 @@
+MCU = K32L2B31A
+
+CFLAGS += -DCPU_K32L2B31VLH0A
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2B31xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
similarity index 97%
rename from hw/bsp/kuiic/kuiic.c
rename to hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
index 7aaa9e03c..b83d5c820 100644
--- a/hw/bsp/kuiic/kuiic.c
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@@ -25,7 +25,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "../board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "fsl_smc.h"
#include "fsl_gpio.h"
@@ -96,10 +96,10 @@ void board_init(void)
CLOCK_EnableClock(kCLOCK_PortD);
CLOCK_EnableClock(kCLOCK_PortE);
-
+
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 };
GPIO_PinInit(GPIOA, 1U, &led_config);
- PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);
+ PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);
led_config.outputLogic = 0;
GPIO_PinInit(GPIOA, 2U, &led_config);
PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio);
@@ -108,10 +108,10 @@ void board_init(void)
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
const port_pin_config_t BUTTON_CFG = {
- kPORT_PullUp,
- kPORT_FastSlewRate,
- kPORT_PassiveFilterDisable,
- kPORT_LowDriveStrength,
+ kPORT_PullUp,
+ kPORT_FastSlewRate,
+ kPORT_PassiveFilterDisable,
+ kPORT_LowDriveStrength,
kPORT_MuxAsGpio
};
PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
@@ -121,7 +121,7 @@ void board_init(void)
PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
/* PORTA2 (pin 24) is configured as LPUART0_TX */
PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
-
+
SIM->SOPT5 = ((SIM->SOPT5 &
/* Mask bits to zero which are setting */
(~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
diff --git a/hw/bsp/kinetis_k32l2/family.mk b/hw/bsp/kinetis_k32l2/family.mk
new file mode 100644
index 000000000..357485762
--- /dev/null
+++ b/hw/bsp/kinetis_k32l2/family.mk
@@ -0,0 +1,32 @@
+UF2_FAMILY_ID = 0x7f83e793
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L
+
+SRC_C += \
+ src/portable/nxp/khci/dcd_khci.c \
+ src/portable/nxp/khci/hcd_khci.c \
+ $(MCU_DIR)/system_$(MCU).c \
+ $(MCU_DIR)/drivers/fsl_clock.c \
+ $(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+ $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(MCU_DIR) \
+ $(TOP)/$(MCU_DIR)/project_template \
+ $(TOP)/$(MCU_DIR)/drivers \
+ $(TOP)/$(SDK_DIR)/drivers/smc \
+ $(TOP)/$(SDK_DIR)/drivers/common \
+ $(TOP)/$(SDK_DIR)/drivers/gpio \
+ $(TOP)/$(SDK_DIR)/drivers/port \
+ $(TOP)/$(SDK_DIR)/drivers/lpuart \
+
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..2a2bce261
--- /dev/null
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 8 MHz}
+- {id: PLLFLLCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '2', locked: true}
+- {id: MCG.VDIV.scale, value: '24', locked: true}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV1.scale, value: '2'}
+- {id: SIM.PLLFLLSEL.sel, value: SIM.MCGPLLCLK_DIV2}
+- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.UART0SRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.USBSRCSEL.sel, value: SIM.PLLFLLSEL}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+ {
+ .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
+ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
+ .drs = kMCG_DrsLow, /* Low frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .pll0Config =
+ {
+ .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+ .prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
+ .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
+ },
+ };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+ {
+ .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+ .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+ .clkdiv1 = 0x10010000U, /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV4: /2 */
+ };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+ {
+ .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
+ .oscerConfig =
+ {
+ .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+ }
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Set the system clock dividers in SIM to safe value. */
+ CLOCK_SetSimSafeDivs();
+ /* Initializes OSC0 according to board configuration. */
+ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+ CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+ /* Configure FLL external reference divider (FRDIV). */
+ CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+ /* Set MCG to PEE mode. */
+ CLOCK_BootToPeeMode(kMCG_OscselOsc,
+ kMCG_PllClkSelPll0,
+ &mcgConfig_BOARD_BootClockRUN.pll0Config);
+ /* Configure the Internal Reference clock (MCGIRCLK). */
+ CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+ mcgConfig_BOARD_BootClockRUN.ircs,
+ mcgConfig_BOARD_BootClockRUN.fcrdiv);
+ /* Set the clock configuration in SIM module. */
+ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 800 kHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+ {
+ .mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
+ .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
+ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
+ .drs = kMCG_DrsLow, /* Low frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .pll0Config =
+ {
+ .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+ .prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
+ .vdiv = 0x0U, /* VCO divider: multiplied by 24 */
+ },
+ };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+ {
+ .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+ .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
+ .clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5 */
+ };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+ {
+ .freq = 0U, /* Oscillator frequency: 0Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
+ .oscerConfig =
+ {
+ .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+ }
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+ /* Set the system clock dividers in SIM to safe value. */
+ CLOCK_SetSimSafeDivs();
+ /* Set MCG to BLPI mode. */
+ CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+ mcgConfig_BOARD_BootClockVLPR.ircs,
+ mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+ /* Set the clock configuration in SIM module. */
+ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+ /* Set VLPR power mode. */
+ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+ SMC_SetPowerModeVlpr(SMC, false);
+#else
+ SMC_SetPowerModeVlpr(SMC);
+#endif
+ while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+ {
+ }
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
new file mode 100644
index 000000000..1033d4e55
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis_kl/family.c
similarity index 73%
rename from hw/bsp/frdm_kl25z/frdm_kl25z.c
rename to hw/bsp/kinetis_kl/family.c
index 8d93fdbaa..c436be3e6 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@@ -21,11 +21,10 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
*/
-#include "../board.h"
+#include "bsp/board_api.h"
+#include "board.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_port.h"
@@ -40,45 +39,13 @@
void USB0_IRQHandler(void)
{
#if CFG_TUH_ENABLED
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
#if CFG_TUD_ENABLED
tud_int_handler(0);
#endif
}
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-#define LED_PINMUX IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT GPIOB
-#define LED_PIN_CLOCK kCLOCK_PortB
-#define LED_PIN_PORT PORTB
-#define LED_PIN 19U
-#define LED_PIN_FUNCTION kPORT_MuxAsGpio
-#define LED_STATE_ON 0
-
-// Button
-#define BUTTON_PORT GPIOC
-#define BUTTON_PIN_CLOCK kCLOCK_PortC
-#define BUTTON_PIN_PORT PORTC
-#define BUTTON_PIN 9U
-#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio
-#define BUTTON_STATE_ACTIVE 0
-
-// UART
-#define UART_PORT UART0
-#define UART_PIN_CLOCK kCLOCK_PortA
-#define UART_PIN_PORT PORTA
-#define UART_PIN_RX 1u
-#define UART_PIN_TX 2u
-#define UART_PIN_FUNCTION kPORT_MuxAlt2
-#define SOPT5_UART0RXSRC_UART_RX 0x00u /*!< UART0 receive data source select: UART0_RX pin */
-#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!< UART0 transmit data source select: UART0_TX pin */
-
-const uint8_t dcd_data[] = { 0x00 };
-
void board_init(void)
{
BOARD_BootClockRUN();
@@ -103,7 +70,7 @@ void board_init(void)
// Button
CLOCK_EnableClock(BUTTON_PIN_CLOCK);
port_pin_config_t button_port = {
- .pullSelect = kPORT_PullUp,
+ .pullSelect = kPORT_PullUp,
.mux = BUTTON_PIN_FUNCTION,
};
PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port);
@@ -139,13 +106,13 @@ void board_init(void)
void board_led_write(bool state)
{
- GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+ GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
}
uint32_t board_button_read(void)
{
#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
- return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN);
+ return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
#endif
return 0;
}
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
new file mode 100644
index 000000000..4151979a0
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -0,0 +1,107 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+ ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
+ ${SDK_DIR}/drivers/uart/fsl_uart.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ ${SDK_DIR}/drivers/common
+ ${SDK_DIR}/drivers/gpio
+ ${SDK_DIR}/drivers/lpsci
+ ${SDK_DIR}/drivers/port
+ ${SDK_DIR}/drivers/smc
+ ${SDK_DIR}/drivers/uart
+ )
+ update_board(${BOARD_TARGET})
+
+ # LD_FILE and STARTUP_FILE can be defined in board.cmake
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ # nanolib
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+ ${TOP}/src/portable/nxp/khci/hcd_khci.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
new file mode 100644
index 000000000..edb2f3366
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -0,0 +1,34 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \
+
+LDFLAGS += \
+ -Wl,--defsym,__stack_size__=0x400 \
+ -Wl,--defsym,__heap_size__=0
+
+SRC_C += \
+ src/portable/nxp/khci/dcd_khci.c \
+ src/portable/nxp/khci/hcd_khci.c \
+ $(MCU_DIR)/system_$(MCU).c \
+ $(MCU_DIR)/drivers/fsl_clock.c \
+ $(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+ $(SDK_DIR)/drivers/lpsci/fsl_lpsci.c \
+ $(SDK_DIR)/drivers/uart/fsl_uart.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(MCU_DIR) \
+ $(TOP)/$(MCU_DIR)/drivers \
+ $(TOP)/$(SDK_DIR)/drivers/common \
+ $(TOP)/$(SDK_DIR)/drivers/gpio \
+ $(TOP)/$(SDK_DIR)/drivers/lpsci \
+ $(TOP)/$(SDK_DIR)/drivers/port \
+ $(TOP)/$(SDK_DIR)/drivers/smc \
+ $(TOP)/$(SDK_DIR)/drivers/uart \
diff --git a/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
new file mode 100644
index 000000000..b38aa827c
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+** Processors: MKL25Z128VFM4
+** MKL25Z128VFT4
+** MKL25Z128VLH4
+** MKL25Z128VLK4
+**
+** Compiler: GNU C Compiler
+** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
+** Version: rev. 2.5, 2015-02-19
+** Build: b170214
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0200 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200
+ m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
+ m_data (RW) : ORIGIN = 0x1FFFF000, LENGTH = 0x00004000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .flash_config :
+ {
+ . = ALIGN(4);
+ KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
+ . = ALIGN(4);
+ } > m_flash_config
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ /* reserve MTB memory at the beginning of m_data */
+ .mtb : /* MTB buffer address as defined by the hardware */
+ {
+ . = ALIGN(8);
+ _mtb_start = .;
+ KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+ . = ALIGN(8);
+ _mtb_end = .;
+ } > m_data
+
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > m_data
+
+ __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+ __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
new file mode 100644
index 000000000..dc1438f3a
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
@@ -0,0 +1,383 @@
+/* ---------------------------------------------------------------------------------------*/
+/* @file: startup_MKL25Z4.s */
+/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
+/* MKL25Z4 */
+/* @version: 2.5 */
+/* @date: 2015-2-19 */
+/* @build: b170112 */
+/* ---------------------------------------------------------------------------------------*/
+/* */
+/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. */
+/* Copyright 2016 - 2017 NXP */
+/* Redistribution and use in source and binary forms, with or without modification, */
+/* are permitted provided that the following conditions are met: */
+/* */
+/* o Redistributions of source code must retain the above copyright notice, this list */
+/* of conditions and the following disclaimer. */
+/* */
+/* o Redistributions in binary form must reproduce the above copyright notice, this */
+/* list of conditions and the following disclaimer in the documentation and/or */
+/* other materials provided with the distribution. */
+/* */
+/* o Neither the name of the copyright holder nor the names of its */
+/* contributors may be used to endorse or promote products derived from this */
+/* software without specific prior written permission. */
+/* */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors */
+/*****************************************************************************/
+ .syntax unified
+ .arch armv6-m
+
+ .section .isr_vector, "a"
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler*/
+ .long HardFault_Handler /* Hard Fault Handler*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long SVC_Handler /* SVCall Handler*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long PendSV_Handler /* PendSV Handler*/
+ .long SysTick_Handler /* SysTick Handler*/
+
+ /* External Interrupts*/
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
+ .long Reserved20_IRQHandler /* Reserved interrupt*/
+ .long FTFA_IRQHandler /* Command complete and read collision*/
+ .long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/
+ .long LLWU_IRQHandler /* Low leakage wakeup Unit*/
+ .long I2C0_IRQHandler /* I2C0 interrupt*/
+ .long I2C1_IRQHandler /* I2C1 interrupt*/
+ .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
+ .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
+ .long UART0_IRQHandler /* UART0 status and error*/
+ .long UART1_IRQHandler /* UART1 status and error*/
+ .long UART2_IRQHandler /* UART2 status and error*/
+ .long ADC0_IRQHandler /* ADC0 interrupt*/
+ .long CMP0_IRQHandler /* CMP0 interrupt*/
+ .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
+ .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
+ .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
+ .long RTC_IRQHandler /* RTC alarm*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds*/
+ .long PIT_IRQHandler /* PIT interrupt*/
+ .long Reserved39_IRQHandler /* Reserved interrupt*/
+ .long USB0_IRQHandler /* USB0 interrupt*/
+ .long DAC0_IRQHandler /* DAC0 interrupt*/
+ .long TSI0_IRQHandler /* TSI0 interrupt*/
+ .long MCG_IRQHandler /* MCG interrupt*/
+ .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
+ .long Reserved45_IRQHandler /* Reserved interrupt*/
+ .long PORTA_IRQHandler /* PORTA Pin detect*/
+ .long PORTD_IRQHandler /* PORTD Pin detect*/
+
+ .size __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+ .section .FlashConfig, "a"
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFE
+
+ .text
+ .thumb
+
+/* Reset Handler */
+
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ cpsid i /* Mask interrupts */
+ .equ VTOR, 0xE000ED08
+ ldr r0, =VTOR
+ ldr r1, =__isr_vector
+ str r1, [r0]
+ ldr r2, [r1]
+ msr msp, r2
+#ifndef __NO_SYSTEM_INIT
+ ldr r0,=SystemInit
+ blx r0
+#endif
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+
+#ifdef __STARTUP_CLEAR_BSS
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * Loop to zero out BSS section, which uses following symbols
+ * in linker script:
+ * __bss_start__: start of BSS section. Must align to 4
+ * __bss_end__: end of BSS section. Must align to 4
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ subs r2, r1
+ ble .LC3
+
+ movs r0, 0
+.LC2:
+ str r0, [r1, r2]
+ subs r2, 4
+ bge .LC2
+.LC3:
+#endif
+ cpsie i /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+ ldr r0,=__START
+ blx r0
+#else
+ ldr r0,=__libc_init_array
+ blx r0
+ ldr r0,=main
+ bx r0
+#endif
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak DefaultISR
+ .type DefaultISR, %function
+DefaultISR:
+ ldr r0, =DefaultISR
+ bx r0
+ .size DefaultISR, . - DefaultISR
+
+ .align 1
+ .thumb_func
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ ldr r0,=NMI_Handler
+ bx r0
+ .size NMI_Handler, . - NMI_Handler
+
+ .align 1
+ .thumb_func
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ ldr r0,=HardFault_Handler
+ bx r0
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .align 1
+ .thumb_func
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ ldr r0,=SVC_Handler
+ bx r0
+ .size SVC_Handler, . - SVC_Handler
+
+ .align 1
+ .thumb_func
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ ldr r0,=PendSV_Handler
+ bx r0
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .align 1
+ .thumb_func
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ ldr r0,=SysTick_Handler
+ bx r0
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .align 1
+ .thumb_func
+ .weak DMA0_IRQHandler
+ .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+ ldr r0,=DMA0_DriverIRQHandler
+ bx r0
+ .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMA1_IRQHandler
+ .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+ ldr r0,=DMA1_DriverIRQHandler
+ bx r0
+ .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMA2_IRQHandler
+ .type DMA2_IRQHandler, %function
+DMA2_IRQHandler:
+ ldr r0,=DMA2_DriverIRQHandler
+ bx r0
+ .size DMA2_IRQHandler, . - DMA2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMA3_IRQHandler
+ .type DMA3_IRQHandler, %function
+DMA3_IRQHandler:
+ ldr r0,=DMA3_DriverIRQHandler
+ bx r0
+ .size DMA3_IRQHandler, . - DMA3_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak I2C0_IRQHandler
+ .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+ ldr r0,=I2C0_DriverIRQHandler
+ bx r0
+ .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak I2C1_IRQHandler
+ .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+ ldr r0,=I2C1_DriverIRQHandler
+ bx r0
+ .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SPI0_IRQHandler
+ .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+ ldr r0,=SPI0_DriverIRQHandler
+ bx r0
+ .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SPI1_IRQHandler
+ .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+ ldr r0,=SPI1_DriverIRQHandler
+ bx r0
+ .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART0_IRQHandler
+ .type UART0_IRQHandler, %function
+UART0_IRQHandler:
+ ldr r0,=UART0_DriverIRQHandler
+ bx r0
+ .size UART0_IRQHandler, . - UART0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART1_IRQHandler
+ .type UART1_IRQHandler, %function
+UART1_IRQHandler:
+ ldr r0,=UART1_DriverIRQHandler
+ bx r0
+ .size UART1_IRQHandler, . - UART1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART2_IRQHandler
+ .type UART2_IRQHandler, %function
+UART2_IRQHandler:
+ ldr r0,=UART2_DriverIRQHandler
+ bx r0
+ .size UART2_IRQHandler, . - UART2_IRQHandler
+
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, DefaultISR
+ .endm
+
+/* Exception Handlers */
+ def_irq_handler DMA0_DriverIRQHandler
+ def_irq_handler DMA1_DriverIRQHandler
+ def_irq_handler DMA2_DriverIRQHandler
+ def_irq_handler DMA3_DriverIRQHandler
+ def_irq_handler Reserved20_IRQHandler
+ def_irq_handler FTFA_IRQHandler
+ def_irq_handler LVD_LVW_IRQHandler
+ def_irq_handler LLWU_IRQHandler
+ def_irq_handler I2C0_DriverIRQHandler
+ def_irq_handler I2C1_DriverIRQHandler
+ def_irq_handler SPI0_DriverIRQHandler
+ def_irq_handler SPI1_DriverIRQHandler
+ def_irq_handler UART0_DriverIRQHandler
+ def_irq_handler UART1_DriverIRQHandler
+ def_irq_handler UART2_DriverIRQHandler
+ def_irq_handler ADC0_IRQHandler
+ def_irq_handler CMP0_IRQHandler
+ def_irq_handler TPM0_IRQHandler
+ def_irq_handler TPM1_IRQHandler
+ def_irq_handler TPM2_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler RTC_Seconds_IRQHandler
+ def_irq_handler PIT_IRQHandler
+ def_irq_handler Reserved39_IRQHandler
+ def_irq_handler USB0_IRQHandler
+ def_irq_handler DAC0_IRQHandler
+ def_irq_handler TSI0_IRQHandler
+ def_irq_handler MCG_IRQHandler
+ def_irq_handler LPTMR0_IRQHandler
+ def_irq_handler Reserved45_IRQHandler
+ def_irq_handler PORTA_IRQHandler
+ def_irq_handler PORTD_IRQHandler
+
+ .end
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
deleted file mode 100644
index 39e9d9deb..000000000
--- a/hw/bsp/kuiic/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) tools/uf2
-
-# This board uses TinyUF2 for updates
-UF2_FAMILY_ID = 0x7f83e793
-
-CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
- -DCPU_K32L2B31VLH0A \
- -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = /hw/bsp/$(BOARD)/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
- src/portable/nxp/khci/dcd_khci.c \
- $(MCU_DIR)/system_K32L2B31A.c \
- $(MCU_DIR)/drivers/fsl_clock.c \
- $(SDK_DIR)/drivers/gpio/fsl_gpio.c \
- $(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
- $(TOP)/hw/bsp/$(BOARD) \
- $(TOP)/$(SDK_DIR)/CMSIS/Include \
- $(TOP)/$(SDK_DIR)/drivers/smc \
- $(TOP)/$(SDK_DIR)/drivers/common \
- $(TOP)/$(SDK_DIR)/drivers/gpio \
- $(TOP)/$(SDK_DIR)/drivers/port \
- $(TOP)/$(SDK_DIR)/drivers/lpuart \
- $(TOP)/$(MCU_DIR) \
- $(TOP)/$(MCU_DIR)/drivers
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
new file mode 100644
index 000000000..fdc17374b
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
@@ -0,0 +1,24 @@
+MCU = 11uxx
+MCU_DRV = 11xx
+
+CFLAGS += \
+ -DCORE_M0 \
+ -DCFG_EXAMPLE_MSC_READONLY \
+ -DCFG_EXAMPLE_VIDEO_READONLY \
+ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# mcu driver cause following warnings
+CFLAGS += \
+ -Wno-error=strict-prototypes \
+ -Wno-error=unused-parameter \
+ -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u37.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U37/401
+PYOCD_TARGET = lpc11u37
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
similarity index 82%
rename from hw/bsp/lpcxpresso11u37/lpc11u37.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
index 6a2dfb7f5..8e0a4e4c6 100644
--- a/hw/bsp/lpcxpresso11u37/lpc11u37.ld
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
@@ -12,24 +12,24 @@
MEMORY
{
/* Define each memory region */
- MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
- RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
- RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+ MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
+ RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash128 = 0x0 ; /* MFlash128 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
- __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
- __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
- __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
- __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
- __base_RAM2 = 0x20004000 ; /* RAM2 */
- __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
- __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __base_MFlash128 = 0x0 ; /* MFlash128 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
+ __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
+ __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+ __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+ __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
+ __base_RAM2 = 0x20004000 ; /* RAM2 */
+ __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
ENTRY(ResetISR)
@@ -74,9 +74,9 @@ SECTIONS
} > MFlash128
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash128
@@ -88,9 +88,9 @@ SECTIONS
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash128
__exidx_end = .;
-
+
_etext = .;
-
+
/* DATA section for RamUsb2 */
.data_RAM2 : ALIGN(4)
@@ -176,11 +176,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
- + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+ + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
)
);
@@ -192,4 +192,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
similarity index 99%
rename from hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
rename to hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
index 11f1797a2..900c57936 100644
--- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
new file mode 100644
index 000000000..fbe97b853
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
@@ -0,0 +1,18 @@
+MCU = 11u6x
+MCU_DRV = 11u6x
+
+CFLAGS += \
+ -DCORE_M0PLUS \
+ -D__VTOR_PRESENT=0 \
+ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u68.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
+PYOCD_TARGET = lpc11u68
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
similarity index 81%
rename from hw/bsp/lpcxpresso11u68/lpc11u68.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
index 56d9e4b89..4a35b192e 100644
--- a/hw/bsp/lpcxpresso11u68/lpc11u68.ld
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
@@ -11,29 +11,29 @@
MEMORY
{
/* Define each memory region */
- MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
- Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
- Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
- Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+ Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+ Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash256 = 0x0 ; /* MFlash256 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
- __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
- __base_Ram0_32 = 0x10000000 ; /* Ram0_32 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */
- __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
- __base_Ram1_2 = 0x20000000 ; /* Ram1_2 */
- __base_RAM2 = 0x20000000 ; /* RAM2 */
- __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */
- __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */
- __base_Ram2USB_2 = 0x20004000 ; /* Ram2USB_2 */
- __base_RAM3 = 0x20004000 ; /* RAM3 */
- __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */
- __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __base_MFlash256 = 0x0 ; /* MFlash256 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+ __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+ __base_Ram0_32 = 0x10000000 ; /* Ram0_32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_Ram1_2 = 0x20000000 ; /* Ram1_2 */
+ __base_RAM2 = 0x20000000 ; /* RAM2 */
+ __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */
+ __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */
+ __base_Ram2USB_2 = 0x20004000 ; /* Ram2USB_2 */
+ __base_RAM3 = 0x20004000 ; /* RAM3 */
+ __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */
ENTRY(ResetISR)
@@ -82,9 +82,9 @@ SECTIONS
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
@@ -98,7 +98,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* possible MTB section for Ram1_2 */
.mtb_buffer_RAM2 (NOLOAD) :
{
@@ -172,7 +172,7 @@ SECTIONS
*(.bss.$Ram1_2*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > Ram1_2
+ } > Ram1_2
/* BSS section for Ram2USB_2 */
.bss_RAM3 : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
*(.bss.$Ram2USB_2*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
- } > Ram2USB_2
+ } > Ram2USB_2
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -201,7 +201,7 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$Ram1_2*)
. = ALIGN(4) ;
- } > Ram1_2
+ } > Ram1_2
/* NOINIT section for Ram2USB_2 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -209,13 +209,13 @@ SECTIONS
*(.noinit.$RAM3*)
*(.noinit.$Ram2USB_2*)
. = ALIGN(4) ;
- } > Ram2USB_2
+ } > Ram2USB_2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > Ram0_32
@@ -223,11 +223,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
- + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+ + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
)
);
@@ -239,4 +239,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
similarity index 99%
rename from hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
rename to hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
index e33a5c6e5..df895804d 100644
--- a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
new file mode 100644
index 000000000..dee85da90
--- /dev/null
+++ b/hw/bsp/lpc11/family.mk
@@ -0,0 +1,38 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc$(MCU)/lpc_chip_$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
+CFLAGS += \
+ -flto \
+ -nostdlib \
+ -D__USE_LPCOPEN \
+ -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+SRC_C += \
+ src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+ $(MCU_DIR)/../gcc/cr_startup_lpc$(MCU_DRV).c \
+ $(MCU_DIR)/src/chip_$(MCU_DRV).c \
+ $(MCU_DIR)/src/clock_$(MCU_DRV).c \
+ $(MCU_DIR)/src/iocon_$(MCU_DRV).c \
+ $(MCU_DIR)/src/sysinit_$(MCU_DRV).c
+
+ifeq ($(MCU),11u6x)
+SRC_C += \
+ $(MCU_DIR)/src/gpio_$(MCU_DRV).c \
+ $(MCU_DIR)/src/syscon_$(MCU_DRV).c \
+
+else
+
+SRC_C += \
+ $(MCU_DIR)/src/gpio_$(MCU_DRV)_1.c \
+ $(MCU_DIR)/src/sysctl_$(MCU_DRV).c
+endif
+
+INC += \
+ $(TOP)/$(MCU_DIR)/inc
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
new file mode 100644
index 000000000..31eb2f28f
--- /dev/null
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
@@ -0,0 +1,13 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+CFLAGS += \
+ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1347.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1347
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1347/lpc1347.ld b/hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
similarity index 81%
rename from hw/bsp/lpcxpresso1347/lpc1347.ld
rename to hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
index 42a4bb25c..a2111cd1c 100644
--- a/hw/bsp/lpcxpresso1347/lpc1347.ld
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
@@ -11,29 +11,29 @@
MEMORY
{
/* Define each memory region */
- MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */
- RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
- RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
- RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
+ MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */
+ RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+ RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash64 = 0x0 ; /* MFlash64 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */
- __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */
- __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
- __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
- __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
- __base_RAM2 = 0x20004000 ; /* RAM2 */
- __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
- __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
- __base_RamPeriph2 = 0x20000000 ; /* RamPeriph2 */
- __base_RAM3 = 0x20000000 ; /* RAM3 */
- __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */
- __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */
+ __base_MFlash64 = 0x0 ; /* MFlash64 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */
+ __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */
+ __base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+ __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+ __base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
+ __base_RAM2 = 0x20004000 ; /* RAM2 */
+ __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
+ __base_RamPeriph2 = 0x20000000 ; /* RamPeriph2 */
+ __base_RAM3 = 0x20000000 ; /* RAM3 */
+ __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */
+ __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */
ENTRY(ResetISR)
@@ -82,9 +82,9 @@ SECTIONS
} > MFlash64
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash64
@@ -98,7 +98,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamUsb2 */
.data_RAM2 : ALIGN(4)
@@ -153,7 +153,7 @@ SECTIONS
*(.bss.$RamUsb2*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamUsb2
+ } > RamUsb2
/* BSS section for RamPeriph2 */
.bss_RAM3 : ALIGN(4)
@@ -163,7 +163,7 @@ SECTIONS
*(.bss.$RamPeriph2*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
- } > RamPeriph2
+ } > RamPeriph2
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamUsb2*)
. = ALIGN(4) ;
- } > RamUsb2
+ } > RamUsb2
/* NOINIT section for RamPeriph2 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -190,13 +190,13 @@ SECTIONS
*(.noinit.$RAM3*)
*(.noinit.$RamPeriph2*)
. = ALIGN(4) ;
- } > RamPeriph2
+ } > RamPeriph2
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc8
@@ -204,11 +204,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -222,4 +222,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
similarity index 98%
rename from hw/bsp/lpcxpresso1347/lpcxpresso1347.c
rename to hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
index a9a67ae3a..e8c85ae22 100644
--- a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
@@ -64,7 +64,7 @@ const uint32_t ExtRateIn = 0;
/* Pin muxing table, only items that need changing from their default pin
state are in this table. */
-static const PINMUX_GRP_T pinmuxing[] =
+static const PINMUX_GRP_T pinmuxing[] =
{
{0, 1, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_1 used for CLKOUT */
{0, 2, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)}, /* PIO0_2 used for SSEL */
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpc13/family.mk
similarity index 63%
rename from hw/bsp/lpcxpresso1347/board.mk
rename to hw/bsp/lpc13/family.mk
index bf9c97c82..10cf4969d 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpc13/family.mk
@@ -1,26 +1,24 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
-nostdlib \
-DCORE_M3 \
-D__USE_LPCOPEN \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_EXAMPLE_VIDEO_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
- -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
- -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# startup.c and lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
SRC_C += \
src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
@@ -34,12 +32,3 @@ SRC_C += \
INC += \
$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1347
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
index 6dd12ade1..d8079717e 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
@@ -13,29 +13,29 @@
MEMORY
{
/* Define each memory region */
- MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
- Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
- Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
- Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
+ MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+ Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
+ Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
+ Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash256 = 0x0 ; /* MFlash256 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
- __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
- __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */
- __base_RAM = 0x2000000 ; /* RAM */
- __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
- __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
- __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */
- __base_RAM2 = 0x2004000 ; /* RAM2 */
- __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
- __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
- __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */
- __base_RAM3 = 0x2008000 ; /* RAM3 */
- __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
- __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
+ __base_MFlash256 = 0x0 ; /* MFlash256 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+ __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+ __base_Ram0_16 = 0x2000000 ; /* Ram0_16 */
+ __base_RAM = 0x2000000 ; /* RAM */
+ __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
+ __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
+ __base_Ram1_16 = 0x2004000 ; /* Ram1_16 */
+ __base_RAM2 = 0x2004000 ; /* RAM2 */
+ __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
+ __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
+ __base_Ram2_4 = 0x2008000 ; /* Ram2_4 */
+ __base_RAM3 = 0x2008000 ; /* RAM3 */
+ __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
+ __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
ENTRY(ResetISR)
@@ -84,9 +84,9 @@ SECTIONS
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
@@ -98,9 +98,9 @@ SECTIONS
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
-
+
_etext = .;
-
+
/* DATA section for Ram1_16 */
.data_RAM2 : ALIGN(4)
@@ -225,11 +225,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -243,4 +243,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index 7f5984a3e..cd5c9ab15 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index c7dd3f8be..9f489832f 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -1,18 +1,16 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
-nostdlib \
-DCORE_M3 \
-D__USE_LPCOPEN \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
- -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
@@ -34,6 +32,3 @@ SRC_C += \
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
new file mode 100644
index 000000000..e22c4f64b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
@@ -0,0 +1,8 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1769.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1769
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1769/lpc1769.ld b/hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
similarity index 81%
rename from hw/bsp/lpcxpresso1769/lpc1769.ld
rename to hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
index d1c83d8e2..095bd3d92 100644
--- a/hw/bsp/lpcxpresso1769/lpc1769.ld
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
@@ -11,24 +11,24 @@
MEMORY
{
/* Define each memory region */
- MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
- RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
- RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash512 = 0x0 ; /* MFlash512 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
- __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
- __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
- __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
- __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
- __base_RAM2 = 0x2007c000 ; /* RAM2 */
- __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
- __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
ENTRY(ResetISR)
@@ -72,9 +72,9 @@ SECTIONS
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamAHB32 */
.data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
*(.bss.$RamAHB32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamAHB32
+ } > RamAHB32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamAHB32*)
. = ALIGN(4) ;
- } > RamAHB32
+ } > RamAHB32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc32
@@ -163,11 +163,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
similarity index 99%
rename from hw/bsp/lpcxpresso1769/lpcxpresso1769.c
rename to hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
index b7bce93d2..8c26b906f 100644
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// USB Interrupt Handler
@@ -37,7 +37,7 @@ void USB_IRQHandler(void)
#endif
#if CFG_TUH_ENABLED
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
diff --git a/hw/bsp/lpc17/boards/mbed1768/board.mk b/hw/bsp/lpc17/boards/mbed1768/board.mk
new file mode 100644
index 000000000..a982a970b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/mbed1768/board.mk
@@ -0,0 +1,9 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1768.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1768
+PYOCD_TARGET = lpc1768
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/mbed1768/lpc1768.ld b/hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
similarity index 81%
rename from hw/bsp/mbed1768/lpc1768.ld
rename to hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
index d1c83d8e2..095bd3d92 100644
--- a/hw/bsp/mbed1768/lpc1768.ld
+++ b/hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
@@ -11,24 +11,24 @@
MEMORY
{
/* Define each memory region */
- MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
- RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
- RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
- __base_MFlash512 = 0x0 ; /* MFlash512 */
- __base_Flash = 0x0 ; /* Flash */
- __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
- __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
- __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
- __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
- __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
- __base_RAM2 = 0x2007c000 ; /* RAM2 */
- __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
- __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __base_MFlash512 = 0x0 ; /* MFlash512 */
+ __base_Flash = 0x0 ; /* Flash */
+ __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB32 = 0x2007c000 ; /* RamAHB32 */
+ __base_RAM2 = 0x2007c000 ; /* RAM2 */
+ __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+ __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
ENTRY(ResetISR)
@@ -72,9 +72,9 @@ SECTIONS
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamAHB32 */
.data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
*(.bss.$RamAHB32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamAHB32
+ } > RamAHB32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamAHB32*)
. = ALIGN(4) ;
- } > RamAHB32
+ } > RamAHB32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc32
@@ -163,11 +163,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
similarity index 98%
rename from hw/bsp/mbed1768/mbed1768.c
rename to hw/bsp/lpc17/boards/mbed1768/mbed1768.c
index 08cf3adbd..613dcb570 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
#define LED_PORT 1
#define LED_PIN 18
@@ -151,7 +151,7 @@ void USB_IRQHandler(void)
#endif
#if CFG_TUH_ENABLED
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpc17/family.mk
similarity index 68%
rename from hw/bsp/lpcxpresso1769/board.mk
rename to hw/bsp/lpc17/family.mk
index 34b4d6dc0..44b406d90 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -1,10 +1,11 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
-nostdlib \
-DCORE_M3 \
-D__USE_LPCOPEN \
@@ -14,13 +15,15 @@ CFLAGS += \
# lpc_types.h cause following errors
CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
SRC_C += \
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
+ src/portable/ohci/ohci.c \
+ src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
$(MCU_DIR)/src/chip_17xx_40xx.c \
$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -28,16 +31,7 @@ SRC_C += \
$(MCU_DIR)/src/iocon_17xx_40xx.c \
$(MCU_DIR)/src/sysctl_17xx_40xx.c \
$(MCU_DIR)/src/sysinit_17xx_40xx.c \
- $(MCU_DIR)/src/uart_17xx_40xx.c
+ $(MCU_DIR)/src/uart_17xx_40xx.c \
INC += \
$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1769
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f80413c0
--- /dev/null
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< MFlashA512
-
+
_etext = .;
-
+
/* DATA section for RamLoc40 */
.data_RAM2 : ALIGN(4)
@@ -377,17 +377,17 @@ SECTIONS
. = ALIGN(4) ;
_end_noinit = .;
PROVIDE(__end_noinit_RAM = .) ;
- PROVIDE(__end_noinit_RamLoc32 = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
} > RamLoc32 AT> RamLoc32
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -401,4 +401,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
new file mode 100644
index 000000000..f6fae89d7
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1857)
+
+set(JLINK_DEVICE LPC1857)
+set(PYOCD_TARGET LPC1857)
+set(NXPLINK_DEVICE LPC1857:MCB1857)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+
+function(update_board TARGET)
+ # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
index 6111da975..93b3cd112 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.h
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -41,10 +41,17 @@
#define UART_DEV LPC_USART3
-static inline void board_lpc18_pinmux(void)
-{
- const PINMUX_GRP_T pinmuxing[] =
- {
+static inline void board_lpc18_pinmux(void) {
+ const PINMUX_GRP_T pinmuxing[] = {
+ // ETM Trace
+ #ifdef TRACE_ETM
+ { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
+ { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+ { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+ { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+ { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+ #endif
+
// LEDs
{ 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
{ 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
@@ -64,7 +71,6 @@ static inline void board_lpc18_pinmux(void)
// USB0
{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
-
{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
{ 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
};
@@ -72,8 +78,7 @@ static inline void board_lpc18_pinmux(void)
Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
/* Pin clock mux values, re-used structure, value in first index is meaningless */
- const PINMUX_GRP_T pinclockmuxing[] =
- {
+ const PINMUX_GRP_T pinclockmuxing[] = {
{ 0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
{ 0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
{ 0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
@@ -81,8 +86,7 @@ static inline void board_lpc18_pinmux(void)
};
/* Clock pins only, group field not used */
- for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
- {
+ for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
}
}
diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
index 9a308e342..9a67e8946 100644
--- a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
+++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
@@ -11,44 +11,44 @@
MEMORY
{
/* Define each memory region */
- MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
- MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
- RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
- RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
- RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
- RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
- RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+ MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
}
/* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
-__base_Flash = 0x1a000000 ; /* Flash */
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
-__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
-__base_Flash2 = 0x1b000000 ; /* Flash2 */
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
-__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
-__base_RAM = 0x10000000 ; /* RAM */
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
-__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
-__base_RAM2 = 0x10080000 ; /* RAM2 */
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
-__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
-__base_RAM3 = 0x20000000 ; /* RAM3 */
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
-__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
-__base_RAM4 = 0x20008000 ; /* RAM4 */
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
-__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
-__base_RAM5 = 0x2000c000 ; /* RAM5 */
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
-__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
ENTRY(ResetISR)
@@ -118,9 +118,9 @@ SECTIONS
} > MFlashA512
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlashA512
@@ -134,7 +134,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamLoc40 */
.data_RAM2 : ALIGN(4)
@@ -215,7 +215,7 @@ SECTIONS
*(.bss.$RamLoc40*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamLoc40
+ } > RamLoc40
/* BSS section for RamAHB32 */
.bss_RAM3 : ALIGN(4)
@@ -225,7 +225,7 @@ SECTIONS
*(.bss.$RamAHB32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
- } > RamAHB32
+ } > RamAHB32
/* BSS section for RamAHB16 */
.bss_RAM4 : ALIGN(4)
@@ -235,7 +235,7 @@ SECTIONS
*(.bss.$RamAHB16*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM4 = .) ;
- } > RamAHB16
+ } > RamAHB16
/* BSS section for RamAHB_ETB16 */
.bss_RAM5 : ALIGN(4)
@@ -245,7 +245,7 @@ SECTIONS
*(.bss.$RamAHB_ETB16*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM5 = .) ;
- } > RamAHB_ETB16
+ } > RamAHB_ETB16
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -264,7 +264,7 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamLoc40*)
. = ALIGN(4) ;
- } > RamLoc40
+ } > RamLoc40
/* NOINIT section for RamAHB32 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -272,7 +272,7 @@ SECTIONS
*(.noinit.$RAM3*)
*(.noinit.$RamAHB32*)
. = ALIGN(4) ;
- } > RamAHB32
+ } > RamAHB32
/* NOINIT section for RamAHB16 */
.noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -280,7 +280,7 @@ SECTIONS
*(.noinit.$RAM4*)
*(.noinit.$RamAHB16*)
. = ALIGN(4) ;
- } > RamAHB16
+ } > RamAHB16
/* NOINIT section for RamAHB_ETB16 */
.noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -288,13 +288,13 @@ SECTIONS
*(.noinit.$RAM5*)
*(.noinit.$RamAHB_ETB16*)
. = ALIGN(4) ;
- } > RamAHB_ETB16
+ } > RamAHB_ETB16
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc32
@@ -302,11 +302,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -320,4 +320,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
new file mode 100644
index 000000000..f94960f09
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
@@ -0,0 +1,37 @@
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ Project.AddSvdFile ("Cortex-M3.svd");
+ Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd");
+
+ Project.SetDevice ("LPC1857");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("50 MHz");
+
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetTracePortWidth (4);
+
+ //File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf");
+ File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf");
+}
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+ //
+ // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+ //
+ // Project.SetJLinkScript("./NXP_LPC1857JET256_TraceExample.pex");
+}
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 72c20e034..e6abecb4b 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#ifdef BOARD_TUD_RHPORT
@@ -43,25 +43,23 @@
//--------------------------------------------------------------------+
// USB Interrupt Handler
//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
#if PORT_SUPPORT_DEVICE(0)
- tud_int_handler(0);
+ tud_int_handler(0);
#endif
#if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
#if PORT_SUPPORT_DEVICE(1)
- tud_int_handler(1);
+ tud_int_handler(1);
#endif
#if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1);
+ tuh_int_handler(1, true);
#endif
}
@@ -69,26 +67,31 @@ void USB1_IRQHandler(void)
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
-
/* System configuration variables used by chip driver */
const uint32_t OscRateIn = 12000000;
const uint32_t ExtRateIn = 0;
// Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
#ifdef __USE_LPCOPEN
- extern void (* const g_pfnVectors[])(void);
+ extern void (*const g_pfnVectors[])(void);
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
- *pSCB_VTOR = (unsigned int) g_pfnVectors;
+ *pSCB_VTOR = (unsigned int) g_pfnVectors;
#endif
board_lpc18_pinmux();
- Chip_SetupXtalClocking();
+
+#ifdef TRACE_ETM
+ // Trace clock is limited to 60MHz, limit CPU clock to 120MHz
+ Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true);
+#else
+ // CPU clock max to 180 Mhz
+ Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
+#endif
+
}
-void board_init(void)
-{
+void board_init(void) {
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE
@@ -128,27 +131,22 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
// active low
return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
}
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
return Chip_UART_Read(UART_DEV, buf, len);
}
-int board_uart_write(void const * buf, int len)
-{
- uint8_t const* buf8 = (uint8_t const*) buf;
- for(int i=0; iDHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 5
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamPeriph32 */
.data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
*(.bss.$RamPeriph32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamPeriph32
+ } > RamPeriph32
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamPeriph32*)
. = ALIGN(4) ;
- } > RamPeriph32
+ } > RamPeriph32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc64
@@ -163,11 +163,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
new file mode 100644
index 000000000..6aaf1076d
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
@@ -0,0 +1,238 @@
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ Edit.SysVar (VAR_POWER_SAMPLING_SPEED, FREQ_100_KHZ);
+ Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+ Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC408x_7x_v0.7.svd");
+
+ Project.SetDevice ("LPC4088");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("50 MHz");
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetTracePortWidth (4);
+
+ // User settings
+ File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ea4088-quickstart/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+* TargetReset
+*
+* Function description
+* Replaces the default target device reset routine. Optional.
+*
+* Notes
+* This example demonstrates the usage when
+* debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+// unsigned int SP;
+// unsigned int PC;
+// unsigned int VectorTableAddr;
+//
+// Exec.Reset();
+//
+// VectorTableAddr = Elf.GetBaseAddr();
+//
+// if (VectorTableAddr != 0xFFFFFFFF) {
+//
+// Util.Log("Resetting Program.");
+//
+// SP = Target.ReadU32(VectorTableAddr);
+// Target.SetReg("SP", SP);
+//
+// PC = Target.ReadU32(VectorTableAddr + 4);
+// Target.SetReg("PC", PC);
+// }
+//}
+
+/*********************************************************************
+*
+* BeforeTargetReset
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetReset
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr == 0xFFFFFFFF) {
+ Util.Log("Project file error: failed to get program base");
+ } else {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
+
+/*********************************************************************
+*
+* DebugStart
+*
+* Function description
+* Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+* TargetConnect
+*
+* Function description
+* Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+* AfterTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* TargetDownload
+*
+* Function description
+* Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDownload
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr == 0xFFFFFFFF) {
+ Util.Log("Project file error: failed to get program base");
+ } else {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
+
+/*********************************************************************
+*
+* BeforeTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetHalt
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/lpc40/family.c
similarity index 60%
rename from hw/bsp/ea4088qs/ea4088qs.c
rename to hw/bsp/lpc40/family.c
index 7150ed393..d6c8ef32a 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/lpc40/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,89 +25,60 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
+#include "board.h"
//--------------------------------------------------------------------+
// USB Interrupt Handler
//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
#if CFG_TUD_ENABLED
- tud_int_handler(0);
+ tud_int_handler(0);
#endif
#if CFG_TUH_ENABLED
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
-#define LED_PORT 2
-#define LED_PIN 19
-
-#define BUTTON_PORT 2
-#define BUTTON_PIN 10
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
- // LED
- {2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
-
- // Button
- {2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
- // USB1 as Host
- {0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
- {0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
- {1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
- {1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
-// {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
-// {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
-
- // USB2 as Device
- {0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
- {0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
- {0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
-
- /* VBUS is not connected on this board, so leave the pin at default setting. */
- /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
// Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
#ifdef __USE_LPCOPEN
- extern void (* const g_pfnVectors[])(void);
+ extern void (*const g_pfnVectors[])(void);
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
- *pSCB_VTOR = (unsigned int) g_pfnVectors;
+ *pSCB_VTOR = (unsigned int) g_pfnVectors;
-#if __FPU_USED == 1
- fpuInit();
-#endif
+ #if __FPU_USED == 1
+ fpuInit();
+ #endif
#endif // __USE_LPCOPEN
Chip_IOCON_Init(LPC_IOCON);
Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
- /* CPU clock source starts with IRC */
- /* Enable PBOOST for CPU clock over 100MHz */
- Chip_SYSCTL_EnableBoost();
+#ifdef TRACE_ETM
+ const PINMUX_GRP_T trace_pinmux[] = {
+ {2, 2, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+ {2, 3, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+ {2, 4, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+ {2, 5, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+ {2, 6, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+ };
+ Chip_IOCON_SetPinMuxing(LPC_IOCON, trace_pinmux, sizeof(trace_pinmux) / sizeof(PINMUX_GRP_T));
+#endif
+
+ /* CPU clock source starts with IRC */
+ /* Enable PBOOST for CPU clock over 100MHz */
+ Chip_SYSCTL_EnableBoost();
Chip_SetupXtalClocking();
}
-void board_init(void)
-{
+void board_init(void) {
SystemCoreClockUpdate();
#if CFG_TUSB_OS == OPT_OS_NONE
@@ -129,15 +100,14 @@ void board_init(void)
// UART
//------------- USB -------------//
- Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
// Port1 as Host, Port2: Device
Chip_USB_Init();
enum {
USBCLK_DEVCIE = 0x12, // AHB + Device
- USBCLK_HOST = 0x19 , // AHB + OTG + Host
- USBCLK_ALL = 0x1B // Host + Device + OTG + AHB
+ USBCLK_HOST = 0x19, // AHB + OTG + Host
+ USBCLK_ALL = 0x1B // Host + Device + OTG + AHB
};
LPC_USB->OTGClkCtrl = USBCLK_ALL;
@@ -151,40 +121,37 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
}
-uint32_t board_button_read(void)
-{
- // active low
- return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+uint32_t board_button_read(void) {
+ return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
//return UART_ReceiveByte(BOARD_UART_PORT);
- (void) buf; (void) len;
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
//UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
- (void) buf; (void) len;
+ (void) buf;
+ (void) len;
return 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
new file mode 100644
index 000000000..56eb37a2f
--- /dev/null
+++ b/hw/bsp/lpc40/family.cmake
@@ -0,0 +1,102 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/../gcc/cr_startup_lpc40xx.c
+ ${SDK_DIR}/src/chip_17xx_40xx.c
+ ${SDK_DIR}/src/clock_17xx_40xx.c
+ ${SDK_DIR}/src/fpu_init.c
+ ${SDK_DIR}/src/gpio_17xx_40xx.c
+ ${SDK_DIR}/src/iocon_17xx_40xx.c
+ ${SDK_DIR}/src/sysctl_17xx_40xx.c
+ ${SDK_DIR}/src/sysinit_17xx_40xx.c
+ ${SDK_DIR}/src/uart_17xx_40xx.c
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -nostdlib
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ __USE_LPCOPEN
+ CORE_M4
+ CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\".data.$RAM2\"\)\)\)
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/inc
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+ ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+ ${TOP}/src/portable/ohci/ohci.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/lpc40/family.mk
similarity index 71%
rename from hw/bsp/ea4088qs/board.mk
rename to hw/bsp/lpc40/family.mk
index b325dfeb4..c11325890 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -1,12 +1,11 @@
DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-nostdlib \
-DCORE_M4 \
-D__USE_LPCOPEN \
@@ -16,31 +15,19 @@ CFLAGS += \
# mcu driver cause following warnings
CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
-
# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld
-
SRC_C += \
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
$(MCU_DIR)/src/chip_17xx_40xx.c \
$(MCU_DIR)/src/clock_17xx_40xx.c \
+ $(MCU_DIR)/src/fpu_init.c \
$(MCU_DIR)/src/gpio_17xx_40xx.c \
$(MCU_DIR)/src/iocon_17xx_40xx.c \
$(MCU_DIR)/src/sysctl_17xx_40xx.c \
$(MCU_DIR)/src/sysinit_17xx_40xx.c \
$(MCU_DIR)/src/uart_17xx_40xx.c \
- $(MCU_DIR)/src/fpu_init.c
INC += \
- $(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4088
-
-# flash using jlink
-flash: flash-jlink
+ $(TOP)/$(MCU_DIR)/inc \
+ $(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f80413c0
--- /dev/null
+++ b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< MFlashA512
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlashA512
@@ -135,7 +135,7 @@ SECTIONS
__exidx_end = .;
_etext = .;
-
+
/* DATA section for RamLoc40 */
.data_RAM2 : ALIGN(4)
@@ -216,7 +216,7 @@ SECTIONS
*(.bss.$RamLoc40*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
- } > RamLoc40
+ } > RamLoc40
/* BSS section for RamAHB32 */
.bss_RAM3 : ALIGN(4)
@@ -226,7 +226,7 @@ SECTIONS
*(.bss.$RamAHB32*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
- } > RamAHB32
+ } > RamAHB32
/* BSS section for RamAHB16 */
.bss_RAM4 : ALIGN(4)
@@ -236,7 +236,7 @@ SECTIONS
*(.bss.$RamAHB16*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM4 = .) ;
- } > RamAHB16
+ } > RamAHB16
/* BSS section for RamAHB_ETB16 */
.bss_RAM5 : ALIGN(4)
@@ -246,7 +246,7 @@ SECTIONS
*(.bss.$RamAHB_ETB16*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM5 = .) ;
- } > RamAHB_ETB16
+ } > RamAHB_ETB16
/* MAIN BSS SECTION */
.bss : ALIGN(4)
@@ -265,7 +265,7 @@ SECTIONS
*(.noinit.$RAM2*)
*(.noinit.$RamLoc40*)
. = ALIGN(4) ;
- } > RamLoc40
+ } > RamLoc40
/* NOINIT section for RamAHB32 */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -273,7 +273,7 @@ SECTIONS
*(.noinit.$RAM3*)
*(.noinit.$RamAHB32*)
. = ALIGN(4) ;
- } > RamAHB32
+ } > RamAHB32
/* NOINIT section for RamAHB16 */
.noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -281,7 +281,7 @@ SECTIONS
*(.noinit.$RAM4*)
*(.noinit.$RamAHB16*)
. = ALIGN(4) ;
- } > RamAHB16
+ } > RamAHB16
/* NOINIT section for RamAHB_ETB16 */
.noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -289,13 +289,13 @@ SECTIONS
*(.noinit.$RAM5*)
*(.noinit.$RamAHB_ETB16*)
. = ALIGN(4) ;
- } > RamAHB_ETB16
+ } > RamAHB_ETB16
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
- *(.noinit*)
+ *(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RamLoc32
@@ -303,11 +303,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -321,4 +321,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/lpc43/boards/ea4357/pca9532.c
similarity index 99%
rename from hw/bsp/ea4357/pca9532.c
rename to hw/bsp/lpc43/boards/ea4357/pca9532.c
index eae3805c2..150167cde 100644
--- a/hw/bsp/ea4357/pca9532.c
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.c
@@ -57,7 +57,7 @@ static uint16_t ledStateShadow = 0;
* Local Functions
*****************************************************************************/
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
+static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
{
I2CM_XFER_T i2cData;
@@ -75,7 +75,7 @@ static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
return SUCCESS;
}
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
+static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
{
I2CM_XFER_T i2cData;
@@ -181,7 +181,7 @@ uint16_t pca9532_getLedState (uint32_t shadow)
* A blinking LED may be reported as on or off depending on
* its state when reading the Input register.
*/
-
+
buf[0] = PCA9532_INPUT0;
I2CWrite(PCA9532_I2C_ADDR, buf, 1);
diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/lpc43/boards/ea4357/pca9532.h
similarity index 97%
rename from hw/bsp/ea4357/pca9532.h
rename to hw/bsp/lpc43/boards/ea4357/pca9532.h
index 7a7c6e145..f21c1ff09 100644
--- a/hw/bsp/ea4357/pca9532.h
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.h
@@ -48,7 +48,7 @@
#define KEY_MASK 0x000F
/*
- * MMC Card Detect and MMC Write Protect are mapped to LED4
+ * MMC Card Detect and MMC Write Protect are mapped to LED4
* and LED5 on the PCA9532. Please note that WP is active low.
*/
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
new file mode 100644
index 000000000..0858a97d5
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC43S67_M4)
+
+set(JLINK_DEVICE LPC43S67_M4)
+set(PYOCD_TARGET LPC43S67)
+set(NXPLINK_DEVICE LPC43S67:LPCXPRESSO43S67)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4367.ld)
+
+function(update_board TARGET)
+ # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
new file mode 100644
index 000000000..4dd90fe29
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
@@ -0,0 +1,73 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_LPCXPRESSO43S67_H_
+#define _BOARD_LPCXPRESSO43S67_H_
+
+// Note: For USB Host demo, install JP4
+// WARNING: don't install JP4 when running as device
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED Red
+#define LED_PORT 3
+#define LED_PIN 7
+#define LED_STATE_ON 0
+
+// ISP Button (SW2)
+#define BUTTON_PORT 0
+#define BUTTON_PIN 7
+#define BUTTON_STATE_ACTIVE 0
+
+#define UART_DEV LPC_USART0
+
+static const PINMUX_GRP_T pinmuxing[] = {
+ // LEDs P6_11 as GPIO3[7]
+ { 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
+
+ // Button P2_7 as GPIO0[7]
+ { 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
+
+ // UART
+ { 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
+ { 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+ // USB0
+ //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
+
+ // USB 1
+ //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
+ //{ 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+ {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
new file mode 100644
index 000000000..eeb02e311
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
@@ -0,0 +1,6 @@
+LD_FILE = $(BOARD_PATH)/lpc4367.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC43S67_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
new file mode 100644
index 000000000..c03149b8b
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
@@ -0,0 +1,402 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC4337
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on Aug 14, 2023, 3:36:29 PM
+ */
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+ MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+ RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+ RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+ /* Define a symbol for the top of each memory region */
+ __base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
+ __base_Flash = 0x1a000000 ; /* Flash */
+ __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+ __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+ __base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
+ __base_Flash2 = 0x1b000000 ; /* Flash2 */
+ __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+ __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+ __base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+ __base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
+ __base_RAM2 = 0x10080000 ; /* RAM2 */
+ __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+ __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+ __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
+ __base_RAM3 = 0x20000000 ; /* RAM3 */
+ __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
+ __base_RAM4 = 0x20008000 ; /* RAM4 */
+ __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+ __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+ __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
+ __base_RAM5 = 0x2000c000 ; /* RAM5 */
+ __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+ __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ .text_Flash2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.text_Flash2) /* for compatibility with previous releases */
+ *(.text_MFlashB512) /* for compatibility with previous releases */
+ *(.text.$Flash2)
+ *(.text.$MFlashB512)
+ *(.text_Flash2.*) /* for compatibility with previous releases */
+ *(.text_MFlashB512.*) /* for compatibility with previous releases */
+ *(.text.$Flash2.*)
+ *(.text.$MFlashB512.*)
+ *(.rodata.$Flash2)
+ *(.rodata.$MFlashB512)
+ *(.rodata.$Flash2.*)
+ *(.rodata.$MFlashB512.*) } > MFlashB512
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ LONG(LOADADDR(.data_RAM4));
+ LONG( ADDR(.data_RAM4));
+ LONG( SIZEOF(.data_RAM4));
+ LONG(LOADADDR(.data_RAM5));
+ LONG( ADDR(.data_RAM5));
+ LONG( SIZEOF(.data_RAM5));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ LONG( ADDR(.bss_RAM4));
+ LONG( SIZEOF(.bss_RAM4));
+ LONG( ADDR(.bss_RAM5));
+ LONG( SIZEOF(.bss_RAM5));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+ } > MFlashA512
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlashA512
+
+ .ARM.exidx : ALIGN(4)
+ {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > MFlashA512
+
+ _etext = .;
+
+ /* DATA section for RamLoc40 */
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM2 = .) ;
+ PROVIDE(__start_data_RamLoc40 = .) ;
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamLoc40)
+ *(.data.$RAM2)
+ *(.data.$RamLoc40)
+ *(.data.$RAM2.*)
+ *(.data.$RamLoc40.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM2 = .) ;
+ PROVIDE(__end_data_RamLoc40 = .) ;
+ } > RamLoc40 AT>MFlashA512
+
+ /* DATA section for RamAHB32 */
+
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM3 = .) ;
+ PROVIDE(__start_data_RamAHB32 = .) ;
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM3)
+ *(.data.$RamAHB32)
+ *(.data.$RAM3.*)
+ *(.data.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM3 = .) ;
+ PROVIDE(__end_data_RamAHB32 = .) ;
+ } > RamAHB32 AT>MFlashA512
+
+ /* DATA section for RamAHB16 */
+
+ .data_RAM4 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM4 = .) ;
+ PROVIDE(__start_data_RamAHB16 = .) ;
+ *(.ramfunc.$RAM4)
+ *(.ramfunc.$RamAHB16)
+ *(.data.$RAM4)
+ *(.data.$RamAHB16)
+ *(.data.$RAM4.*)
+ *(.data.$RamAHB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM4 = .) ;
+ PROVIDE(__end_data_RamAHB16 = .) ;
+ } > RamAHB16 AT>MFlashA512
+
+ /* DATA section for RamAHB_ETB16 */
+
+ .data_RAM5 : ALIGN(4)
+ {
+ FILL(0xff)
+ PROVIDE(__start_data_RAM5 = .) ;
+ PROVIDE(__start_data_RamAHB_ETB16 = .) ;
+ *(.ramfunc.$RAM5)
+ *(.ramfunc.$RamAHB_ETB16)
+ *(.data.$RAM5)
+ *(.data.$RamAHB_ETB16)
+ *(.data.$RAM5.*)
+ *(.data.$RamAHB_ETB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_data_RAM5 = .) ;
+ PROVIDE(__end_data_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT>MFlashA512
+
+ /* MAIN DATA SECTION */
+ .uninit_RESERVED (NOLOAD) : ALIGN(4)
+ {
+ _start_uninit_RESERVED = .;
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc32 AT> RamLoc32
+
+ /* Main DATA section (RamLoc32) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ PROVIDE(__start_data_RAM = .) ;
+ PROVIDE(__start_data_RamLoc32 = .) ;
+ *(vtable)
+ *(.ramfunc*)
+ KEEP(*(CodeQuickAccess))
+ KEEP(*(DataQuickAccess))
+ *(RamFunction)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ PROVIDE(__end_data_RAM = .) ;
+ PROVIDE(__end_data_RamLoc32 = .) ;
+ } > RamLoc32 AT>MFlashA512
+
+ /* BSS section for RamLoc40 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM2 = .) ;
+ PROVIDE(__start_bss_RamLoc40 = .) ;
+ *(.bss.$RAM2)
+ *(.bss.$RamLoc40)
+ *(.bss.$RAM2.*)
+ *(.bss.$RamLoc40.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM2 = .) ;
+ PROVIDE(__end_bss_RamLoc40 = .) ;
+ } > RamLoc40 AT> RamLoc40
+
+ /* BSS section for RamAHB32 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM3 = .) ;
+ PROVIDE(__start_bss_RamAHB32 = .) ;
+ *(.bss.$RAM3)
+ *(.bss.$RamAHB32)
+ *(.bss.$RAM3.*)
+ *(.bss.$RamAHB32.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM3 = .) ;
+ PROVIDE(__end_bss_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* BSS section for RamAHB16 */
+ .bss_RAM4 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM4 = .) ;
+ PROVIDE(__start_bss_RamAHB16 = .) ;
+ *(.bss.$RAM4)
+ *(.bss.$RamAHB16)
+ *(.bss.$RAM4.*)
+ *(.bss.$RamAHB16.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM4 = .) ;
+ PROVIDE(__end_bss_RamAHB16 = .) ;
+ } > RamAHB16 AT> RamAHB16
+
+ /* BSS section for RamAHB_ETB16 */
+ .bss_RAM5 : ALIGN(4)
+ {
+ PROVIDE(__start_bss_RAM5 = .) ;
+ PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
+ *(.bss.$RAM5)
+ *(.bss.$RamAHB_ETB16)
+ *(.bss.$RAM5.*)
+ *(.bss.$RamAHB_ETB16.*)
+ . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+ PROVIDE(__end_bss_RAM5 = .) ;
+ PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ PROVIDE(__start_bss_RAM = .) ;
+ PROVIDE(__start_bss_RamLoc32 = .) ;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(__end_bss_RAM = .) ;
+ PROVIDE(__end_bss_RamLoc32 = .) ;
+ PROVIDE(end = .);
+ } > RamLoc32 AT> RamLoc32
+
+ /* NOINIT section for RamLoc40 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM2 = .) ;
+ PROVIDE(__start_noinit_RamLoc40 = .) ;
+ *(.noinit.$RAM2)
+ *(.noinit.$RamLoc40)
+ *(.noinit.$RAM2.*)
+ *(.noinit.$RamLoc40.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM2 = .) ;
+ PROVIDE(__end_noinit_RamLoc40 = .) ;
+ } > RamLoc40 AT> RamLoc40
+
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM3 = .) ;
+ PROVIDE(__start_noinit_RamAHB32 = .) ;
+ *(.noinit.$RAM3)
+ *(.noinit.$RamAHB32)
+ *(.noinit.$RAM3.*)
+ *(.noinit.$RamAHB32.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM3 = .) ;
+ PROVIDE(__end_noinit_RamAHB32 = .) ;
+ } > RamAHB32 AT> RamAHB32
+
+ /* NOINIT section for RamAHB16 */
+ .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM4 = .) ;
+ PROVIDE(__start_noinit_RamAHB16 = .) ;
+ *(.noinit.$RAM4)
+ *(.noinit.$RamAHB16)
+ *(.noinit.$RAM4.*)
+ *(.noinit.$RamAHB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM4 = .) ;
+ PROVIDE(__end_noinit_RamAHB16 = .) ;
+ } > RamAHB16 AT> RamAHB16
+
+ /* NOINIT section for RamAHB_ETB16 */
+ .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ {
+ PROVIDE(__start_noinit_RAM5 = .) ;
+ PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
+ *(.noinit.$RAM5)
+ *(.noinit.$RamAHB_ETB16)
+ *(.noinit.$RAM5.*)
+ *(.noinit.$RamAHB_ETB16.*)
+ . = ALIGN(4) ;
+ PROVIDE(__end_noinit_RAM5 = .) ;
+ PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
+ } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ PROVIDE(__start_noinit_RAM = .) ;
+ PROVIDE(__start_noinit_RamLoc32 = .) ;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ PROVIDE(__end_noinit_RAM = .) ;
+ PROVIDE(__end_noinit_RamLoc32 = .) ;
+ } > RamLoc32 AT> RamLoc32
+
+ PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+ PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+ /* ## Create checksum value (used in startup) ## */
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+ ) );
+
+ /* Provide basic symbols giving location and size of main text
+ * block, including initial values of RW data sections. Note that
+ * these will need extending to give a complete picture with
+ * complex images (e.g multiple Flash banks).
+ */
+ _image_start = LOADADDR(.text);
+ _image_end = LOADADDR(.data) + SIZEOF(.data);
+ _image_size = _image_end - _image_start;
+}
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/lpc43/family.c
similarity index 73%
rename from hw/bsp/ea4357/ea4357.c
rename to hw/bsp/lpc43/family.c
index f88d3b89e..8be729f7d 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/lpc43/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,34 +24,20 @@
* This file is part of the TinyUSB stack.
*/
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
#include "chip.h"
-#include "../board.h"
-#include "pca9532.h"
-#define UART_DEV LPC_USART0
-#define UART_PORT 0x0f
-#define UART_PIN_TX 10
-#define UART_PIN_RX 11
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
-// P9_1 joystick down
-#define BUTTON_PORT 4
-#define BUTTON_PIN 13
-
-//static const struct {
-// uint8_t mux_port;
-// uint8_t mux_pin;
-//
-// uint8_t gpio_port;
-// uint8_t gpio_pin;
-//}buttons[] =
-//{
-// {0x0a, 3, 4, 10 }, // Joystick up
-// {0x09, 1, 4, 13 }, // Joystick down
-// {0x0a, 2, 4, 9 }, // Joystick left
-// {0x09, 0, 4, 12 }, // Joystick right
-// {0x0a, 1, 4, 8 }, // Joystick press
-// {0x02, 7, 0, 7 }, // SW6
-//};
+#include "bsp/board_api.h"
+#include "board.h"
#ifdef BOARD_TUD_RHPORT
#define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
@@ -65,56 +51,46 @@
#define PORT_SUPPORT_HOST(_n) 0
#endif
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
/* System configuration variables used by chip driver */
const uint32_t OscRateIn = 12000000;
const uint32_t ExtRateIn = 0;
-static const PINMUX_GRP_T pinmuxing[] =
-{
- // Button ( Joystick down )
- {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
-
- // UART
- {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
- {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
-
- // USB
-};
-
-/* Pin clock mux values, re-used structure, value in first index is meaningless */
-static const PINMUX_GRP_T pinclockmuxing[] =
-{
- {0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
- {0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
- {0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
- {0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-};
+/*------------------------------------------------------------------*/
+/* BOARD API
+ *------------------------------------------------------------------*/
// Invoked by startup code
void SystemInit(void)
{
#ifdef __USE_LPCOPEN
- extern void (* const g_pfnVectors[])(void);
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+
+#ifdef __ICCARM__
+ extern void *__vector_table;
+ *pSCB_VTOR = (unsigned int) &__vector_table;
+
+#elif defined(__ARMCC_VERSION)
+ extern void *__Vectors;
+ *pSCB_VTOR = (unsigned int) &__Vectors;
+
+#else // other compoiler using cr_startup_lpc43xx.c
+ extern void (* const g_pfnVectors[])(void);
*pSCB_VTOR = (unsigned int) g_pfnVectors;
+#endif
#if __FPU_USED == 1
fpuInit();
#endif
-#endif // __USE_LPCOPEN
- /* Setup system level pin muxing */
- Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+#endif
- /* Clock pins only, group field not used */
- for (int i = 0; i <(int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
- {
- Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
- }
+ /* Setup system level pin muxing */
+ Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+// /* Clock pins only, group field not used */
+// for ( int i = 0; i < (int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++ ) {
+// Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+// }
Chip_SetupXtalClocking();
}
@@ -133,13 +109,16 @@ void board_init(void)
Chip_GPIO_Init(LPC_GPIO_PORT);
+#ifdef __PCA9532C_H
// LED via pca9532 I2C
Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
Chip_I2C_Init(I2C0);
Chip_I2C_SetClockRate(I2C0, 100000);
Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
-
pca9532_init();
+#else
+ Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
+#endif
// Button
Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
@@ -234,7 +213,7 @@ void USB0_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
@@ -245,7 +224,7 @@ void USB1_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1);
+ tuh_int_handler(1, true);
#endif
}
@@ -253,34 +232,37 @@ void USB1_IRQHandler(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
- if (state)
- {
- pca9532_setLeds( LED1, 0 );
- }else
- {
- pca9532_setLeds( 0, LED1);
+void board_led_write(bool state) {
+ #ifdef __PCA9532C_H
+ if ( state ) {
+ pca9532_setLeds(LED1, 0);
+ } else {
+ pca9532_setLeds(0, LED1);
}
+ #else
+ Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : !LED_STATE_ON);
+ #endif
}
-uint32_t board_button_read(void)
-{
- // active low
- return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+uint32_t board_button_read(void) {
+ return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ if ( max_len < 16 ) return 0;
+ uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+ Chip_IAP_ReadUID(id32);
+ return 16;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
return Chip_UART_Read(UART_DEV, buf, len);
}
-int board_uart_write(void const * buf, int len)
-{
- uint8_t const* buf8 = (uint8_t const*) buf;
- for(int i=0; iDHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif()
+
+ add_library(${BOARD_TARGET} STATIC
+ # driver
+ ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+ ${SDK_DIR}/drivers/common/fsl_common_arm.c
+ ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+ ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+ # mcu
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+ )
+
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+ BOARD_TUD_RHPORT=${PORT}
+ BOARD_TUH_RHPORT=${HOST_PORT}
+ )
+ # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+ if (PORT EQUAL 1)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+ CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ )
+ else ()
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+ BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ )
+ endif ()
+
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${TOP}/lib/sct_neopixel
+ # driver
+ ${SDK_DIR}/drivers/common
+ ${SDK_DIR}/drivers/flexcomm
+ ${SDK_DIR}/drivers/lpc_iocon
+ ${SDK_DIR}/drivers/lpc_gpio
+ ${SDK_DIR}/drivers/lpuart
+ ${SDK_DIR}/drivers/sctimer
+ # mcu
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+ endif ()
+
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${LD_FILE_GNU}"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+
+ # https://github.com/gsteiert/sct_neopixel/pull/1
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+ COMPILE_FLAGS "-Wno-unused-parameter")
+ endif ()
+
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+ #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 39111d1ad..46a5f7930 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -1,22 +1,18 @@
SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
- -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
ifeq ($(PORT), 1)
$(info "PORT1 High Speed")
CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
+ CFLAGS += -DBOARD_TUD_RHPORT=1
# LPC55 Highspeed Port1 can only write to USB_SRAM region
CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
else
@@ -36,11 +32,12 @@ SRC_C += \
$(MCU_DIR)/drivers/fsl_reset.c \
$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
- $(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+ $(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+ $(SDK_DIR)/drivers/common/fsl_common_arm.c
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
@@ -49,6 +46,3 @@ INC += \
$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..fc0ab1f2d
--- /dev/null
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<= __HeapLimit, "region m_data overflowed with stack and heap")
}
-
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
new file mode 100644
index 000000000..3324ce888
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -0,0 +1,19 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+ set(PORT 1)
+endif()
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_LPC55S69JBD100_cm33_core0
+ )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
new file mode 100644
index 000000000..b3d0c3349
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT LPC55S28)
+set(MCU_CORE LPC55S28)
+
+set(JLINK_DEVICE LPC55S28)
+set(PYOCD_TARGET LPC55S28)
+set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+ set(PORT 1)
+endif()
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_LPC55S28JBD100
+ )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
new file mode 100644
index 000000000..b52ec2f9d
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -0,0 +1,17 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69_M33_0)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+ set(PORT 1)
+endif()
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_LPC55S69JBD100_cm33_core0
+ )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake
new file mode 100644
index 000000000..fd7cb6de6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ CPU_LPC55S69JBD100_cm33_core0
+ # port 1 is highspeed
+ # BOARD_TUD_RHPORT=1
+ )
+endfunction()
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 5b6c56dd3..0fd85988a 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@@ -24,15 +24,18 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_power.h"
#include "fsl_iocon.h"
#include "fsl_usart.h"
+
+#ifdef NEOPIXEL_PIN
#include "fsl_sctimer.h"
#include "sct_neopixel.h"
+#endif
#ifdef BOARD_TUD_RHPORT
#define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
new file mode 100644
index 000000000..dce197b2d
--- /dev/null
+++ b/hw/bsp/lpc55/family.cmake
@@ -0,0 +1,159 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
+
+if (NOT DEFINED PORT)
+ set(PORT 0)
+endif()
+
+# Host port will be the other port if available
+set(HOST_PORT $)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (TARGET ${BOARD_TARGET})
+ return()
+ endif ()
+
+ add_library(${BOARD_TARGET} STATIC
+ # driver
+ ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+ ${SDK_DIR}/drivers/common/fsl_common_arm.c
+ ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+ ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+ # mcu
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+ )
+
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+ BOARD_TUD_RHPORT=${PORT}
+ BOARD_TUH_RHPORT=${HOST_PORT}
+ )
+ # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+ if (PORT EQUAL 1)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+ CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ )
+ else ()
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+ BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+ )
+ endif ()
+
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${TOP}/lib/sct_neopixel
+ # driver
+ ${SDK_DIR}/drivers/common
+ ${SDK_DIR}/drivers/flexcomm
+ ${SDK_DIR}/drivers/lpc_iocon
+ ${SDK_DIR}/drivers/lpc_gpio
+ ${SDK_DIR}/drivers/lpuart
+ ${SDK_DIR}/drivers/sctimer
+ # mcu
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+ endif ()
+
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${LD_FILE_GNU}"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ # external driver
+ ${TOP}/lib/sct_neopixel/sct_neopixel.c
+ )
+
+ # https://github.com/gsteiert/sct_neopixel/pull/1
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+ COMPILE_FLAGS "-Wno-unused-parameter")
+ endif ()
+
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+ #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 9d6702b94..a87fa5acf 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,19 +1,15 @@
UF2_FAMILY_ID = 0x2abc77ec
SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += lib/sct_neopixel $(SDK_DIR)
+DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
# Default to Highspeed PORT1
PORT ?= 1
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m33 \
- -mfloat-abi=hard \
- -mfpu=fpv5-sp-d16 \
-DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
-DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-DBOARD_TUD_RHPORT=$(PORT)
@@ -51,7 +47,7 @@ SRC_C += \
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/sct_neopixel \
- $(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(SDK_DIR)/drivers/common \
@@ -63,6 +59,3 @@ INC += \
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
deleted file mode 100644
index be6d2ed52..000000000
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0 \
- -nostdlib \
- -DCORE_M0 \
- -D__USE_LPCOPEN \
- -DCFG_EXAMPLE_MSC_READONLY \
- -DCFG_EXAMPLE_VIDEO_READONLY \
- -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
- -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
- -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u37.ld
-
-SRC_C += \
- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
- $(MCU_DIR)/../gcc/cr_startup_lpc11xx.c \
- $(MCU_DIR)/src/chip_11xx.c \
- $(MCU_DIR)/src/clock_11xx.c \
- $(MCU_DIR)/src/gpio_11xx_1.c \
- $(MCU_DIR)/src/iocon_11xx.c \
- $(MCU_DIR)/src/sysctl_11xx.c \
- $(MCU_DIR)/src/sysinit_11xx.c
-
-INC += \
- $(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U37/401
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
- pyocd flash -t lpc11u37 $<
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
deleted file mode 100644
index 922414f82..000000000
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
- -nostdlib \
- -DCORE_M0PLUS \
- -D__VTOR_PRESENT=0 \
- -D__USE_LPCOPEN \
- -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
- -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
- -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u68.ld
-
-SRC_C += \
- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
- $(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
- $(MCU_DIR)/src/chip_11u6x.c \
- $(MCU_DIR)/src/clock_11u6x.c \
- $(MCU_DIR)/src/gpio_11u6x.c \
- $(MCU_DIR)/src/iocon_11u6x.c \
- $(MCU_DIR)/src/syscon_11u6x.c \
- $(MCU_DIR)/src/sysinit_11u6x.c
-
-INC += \
- $(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U68
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
- pyocd flash -t lpc11u68 $<
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
deleted file mode 100644
index b0d885866..000000000
--- a/hw/bsp/mbed1768/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
- -flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
- -nostdlib \
- -DCORE_M3 \
- -D__USE_LPCOPEN \
- -DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
- -DRTC_EV_SUPPORT=0
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
-
-SRC_C += \
- src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
- $(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
- $(MCU_DIR)/src/chip_17xx_40xx.c \
- $(MCU_DIR)/src/clock_17xx_40xx.c \
- $(MCU_DIR)/src/gpio_17xx_40xx.c \
- $(MCU_DIR)/src/iocon_17xx_40xx.c \
- $(MCU_DIR)/src/sysctl_17xx_40xx.c \
- $(MCU_DIR)/src/sysinit_17xx_40xx.c \
- $(MCU_DIR)/src/uart_17xx_40xx.c
-
-INC += \
- $(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1768
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
- pyocd flash -t lpc1768 $<
-
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..fc0ab1f2d
--- /dev/null
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<
+ )
+ target_sources(${TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+ )
+endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h
new file mode 100644
index 000000000..eae98bfa7
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO GPIO3
+#define LED_CLK kCLOCK_Gpio3
+#define LED_PIN 4 // red
+#define LED_STATE_ON 0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO GPIO0
+#define BUTTON_CLK kCLOCK_Gpio0
+#define BUTTON_PIN 6
+#define BUTTON_STATE_ACTIVE 0
+
+// UART
+#define UART_DEV LPUART4
+
+static inline void board_uart_init_clock(void) {
+ /* attach FRO 12M to FLEXCOMM4 */
+ CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+ CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+ RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
new file mode 100644
index 000000000..aaad5e73e
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CFLAGS += -DCPU_MCXN947VDF_cm33_core0
+
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+ /*!< Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+ /*!< Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+ /*!< Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+ /*!< Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
+
+ /*!< Set up PLL0 */
+ const pll_setup_t pll0Setup = {
+ .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+ .pllndiv = SCG_APLLNDIV_NDIV(8U),
+ .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+ .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+ .pllRate = 150000000U
+ };
+ CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
+ CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+ /*!< Enable SCG clock */
+ CLOCK_EnableClock(kCLOCK_Scg);
+
+ CLOCK_SetupExtClocking(24000000U);
+ CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
+
+ /*!< Set up PLL1 */
+ const pll_setup_t pll1Setup = {
+ .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+ .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+ .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+ .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+ .pllRate = 100000000U
+ };
+ CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
+ CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
new file mode 100644
index 000000000..acc2f3e45
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+ slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+ invert_input: normal}
+ - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+ slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+ - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
+ pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+ /* Enables the clock for PORT1: Enables clock */
+ CLOCK_EnableClock(kCLOCK_Port1);
+ /* Enables the clock for PORT3: Enables clock */
+ CLOCK_EnableClock(kCLOCK_Port3);
+
+ const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+ kPORT_PullDisable,
+ /* Low internal pull resistor value is selected. */
+ kPORT_LowPullResistor,
+ /* Fast slew rate is configured */
+ kPORT_FastSlewRate,
+ /* Passive input filter is disabled */
+ kPORT_PassiveFilterDisable,
+ /* Open drain output is disabled */
+ kPORT_OpenDrainDisable,
+ /* Low drive strength is configured */
+ kPORT_LowDriveStrength,
+ /* Pin is configured as FC4_P0 */
+ kPORT_MuxAlt2,
+ /* Digital input enabled */
+ kPORT_InputBufferEnable,
+ /* Digital input is not inverted */
+ kPORT_InputNormal,
+ /* Pin Control Register fields [15:0] are not locked */
+ kPORT_UnlockRegister};
+ /* PORT1_8 (pin A1) is configured as FC4_P0 */
+ PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+ const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+ kPORT_PullDisable,
+ /* Low internal pull resistor value is selected. */
+ kPORT_LowPullResistor,
+ /* Fast slew rate is configured */
+ kPORT_FastSlewRate,
+ /* Passive input filter is disabled */
+ kPORT_PassiveFilterDisable,
+ /* Open drain output is disabled */
+ kPORT_OpenDrainDisable,
+ /* Low drive strength is configured */
+ kPORT_LowDriveStrength,
+ /* Pin is configured as FC4_P1 */
+ kPORT_MuxAlt2,
+ /* Digital input enabled */
+ kPORT_InputBufferEnable,
+ /* Digital input is not inverted */
+ kPORT_InputNormal,
+ /* Pin Control Register fields [15:0] are not locked */
+ kPORT_UnlockRegister};
+ /* PORT1_9 (pin B1) is configured as FC4_P1 */
+ PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+ const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
+ kPORT_PullDisable,
+ /* Low internal pull resistor value is selected. */
+ kPORT_LowPullResistor,
+ /* Fast slew rate is configured */
+ kPORT_FastSlewRate,
+ /* Passive input filter is disabled */
+ kPORT_PassiveFilterDisable,
+ /* Open drain output is disabled */
+ kPORT_OpenDrainDisable,
+ /* Low drive strength is configured */
+ kPORT_LowDriveStrength,
+ /* Pin is configured as PIO3_4 */
+ kPORT_MuxAlt0,
+ /* Digital input enabled */
+ kPORT_InputBufferEnable,
+ /* Digital input is not inverted */
+ kPORT_InputNormal,
+ /* Pin Control Register fields [15:0] are not locked */
+ kPORT_UnlockRegister};
+ /* PORT3_4 (pin F14) is configured as PIO3_4 */
+ PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+ JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+ return 0;
+}
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
new file mode 100644
index 000000000..8672ca63f
--- /dev/null
+++ b/hw/bsp/mcx/family.c
@@ -0,0 +1,245 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board_api.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+#include "board.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+
+#ifdef BOARD_TUD_RHPORT
+ #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
+#else
+ #define PORT_SUPPORT_DEVICE(_n) 0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+ #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
+#else
+ #define PORT_SUPPORT_HOST(_n) 0
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_FS_IRQHandler(void)
+{
+ tud_int_handler(0);
+}
+
+void USB1_HS_IRQHandler(void)
+{
+ tud_int_handler(1);
+}
+
+void board_init(void)
+{
+ BOARD_InitPins();
+ BOARD_InitBootClocks();
+ CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+
+ // 1ms tick timer
+ SysTick_Config(SystemCoreClock / 1000);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+ // LED
+ CLOCK_EnableClock(LED_CLK);
+ gpio_pin_config_t led_config = {
+ kGPIO_DigitalOutput,
+ 0,
+ };
+ GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
+ board_led_write(0);
+
+#ifdef NEOPIXEL_PIN
+ // Neopixel
+ static uint32_t pixelData[NEOPIXEL_NUMBER];
+ IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
+
+ sctpix_init(NEOPIXEL_TYPE);
+ sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
+ sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
+ sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
+ sctpix_show();
+#endif
+
+ // Button
+#ifdef BUTTON_GPIO
+ CLOCK_EnableClock(BUTTON_CLK);
+ gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+ GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+ // UART
+// IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
+// IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
+
+ // Enable UART when debug log is on
+ board_uart_init_clock();
+
+ lpuart_config_t uart_config;
+ LPUART_GetDefaultConfig(&uart_config);
+ uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+ uart_config.enableTx = true;
+ uart_config.enableRx = true;
+ LPUART_Init(UART_DEV, &uart_config, 12000000u);
+#endif
+
+ // USB VBUS
+ /* PORT0 PIN22 configured as USB0_VBUS */
+
+#if PORT_SUPPORT_DEVICE(0)
+ // Port0 is Full Speed
+
+ CLOCK_AttachClk(kCLK_48M_to_USB0);
+ CLOCK_EnableClock(kCLOCK_Usb0Ram);
+ CLOCK_EnableClock(kCLOCK_Usb0Fs);
+ CLOCK_EnableUsbfsClock();
+#endif
+
+#if PORT_SUPPORT_DEVICE(1)
+ // Port1 is High Speed
+
+ // Power
+ SPC0->ACTIVE_VDELAY = 0x0500;
+ /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
+ SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+ SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+ SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+ /* Wait until it is done */
+ while (SPC0->SC & SPC_SC_BUSY_MASK) {}
+ if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+ SCG0->TRIM_LOCK = 0x5a5a0001U;
+ SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+ /* wait LDO ready */
+ while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
+ }
+ SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+ SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+ /* xtal = 20 ~ 30MHz */
+ SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+ SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+ while (1) {
+ if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+ break;
+ }
+ }
+
+ // Clock
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+ CLOCK_EnableClock(kCLOCK_UsbHs);
+ CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+ CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
+ CLOCK_EnableUsbhsClock();
+
+ // USB PHY
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+ USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+ // Enable PHY support for Low speed device + LS via FS Hub
+ USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+ // Enable all power for normal operation
+ USBPHY->PWD = 0;
+
+ // TX Timing
+ uint32_t phytx = USBPHY->TX;
+ phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+ phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
+ //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+ USBPHY->TX = phytx;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+ GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+
+#ifdef NEOPIXEL_PIN
+ if (state) {
+ sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
+ sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
+ } else {
+ sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
+ sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
+ }
+ sctpix_show();
+#endif
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_GPIO
+ return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+ (void) buf; (void) len;
+ return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+ LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+ return len;
+#else
+ (void) buf; (void) len;
+ return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+ return system_ticks;
+}
+#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
new file mode 100644
index 000000000..b3a4a846e
--- /dev/null
+++ b/hw/bsp/mcx/family.cmake
@@ -0,0 +1,110 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ # external driver
+ #lib/sct_neopixel/sct_neopixel.c
+
+ # driver
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+ # mcu
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+ ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+ )
+ # target_compile_definitions(${BOARD_TARGET} PUBLIC
+ # )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ # driver
+ # mcu
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${SDK_DIR}/devices/${MCU_VARIANT}
+ ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+ )
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+ ${TOP}/src/portable/chipidea/$
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+ #family_flash_nxplink(${TARGET})
+ #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
new file mode 100644
index 000000000..e384aa8eb
--- /dev/null
+++ b/hw/bsp/mcx/family.mk
@@ -0,0 +1,49 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+
+# Default to Highspeed PORT1
+PORT ?= 1
+
+CFLAGS += \
+ -flto \
+ -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+ -DBOARD_TUD_RHPORT=$(PORT) \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+ifeq ($(PORT), 1)
+ $(info "PORT1 High Speed")
+ CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
+else
+ $(info "PORT0 Full Speed")
+ CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+ SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
+endif
+
+SRC_C += \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
+ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+
+INC += \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
new file mode 100644
index 000000000..bda3daf91
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+ -DHSE_VALUE=8000000
+
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = stm32f411ve
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
similarity index 66%
rename from hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
rename to hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
index 7ee40671c..796ed04f6 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
@@ -1,39 +1,35 @@
/*
-*****************************************************************************
-**
-
-** File : LinkerScript.ld
-**
-** Abstract : Linker script for STM32H743XIHx Device with
-** 2048KByte FLASH, 128KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-**
-** Distribution: The file is distributed as is, without any warranty
-** of any kind.
-**
-** (c)Copyright Ac6.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Ac6 permit registered System Workbench for MCU users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
-_estack = 0x20020000; /* end of RAM */
+_estack = 0x2001FFFF; /* end of RAM */
+
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
@@ -41,12 +37,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
-DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
}
/* Define output sections */
@@ -118,7 +110,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -127,9 +119,9 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
- } >DTCMRAM AT> FLASH
+ } >RAM AT> FLASH
+
-
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -144,7 +136,7 @@ SECTIONS
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
- } >DTCMRAM
+ } >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
@@ -155,9 +147,9 @@ SECTIONS
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
- } >DTCMRAM
+ } >RAM
+
-
/* Remove information from the standard libraries */
/DISCARD/ :
@@ -169,5 +161,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
new file mode 100644
index 000000000..a4bd95fab
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
@@ -0,0 +1,182 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* WeAct BluePillPlus with MM32F3273G6P */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+ tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+ /* Select USBCLK source */
+ // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+ RCC->CFGR &= ~(0x3 << 22);
+ RCC->CFGR |= (0x1 << 22);
+
+ /* Enable USB clock */
+ RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+// usb clock
+ USB_DeviceClockInit();
+
+ if ( SysTick_Config(SystemCoreClock / 1000) )
+ {
+ while ( 1 )
+ ;
+ }
+ NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+ // LED on PB2
+ GPIO_InitTypeDef GPIO_InitStruct;
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, ENABLE);
+ GPIO_StructInit(&GPIO_InitStruct);
+
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ board_led_write(true);
+
+ // KEY on PA0
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+ GPIO_StructInit(&GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ // UART
+ UART_InitTypeDef UART_InitStruct;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); //
+ //UART initialset
+
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+ UART_StructInit(&UART_InitStruct);
+ UART_InitStruct.UART_BaudRate = baudrate;
+ UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+ UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit
+ UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit
+ UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control
+ UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode
+
+ UART_Init(UART1, &UART_InitStruct); //initial uart 1
+ UART_Cmd(UART1, ENABLE); //enable uart 1
+
+ //UART1_TX GPIOA.9
+ GPIO_StructInit(&GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ //UART1_RX GPIOA.10
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+ state ? (GPIO_ResetBits(GPIOB, GPIO_Pin_2)) : (GPIO_SetBits(GPIOB, GPIO_Pin_2));
+}
+
+uint32_t board_button_read (void)
+{
+ uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_SET;
+ return key;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+ const char *buff = buf;
+ while ( len )
+ {
+ while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+ ; //The loop is sent until it is finished
+ UART1->TDR = (*buff & 0xFF);
+ buff++;
+ len--;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+ return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
index b7663926f..a0d92d1c7 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -1,6 +1,10 @@
+CFLAGS += \
+ -DHSE_VALUE=8000000
+
LD_FILE = $(BOARD_PATH)/flash.ld
SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
# For flash-jlink target
#JLINK_DEVICE = stm32f411ve
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
index 0b45ee7bd..796ed04f6 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 MM32 SE TEAM
@@ -110,7 +110,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -121,7 +121,7 @@ SECTIONS
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -149,7 +149,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
index 9793ba241..086532179 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020 MM32 SE TEAM
@@ -27,7 +27,7 @@
#include "mm32_device.h"
#include "hal_conf.h"
#include "tusb.h"
-#include "../board.h"
+#include "bsp/board_api.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
@@ -57,7 +57,7 @@ const int baudrate = 115200;
void board_init (void)
{
-// usb clock
+// usb clock
USB_DeviceClockInit();
if ( SysTick_Config(SystemCoreClock / 1000) )
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
new file mode 100644
index 000000000..a778e749f
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += \
+ -DHSE_VALUE=12000000
+
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = MM32F3273G8P
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
similarity index 64%
rename from hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
rename to hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
index e99bb977b..796ed04f6 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
@@ -1,55 +1,44 @@
/*
-******************************************************************************
-**
-** File : LinkerScript.ld
-**
-** Author : STM32CubeIDE
-**
-** Abstract : Linker script for STM32H7 series
-** 2048Kbytes FLASH and 192Kbytes RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Distribution: The file is distributed as is, without any warranty
-** of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2019 STMicroelectronics.
-** All rights reserved.
-**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-** opensource.org/licenses/BSD-3-Clause
-**
-****************************************************************************
-*/
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
-_estack = 0x20020000; /* end of RAM */
+_estack = 0x2001FFFF; /* end of RAM */
+
/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x2000 ; /* required amount of heap */
-_Min_Stack_Size = 0x2000 ; /* required amount of stack */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
- RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
- RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
- RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
- ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
}
/* Define output sections */
@@ -127,13 +116,12 @@ SECTIONS
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
- *(.RamFunc) /* .RamFunc sections */
- *(.RamFunc*) /* .RamFunc* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -161,6 +149,8 @@ SECTIONS
. = ALIGN(8);
} >RAM
+
+
/* Remove information from the standard libraries */
/DISCARD/ :
{
@@ -171,5 +161,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
new file mode 100644
index 000000000..bd2d36ae0
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
@@ -0,0 +1,182 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* DshanMCU Pitaya Lite with MM32F3273 */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+ tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+ /* Select USBCLK source */
+ // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+ RCC->CFGR &= ~(0x3 << 22);
+ RCC->CFGR |= (0x1 << 22);
+
+ /* Enable USB clock */
+ RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+// usb clock
+// requires SYSCLK_FREQ_XXMHz (HSE_VALUE*8) in system_mm32f327x.c
+ USB_DeviceClockInit();
+
+ if ( SysTick_Config(SystemCoreClock / 1000) )
+ {
+ while ( 1 )
+ ;
+ }
+ NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+ // LED on PA1
+ GPIO_InitTypeDef GPIO_InitStruct;
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+ GPIO_StructInit(&GPIO_InitStruct);
+
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_1;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ board_led_write(true);
+
+ // KEY on PA0
+ GPIO_StructInit(&GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_FLOATING;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ // UART
+ UART_InitTypeDef UART_InitStruct;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock
+ RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); //
+ //UART initialset
+
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+ GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+ UART_StructInit(&UART_InitStruct);
+ UART_InitStruct.UART_BaudRate = baudrate;
+ UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+ UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit
+ UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit
+ UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control
+ UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode
+
+ UART_Init(UART1, &UART_InitStruct); //initial uart 1
+ UART_Cmd(UART1, ENABLE); //enable uart 1
+
+ //UART1_TX GPIOA.9
+ GPIO_StructInit(&GPIO_InitStruct);
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ //UART1_RX GPIOA.10
+ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+ state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_1)) : (GPIO_SetBits(GPIOA, GPIO_Pin_1));
+}
+
+uint32_t board_button_read (void)
+{
+ uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_RESET;
+ return key;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+ const char *buff = buf;
+ while ( len )
+ {
+ while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+ ; //The loop is sent until it is finished
+ UART1->TDR = (*buff & 0xFF);
+ buff++;
+ len--;
+ }
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+ system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+ return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 1a9f51191..d5b6e315a 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -3,15 +3,12 @@ SDK_DIR = hw/mcu/mindmotion/mm32sdk
DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
- -mfloat-abi=soft \
-nostdlib -nostartfiles \
- -DCFG_TUSB_MCU=OPT_MCU_MM32F327X
+ -DCFG_TUSB_MCU=OPT_MCU_MM32F327X
# suppress warning caused by vendor mcu driver
CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
@@ -22,15 +19,12 @@ SRC_C += \
$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
-
+
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
# flash target using on-board
flash: flash-jlink
diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c
index 4b8ae393d..5bb3d3866 100644
--- a/hw/bsp/msp430/family.c
+++ b/hw/bsp/msp430/family.c
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "msp430.h"
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 3d2d4085e..d5ef7f930 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "msp.h"
@@ -34,7 +34,7 @@
void USB0_IRQHandler(void)
{
#if CFG_TUH_ENABLED
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
#if CFG_TUD_ENABLED
tud_int_handler(0);
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index e3cb90abc..b5ade6a52 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -1,13 +1,11 @@
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti
+#include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
CFLAGS += \
-flto \
- -mthumb \
-mslow-flash-data \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-D__MSP432E401Y__ \
-DCFG_TUSB_MCU=OPT_MCU_MSP432E4
@@ -33,9 +31,6 @@ INC += \
SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
# For flash-jlink target
JLINK_DEVICE = MSP432E401Y
JLINK_IF = SWD
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 3e901567c..99c1f194c 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -37,11 +37,11 @@ INC += \
$(TOP)/$(MCU_DIR)/inc/config_43xx
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
# For flash-jlink target
JLINK_DEVICE = LPC4330
-JLINK_IF = swd
+JLINK_IF = swd
# flash using jlink
flash: flash-jlink
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index 4fc314165..bd84e449b 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "chip.h"
-#include "../board.h"
+#include "../board_api.h"
#define LED_PORT 1
#define LED_PIN 12
@@ -214,7 +214,7 @@ void USB0_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(0)
- tuh_int_handler(0);
+ tuh_int_handler(0, true);
#endif
}
@@ -225,7 +225,7 @@ void USB1_IRQHandler(void)
#endif
#if PORT_SUPPORT_HOST(1)
- tuh_int_handler(1);
+ tuh_int_handler(1, true);
#endif
}
diff --git a/hw/bsp/ngx4330/ngx4330.ld b/hw/bsp/ngx4330/ngx4330.ld
index 7bd363f08..300869c20 100644
--- a/hw/bsp/ngx4330/ngx4330.ld
+++ b/hw/bsp/ngx4330/ngx4330.ld
@@ -12,39 +12,39 @@
MEMORY
{
/* Define each memory region */
- RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */
- RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */
- RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
- RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
- RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
- SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */
+ RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */
+ RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+ SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */
}
/* Define a symbol for the top of each memory region */
- __base_RamLoc128 = 0x10000000 ; /* RamLoc128 */
- __base_RAM = 0x10000000 ; /* RAM */
- __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */
- __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */
- __base_RamLoc72 = 0x10080000 ; /* RamLoc72 */
- __base_RAM2 = 0x10080000 ; /* RAM2 */
- __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */
- __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */
- __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
- __base_RAM3 = 0x20000000 ; /* RAM3 */
- __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
- __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
- __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
- __base_RAM4 = 0x20008000 ; /* RAM4 */
- __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
- __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
- __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
- __base_RAM5 = 0x2000c000 ; /* RAM5 */
- __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
- __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
- __base_SPIFI = 0x14000000 ; /* SPIFI */
- __base_Flash = 0x14000000 ; /* Flash */
- __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */
- __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */
+ __base_RamLoc128 = 0x10000000 ; /* RamLoc128 */
+ __base_RAM = 0x10000000 ; /* RAM */
+ __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */
+ __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */
+ __base_RamLoc72 = 0x10080000 ; /* RamLoc72 */
+ __base_RAM2 = 0x10080000 ; /* RAM2 */
+ __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */
+ __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */
+ __base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
+ __base_RAM3 = 0x20000000 ; /* RAM3 */
+ __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+ __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+ __base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
+ __base_RAM4 = 0x20008000 ; /* RAM4 */
+ __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+ __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+ __base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
+ __base_RAM5 = 0x2000c000 ; /* RAM5 */
+ __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+ __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+ __base_SPIFI = 0x14000000 ; /* SPIFI */
+ __base_Flash = 0x14000000 ; /* Flash */
+ __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */
+ __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */
ENTRY(ResetISR)
@@ -103,9 +103,9 @@ SECTIONS
} > SPIFI
/*
* for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
+ * with C++ and STDC++) use this.
*/
- .ARM.extab : ALIGN(4)
+ .ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SPIFI
@@ -117,9 +117,9 @@ SECTIONS
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SPIFI
__exidx_end = .;
-
+
_etext = .;
-
+
/* DATA section for RamLoc72 */
.data_RAM2 : ALIGN(4)
@@ -322,11 +322,11 @@ SECTIONS
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0);
/* ## Create checksum value (used in startup) ## */
- PROVIDE(__valid_user_code_checksum = 0 -
- (_vStackTop
- + (ResetISR + 1)
- + (NMI_Handler + 1)
- + (HardFault_Handler + 1)
+ PROVIDE(__valid_user_code_checksum = 0 -
+ (_vStackTop
+ + (ResetISR + 1)
+ + (NMI_Handler + 1)
+ + (HardFault_Handler + 1)
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -340,4 +340,4 @@ SECTIONS
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..efd26a3a7
--- /dev/null
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "nrf.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< RAM
-
- .fs_data :
- {
- PROVIDE(__start_fs_data = .);
- KEEP(*(.fs_data))
- PROVIDE(__stop_fs_data = .);
- } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
index f570740b6..b7cac1019 100755
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
@@ -20,7 +20,7 @@ SECTIONS
KEEP(*(.svc_data))
PROVIDE(__stop_svc_data = .);
} > RAM
-
+
.fs_data :
{
PROVIDE(__start_fs_data = .);
@@ -29,4 +29,4 @@ SECTIONS
} > RAM
} INSERT AFTER .data;
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
new file mode 100644
index 000000000..93647063a
--- /dev/null
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/arduino_nano33_ble.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
index d548e01c3..00fa8d8ea 100644
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
index a86c9dc7f..3dd354efa 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
@@ -1,6 +1,9 @@
MCU_VARIANT = nrf52840
CFLAGS += -DNRF52840_XXAA
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
deleted file mode 100755
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
- /* SRAM required by S132 depend on
- * - Attribute Table Size
- * - Vendor UUID count
- * - Max ATT MTU
- * - Concurrent connection peripheral + central + secure links
- * - Event Len, HVN queue, Write CMD queue
- */
- RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
- . = ALIGN(4);
- .svc_data :
- {
- PROVIDE(__start_svc_data = .);
- KEEP(*(.svc_data))
- PROVIDE(__stop_svc_data = .);
- } > RAM
-
- .fs_data :
- {
- PROVIDE(__start_fs_data = .);
- KEEP(*(.fs_data))
- PROVIDE(__stop_fs_data = .);
- } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
new file mode 100644
index 000000000..726438d05
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -0,0 +1,9 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+#set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+# enable max3421 host driver for this board
+set(MAX3421_HOST 1)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 3208a948a..3d59516d8 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -45,6 +45,13 @@
#define UART_RX_PIN 24
#define UART_TX_PIN 25
+// SPI for USB host shield
+#define MAX3421_SCK_PIN 14
+#define MAX3421_MOSI_PIN 13
+#define MAX3421_MISO_PIN 15
+#define MAX3421_CS_PIN 27 // D10
+#define MAX3421_INTR_PIN 26 // D9
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
index f31899eb7..488f07b82 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
@@ -1,6 +1,12 @@
MCU_VARIANT = nrf52840
CFLAGS += -DNRF52840_XXAA
+# enable max3421 host driver for this board
+MAX3421_HOST = 1
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
index ece6e34cb..605deea24 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
@@ -1,6 +1,9 @@
MCU_VARIANT = nrf52840
CFLAGS += -DNRF52840_XXAA
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
deleted file mode 100644
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
- /* SRAM required by S132 depend on
- * - Attribute Table Size
- * - Vendor UUID count
- * - Max ATT MTU
- * - Concurrent connection peripheral + central + secure links
- * - Event Len, HVN queue, Write CMD queue
- */
- RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
- . = ALIGN(4);
- .svc_data :
- {
- PROVIDE(__start_svc_data = .);
- KEEP(*(.svc_data))
- PROVIDE(__stop_svc_data = .);
- } > RAM
-
- .fs_data :
- {
- PROVIDE(__start_fs_data = .);
- KEEP(*(.fs_data))
- PROVIDE(__stop_fs_data = .);
- } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
index 132173a80..33c370f53 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
@@ -1,6 +1,9 @@
MCU_VARIANT = nrf52840
CFLAGS += -DNRF52840_XXAA
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
deleted file mode 100644
index 5314a4e93..000000000
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
- /* SRAM required by S132 depend on
- * - Attribute Table Size
- * - Vendor UUID count
- * - Max ATT MTU
- * - Concurrent connection peripheral + central + secure links
- * - Event Len, HVN queue, Write CMD queue
- */
- RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
- . = ALIGN(4);
- .svc_data :
- {
- PROVIDE(__start_svc_data = .);
- KEEP(*(.svc_data))
- PROVIDE(__stop_svc_data = .);
- } > RAM
-
- .fs_data :
- {
- PROVIDE(__start_fs_data = .);
- KEEP(*(.fs_data))
- PROVIDE(__stop_fs_data = .);
- } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
new file mode 100644
index 000000000..ffa5932c1
--- /dev/null
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/nrf52840_mdk_dongle.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
index 01dd1f24f..072cb2714 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
index 3afa234aa..f25ec8f34 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
@@ -12,4 +12,4 @@ $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
flash: $(BUILD)/$(PROJECT).zip
@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
- $(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
\ No newline at end of file
+ $(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
new file mode 100644
index 000000000..693d7beed
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index ab12d21aa..9459e7911 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -31,18 +31,27 @@
extern "C" {
#endif
+#define _PINNUM(port, pin) ((port)*32 + (pin))
+
// LED
#define LED_PIN 13
#define LED_STATE_ON 0
// Button
-#define BUTTON_PIN 11
+#define BUTTON_PIN 25 // button 4
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_RX_PIN 8
#define UART_TX_PIN 6
+// SPI for USB host shield
+#define MAX3421_SCK_PIN _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
new file mode 100644
index 000000000..fa7ab9e23
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
@@ -0,0 +1,238 @@
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ // Dialog-generated settings
+ Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+ Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+
+ Project.SetDevice ("nRF52840_xxAA");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("8 MHz");
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetTracePortWidth (4);
+
+ // User settings
+ File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10056/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+* TargetReset
+*
+* Function description
+* Replaces the default target device reset routine. Optional.
+*
+* Notes
+* This example demonstrates the usage when
+* debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+// unsigned int SP;
+// unsigned int PC;
+// unsigned int VectorTableAddr;
+//
+// Exec.Reset();
+//
+// VectorTableAddr = Elf.GetBaseAddr();
+//
+// if (VectorTableAddr != 0xFFFFFFFF) {
+//
+// Util.Log("Resetting Program.");
+//
+// SP = Target.ReadU32(VectorTableAddr);
+// Target.SetReg("SP", SP);
+//
+// PC = Target.ReadU32(VectorTableAddr + 4);
+// Target.SetReg("PC", PC);
+// }
+//}
+
+/*********************************************************************
+*
+* BeforeTargetReset
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetReset
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr == 0xFFFFFFFF) {
+ Util.Log("Project file error: failed to get program base");
+ } else {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
+
+/*********************************************************************
+*
+* DebugStart
+*
+* Function description
+* Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+* TargetConnect
+*
+* Function description
+* Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+* AfterTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* TargetDownload
+*
+* Function description
+* Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDownload
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr == 0xFFFFFFFF) {
+ Util.Log("Project file error: failed to get program base");
+ } else {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
+
+/*********************************************************************
+*
+* BeforeTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetHalt
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/nrf/boards/pca10059/board.cmake b/hw/bsp/nrf/boards/pca10059/board.cmake
new file mode 100644
index 000000000..c79eb5964
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10059/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/pca10059.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h
index 0810be648..ea3f4030d 100644
--- a/hw/bsp/nrf/boards/pca10059/board.h
+++ b/hw/bsp/nrf/boards/pca10059/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
new file mode 100644
index 000000000..ca5399a3a
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT nrf5340_application)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
+
+function(update_board TARGET)
+ target_sources(${TARGET} PRIVATE
+ ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
+ )
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
new file mode 100644
index 000000000..ad3379bf6
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -0,0 +1,59 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define _PINNUM(port, pin) ((port)*32 + (pin))
+
+// LED
+#define LED_PIN 28
+#define LED_STATE_ON 0
+
+// Button
+#define BUTTON_PIN 23
+#define BUTTON_STATE_ACTIVE 0
+
+// UART
+#define UART_RX_PIN 32
+#define UART_TX_PIN 33
+
+// SPI for USB host shield
+#define MAX3421_SCK_PIN _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
new file mode 100644
index 000000000..9c4edbafc
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -0,0 +1,14 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = nrf5340_application
+CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
+
+LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
+
+SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
+
+# caused by void SystemStoreFICRNS() (without void) in system_nrf5340_application.c
+CFLAGS += -Wno-error=strict-prototypes
+
+# flash using jlink
+JLINK_DEVICE = nrf5340_xxaa_app
+flash: flash-jlink
diff --git a/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
new file mode 100644
index 000000000..4ad0376a4
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
@@ -0,0 +1,335 @@
+/*********************************************************************
+* (c) SEGGER Microcontroller GmbH *
+* The Embedded Experts *
+* www.segger.com *
+**********************************************************************
+
+File :
+Created : 30 Jun 2021 13:37
+Ozone Version : V3.24a
+*/
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ // Dialog-generated settings
+ Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd");
+ Project.AddSvdFile ("./nrf5340_application.svd");
+ Project.SetDevice ("nRF5340_xxAA_APP");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("16 MHz");
+
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetTracePortWidth (4);
+
+ // User settings
+ File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10095/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+* OnStartupComplete
+*
+* Function description
+* Called when program execution has reached/passed
+* the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+* TargetReset
+*
+* Function description
+* Replaces the default target device reset routine. Optional.
+*
+* Notes
+* This example demonstrates the usage when
+* debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+// unsigned int SP;
+// unsigned int PC;
+// unsigned int VectorTableAddr;
+//
+// VectorTableAddr = Elf.GetBaseAddr();
+// //
+// // Set up initial stack pointer
+// //
+// if (VectorTableAddr != 0xFFFFFFFF) {
+// SP = Target.ReadU32(VectorTableAddr);
+// Target.SetReg("SP", SP);
+// }
+// //
+// // Set up entry point PC
+// //
+// PC = Elf.GetEntryPointPC();
+//
+// if (PC != 0xFFFFFFFF) {
+// Target.SetReg("PC", PC);
+// } else if (VectorTableAddr != 0xFFFFFFFF) {
+// PC = Target.ReadU32(VectorTableAddr + 4);
+// Target.SetReg("PC", PC);
+// } else {
+// Util.Error("Project file error: failed to set entry point PC", 1);
+// }
+//}
+
+/*********************************************************************
+*
+* BeforeTargetReset
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetReset
+*
+* Function description
+* Event handler routine. Optional.
+* The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+ _SetupTarget();
+}
+
+/*********************************************************************
+*
+* DebugStart
+*
+* Function description
+* Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+* TargetConnect
+*
+* Function description
+* Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+* AfterTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* TargetDownload
+*
+* Function description
+* Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+* The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+ _SetupTarget();
+}
+
+/*********************************************************************
+*
+* BeforeTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetHalt
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetResume
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+* OnSnapshotLoad
+*
+* Function description
+* Called upon loading a snapshot. Optional.
+*
+* Additional information
+* This function is used to restore the target state in cases
+* where values cannot simply be written to the target.
+* Typical use: GPIO clock needs to be enabled, before
+* GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+* OnSnapshotSave
+*
+* Function description
+* Called upon saving a snapshot. Optional.
+*
+* Additional information
+* This function is usually used to save values of the target
+* state which can either not be trivially read,
+* or need to be restored in a specific way or order.
+* Typically use: Memory Mapped Registers,
+* such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+* OnError
+*
+* Function description
+* Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+* _SetupTarget
+*
+* Function description
+* Setup the target.
+* Called by AfterTargetReset() and AfterTargetDownload().
+*
+* Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+ //
+ // Set up initial stack pointer
+ //
+ SP = Target.ReadU32(VectorTableAddr);
+ if (SP != 0xFFFFFFFF) {
+ Target.SetReg("SP", SP);
+ }
+ //
+ // Set up entry point PC
+ //
+ PC = Elf.GetEntryPointPC();
+ if (PC != 0xFFFFFFFF) {
+ Target.SetReg("PC", PC);
+ } else {
+ Util.Error("Project script error: failed to set up entry point PC", 1);
+ }
+}
diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake
new file mode 100644
index 000000000..c30026815
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10100/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52833)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52833_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h
index 881133035..2b2579732 100644
--- a/hw/bsp/nrf/boards/pca10100/board.h
+++ b/hw/bsp/nrf/boards/pca10100/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
new file mode 100644
index 000000000..693d7beed
--- /dev/null
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
index dcf829d9c..bc203f073 100644
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index a07332d4c..c431389f3 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,24 +24,40 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wundef"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
#include "nrfx.h"
-#include "nrfx/hal/nrf_gpio.h"
-#include "nrfx/drivers/include/nrfx_power.h"
-#include "nrfx/drivers/include/nrfx_uarte.h"
+#include "hal/nrf_gpio.h"
+#include "drivers/include/nrfx_gpiote.h"
+#include "drivers/include/nrfx_power.h"
+#include "drivers/include/nrfx_uarte.h"
+#include "drivers/include/nrfx_spim.h"
#ifdef SOFTDEVICE_PRESENT
#include "nrf_sdm.h"
#include "nrf_soc.h"
#endif
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
+void USBD_IRQHandler(void) {
tud_int_handler(0);
}
@@ -49,26 +65,53 @@ void USBD_IRQHandler(void)
/* MACRO TYPEDEF CONSTANT ENUM
*------------------------------------------------------------------*/
+// Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h
+enum {
+ USB_EVT_DETECTED = 0,
+ USB_EVT_REMOVED = 1,
+ USB_EVT_READY = 2
+};
+
+#ifdef NRF5340_XXAA
+ #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
+ #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
+ #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
+#else
+ #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
+ #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk
+ #define OUTPUTRDY_Msk POWER_USBREGSTATUS_OUTPUTRDY_Msk
+#endif
+
static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
// tinyusb function that handles power event (detected, ready, removed)
// We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
extern void tusb_hal_nrf_power_event(uint32_t event);
-
// nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
-TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
-{
+TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
tusb_hal_nrf_power_event((uint32_t) event);
}
-void board_init(void)
-{
+//------------- Host using MAX2341E -------------//
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static void max3421_init(void);
+
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
+#endif
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void board_init(void) {
// stop LF clock just in case we jump from application without reset
NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
// Use Internal OSC to compatible with all boards
- NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_RC;
+ NRF_CLOCK->LFCLKSRC = LFCLK_SRC_RC;
NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
// LED
@@ -79,22 +122,21 @@ void board_init(void)
nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP);
// 1ms tick timer
- SysTick_Config(SystemCoreClock/1000);
+ SysTick_Config(SystemCoreClock / 1000);
// UART
- nrfx_uarte_config_t uart_cfg =
- {
- .pseltxd = UART_TX_PIN,
- .pselrxd = UART_RX_PIN,
- .pselcts = NRF_UARTE_PSEL_DISCONNECTED,
- .pselrts = NRF_UARTE_PSEL_DISCONNECTED,
- .p_context = NULL,
- .baudrate = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
- .interrupt_priority = 7,
- .hal_cfg = {
- .hwfc = NRF_UARTE_HWFC_DISABLED,
- .parity = NRF_UARTE_PARITY_EXCLUDED,
- }
+ nrfx_uarte_config_t uart_cfg = {
+ .pseltxd = UART_TX_PIN,
+ .pselrxd = UART_RX_PIN,
+ .pselcts = NRF_UARTE_PSEL_DISCONNECTED,
+ .pselrts = NRF_UARTE_PSEL_DISCONNECTED,
+ .p_context = NULL,
+ .baudrate = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+ .interrupt_priority = 7,
+ .hal_cfg = {
+ .hwfc = NRF_UARTE_HWFC_DISABLED,
+ .parity = NRF_UARTE_PARITY_EXCLUDED,
+ }
};
nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
@@ -123,67 +165,73 @@ void board_init(void)
#endif
{
// Power module init
- const nrfx_power_config_t pwr_cfg = { 0 };
+ const nrfx_power_config_t pwr_cfg = {0};
nrfx_power_init(&pwr_cfg);
// Register tusb function as USB power handler
// cause cast-function-type warning
- const nrfx_power_usbevt_config_t config = { .handler = power_event_handler };
+ const nrfx_power_usbevt_config_t config = {.handler = power_event_handler};
nrfx_power_usbevt_init(&config);
-
nrfx_power_usbevt_enable();
+ // USB power may already be ready at this time -> no event generated
+ // We need to invoke the handler based on the status initially
+#ifdef NRF5340_XXAA
+ usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
+#else
usb_reg = NRF_POWER->USBREGSTATUS;
+#endif
}
- if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED);
- if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY);
+ if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
+ if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY);
#endif
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+ max3421_init();
+#endif
+
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
- nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
// return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
#ifdef SOFTDEVICE_PRESENT
// process SOC event from SD
-uint32_t proc_soc(void)
-{
+uint32_t proc_soc(void) {
uint32_t soc_evt;
uint32_t err = sd_evt_get(&soc_evt);
@@ -200,25 +248,115 @@ uint32_t proc_soc(void)
return err;
}
-uint32_t proc_ble(void)
-{
+uint32_t proc_ble(void) {
// do nothing with ble
return NRF_ERROR_NOT_FOUND;
}
-void SD_EVT_IRQHandler(void)
-{
+void SD_EVT_IRQHandler(void) {
// process BLE and SOC until there is no more events
- while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
- {
-
+ while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) {
}
}
-void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
-{
+void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
(void) id;
(void) pc;
(void) info;
}
#endif
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+ if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
+ tuh_int_handler(1, true);
+}
+
+static void max3421_init(void) {
+ // MAX3421 need 3.3v signal (may not be needed)
+// #if defined(UICR_REGOUT0_VOUT_Msk)
+// if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
+// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+// NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
+//
+// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+// NVIC_SystemReset();
+// }
+// #endif
+
+ // manually manage CS
+ nrf_gpio_cfg_output(MAX3421_CS_PIN);
+ nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
+
+ // USB host using max3421e usb controller via SPI
+ nrfx_spim_config_t cfg = {
+ .sck_pin = MAX3421_SCK_PIN,
+ .mosi_pin = MAX3421_MOSI_PIN,
+ .miso_pin = MAX3421_MISO_PIN,
+ .ss_pin = NRFX_SPIM_PIN_NOT_USED,
+ .ss_active_high = false,
+ .irq_priority = 3,
+ .orc = 0xFF,
+ // default setting 4 Mhz, Mode 0, MSB first
+ .frequency = NRF_SPIM_FREQ_4M,
+ .mode = NRF_SPIM_MODE_0,
+ .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+ };
+
+ // no handler --> blocking
+ nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+
+ // max3421e interrupt pin
+ nrfx_gpiote_init(1);
+ nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+ in_config.pull = NRF_GPIO_PIN_PULLUP;
+
+ NVIC_SetPriority(GPIOTE_IRQn, 2);
+
+ nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+ nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+ (void) rhport;
+
+ // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
+ // when disabled and re-enabled.
+ if (enabled) {
+ NVIC_EnableIRQ(GPIOTE_IRQn);
+ } else {
+ NVIC_DisableIRQ(GPIOTE_IRQn);
+ }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+ (void) rhport;
+ nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+ (void) rhport;
+
+ nrfx_spim_xfer_desc_t xfer = {
+ .p_tx_buffer = tx_buf,
+ .tx_length = tx_buf ? xfer_bytes : 0,
+ .p_rx_buffer = rx_buf,
+ .rx_length = rx_buf ? xfer_bytes : 0,
+ };
+
+ return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
+
+#endif
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
new file mode 100644
index 000000000..99d9ac6dd
--- /dev/null
+++ b/hw/bsp/nrf/family.cmake
@@ -0,0 +1,135 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+if (MCU_VARIANT STREQUAL "nrf5340_application")
+ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+ set(JLINK_DEVICE nrf5340_xxaa_app)
+else ()
+ set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+ set(JLINK_DEVICE ${MCU_VARIANT}_xxaa)
+endif ()
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ # driver
+ ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c
+ ${NRFX_DIR}/drivers/src/nrfx_gpiote.c
+ ${NRFX_DIR}/drivers/src/nrfx_power.c
+ ${NRFX_DIR}/drivers/src/nrfx_spim.c
+ ${NRFX_DIR}/drivers/src/nrfx_uarte.c
+ # mcu
+ ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET)
+
+ if (MCU_VARIANT STREQUAL "nrf52840")
+ target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA)
+ elseif (MCU_VARIANT STREQUAL "nrf52833")
+ target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52833_XXAA)
+ elseif (MCU_VARIANT STREQUAL "nrf5340_application")
+ target_compile_definitions(${BOARD_TARGET} PUBLIC NRF5340_XXAA NRF5340_XXAA_APPLICATION)
+ endif ()
+
+ if (TRACE_ETM STREQUAL "1")
+ # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
+ target_compile_definitions(${BOARD_TARGET} PUBLIC ENABLE_TRACE)
+ endif ()
+
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${NRFX_DIR}
+ ${NRFX_DIR}/mdk
+ ${NRFX_DIR}/hal
+ ${NRFX_DIR}/drivers/include
+ ${NRFX_DIR}/drivers/src
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ set(LD_FILE_GNU ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S)
+ endif ()
+
+ target_sources(${BOARD_TARGET} PUBLIC
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${LD_FILE_GNU}"
+ -L${NRFX_DIR}/mdk
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d8283a9e6..4b53b9a4f 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -1,48 +1,43 @@
UF2_FAMILY_ID = 0xADA52840
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
+
+NRFX_DIR = hw/mcu/nordic/nrfx
include $(TOP)/$(BOARD_PATH)/board.mk
+# nRF52 is cortex-m4, nRF53 is cortex-m33
+CPU_CORE ?= cortex-m4
+
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-DCFG_TUSB_MCU=OPT_MCU_NRF5X \
-DCONFIG_GPIO_AS_PINRESET
# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
-# All source paths should be relative to the top level.
-LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
-
-LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
+LDFLAGS += -L$(TOP)/${NRFX_DIR}/mdk
SRC_C += \
src/portable/nordic/nrf5x/dcd_nrf5x.c \
- hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
- hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
- hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
+ ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c \
+ ${NRFX_DIR}/drivers/src/nrfx_gpiote.c \
+ ${NRFX_DIR}/drivers/src/nrfx_power.c \
+ ${NRFX_DIR}/drivers/src/nrfx_spim.c \
+ ${NRFX_DIR}/drivers/src/nrfx_uarte.c \
+ ${NRFX_DIR}/mdk/system_$(MCU_VARIANT).c
INC += \
$(TOP)/$(BOARD_PATH) \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
- $(TOP)/hw/mcu/nordic \
- $(TOP)/hw/mcu/nordic/nrfx \
- $(TOP)/hw/mcu/nordic/nrfx/mdk \
- $(TOP)/hw/mcu/nordic/nrfx/hal \
- $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
- $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+ $(TOP)/${NRFX_DIR} \
+ $(TOP)/${NRFX_DIR}/mdk \
+ $(TOP)/${NRFX_DIR}/hal \
+ $(TOP)/${NRFX_DIR}/drivers/include \
+ $(TOP)/${NRFX_DIR}/drivers/src \
-SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
+SRC_S += ${NRFX_DIR}/mdk/gcc_startup_$(MCU_VARIANT).S
ASFLAGS += -D__HEAP_SIZE=0
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
# For flash-jlink target
-JLINK_DEVICE = $(MCU_VARIANT)_xxaa
+JLINK_DEVICE ?= $(MCU_VARIANT)_xxaa
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
similarity index 95%
rename from hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
rename to hw/bsp/nrf/linker/nrf52840_s140_v6.ld
index 5314a4e93..e27fa1c91 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
* - Max ATT MTU
* - Concurrent connection peripheral + central + secure links
* - Event Len, HVN queue, Write CMD queue
- */
+ */
RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
}
@@ -26,7 +26,7 @@ SECTIONS
KEEP(*(.svc_data))
PROVIDE(__stop_svc_data = .);
} > RAM
-
+
.fs_data :
{
PROVIDE(__start_fs_data = .);
@@ -35,4 +35,4 @@ SECTIONS
} > RAM
} INSERT AFTER .data;
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
new file mode 100644
index 000000000..95ef33ce4
--- /dev/null
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -0,0 +1,45 @@
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+#define NRFX_POWER_ENABLED 1
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+
+#define NRFX_CLOCK_ENABLED 0
+#define NRFX_GPIOTE_ENABLED 1
+
+#define NRFX_UARTE_ENABLED 1
+#define NRFX_UARTE0_ENABLED 1
+
+#define NRFX_SPIM_ENABLED 1
+#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi
+
+#define NRFX_PRS_ENABLED 0
+#define NRFX_USBREG_ENABLED 1
+
+#if defined(NRF51)
+#include
+#elif defined(NRF52805_XXAA)
+#include
+#elif defined(NRF52810_XXAA)
+#include
+#elif defined(NRF52811_XXAA)
+#include
+#elif defined(NRF52820_XXAA)
+#include
+#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
+#include
+#elif defined(NRF52833_XXAA)
+#include
+#elif defined(NRF52840_XXAA)
+#include
+#elif defined(NRF5340_XXAA_APPLICATION)
+#include
+#elif defined(NRF5340_XXAA_NETWORK)
+ #include
+#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
+ #include
+#else
+ #error "Unknown device."
+#endif
+
+#endif // NRFX_CONFIG_H__
diff --git a/hw/mcu/nordic/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h
similarity index 74%
rename from hw/mcu/nordic/nrfx_glue.h
rename to hw/bsp/nrf/nrfx_glue.h
index cdf49b4ab..ef756c670 100644
--- a/hw/mcu/nordic/nrfx_glue.h
+++ b/hw/bsp/nrf/nrfx_glue.h
@@ -220,6 +220,75 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
/** @} */
+//------------------------------------------------------------------------------
+
+#include
+
+/**
+ * @brief Atomic 32 bit unsigned type.
+ */
+#define nrfx_atomic_t nrfx_atomic_u32_t
+
+/**
+ * @brief Stores value to an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value to store.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value)
+
+/**
+ * @brief Performs logical OR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of second operand of OR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value)
+
+/**
+ * @brief Performs logical AND operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of second operand of AND operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value)
+
+/**
+ * @brief Performs logical XOR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of second operand of XOR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value)
+
+/**
+ * @brief Performs logical ADD operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of second operand of ADD operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value)
+
+/**
+ * @brief Performs logical SUB operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value Value of second operand of SUB operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value)
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/mcu/nordic/nrfx_log.h b/hw/bsp/nrf/nrfx_log.h
similarity index 100%
rename from hw/mcu/nordic/nrfx_log.h
rename to hw/bsp/nrf/nrfx_log.h
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index ad2ee1ea0..aa8f00e70 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -35,7 +35,7 @@ INC += \
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC121SC2AE
diff --git a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
+++ b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
-
+
*(.rodata*)
KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
index 7117a3422..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
+++ b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index 000c8cd95..bf7610a7b 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -31,7 +31,7 @@ INC += \
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC125SC2AE
diff --git a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
+++ b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
-
+
*(.rodata*)
KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
index 7117a3422..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
+++ b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 0dcd897cb..46f53420c 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -37,7 +37,7 @@ INC += \
$(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC126VG4AE
diff --git a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
index da62e7bd2..9974127a8 100644
--- a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
+++ b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 4d7aac7f5..b1f9245a6 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -30,7 +30,7 @@ INC += \
$(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC120LE3
diff --git a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
index 0d78116b8..18a189d8c 100644
--- a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
+++ b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "NUC100Series.h"
#include "clk.h"
#include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index f27577e36..3e48d3998 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -42,14 +42,14 @@ INC += \
$(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
# For flash-jlink target
JLINK_DEVICE = NUC505YO13Y
# Note
-# To be able to program the SPI flash, it need to boot with ICP mode "1011".
-# However, in ICP mode, opencod cannot establish connection to the mcu.
+# To be able to program the SPI flash, it need to boot with ICP mode "1011".
+# However, in ICP mode, opencod cannot establish connection to the mcu.
# Therefore, there is no easy command line flash for NUC505
# It is probably better to just use Nuvoton NuMicro ICP programming on windows to program the board
# - 1111 "SPI" (run from internal flash)
diff --git a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
index 49e66d2d0..3ec0066a3 100644
--- a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
+++ b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "NUC505Series.h"
//--------------------------------------------------------------------+
diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
index e47ec5f31..0bb6cb728 100644
--- a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c
index 786f04978..895e23899 100644
--- a/hw/bsp/pic32mz/family.c
+++ b/hw/bsp/pic32mz/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4ef5dd883
--- /dev/null
+++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,180 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
+#include "bsp_api.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ BOARD_TUD_RHPORT=${PORT}
+ BOARD_TUH_RHPORT=${HOST_PORT}
+ # port 0 is fullspeed, port 1 is highspeed
+ BOARD_TUD_MAX_SPEED=$
+ BOARD_TUH_MAX_SPEED=$
+ )
+endfunction()
diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h
new file mode 100644
index 000000000..7841ec8b8
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.h
@@ -0,0 +1,68 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED
+#define LED_STATE_ON 1
+
+#define SW1 BSP_IO_PORT_04_PIN_08 // D12
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
+ { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+
+ // USB FS
+ { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
+ { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+ { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+
+ // USB HS
+ { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
+ { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+ { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+
+ // ETM Trace
+ #ifdef TRACE_ETM
+ { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ #endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk
new file mode 100644
index 000000000..6a5c2ffce
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.mk
@@ -0,0 +1,12 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+LD_FILE = ${BOARD_PATH}/${BOARD}.ld
+
+# Port 1 is highspeed
+PORT ?= 1
+
+JLINK_DEVICE = R7FA6M5BH
+DFU_UTIL_OPTION = -d 2341:0368 -a 0
+
+flash: flash-dfu-util
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..33d381850
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,63 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+#else
+ #define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..6845183db
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+#define BSP_MCU_FEATURE_SET ('B')
+#define BSP_ROM_SIZE_BYTES (2097152)
+#define BSP_RAM_SIZE_BYTES (524288)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..d5428540f
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,387 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M5 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+#else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+
+#if defined(_RA_TZ_SECURE)
+ #define BSP_TZ_SECURE_BUILD (1)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #elif defined(_RA_TZ_NONSECURE)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (1)
+ #else
+#define BSP_TZ_SECURE_BUILD (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT (1)
+#define SCB_AIRCR_BFHFNMINS_VAL (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL (1)
+#define SCB_AIRCR_PRIS_VAL (0)
+#define TZ_FPU_NS_USAGE (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+ (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+ 0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+ 0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+ 0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+ 0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+ 0xfffffffc) /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+ 0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+ 0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+ 0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (\
+ 1 | \
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+ 4 | \
+ 0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..0eb5e0516
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,37 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
new file mode 100644
index 000000000..ba15588e6
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
@@ -0,0 +1,25 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x80000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x200000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x68000000;
+OSPI_DEVICE_0_LENGTH = 0x8000000;
+OSPI_DEVICE_1_START = 0x70000000;
+OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+/* Board has bootloader */
+FLASH_IMAGE_START = 0x10000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
new file mode 100644
index 000000000..4188d3188
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC)
+# target_sources(${TARGET} PRIVATE)
+# target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
new file mode 100644
index 000000000..c132387bc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 BSP_IO_PORT_01_PIN_06
+#define LED_STATE_ON 1
+
+#define SW1 BSP_IO_PORT_01_PIN_05
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+ {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+ // USB FS D+, D-, VBus
+ {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
new file mode 100644
index 000000000..f257c0000
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..11d5795df
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..d810dabb2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CFP
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (262144)
+#define BSP_RAM_SIZE_BYTES (32768)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..72cdb89e6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,78 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA4M1 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+ #define BSP_HOCO_HZ (64000000)
+#else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..554126523
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
new file mode 100644
index 000000000..dfd5fc95a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m3)
+
+set(JLINK_DEVICE R7FA4M3AF)
+
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC)
+# target_sources(${TARGET} PRIVATE)
+# target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
new file mode 100644
index 000000000..9dd2545a0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define LED_STATE_ON 1
+
+#define SW1 (BSP_IO_PORT_00_PIN_05)
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+ {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+ // USB FS
+ {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
new file mode 100644
index 000000000..5987269b5
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra4m3
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M3AF
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..862ec25b7
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,63 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (1)
+#else
+#define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x800)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..1a0bc02e2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M3AF3CFB
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (1048576)
+#define BSP_RAM_SIZE_BYTES (131072)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (144)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..26e184a94
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,386 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+#define BSP_MCU_GROUP_RA4M3 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+
+#define BSP_CFG_FLL_ENABLE (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+
+#if defined(_RA_TZ_SECURE)
+ #define BSP_TZ_SECURE_BUILD (1)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #elif defined(_RA_TZ_NONSECURE)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (1)
+ #else
+#define BSP_TZ_SECURE_BUILD (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT (1)
+#define SCB_AIRCR_BFHFNMINS_VAL (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL (1)
+#define SCB_AIRCR_PRIS_VAL (0)
+#define TZ_FPU_NS_USAGE (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+ (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+ 0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+ 0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+ (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+ 0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+ (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+ (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+ (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+ (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+ 0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+ 0xfffffffc) /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+ 0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+ (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+ (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+ 0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+ 0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (\
+ 1 | \
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+ 4 | \
+ 0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..80641945d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,25 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
new file mode 100644
index 000000000..b2f41a354
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m1)
+
+set(JLINK_DEVICE R7FA6M1AD)
+
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC)
+# target_sources(${TARGET} PRIVATE)
+# target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
new file mode 100644
index 000000000..f73a08fc0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -0,0 +1,51 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 BSP_IO_PORT_01_PIN_12
+#define LED_STATE_ON 1
+
+#define SW1 BSP_IO_PORT_04_PIN_15
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT },
+ { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+ // USB FS
+ { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.mk b/hw/bsp/ra/boards/ra6m1_ek/board.mk
new file mode 100644
index 000000000..f06b693d8
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra6m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M1AD
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..772e5e5b1
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,68 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+#else
+ #define BSP_CFG_RTOS (0)
+#endif
+#endif
+
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..40bb3a3bf
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M1AD3CFP
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (524288)
+#define BSP_RAM_SIZE_BYTES (262144)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..5fedd754f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M1 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+#else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+#else
+ /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+ #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..945a6010b
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,23 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
new file mode 100644
index 000000000..c91d48a32
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -0,0 +1,22 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m5)
+
+set(JLINK_DEVICE R7FA6M5BH)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+set(PORT 1)
+endif()
+
+# Host port will be the other port
+set(HOST_PORT $)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ BOARD_TUD_RHPORT=${PORT}
+ BOARD_TUH_RHPORT=${HOST_PORT}
+ # port 0 is fullspeed, port 1 is highspeed
+ BOARD_TUD_MAX_SPEED=$
+ BOARD_TUH_MAX_SPEED=$
+ )
+endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
new file mode 100644
index 000000000..779f71810
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -0,0 +1,68 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 BSP_IO_PORT_00_PIN_08
+#define LED_STATE_ON 1
+
+#define SW1 BSP_IO_PORT_00_PIN_05
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
+ { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+
+ // USB FS
+ { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
+ { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+ { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+
+ // USB HS
+ { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
+ { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+ { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+
+ // ETM Trace
+ #ifdef TRACE_ETM
+ { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+ #endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
new file mode 100644
index 000000000..a5c933764
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -0,0 +1,10 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M5BH
+
+# Port 1 is highspeed
+PORT ?= 1
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..33d381850
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,63 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+#else
+ #define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..6845183db
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+#define BSP_MCU_FEATURE_SET ('B')
+#define BSP_ROM_SIZE_BYTES (2097152)
+#define BSP_RAM_SIZE_BYTES (524288)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..d5428540f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,387 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M5 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+#else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+
+#if defined(_RA_TZ_SECURE)
+ #define BSP_TZ_SECURE_BUILD (1)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #elif defined(_RA_TZ_NONSECURE)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (1)
+ #else
+#define BSP_TZ_SECURE_BUILD (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT (1)
+#define SCB_AIRCR_BFHFNMINS_VAL (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL (1)
+#define SCB_AIRCR_PRIS_VAL (0)
+#define TZ_FPU_NS_USAGE (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+ (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+ 0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+ 0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+ 0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+ 0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+ 0xfffffffc) /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+ 0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+ 0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+ 0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (\
+ 1 | \
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+ 4 | \
+ 0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..0eb5e0516
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,37 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
new file mode 100644
index 000000000..7b8ee9c95
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -0,0 +1,106 @@
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ Project.AddSvdFile ("Cortex-M33.svd");
+ Project.AddSvdFile ("./R7FA6M5BH.svd");
+
+ Project.SetDevice ("R7FA6M5BH");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("50 MHz");
+
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetTracePortWidth (4);
+
+ //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+ //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf");
+ File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf");
+}
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+ // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+ Project.SetJLinkScript("../../../debug.jlinkscript");
+}
+
+/*********************************************************************
+*
+* AfterTargetReset
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr != 0xFFFFFFFF) {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+ } else {
+ Util.Log("Project file error: failed to get program base");
+ }
+
+ PC = Elf.GetEntryPointPC();
+
+ if (PC != 0xFFFFFFFF) {
+ Target.SetReg("PC", PC);
+ } else if (VectorTableAddr != 0xFFFFFFFF) {
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
+
+/*********************************************************************
+*
+* AfterTargetDownload
+*
+* Function description
+* Event handler routine.
+* - Sets the PC register to program reset value.
+* - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+
+ if (VectorTableAddr != 0xFFFFFFFF) {
+ SP = Target.ReadU32(VectorTableAddr);
+ Target.SetReg("SP", SP);
+ } else {
+ Util.Log("Project file error: failed to get program base");
+ }
+
+ PC = Elf.GetEntryPointPC();
+
+ if (PC != 0xFFFFFFFF) {
+ Target.SetReg("PC", PC);
+ } else if (VectorTableAddr != 0xFFFFFFFF) {
+ PC = Target.ReadU32(VectorTableAddr + 4);
+ Target.SetReg("PC", PC);
+ }
+}
diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake
new file mode 100644
index 000000000..34780d776
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.cmake
@@ -0,0 +1,11 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+# target_compile_definitions(${TARGET} PUBLIC)
+# target_sources(${TARGET} PRIVATE)
+# target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h
new file mode 100644
index 000000000..72abda27f
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 BSP_IO_PORT_01_PIN_11 // D13
+#define LED_STATE_ON 1
+
+#define SW1 BSP_IO_PORT_01_PIN_10 // D12
+#define BUTTON_STATE_ACTIVE 0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+ {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+ {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+ // USB FS D+, D-, VBus
+ {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+ {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
new file mode 100644
index 000000000..b7075eec0
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -0,0 +1,9 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+LD_FILE = ${BOARD_PATH}/${BOARD}.ld
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..c1d1022cc
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..336918800
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CNE
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (262144)
+#define BSP_RAM_SIZE_BYTES (32768)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_QFN
+#define BSP_PACKAGE_PINS (48)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..fc604eb3b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,87 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA4M1 (1)
+#define BSP_LOCO_HZ (32768)
+#define BSP_MOCO_HZ (8000000)
+#define BSP_SUB_CLOCK_HZ (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+ #define BSP_HOCO_HZ (64000000)
+#else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
+#define BSP_MCU_VBATT_SUPPORT (1)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..63618ec4b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
new file mode 100644
index 000000000..45f11dfb1
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
@@ -0,0 +1,25 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+/* Uno R4 has bootloader */
+FLASH_IMAGE_START = 0x4000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/debug.jlinkscript b/hw/bsp/ra/debug.jlinkscript
new file mode 100644
index 000000000..b34cfaa7f
--- /dev/null
+++ b/hw/bsp/ra/debug.jlinkscript
@@ -0,0 +1,4 @@
+int SetupTarget(void) {
+ JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x80000");
+ return 0;
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
new file mode 100644
index 000000000..fdf4c8666
--- /dev/null
+++ b/hw/bsp/ra/family.c
@@ -0,0 +1,279 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Rafael Silva
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+#include "renesas.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY (0xA500U)
+
+static const ioport_cfg_t family_pin_cfg = {
+ .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = board_pin_cfg,
+};
+static ioport_instance_ctrl_t port_ctrl;
+
+//--------------------------------------------------------------------+
+// Vector Data
+//--------------------------------------------------------------------+
+
+BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS)
+const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+ [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+ [1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
+ [2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
+ [3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+ [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */
+ [5] = usbhs_d0fifo_handler, /* USBHS FIFO 0 (DMA transfer request 0) */
+ [6] = usbhs_d1fifo_handler, /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
+};
+
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+ [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
+ [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+ [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+ [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1), /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+ [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */
+ [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0), /* USBHS FIFO 0 (DMA transfer request 0) */
+ [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1), /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
+};
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_init(void) {
+ // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4
+ // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ)
+ __enable_irq();
+
+ /* Configure pins. */
+ R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
+
+#ifdef TRACE_ETM
+ // TRCKCR is protected by PRCR bit0 register
+ R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
+
+ // Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2
+ R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
+
+ R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+ NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+ NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+ NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+ board_led_write(false);
+}
+
+void board_init_after_tusb(void) {
+ // For board that use USB LDO regulator
+#if defined(BOARD_UNO_R4)
+ R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk;
+#endif
+}
+
+void board_led_write(bool state) {
+ R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
+}
+
+uint32_t board_button_read(void) {
+ bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE;
+ R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
+ return lvl == BUTTON_STATE_ACTIVE;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+ system_ticks++;
+}
+
+uint32_t board_millis(void) {
+ return system_ticks;
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT)
+ #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
+#else
+ #define PORT_SUPPORT_DEVICE(_n) 0
+#endif
+
+#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT)
+ #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n)
+#else
+ #define PORT_SUPPORT_HOST(_n) 0
+#endif
+
+//------------- USB0 FullSpeed -------------//
+void usbfs_interrupt_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+
+ #if PORT_SUPPORT_HOST(0)
+ tuh_int_handler(0, true);
+ #endif
+
+ #if PORT_SUPPORT_DEVICE(0)
+ tud_int_handler(0);
+ #endif
+}
+
+void usbfs_resume_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+
+ #if PORT_SUPPORT_HOST(0)
+ tuh_int_handler(0, true);
+ #endif
+
+ #if PORT_SUPPORT_DEVICE(0)
+ tud_int_handler(0);
+ #endif
+}
+
+void usbfs_d0fifo_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+ // TODO not used yet
+}
+
+void usbfs_d1fifo_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+ // TODO not used yet
+}
+
+//------------- USB1 HighSpeed -------------//
+#ifdef BOARD_HAS_USB_HIGHSPEED
+
+void usbhs_interrupt_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+
+ #if PORT_SUPPORT_HOST(1)
+ tuh_int_handler(1, true);
+ #endif
+
+ #if PORT_SUPPORT_DEVICE(1)
+ tud_int_handler(1);
+ #endif
+}
+
+void usbhs_d0fifo_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+ // TODO not used yet
+}
+
+void usbhs_d1fifo_handler(void) {
+ IRQn_Type irq = R_FSP_CurrentIrqGet();
+ R_BSP_IrqStatusClear(irq);
+ // TODO not used yet
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// stdlib
+//--------------------------------------------------------------------+
+
+int close(int fd) {
+ (void) fd;
+ return -1;
+}
+
+int fstat(int fd, void *pstat) {
+ (void) fd;
+ (void) pstat;
+ return 0;
+}
+
+off_t lseek(int fd, off_t pos, int whence) {
+ (void) fd;
+ (void) pos;
+ (void) whence;
+ return 0;
+}
+
+int isatty(int fd) {
+ (void) fd;
+ return 1;
+}
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
new file mode 100644
index 000000000..11bc7c668
--- /dev/null
+++ b/hw/bsp/ra/family.cmake
@@ -0,0 +1,133 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+#set(FREERTOS_PORT A_CUSTOM_PORT CACHE INTERNAL "")
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+ ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/system.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_clocks.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_common.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_delay.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_group_irq.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_guard.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_io.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
+ ${FSP_RA}/src/bsp/mcu/all/bsp_security.c
+ ${FSP_RA}/src/r_ioport/r_ioport.c
+ )
+
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ -ffreestanding
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp
+ ${CMSIS_DIR}/CMSIS/Core/Include
+ ${FSP_RA}/inc
+ ${FSP_RA}/inc/api
+ ${FSP_RA}/inc/instances
+ ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
+ ${FSP_RA}/src/bsp/mcu/all
+ ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld)
+ endif ()
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ # linker file
+ "LINKER:--script=${LD_FILE_GNU}"
+ -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc
+ -nostartfiles
+ # nanolib
+ --specs=nano.specs
+ --specs=nosys.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ )
+
+# # RA has custom freertos port
+# if (NOT TARGET freertos_kernel_port)
+# add_library(freertos_kernel_port STATIC)
+# target_sources(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port/port.c)
+# target_include_directories(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port)
+#
+# target_link_libraries(freertos_kernel_port PUBLIC freertos_kernel)
+# endif ()
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
+ ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+ ${TOP}/src/portable/renesas/rusb2/rusb2_common.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+
+ if (DEFINED DFU_UTIL_VID_PID)
+ family_add_bin_hex(${TARGET})
+ family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID})
+ endif ()
+endfunction()
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
new file mode 100644
index 000000000..9afb38e06
--- /dev/null
+++ b/hw/bsp/ra/family.mk
@@ -0,0 +1,73 @@
+DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
+
+FSP_RA = hw/mcu/renesas/fsp/ra/fsp
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+# Don't include options setting in .bin file since it create unnecessary large file due to padding
+OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss
+
+# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
+PORT ?= 0
+
+CFLAGS += \
+ -flto \
+ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
+ -DBOARD_TUD_RHPORT=$(PORT) \
+ -Wno-error=undef \
+ -Wno-error=strict-prototypes \
+ -Wno-error=cast-align \
+ -Wno-error=cast-qual \
+ -Wno-error=unused-but-set-variable \
+ -Wno-error=unused-variable \
+ -nostdlib \
+ -nostartfiles \
+ -ffreestanding
+
+ifeq ($(PORT), 1)
+ CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+ $(info "Using PORT 1 HighSpeed")
+else
+ CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+ $(info "Using PORT 0 FullSpeed")
+endif
+
+SRC_C += \
+ src/portable/renesas/rusb2/dcd_rusb2.c \
+ src/portable/renesas/rusb2/hcd_rusb2.c \
+ src/portable/renesas/rusb2/rusb2_common.c \
+ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
+ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_common.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_delay.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_group_irq.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_guard.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_io.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_irq.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_register_protection.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_rom_registers.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_sbrk.c \
+ $(FSP_RA)/src/bsp/mcu/all/bsp_security.c \
+ $(FSP_RA)/src/r_ioport/r_ioport.c \
+
+INC += \
+ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+ $(TOP)/$(BOARD_PATH) \
+ $(TOP)/$(BOARD_PATH)/fsp_cfg \
+ $(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \
+ $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
+ $(TOP)/$(FSP_RA)/inc \
+ $(TOP)/$(FSP_RA)/inc/api \
+ $(TOP)/$(FSP_RA)/inc/instances \
+ $(TOP)/$(FSP_RA)/src/bsp/mcu/all \
+ $(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
+
+ifndef LD_FILE
+LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
+endif
+
+LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
+
+# For freeRTOS port source
+# hack to use the port provided by renesas
+FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/hw/bsp/ra/linker/gcc/fsp.ld b/hw/bsp/ra/linker/gcc/fsp.ld
new file mode 100644
index 000000000..453d46f24
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/fsp.ld
@@ -0,0 +1,716 @@
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0;
+NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START;
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* Initialized ITCM data. */
+ .itcm_data :
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start__ = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* All ITCM data end */
+ __itcm_data_end__ = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192);
+ } > ITCM
+
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ . = ALIGN(128);
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ /* Start address of the initial values for .dtcm_data. */
+ __dtcm_data_init_start = __etext + __data_end__ - __data_start__;
+
+ /* Initialized DTCM data. */
+ .dtcm_data :
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start__ = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end__ = .;
+ } > DTCM AT > FLASH
+
+ /* Uninitialized DTCM data. */
+ .dtcm_noinit (NOLOAD):
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_noinit_start = .;
+
+ KEEP(*(.dtcm_noinit*))
+
+ /* Uninitialized DTCM data end */
+ __dtcm_noinit_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192);
+ } > DTCM
+
+ /* TrustZone Secure Gateway Stubs Section. */
+
+ /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */
+ /* 1. Get the address to the next block after the .data section in FLASH. */
+ DATA_END = LOADADDR(.data) + SIZEOF(.data);
+ /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024);
+ /* 3. Manually specify the start location for .gnu.sgstubs */
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+ .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
+ .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
+ .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ PROVIDE(end = .);
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld
new file mode 100644
index 000000000..218acbb2a
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra4m1.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld
new file mode 100644
index 000000000..7b3a63fbe
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra4m3.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x20000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x100000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld
new file mode 100644
index 000000000..91d27f74c
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra6m1.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x1FFE0000;
+RAM_LENGTH = 0x40000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x80000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x0100A150;
+ID_CODE_LENGTH = 0x10;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld
new file mode 100644
index 000000000..af747fd9b
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra6m5.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x80000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x200000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x68000000;
+OSPI_DEVICE_0_LENGTH = 0x8000000;
+OSPI_DEVICE_1_START = 0x70000000;
+OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/r_ioport_cfg.h b/hw/bsp/ra/r_ioport_cfg.h
new file mode 100644
index 000000000..cb7c07932
--- /dev/null
+++ b/hw/bsp/ra/r_ioport_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
new file mode 100644
index 000000000..ca667faa3
--- /dev/null
+++ b/hw/bsp/ra/vector_data.h
@@ -0,0 +1,36 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#ifndef VECTOR_DATA_H
+#define VECTOR_DATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ISR prototypes */
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+void usbhs_interrupt_handler(void);
+void usbhs_d0fifo_handler(void);
+void usbhs_d1fifo_handler(void);
+#endif
+
+/* Vector table allocations */
+#define USBFS_INT_IRQn 0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3
+
+#define USBHS_USB_INT_RESUME_IRQn 4 /* USBHS USB INT RESUME (USBHS interrupt) */
+#define USBHS_FIFO_0_IRQn 5 /* USBHS FIFO 0 (DMA transfer request 0) */
+#define USBHS_FIFO_1_IRQn 6 /* USBHS FIFO 1 (DMA transfer request 1) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index f25f80e09..063c9580e 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2021, Ha Thach (tinyusb.org)
@@ -31,6 +31,7 @@
extern "C" {
#endif
+// LED
#ifdef PICO_DEFAULT_LED_PIN
#define LED_PIN PICO_DEFAULT_LED_PIN
#define LED_STATE_ON (!(PICO_DEFAULT_LED_PIN_INVERTED))
@@ -40,22 +41,37 @@
#define BUTTON_BOOTSEL
#define BUTTON_STATE_ACTIVE 0
-#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && defined(PICO_DEFAULT_UART)
+// UART
+#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \
+ defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART)
#define UART_DEV PICO_DEFAULT_UART
#define UART_TX_PIN PICO_DEFAULT_UART_TX_PIN
#define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN
#endif
-// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to other pin
-#ifndef PIO_USB_DP_PIN
-#define PIO_USB_DP_PIN 20
+//--------------------------------------------------------------------+
+// PIO_USB
+// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined
+//--------------------------------------------------------------------+
+
+// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#define PICO_DEFAULT_PIO_USB_DP_PIN 16
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18
+#endif
+
+#ifndef PICO_DEFAULT_PIO_USB_DP_PIN
+#define PICO_DEFAULT_PIO_USB_DP_PIN 20
#endif
// VBUS enable pin and its active state
-#define PIO_USB_VBUSEN_PIN 22
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22
+#endif
-#ifndef PIO_USB_VBUSEN_STATE
-#define PIO_USB_VBUSEN_STATE 1
+// VBUS enable state
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_STATE
+#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
#endif
#ifdef __cplusplus
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
index 8280c835d..f9887c09c 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
@@ -1 +1 @@
-set(PICO_BOARD pico)
\ No newline at end of file
+set(PICO_BOARD pico)
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index f7ee56990..aa9d00c23 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -27,12 +27,13 @@
#include "pico/stdlib.h"
#include "pico/binary_info.h"
+#include "pico/unique_id.h"
#include "hardware/gpio.h"
#include "hardware/sync.h"
#include "hardware/structs/ioqspi.h"
#include "hardware/structs/sio.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
@@ -93,12 +94,12 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) {
static void stdio_rtt_write (const char *buf, int length)
{
- SEGGER_RTT_Write(0, buf, length);
+ SEGGER_RTT_Write(0, buf, (unsigned) length);
}
static int stdio_rtt_read (char *buf, int len)
{
- return SEGGER_RTT_Read(0, buf, len);
+ return (int) SEGGER_RTT_Read(0, buf, (unsigned) len);
}
static stdio_driver_t stdio_rtt =
@@ -125,16 +126,16 @@ void board_init(void)
// Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
set_sys_clock_khz(120000, true);
-#ifdef PIO_USB_VBUSEN_PIN
- gpio_init(PIO_USB_VBUSEN_PIN);
- gpio_set_dir(PIO_USB_VBUSEN_PIN, GPIO_OUT);
- gpio_put(PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
+#ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
+ gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN);
+ gpio_set_dir(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, GPIO_OUT);
+ gpio_put(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, PICO_DEFAULT_PIO_USB_VBUSEN_STATE);
#endif
// rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack
// Note: tuh_configure() must be called before tuh_init()
pio_usb_configuration_t pio_cfg = PIO_USB_DEFAULT_CONFIG;
- pio_cfg.pin_dp = PIO_USB_DP_PIN;
+ pio_cfg.pin_dp = PICO_DEFAULT_PIO_USB_DP_PIN;
tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
#endif
@@ -148,8 +149,8 @@ void board_init(void)
#ifndef BUTTON_BOOTSEL
#endif
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
- bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
+#ifdef UART_DEV
+ bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_RX_PIN, GPIO_FUNC_UART));
uart_inst = uart_get_instance(UART_DEV);
stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
#endif
@@ -171,17 +172,15 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
(void) state;
#ifdef LED_PIN
- gpio_put(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+ gpio_put(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
#endif
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
#ifdef BUTTON_BOOTSEL
return BUTTON_STATE_ACTIVE == get_bootsel_button();
#else
@@ -189,12 +188,21 @@ uint32_t board_button_read(void)
#endif
}
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ pico_unique_board_id_t pico_id;
+ pico_get_unique_board_id(&pico_id);
+
+ size_t len = PICO_UNIQUE_BOARD_ID_SIZE_BYTES;
+ if (len > max_len) len = max_len;
+
+ memcpy(id, pico_id.id, len);
+ return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
#ifdef UART_DEV
int count = 0;
- while ( (count < len) && uart_is_readable(uart_inst) )
- {
+ while ( (count < len) && uart_is_readable(uart_inst) ) {
buf[count] = uart_getc(uart_inst);
count++;
}
@@ -205,11 +213,10 @@ int board_uart_read(uint8_t* buf, int len)
#endif
}
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
#ifdef UART_DEV
- char const* bufch = (char const*) buf;
- for(int i=0;iDHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);
+
+ // Configure GCLK for SERCOM
+// GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) |
+ GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+ while (GCLK->STATUS.bit.SYNCBUSY);
+
+ Sercom* sercom = MAX3421_SERCOM;
+
+ // Disable the SPI module
+ sercom->SPI.CTRLA.bit.ENABLE = 0;
+
+ // Reset the SPI module
+ sercom->SPI.CTRLA.bit.SWRST = 1;
+ while (sercom->SPI.SYNCBUSY.bit.SWRST);
+
+ // Set up SPI in master mode, MSB first, SPI mode 0
+ sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+ SERCOM_SPI_CTRLA_MODE(3);
+
+ sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+ while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+ // Set the baud rate
+ sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
+
+ // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
+ gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
+
+ gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
+
+ gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+ gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
+
+ // CS pin
+ gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+ // Enable the SPI module
+ sercom->SPI.CTRLA.bit.ENABLE = 1;
+ while (sercom->SPI.SYNCBUSY.bit.ENABLE);
+
+ //------------- External Interrupt -------------//
+
+ // Enable the APB clock for EIC (External Interrupt Controller)
+ PM->APBAMASK.reg |= PM_APBAMASK_EIC;
+
+ // Configure GCLK for EIC
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+ while (GCLK->STATUS.bit.SYNCBUSY);
+
+ // Configure PA20 as an input with function A (external interrupt)
+ gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+ gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+ gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+ // Disable EIC
+ EIC->CTRL.bit.ENABLE = 0;
+ while (EIC->STATUS.bit.SYNCBUSY);
+
+ // Configure EIC to trigger on falling edge
+ uint8_t const sense_shift = MAX3421_INTR_EIC_ID * 4;
+ EIC->CONFIG[0].reg &= ~(7 << sense_shift);
+ EIC->CONFIG[0].reg |= 2 << sense_shift;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(EIC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+ // Enable External Interrupt
+ EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+ // Enable EIC
+ EIC->CTRL.bit.ENABLE = 1;
+ while (EIC->STATUS.bit.SYNCBUSY);
+}
+
+void EIC_Handler(void) {
+ // Clear the interrupt flag
+ EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+ // Call the TinyUSB interrupt handler
+ tuh_int_handler(1, true);
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+ (void) rhport;
+
+ if (enabled) {
+ NVIC_EnableIRQ(EIC_IRQn);
+ } else {
+ NVIC_DisableIRQ(EIC_IRQn);
+ }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+ (void) rhport;
+ gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+ (void) rhport;
+
+ Sercom* sercom = MAX3421_SERCOM;
+
+ for (size_t count = 0; count < xfer_bytes; count++) {
+ // Wait for the transmit buffer to be empty
+ while (!sercom->SPI.INTFLAG.bit.DRE);
+
+ // Write data to be transmitted
+ uint8_t data = 0x00;
+ if (tx_buf) {
+ data = tx_buf[count];
+ }
+
+ sercom->SPI.DATA.reg = (uint32_t) data;
+
+ // Wait for the receive buffer to be filled
+ while (!sercom->SPI.INTFLAG.bit.RXC);
+
+ // Read received data
+ data = (uint8_t) sercom->SPI.DATA.reg;
+ if (rx_buf) {
+ rx_buf[count] = data;
+ }
+ }
+
+ // wait for bus idle and clear flags
+ while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+ sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
+ return true;
+}
+
#endif
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
new file mode 100644
index 000000000..07186934a
--- /dev/null
+++ b/hw/bsp/samd21/family.cmake
@@ -0,0 +1,105 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samd21)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD21 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/gcc/system_samd21.c
+ ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+ ${SDK_DIR}/hpl/pm/hpl_pm.c
+ ${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c
+ ${SDK_DIR}/hal/src/hal_atomic.c
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}
+ ${SDK_DIR}/config
+ ${SDK_DIR}/include
+ ${SDK_DIR}/hal/include
+ ${SDK_DIR}/hal/utils/include
+ ${SDK_DIR}/hpl/pm
+ ${SDK_DIR}/hpl/port
+ ${SDK_DIR}/hri
+ ${SDK_DIR}/CMSIS/Include
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC CONF_DFLL_OVERWRITE_CALIBRATION=0)
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd21.c)
+ endif ()
+
+ target_sources(${BOARD_TARGET} PRIVATE
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/microchip/samd/dcd_samd.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 95421e753..79c63812d 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -1,43 +1,41 @@
UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
+SDK_DIR = hw/mcu/microchip/samd21
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
-nostdlib -nostartfiles \
-DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
-DCFG_TUSB_MCU=OPT_MCU_SAMD21
# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
- hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
- hw/mcu/microchip/samd21/gcc/system_samd21.c \
- hw/mcu/microchip/samd21/hpl/gclk/hpl_gclk.c \
- hw/mcu/microchip/samd21/hpl/pm/hpl_pm.c \
- hw/mcu/microchip/samd21/hpl/sysctrl/hpl_sysctrl.c \
- hw/mcu/microchip/samd21/hal/src/hal_atomic.c
+ ${SDK_DIR}/gcc/gcc/startup_samd21.c \
+ ${SDK_DIR}/gcc/system_samd21.c \
+ ${SDK_DIR}/hpl/gclk/hpl_gclk.c \
+ ${SDK_DIR}/hpl/pm/hpl_pm.c \
+ ${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c \
+ ${SDK_DIR}/hal/src/hal_atomic.c
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/hw/mcu/microchip/samd21/ \
- $(TOP)/hw/mcu/microchip/samd21/config \
- $(TOP)/hw/mcu/microchip/samd21/include \
- $(TOP)/hw/mcu/microchip/samd21/hal/include \
- $(TOP)/hw/mcu/microchip/samd21/hal/utils/include \
- $(TOP)/hw/mcu/microchip/samd21/hpl/pm/ \
- $(TOP)/hw/mcu/microchip/samd21/hpl/port \
- $(TOP)/hw/mcu/microchip/samd21/hri \
- $(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+ $(TOP)/${SDK_DIR}/ \
+ $(TOP)/${SDK_DIR}/config \
+ $(TOP)/${SDK_DIR}/include \
+ $(TOP)/${SDK_DIR}/hal/include \
+ $(TOP)/${SDK_DIR}/hal/utils/include \
+ $(TOP)/${SDK_DIR}/hpl/pm/ \
+ $(TOP)/${SDK_DIR}/hpl/port \
+ $(TOP)/${SDK_DIR}/hri \
+ $(TOP)/${SDK_DIR}/CMSIS/Include
# flash using bossac at least version 1.8
# can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..32db4ad95
--- /dev/null
+++ b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<APBAMASK.reg, MCLK_APBAMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, SERCOM0_GCLK_ID_SLOW },
+ { &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM1, SERCOM1_GCLK_ID_CORE, SERCOM1_GCLK_ID_SLOW },
+ { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM2, SERCOM2_GCLK_ID_CORE, SERCOM2_GCLK_ID_SLOW },
+ { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM3, SERCOM3_GCLK_ID_CORE, SERCOM3_GCLK_ID_SLOW },
+ { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM4, SERCOM4_GCLK_ID_CORE, SERCOM4_GCLK_ID_SLOW },
+ { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM5, SERCOM5_GCLK_ID_CORE, SERCOM5_GCLK_ID_SLOW },
+ #ifdef SERCOM6_GCLK_ID_CORE
+ { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM6, SERCOM6_GCLK_ID_CORE, SERCOM6_GCLK_ID_SLOW },
+ #endif
+ #ifdef SERCOM7_GCLK_ID_CORE
+ { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM7, SERCOM7_GCLK_ID_CORE, SERCOM7_GCLK_ID_SLOW },
+ #endif
+ };
+
+ Sercom* sercom = MAX3421_SERCOM;
+
+ // Enable the APB clock for SERCOM
+ *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
+
+ // Configure GCLK for SERCOM
+ GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg =
+ GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+ GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg =
+ GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+ // Disable the SPI module
+ sercom->SPI.CTRLA.bit.ENABLE = 0;
+
+ // Reset the SPI module
+ sercom->SPI.CTRLA.bit.SWRST = 1;
+ while (sercom->SPI.SYNCBUSY.bit.SWRST);
+
+ // Set up SPI in master mode, MSB first, SPI mode 0
+ sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+ SERCOM_SPI_CTRLA_MODE(3);
+
+ sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+ while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+ // Set the baud rate
+ uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
+ if (baud_reg) {
+ baud_reg--;
+ }
+
+ sercom->SPI.BAUD.reg = baud_reg;
+
+ // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
+ gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
+
+ gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
+
+ gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+ gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+ gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
+
+ // CS pin
+ gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+ gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+ // Enable the SPI module
+ sercom->SPI.CTRLA.bit.ENABLE = 1;
+ while (sercom->SPI.SYNCBUSY.bit.ENABLE);
+
+ //------------- External Interrupt -------------//
+
+ // Enable the APB clock for EIC (External Interrupt Controller)
+ MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+
+ // Configure GCLK for EIC
+ GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+ // Configure PA20 as an input with function A (external interrupt)
+ gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+ gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+ gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+ // Disable EIC
+ EIC->CTRLA.bit.ENABLE = 0;
+ while (EIC->SYNCBUSY.bit.ENABLE);
+
+ // Configure EIC to trigger on falling edge
+ volatile uint32_t* eic_config;
+ uint8_t sense_shift;
+ if (MAX3421_INTR_EIC_ID < 8) {
+ eic_config = &EIC->CONFIG[0].reg;
+ sense_shift = MAX3421_INTR_EIC_ID * 4;
+ } else {
+ eic_config = &EIC->CONFIG[1].reg;
+ sense_shift = (MAX3421_INTR_EIC_ID - 8) * 4;
+ }
+
+ *eic_config &= ~(7 << sense_shift);
+ *eic_config |= 2 << sense_shift;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+ // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+ NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+ // Enable External Interrupt
+ EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+ // Enable EIC
+ EIC->CTRLA.bit.ENABLE = 1;
+ while (EIC->SYNCBUSY.bit.ENABLE);
+}
+
+void MAX3421_EIC_Handler(void) {
+ // Clear the interrupt flag
+ EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+ // Call the TinyUSB interrupt handler
+ tuh_int_handler(1, true);
+}
+
+// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+ (void) rhport;
+
+ const IRQn_Type irq = EIC_0_IRQn + MAX3421_INTR_EIC_ID;
+ if (enabled) {
+ NVIC_EnableIRQ(irq);
+ } else {
+ NVIC_DisableIRQ(irq);
+ }
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+ (void) rhport;
+ gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+ (void) rhport;
+
+ Sercom* sercom = MAX3421_SERCOM;
+
+ for (size_t count = 0; count < xfer_bytes; count++) {
+ // Wait for the transmit buffer to be empty
+ while (!sercom->SPI.INTFLAG.bit.DRE);
+
+ // Write data to be transmitted
+ uint8_t data = 0x00;
+ if (tx_buf) {
+ data = tx_buf[count];
+ }
+
+ sercom->SPI.DATA.reg = (uint32_t) data;
+
+ // Wait for the receive buffer to be filled
+ while (!sercom->SPI.INTFLAG.bit.RXC);
+
+ // Read received data
+ data = (uint8_t) sercom->SPI.DATA.reg;
+ if (rx_buf) {
+ rx_buf[count] = data;
+ }
+ }
+
+ // wait for bus idle and clear flags
+ while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+ sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
+ return true;
+}
+
#endif
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
new file mode 100644
index 000000000..fa9586066
--- /dev/null
+++ b/hw/bsp/samd51/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samd51)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD51 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ add_library(${BOARD_TARGET} STATIC
+ ${SDK_DIR}/gcc/system_samd51.c
+ ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+ ${SDK_DIR}/hpl/mclk/hpl_mclk.c
+ ${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c
+ ${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c
+ ${SDK_DIR}/hal/src/hal_atomic.c
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${SDK_DIR}/
+ ${SDK_DIR}/config
+ ${SDK_DIR}/include
+ ${SDK_DIR}/hal/include
+ ${SDK_DIR}/hal/utils/include
+ ${SDK_DIR}/hpl/port
+ ${SDK_DIR}/hri
+ ${SDK_DIR}/CMSIS/Include
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+ message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+ endif ()
+
+ if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+ set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd51.c)
+ endif ()
+
+ target_sources(${BOARD_TARGET} PRIVATE
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ --specs=nosys.specs --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/microchip/samd/dcd_samd.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 783bed82a..9a6c67e1a 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -2,19 +2,15 @@ UF2_FAMILY_ID = 0x55114460
DEPS_SUBMODULES += hw/mcu/microchip
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-nostdlib -nostartfiles \
-DCFG_TUSB_MCU=OPT_MCU_SAMD51
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
@@ -37,9 +33,6 @@ INC += \
$(TOP)/hw/mcu/microchip/samd51/hri \
$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
# flash using bossac at least version 1.8
# can be found in arduino15/packages/arduino/tools/bossac/
# Add it to your PATH or change BOSSAC variable to match your installation
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
deleted file mode 100644
index 2d0d928ff..000000000
--- a/hw/bsp/same54xplainedpro/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CONF_CPU_FREQUENCY ?= 48000000
-
-CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mlong-calls \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
- -nostdlib -nostartfiles \
- -D__SAME54P20A__ \
- -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
- -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
- -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
-
-SRC_C += \
- src/portable/microchip/samd/dcd_samd.c \
- hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
- hw/mcu/microchip/same54/gcc/system_same54.c \
- hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
-
-INC += \
- $(TOP)/hw/mcu/microchip/same54/ \
- $(TOP)/hw/mcu/microchip/same54/config \
- $(TOP)/hw/mcu/microchip/same54/include \
- $(TOP)/hw/mcu/microchip/same54/hal/include \
- $(TOP)/hw/mcu/microchip/same54/hal/utils/include \
- $(TOP)/hw/mcu/microchip/same54/hpl/port \
- $(TOP)/hw/mcu/microchip/same54/hri \
- $(TOP)/hw/mcu/microchip/same54/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME54P20
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
- edbg --verbose -t same54 -pv -f $<
diff --git a/hw/bsp/same5x/boards/d5035_01/board.mk b/hw/bsp/same5x/boards/d5035_01/board.mk
new file mode 100644
index 000000000..c53411bb8
--- /dev/null
+++ b/hw/bsp/same5x/boards/d5035_01/board.mk
@@ -0,0 +1,21 @@
+MCU = same51
+
+HWREV ?= 1
+
+CFLAGS += \
+ -D__SAME51J19A__ \
+ -DCONF_CPU_FREQUENCY=80000000 \
+ -DCONF_GCLK_USB_FREQUENCY=48000000 \
+ -DD5035_01=1 \
+ -DBOARD_NAME="\"D5035-01\"" \
+ -DSVC_Handler=SVCall_Handler \
+ -DHWREV=$(HWREV)
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same51j19a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME51J19
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/d5035_01/d5035_01.c b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
similarity index 99%
rename from hw/bsp/d5035_01/d5035_01.c
rename to hw/bsp/same5x/boards/d5035_01/d5035_01.c
index f356851f7..eb5768d0d 100644
--- a/hw/bsp/d5035_01/d5035_01.c
+++ b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
@@ -24,7 +24,7 @@
*/
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include
diff --git a/hw/bsp/d5035_01/same51j19a_flash.ld b/hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
similarity index 100%
rename from hw/bsp/d5035_01/same51j19a_flash.ld
rename to hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
diff --git a/hw/bsp/same5x/boards/same54_xplained/board.mk b/hw/bsp/same5x/boards/same54_xplained/board.mk
new file mode 100644
index 000000000..41cf95bfc
--- /dev/null
+++ b/hw/bsp/same5x/boards/same54_xplained/board.mk
@@ -0,0 +1,12 @@
+MCU = same54
+
+CFLAGS += \
+ -DCONF_CPU_FREQUENCY=48000000 \
+ -D__SAME54P20A__ \
+ -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same54p20a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME54P20
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
similarity index 99%
rename from hw/bsp/same54xplainedpro/same54xplainedpro.c
rename to hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
index ba1eec38b..93adea63e 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
@@ -24,7 +24,7 @@
*/
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include
diff --git a/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
similarity index 99%
rename from hw/bsp/same54xplainedpro/same54p20a_flash.ld
rename to hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
index 97072bfe6..1f427a066 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_flash.ld
+++ b/hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
similarity index 99%
rename from hw/bsp/same54xplainedpro/same54p20a_sram.ld
rename to hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
index 6219f4afe..e6e33ec48 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_sram.ld
+++ b/hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
new file mode 100644
index 000000000..691863f11
--- /dev/null
+++ b/hw/bsp/same5x/family.mk
@@ -0,0 +1,36 @@
+DEPS_SUBMODULES += hw/mcu/microchip
+
+SDK_DIR = hw/mcu/microchip/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
+CFLAGS += \
+ -mthumb \
+ -mlong-calls \
+ -nostdlib -nostartfiles \
+ -DCFG_TUSB_MCU=OPT_MCU_SAME5X
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
+
+SRC_C += \
+ src/portable/microchip/samd/dcd_samd.c \
+ $(SDK_DIR)/gcc/gcc/startup_$(MCU).c \
+ $(SDK_DIR)/gcc/system_$(MCU).c \
+ $(SDK_DIR)/hal/utils/src/utils_syscalls.c
+
+INC += \
+ $(TOP)/$(SDK_DIR) \
+ $(TOP)/$(SDK_DIR)/config \
+ $(TOP)/$(SDK_DIR)/include \
+ $(TOP)/$(SDK_DIR)/hal/include \
+ $(TOP)/$(SDK_DIR)/hal/utils/include \
+ $(TOP)/$(SDK_DIR)/hpl/port \
+ $(TOP)/$(SDK_DIR)/hri \
+ $(TOP)/$(SDK_DIR)/CMSIS/Include
+
+# flash using edbg from https://github.com/ataradov/edbg
+flash-edbg: $(BUILD)/$(PROJECT).bin
+ edbg --verbose -t $(MCU) -pv -f $<
+
+flash: flash-edbg
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 2aa09f5dd..ad5af2020 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -11,7 +11,10 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_SAMX7X
# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
ASF_DIR = hw/mcu/microchip/same70
@@ -44,7 +47,7 @@ INC += \
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
# For flash-jlink target
JLINK_DEVICE = SAME70N19B
diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c
index 6e6ad0602..e5f0da198 100644
--- a/hw/bsp/same70_qmtech/same70_qmtech.c
+++ b/hw/bsp/same70_qmtech/same70_qmtech.c
@@ -24,7 +24,7 @@
*/
#include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "peripheral_clk_config.h"
#include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index cbc51e6b0..769d03e21 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -11,7 +11,10 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_SAMX7X
# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
ASF_DIR = hw/mcu/microchip/same70
@@ -44,7 +47,7 @@ INC += \
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
# For flash-jlink target
JLINK_DEVICE = SAME70Q21B
@@ -53,4 +56,4 @@ JLINK_DEVICE = SAME70Q21B
# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
# edbg -t same70 -F w0,1,1
flash: $(BUILD)/$(PROJECT).bin
- edbg --verbose -t same70 -pv -f $<
+ edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index e6e7db0f3..f532c6927 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -24,7 +24,7 @@
*/
#include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "peripheral_clk_config.h"
#include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index d0d0ade01..ed0d59772 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,10 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_SAMG
# suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference -Wno-error=redundant-decls
+CFLAGS += -Wno-error=undef -Wno-error=null-dereference -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
ASF_DIR = hw/mcu/microchip/samg55
@@ -42,11 +45,11 @@ INC += \
$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
# For flash-jlink target
JLINK_DEVICE = ATSAMG55J19
# flash using edbg from https://github.com/ataradov/edbg
flash: $(BUILD)/$(PROJECT).bin
- edbg --verbose -t samg55 -pv -f $<
+ edbg --verbose -t samg55 -pv -f $<
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c
index 027c88e2f..2ac0c0a29 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg55xplained/samg55xplained.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019, hathach (tinyusb.org)
@@ -24,7 +24,7 @@
*/
#include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "peripheral_clk_config.h"
#include "hal/include/hal_init.h"
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
index a3e03997c..315e40c78 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h
index 13a326000..72e9897b6 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.h
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
index d1aaa44fc..156c3e7e4 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
+++ b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
index 7fc690ab2..735f6afc8 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
index d1aaa44fc..156c3e7e4 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
@@ -14,9 +14,9 @@
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
- *
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c
index 470fde750..438fe8bfa 100644
--- a/hw/bsp/saml2x/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,7 +25,7 @@
*/
#include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
#include "hal/include/hal_gpio.h"
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index afb0afc03..0acb0ed14 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,20 +1,20 @@
UF2_FAMILY_ID = 0x68ed2b88
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
CFLAGS += \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0plus \
-nostdlib -nostartfiles \
-DCONF_OSC32K_CALIB_ENABLE=0 \
-DCFG_TUSB_MCU=OPT_MCU_SAML22
# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
SRC_C += \
src/portable/microchip/samd/dcd_samd.c \
@@ -29,7 +29,7 @@ SRC_C += \
INC += \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/$(MCU_DIR)/ \
+ $(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/config \
$(TOP)/$(MCU_DIR)/include \
$(TOP)/$(MCU_DIR)/hal/include \
@@ -38,9 +38,6 @@ INC += \
$(TOP)/$(MCU_DIR)/hri \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
# flash using bossac at least version 1.8
# can be found in arduino15/packages/arduino/tools/bossac/
# Add it to your PATH or change BOSSAC variable to match your installation
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index ddafa8a2b..f9c1dd4db 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -35,7 +35,7 @@ INC += \
$(TOP)/hw/bsp/$(BOARD)
# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
# For flash-jlink target
JLINK_DEVICE = EFM32GG12B810F1024
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
index b5eb5ed5d..23ef6d7cd 100644
--- a/hw/bsp/sltb009a/sltb009a.c
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2021 Rafael Silva (@perigoso)
@@ -25,7 +25,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "../board.h"
+#include "../board_api.h"
#include "em_device.h"
@@ -712,7 +712,7 @@ uint32_t board_millis(void)
* @retval None
*/
void assert_failed(char *file, uint32_t line)
-{
+{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
diff --git a/hw/bsp/spresense/board_spresense.c b/hw/bsp/spresense/board_spresense.c
index 256bccd15..8cd04a49d 100644
--- a/hw/bsp/spresense/board_spresense.c
+++ b/hw/bsp/spresense/board_spresense.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright 2019 Sony Semiconductor Solutions Corporation
@@ -29,7 +29,7 @@
#include
#include
-#include "bsp/board.h"
+#include "bsp/board_api.h"
/*------------------------------------------------------------------*/
/* MACRO TYPEDEF CONSTANT ENUM
@@ -64,7 +64,7 @@ void board_led_write(bool state)
// a '1' means active (pressed), a '0' means inactive.
uint32_t board_button_read(void)
{
- if (board_gpio_read(BUTTON_PIN))
+ if (board_gpio_read(BUTTON_PIN))
{
return 0;
}
@@ -96,7 +96,7 @@ uint32_t board_millis(void)
/* Wait until RTC is available */
while (g_rtc_enabled == false);
- if (clock_gettime(CLOCK_MONOTONIC, &tp))
+ if (clock_gettime(CLOCK_MONOTONIC, &tp))
{
return 0;
}
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..33440d288
--- /dev/null
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "stm32f0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH
- .ARM.extab : {
+ .ARM.extab : {
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} >FLASH
-
+
.ARM : {
. = ALIGN(4);
__exidx_start = .;
@@ -124,7 +124,7 @@ SECTIONS
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
-
+
.init_array :
{
. = ALIGN(4);
@@ -134,7 +134,7 @@ SECTIONS
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
-
+
.fini_array :
{
. = ALIGN(4);
@@ -149,7 +149,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections into "RAM" Ram type memory */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -158,9 +158,9 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
-
+
} >RAM AT> FLASH
-
+
/* Uninitialized data section into "RAM" Ram type memory */
. = ALIGN(4);
.bss :
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
index f0879e929..8715e0723 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -153,7 +153,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
new file mode 100644
index 000000000..287593f43
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072RBTx_FLASH.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32F072xB
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
index 0b1824b8e..1febd01e8 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 4216ba186..57c658629 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,10 +1,9 @@
+MCU_VARIANT = stm32f072xb
+
CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
-
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
# For flash-jlink target
JLINK_DEVICE = stm32f072rb
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
new file mode 100644
index 000000000..42d778cb5
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072vb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072VBTx_FLASH.ld)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32F072xB
+ LSI_VALUE=40000
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
index 8869d5dc9..7dcfa3e85 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index bb9cba22a..bab889524 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,10 +1,9 @@
+MCU_VARIANT = stm32f072xb
+
CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
-
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
# For flash-jlink target
JLINK_DEVICE = stm32f072vb
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index a7e914128..7ef126ae6 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,14 +25,13 @@
*/
#include "stm32f0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
tud_int_handler(0);
}
@@ -41,8 +40,7 @@ void USB_IRQHandler(void)
//--------------------------------------------------------------------+
UART_HandleTypeDef UartHandle;
-void board_init(void)
-{
+void board_init(void) {
board_stm32f0_clock_init();
// Enable All GPIOs clocks
@@ -68,7 +66,7 @@ void board_init(void)
#endif
// LED
- GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = LED_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -83,20 +81,20 @@ void board_init(void)
HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
// Uart
- GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = UART_GPIO_AF;
HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
- UartHandle.Instance = UART_DEV;
- UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
+ UartHandle.Instance = UART_DEV;
+ UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
- UartHandle.Init.StopBits = UART_STOPBITS_1;
- UartHandle.Init.Parity = UART_PARITY_NONE;
- UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- UartHandle.Init.Mode = UART_MODE_TX_RX;
+ UartHandle.Init.StopBits = UART_STOPBITS_1;
+ UartHandle.Init.Parity = UART_PARITY_NONE;
+ UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ UartHandle.Init.Mode = UART_MODE_TX_RX;
UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
HAL_UART_Init(&UartHandle);
@@ -116,56 +114,60 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
- GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
- return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+ volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+ uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+ uint8_t const len = 12;
+
+ id32[0] = stm32_uuid[0];
+ id32[1] = stm32_uuid[1];
+ id32[2] = stm32_uuid[2];
-int board_uart_write(void const * buf, int len)
-{
- HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
return len;
}
-#if CFG_TUSB_OS == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+ (void) buf;
+ (void) len;
+ return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+ HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+ buf, len, 0xffff);
+ return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+ HAL_IncTick();
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
-void HardFault_Handler (void)
-{
- __asm("BKPT #0\n");
+void HardFault_Handler(void) {
+ __asm("BKPT #0\n");
}
#ifdef USE_FULL_ASSERT
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(uint8_t* file, uint32_t line)
+void assert_failed(const char* file, uint32_t line)
{
(void) file; (void) line;
/* USER CODE BEGIN 6 */
@@ -177,7 +179,5 @@ void assert_failed(uint8_t* file, uint32_t line)
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
}
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
new file mode 100644
index 000000000..e0fc705f8
--- /dev/null
+++ b/hw/bsp/stm32f0/family.cmake
@@ -0,0 +1,113 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+ set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ CFG_EXAMPLE_MSC_READONLY
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_STM32F0 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_stlink(${TARGET})
+ #family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 2983af49e..129a3b73a 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0
# --------------
# Compiler Flags
@@ -15,20 +16,12 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_STM32F0
# GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m0 \
- -mfloat-abi=soft \
-nostdlib -nostartfiles \
# suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
-
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m0
-IAR_ASFLAGS += --cpu cortex-m0
+CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-align
# ------------------------
# All source paths should be relative to the top level.
@@ -42,7 +35,9 @@ SRC_C += \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
- $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
+ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
INC += \
$(TOP)/$(BOARD_PATH) \
@@ -50,5 +45,9 @@ INC += \
$(TOP)/$(ST_CMSIS)/Include \
$(TOP)/$(ST_HAL_DRIVER)/Inc
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
index cfa66b366..b205464f3 100644
--- a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
+++ b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
@@ -30,9 +30,9 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
-#define HAL_MODULE_ENABLED
+#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
@@ -65,15 +65,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
@@ -82,24 +82,24 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator for ADC (HSI14) value.
*/
-#if !defined (HSI14_VALUE)
+#if !defined (HSI14_VALUE)
#define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
@@ -108,7 +108,7 @@
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
-#if !defined (HSI48_VALUE)
+#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
@@ -117,8 +117,8 @@
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE 32000U
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -127,7 +127,7 @@
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
+#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
@@ -143,8 +143,8 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
@@ -175,14 +175,14 @@
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
- #define USE_FULL_ASSERT 1
+ #define USE_FULL_ASSERT 1
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -299,17 +299,17 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+ void assert_failed(const char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
@@ -318,4 +318,3 @@
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..580fe02bb
--- /dev/null
+++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "stm32f1xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<RAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -153,7 +153,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
new file mode 100644
index 000000000..87b8458a2
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103c8)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103X8_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103x8_flash.icf)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32F103xB
+ HSE_VALUE=8000000U
+ CFG_EXAMPLE_VIDEO_READONLY
+ )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
index 57a607ed5..8fa8f4ffa 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index 159b3ecb6..6c5f34501 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
-IAR_LD_FILE = $(BOARD_PATH)/stm32f103x8_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103X8_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103x8_flash.icf
# For flash-jlink target
JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
index da637d1b0..524ac7c03 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -153,7 +153,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
new file mode 100644
index 000000000..67a96c4d1
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103rc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103XC_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103xc_flash.icf)
+
+function(update_board TARGET)
+ target_compile_definitions(${TARGET} PUBLIC
+ STM32F103xB
+ HSE_VALUE=8000000U
+ )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
index bedce7f14..c8dba4268 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
index efea75be7..7e95c1fe1 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
-IAR_LD_FILE = $(BOARD_PATH)/stm32f103xc_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103XC_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103xc_flash.icf
# For flash-jlink target
JLINK_DEVICE = stm32f103rc
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 246d496c8..3b1c5796b 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -25,24 +25,21 @@
*/
#include "stm32f1xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
#include "board.h"
//--------------------------------------------------------------------+
// Forward USB interrupt events to TinyUSB IRQ Handler
//--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
tud_int_handler(0);
}
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
tud_int_handler(0);
}
-void USBWakeUp_IRQHandler(void)
-{
+void USBWakeUp_IRQHandler(void) {
tud_int_handler(0);
}
@@ -50,17 +47,16 @@ void USBWakeUp_IRQHandler(void)
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-void board_init(void)
-{
+void board_init(void) {
board_stm32f1_clock_init();
-
+
// Enable All GPIOs clocks
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
-#if CFG_TUSB_OS == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
@@ -70,9 +66,9 @@ void board_init(void)
NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
#endif
-
+
// LED
- GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = LED_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = LED_STATE_ON ? GPIO_PULLDOWN : GPIO_PULLUP;
@@ -102,57 +98,61 @@ void board_init(void)
// Board porting API
//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
- GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+ GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
}
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
}
-int board_uart_read(uint8_t* buf, int len)
-{
- (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+ (void) max_len;
+ volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+ uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+ uint8_t const len = 12;
+
+ id32[0] = stm32_uuid[0];
+ id32[1] = stm32_uuid[1];
+ id32[2] = stm32_uuid[2];
+
+ return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-int board_uart_write(void const * buf, int len)
-{
- (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+ (void) buf;
+ (void) len;
return 0;
}
-#if CFG_TUSB_OS == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
+ HAL_IncTick();
system_ticks++;
}
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
return system_ticks;
}
+
#endif
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
__asm("BKPT #0\n");
}
#ifdef USE_FULL_ASSERT
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(char *file, uint32_t line)
-{
+void assert_failed(const char *file, uint32_t line)
+{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
@@ -162,7 +162,5 @@ void assert_failed(char *file, uint32_t line)
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
}
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
new file mode 100644
index 000000000..53af35862
--- /dev/null
+++ b/hw/bsp/stm32f1/family.cmake
@@ -0,0 +1,110 @@
+include_guard()
+
+if (NOT BOARD)
+ message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f1)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+ if (NOT TARGET ${BOARD_TARGET})
+ # Startup & Linker script
+ set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+ set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+ add_library(${BOARD_TARGET} STATIC
+ ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+ ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+ ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+ )
+ target_include_directories(${BOARD_TARGET} PUBLIC
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMSIS_5}/CMSIS/Core/Include
+ ${ST_CMSIS}/Include
+ ${ST_HAL_DRIVER}/Inc
+ )
+ target_compile_options(${BOARD_TARGET} PUBLIC
+ )
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ )
+
+ update_board(${BOARD_TARGET})
+
+ if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--script=${LD_FILE_GNU}"
+ -nostartfiles
+ # nanolib
+ --specs=nosys.specs
+ --specs=nano.specs
+ )
+ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+ target_link_options(${BOARD_TARGET} PUBLIC
+ "LINKER:--config=${LD_FILE_IAR}"
+ )
+ endif ()
+ endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+ family_configure_common(${TARGET} ${RTOS})
+
+ # Board target
+ add_board_target(board_${BOARD})
+
+ #---------- Port Specific ----------
+ # These files are built for each example since it depends on example's tusb_config.h
+ target_sources(${TARGET} PUBLIC
+ # BSP
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ )
+ target_include_directories(${TARGET} PUBLIC
+ # family, hw, board
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+ )
+
+ # Add TinyUSB target and port source
+ family_add_tinyusb(${TARGET} OPT_MCU_STM32F1 ${RTOS})
+ target_sources(${TARGET}-tinyusb PUBLIC
+ ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+ )
+ target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+ # Link dependencies
+ target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+ # Flashing
+ family_flash_stlink(${TARGET})
+ #family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 4327f1cf8..c9321c3cb 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -5,6 +5,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
# --------------
# Compiler Flags
@@ -13,18 +14,10 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_STM32F1
# GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
- -mfloat-abi=soft \
-nostdlib -nostartfiles \
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m3
-IAR_ASFLAGS += --cpu cortex-m3
-
# ------------------------
# All source paths should be relative to the top level.
# ------------------------
@@ -43,11 +36,9 @@ INC += \
$(TOP)/$(ST_CMSIS)/Include \
$(TOP)/$(ST_HAL_DRIVER)/Inc
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f103c8
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
# flash target ROM bootloader
flash-dfu-util: $(BUILD)/$(PROJECT).bin
diff --git a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
index a4a3f3086..45ef993da 100644
--- a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
+++ b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
@@ -32,7 +32,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
@@ -69,9 +69,9 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
@@ -86,7 +86,7 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
@@ -95,7 +95,7 @@
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
+#if !defined (LSI_VALUE)
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
@@ -119,7 +119,7 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
+ */
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0x00U /*!< tick interrupt priority */
#define USE_RTOS 0U
@@ -151,7 +151,7 @@
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
@@ -168,7 +168,7 @@
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
-/* Definition of the Ethernet driver buffers size and count */
+/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
@@ -176,9 +176,9 @@
/* Section 2: PHY configuration section */
-/* DP83848 PHY Address*/
+/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY 0x00000FFFU
@@ -190,7 +190,7 @@
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-
+
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
@@ -205,13 +205,13 @@
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
+
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
-
+
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
@@ -233,7 +233,7 @@
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -243,7 +243,7 @@
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
-
+
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f1xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
@@ -251,7 +251,7 @@
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
@@ -310,15 +310,15 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f1xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
+#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h"
@@ -358,17 +358,17 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+ void assert_failed(const char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
similarity index 99%
rename from hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
rename to hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
index 5010435ae..3fce1b578 100644
--- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -153,7 +153,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
new file mode 100644
index 000000000..ba185d199
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+ -DSTM32F207xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F207ZGTx_FLASH.ld
+
+SRC_S += \
+ $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f207zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
similarity index 98%
rename from hw/bsp/stm32f207nucleo/stm32f207nucleo.c
rename to hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
index 619c90d68..dfbe7b743 100644
--- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "../board.h"
+#include "bsp/board_api.h"
#include "stm32f2xx_hal.h"
@@ -105,7 +105,7 @@ void SystemClock_Config(void)
void board_init(void)
{
SystemClock_Config();
-
+
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
@@ -191,6 +191,7 @@ int board_uart_write(void const * buf, int len)
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
+ HAL_IncTick();
system_ticks++;
}
@@ -202,7 +203,7 @@ uint32_t board_millis(void)
void HardFault_Handler (void)
{
- asm("bkpt");
+ __asm("BKPT #0\n");
}
// Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/family.mk
similarity index 53%
rename from hw/bsp/stm32f207nucleo/board.mk
rename to hw/bsp/stm32f2/family.mk
index fa7d28399..ce50b16ad 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -1,24 +1,25 @@
ST_FAMILY = f2
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += \
+ lib/CMSIS_5 \
+ $(ST_CMSIS) \
+ $(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
+
CFLAGS += \
+ -DCFG_TUSB_MCU=OPT_MCU_STM32F2
+
+CFLAGS_GCC += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m3 \
- -mfloat-abi=soft \
-nostdlib -nostartfiles \
- -DSTM32F207xx \
- -DCFG_TUSB_MCU=OPT_MCU_STM32F2
# mcu driver cause following warnings
-CFLAGS += -Wno-error=sign-compare
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
+CFLAGS_GCC += -Wno-error=sign-compare
SRC_C += \
src/portable/synopsys/dwc2/dcd_dwc2.c \
@@ -29,20 +30,8 @@ SRC_C += \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-SRC_S += \
- $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
-
INC += \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(ST_CMSIS)/Include \
$(TOP)/$(ST_HAL_DRIVER)/Inc \
- $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f207zg
-
-# flash target using on-board stlink
-flash: flash-stlink
+ $(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/hw/bsp/stm32f2/stm32f2xx_hal_conf.h
similarity index 96%
rename from hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
rename to hw/bsp/stm32f2/stm32f2xx_hal_conf.h
index 2ab46b260..b38a9d951 100644
--- a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
+++ b/hw/bsp/stm32f2/stm32f2xx_hal_conf.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_HAL_CONF_H
@@ -30,9 +30,9 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
-#define HAL_MODULE_ENABLED
+#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
@@ -42,7 +42,7 @@
/* #define HAL_DMA_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
@@ -52,8 +52,8 @@
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
@@ -65,7 +65,7 @@
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
@@ -73,9 +73,9 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
@@ -86,7 +86,7 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
@@ -95,7 +95,7 @@
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
+#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
@@ -113,8 +113,8 @@
/**
* @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
@@ -126,7 +126,7 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
+ */
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U
@@ -163,7 +163,7 @@
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
@@ -180,7 +180,7 @@
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
-/* Definition of the Ethernet driver buffers size and count */
+/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
@@ -190,7 +190,7 @@
/* LAN8742A PHY Address*/
#define LAN8742A_PHY_ADDRESS 0x00U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY 0x00000FFFU
@@ -202,7 +202,7 @@
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-
+
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
@@ -217,7 +217,7 @@
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
+
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */
@@ -228,7 +228,7 @@
#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */
-
+
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
@@ -240,7 +240,7 @@
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -258,7 +258,7 @@
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f2xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f2xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -276,7 +276,7 @@
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32f2xx_hal_cryp.h"
+ #include "stm32f2xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
@@ -294,7 +294,7 @@
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f2xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
-
+
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f2xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
@@ -309,7 +309,7 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f2xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f2xx_hal_hash.h"
@@ -378,14 +378,14 @@
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f2xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
-
+
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -402,6 +402,6 @@
#endif
#endif /* __STM32F2xx_HAL_CONF_H */
-
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
similarity index 98%
rename from hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
rename to hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
index 7f46c71b2..981107af1 100644
--- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
_siccmram = LOADADDR(.ccmram);
- /* CCM-RAM section
- *
- * IMPORTANT NOTE!
+ /* CCM-RAM section
+ *
+ * IMPORTANT NOTE!
* If initialized variables will be placed in this section,
- * the startup code needs to be modified to copy the init-values.
+ * the startup code needs to be modified to copy the init-values.
*/
.ccmram :
{
@@ -140,12 +140,12 @@ SECTIONS
_sccmram = .; /* create a global symbol at ccmram start */
*(.ccmram)
*(.ccmram*)
-
+
. = ALIGN(4);
_eccmram = .; /* create a global symbol at ccmram end */
} >CCMRAM AT> FLASH
-
+
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@@ -173,7 +173,7 @@ SECTIONS
. = ALIGN(8);
} >RAM
-
+
/* Remove information from the standard libraries */
/DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
new file mode 100644
index 000000000..e387f2d54
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+ -DSTM32F303xC \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F303VCTx_FLASH.ld
+
+SRC_S += \
+ $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f303vc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
similarity index 99%
rename from hw/bsp/stm32f303disco/stm32f303disco.c
rename to hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
index 33552bc07..d6a39a8e2 100644
--- a/hw/bsp/stm32f303disco/stm32f303disco.c
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
@@ -1,4 +1,4 @@
-/*
+/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -24,7 +24,7 @@
* This file is part of the TinyUSB stack.
*/
-#include "../board.h"
+#include "bsp/board_api.h"
#include "stm32f3xx_hal.h"
//--------------------------------------------------------------------+
@@ -193,6 +193,7 @@ int board_uart_write(void const * buf, int len)
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
+ HAL_IncTick();
system_ticks++;
}
diff --git a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
similarity index 96%
rename from hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
rename to hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
index 0abcbb019..82d3765af 100644
--- a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
@@ -30,9 +30,9 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
-#define HAL_MODULE_ENABLED
+#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
@@ -57,7 +57,7 @@
/* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
/* #define HAL_PWR_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SDADC_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
@@ -73,15 +73,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
@@ -90,25 +90,25 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE (40000U)
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -124,11 +124,11 @@
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
+#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
+ * This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
@@ -256,8 +256,8 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f3/family.mk
similarity index 57%
rename from hw/bsp/stm32f303disco/board.mk
rename to hw/bsp/stm32f3/family.mk
index 9dd27a857..a740e9012 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f3/family.mk
@@ -1,26 +1,24 @@
ST_FAMILY = f3
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += \
+ lib/CMSIS_5 \
+ $(ST_CMSIS) \
+ $(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
CFLAGS += \
-flto \
- -mthumb \
- -mabi=aapcs \
- -mcpu=cortex-m4 \
- -mfloat-abi=hard \
- -mfpu=fpv4-sp-d16 \
-nostdlib -nostartfiles \
- -DSTM32F303xC \
-DCFG_TUSB_MCU=OPT_MCU_STM32F3
# mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
-
SRC_C += \
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
@@ -30,20 +28,8 @@ SRC_C += \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-SRC_S += \
- $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
-
INC += \
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(ST_CMSIS)/Include \
$(TOP)/$(ST_HAL_DRIVER)/Inc \
- $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f303vc
-
-# flash target using on-board stlink
-flash: flash-stlink
+ $(TOP)/$(BOARD_PATH)
diff --git a/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..ed90261d0
--- /dev/null
+++ b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+ #include "stm32f4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU 0
+#define configENABLE_FPU 1
+#define configENABLE_TRUSTZONE 0
+#define configMINIMAL_SECURE_STACK_SIZE (1024)
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ SystemCoreClock
+#define configTICK_RATE_HZ ( 1000 )
+#define configMAX_PRIORITIES ( 5 )
+#define configMINIMAL_STACK_SIZE ( 128 )
+#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN 16
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configQUEUE_REGISTRY_SIZE 4
+#define configUSE_QUEUE_SETS 0
+#define configUSE_TIME_SLICING 0
+#define configUSE_NEWLIB_REENTRANT 0
+#define configENABLE_BACKWARD_COMPATIBILITY 1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
+
+#define configSUPPORT_STATIC_ALLOCATION 0
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS 0
+#define configRECORD_STACK_HIGH_ADDRESS 1
+#define configUSE_TRACE_FACILITY 1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES 2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH 32
+#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet 0
+#define INCLUDE_uxTaskPriorityGet 0
+#define INCLUDE_vTaskDelete 0
+#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR 0
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 0
+#define INCLUDE_xTaskGetCurrentTaskHandle 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#define INCLUDE_xTaskGetIdleTaskHandle 0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName 0
+#define INCLUDE_eTaskGetState 0
+#define INCLUDE_xEventGroupSetBitFromISR 0
+#define INCLUDE_xTimerPendFunctionCall 0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define configASSERT(_exp) \
+ do {\
+ if ( !(_exp) ) { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
+ taskDISABLE_INTERRUPTS(); \
+ __asm("BKPT #0\n"); \
+ }\
+ }\
+ } while(0)
+#else
+ #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+#define vPortSVCHandler SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS 4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<